OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Blame information for rev 360

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_registers.v                                             ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 147 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 333 igorm
// Revision 1.28  2004/04/26 15:26:23  igorm
45
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
46
//   previous update of the core.
47
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
48
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
49
//   register. (thanks to Mathias and Torbjorn)
50
// - Multicast reception was fixed. Thanks to Ulrich Gries
51
//
52 321 igorm
// Revision 1.27  2004/04/26 11:42:17  igorm
53
// TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.
54
//
55 320 igorm
// Revision 1.26  2003/11/12 18:24:59  tadejm
56
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
57
//
58 304 tadejm
// Revision 1.25  2003/04/18 16:26:25  mohor
59
// RxBDAddress was updated also when value to r_TxBDNum was written with
60
// greater value than allowed.
61
//
62 283 mohor
// Revision 1.24  2002/11/22 01:57:06  mohor
63
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
64
// synchronized.
65
//
66 261 mohor
// Revision 1.23  2002/11/19 18:13:49  mohor
67
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
68
//
69 253 mohor
// Revision 1.22  2002/11/14 18:37:20  mohor
70
// r_Rst signal does not reset any module any more and is removed from the design.
71
//
72 244 mohor
// Revision 1.21  2002/09/10 10:35:23  mohor
73
// Ethernet debug registers removed.
74
//
75 164 mohor
// Revision 1.20  2002/09/04 18:40:25  mohor
76
// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
77
// the control frames connected.
78
//
79 147 mohor
// Revision 1.19  2002/08/19 16:01:40  mohor
80
// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
81
// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
82
//
83 143 mohor
// Revision 1.18  2002/08/16 22:28:23  mohor
84
// Syntax error fixed.
85
//
86 141 mohor
// Revision 1.17  2002/08/16 22:23:03  mohor
87
// Syntax error fixed.
88
//
89 140 mohor
// Revision 1.16  2002/08/16 22:14:22  mohor
90
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
91
// changed from bit position 10 to 9.
92
//
93 139 mohor
// Revision 1.15  2002/08/14 18:26:37  mohor
94
// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
95
//
96 132 mohor
// Revision 1.14  2002/04/22 14:03:44  mohor
97
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
98
// or not.
99
//
100 102 mohor
// Revision 1.13  2002/02/26 16:18:09  mohor
101
// Reset values are passed to registers through parameters
102
//
103 74 mohor
// Revision 1.12  2002/02/17 13:23:42  mohor
104
// Define missmatch fixed.
105
//
106 69 mohor
// Revision 1.11  2002/02/16 14:03:44  mohor
107
// Registered trimmed. Unused registers removed.
108
//
109 68 mohor
// Revision 1.10  2002/02/15 11:08:25  mohor
110
// File format fixed a bit.
111
//
112 56 mohor
// Revision 1.9  2002/02/14 20:19:41  billditt
113
// Modified for Address Checking,
114
// addition of eth_addrcheck.v
115
//
116
// Revision 1.8  2002/02/12 17:01:19  mohor
117
// HASH0 and HASH1 registers added. 
118
 
119 46 mohor
// Revision 1.7  2002/01/23 10:28:16  mohor
120
// Link in the header changed.
121
//
122 37 mohor
// Revision 1.6  2001/12/05 15:00:16  mohor
123
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
124
// instead of the number of RX descriptors).
125
//
126 34 mohor
// Revision 1.5  2001/12/05 10:22:19  mohor
127
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
128
//
129 32 mohor
// Revision 1.4  2001/10/19 08:43:51  mohor
130
// eth_timescale.v changed to timescale.v This is done because of the
131
// simulation of the few cores in a one joined project.
132
//
133 22 mohor
// Revision 1.3  2001/10/18 12:07:11  mohor
134
// Status signals changed, Adress decoding changed, interrupt controller
135
// added.
136
//
137 21 mohor
// Revision 1.2  2001/09/24 15:02:56  mohor
138
// Defines changed (All precede with ETH_). Small changes because some
139
// tools generate warnings when two operands are together. Synchronization
140
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
141
// demands).
142
//
143 20 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
144
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
145
// Include files fixed to contain no path.
146
// File names and module names changed ta have a eth_ prologue in the name.
147
// File eth_timescale.v is used to define timescale
148
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
149
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
150
// and Mdo_OE. The bidirectional signal must be created on the top level. This
151
// is done due to the ASIC tools.
152
//
153 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
154
// Unconnected signals are now connected.
155
//
156
// Revision 1.1  2001/07/30 21:23:42  mohor
157
// Directory structure changed. Files checked and joind together.
158
//
159
//
160
//
161
//
162
//
163
//
164
 
165 356 olof
`include "ethmac_defines.v"
166 22 mohor
`include "timescale.v"
167 15 mohor
 
168
 
169 68 mohor
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
170 15 mohor
                      r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
171 244 mohor
                      r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
172 21 mohor
                      r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
173 147 mohor
                      TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
174 21 mohor
                      r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
175 15 mohor
                      r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
176 253 mohor
                      r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
177 15 mohor
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
178
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
179 321 igorm
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
180 354 olof
                      r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
181 360 olof
                      dbg_dat,
182 261 mohor
                      StartTxDone, TxClk, RxClk, SetPauseTimer
183 15 mohor
                    );
184
 
185
input [31:0] DataIn;
186 46 mohor
input [7:0] Address;
187 15 mohor
 
188
input Rw;
189 304 tadejm
input [3:0] Cs;
190 15 mohor
input Clk;
191
input Reset;
192
 
193
input WCtrlDataStart;
194
input RStatStart;
195
 
196
input UpdateMIIRX_DATAReg;
197
input [15:0] Prsd;
198
 
199
output [31:0] DataOut;
200
reg    [31:0] DataOut;
201
 
202
output r_RecSmall;
203
output r_Pad;
204
output r_HugEn;
205
output r_CrcEn;
206
output r_DlyCrcEn;
207
output r_FullD;
208
output r_ExDfrEn;
209
output r_NoBckof;
210
output r_LoopBck;
211
output r_IFG;
212
output r_Pro;
213
output r_Iam;
214
output r_Bro;
215
output r_NoPre;
216
output r_TxEn;
217
output r_RxEn;
218 52 billditt
output [31:0] r_HASH0;
219
output [31:0] r_HASH1;
220 15 mohor
 
221 21 mohor
input TxB_IRQ;
222
input TxE_IRQ;
223
input RxB_IRQ;
224 74 mohor
input RxE_IRQ;
225 21 mohor
input Busy_IRQ;
226 15 mohor
 
227
output [6:0] r_IPGT;
228
 
229
output [6:0] r_IPGR1;
230
 
231
output [6:0] r_IPGR2;
232
 
233
output [15:0] r_MinFL;
234
output [15:0] r_MaxFL;
235
 
236
output [3:0] r_MaxRet;
237
output [5:0] r_CollValid;
238
 
239
output r_TxFlow;
240
output r_RxFlow;
241
output r_PassAll;
242
 
243
output r_MiiNoPre;
244
output [7:0] r_ClkDiv;
245
 
246
output r_WCtrlData;
247
output r_RStat;
248
output r_ScanStat;
249
 
250
output [4:0] r_RGAD;
251
output [4:0] r_FIAD;
252
 
253 21 mohor
output [15:0]r_CtrlData;
254 15 mohor
 
255
 
256
input NValid_stat;
257
input Busy_stat;
258
input LinkFail;
259
 
260 21 mohor
output [47:0]r_MAC;
261 34 mohor
output [7:0] r_TxBDNum;
262 21 mohor
output       int_o;
263 147 mohor
output [15:0]r_TxPauseTV;
264
output       r_TxPauseRq;
265
input        RstTxPauseRq;
266
input        TxCtrlEndFrm;
267
input        StartTxDone;
268
input        TxClk;
269
input        RxClk;
270 261 mohor
input        SetPauseTimer;
271 15 mohor
 
272 360 olof
input [31:0] dbg_dat; // debug data input
273
 
274 21 mohor
reg          irq_txb;
275
reg          irq_txe;
276
reg          irq_rxb;
277 74 mohor
reg          irq_rxe;
278 21 mohor
reg          irq_busy;
279 74 mohor
reg          irq_txc;
280
reg          irq_rxc;
281 15 mohor
 
282 147 mohor
reg SetTxCIrq_txclk;
283
reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
284
reg SetTxCIrq;
285
reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
286
 
287
reg SetRxCIrq_rxclk;
288
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
289
reg SetRxCIrq;
290 261 mohor
reg ResetRxCIrq_sync1;
291
reg ResetRxCIrq_sync2;
292
reg ResetRxCIrq_sync3;
293 147 mohor
 
294 304 tadejm
wire [3:0] Write =   Cs  & {4{Rw}};
295
wire       Read  = (|Cs) &   ~Rw;
296 15 mohor
 
297 320 igorm
wire MODER_Sel      = (Address == `ETH_MODER_ADR       );
298
wire INT_SOURCE_Sel = (Address == `ETH_INT_SOURCE_ADR  );
299
wire INT_MASK_Sel   = (Address == `ETH_INT_MASK_ADR    );
300
wire IPGT_Sel       = (Address == `ETH_IPGT_ADR        );
301
wire IPGR1_Sel      = (Address == `ETH_IPGR1_ADR       );
302
wire IPGR2_Sel      = (Address == `ETH_IPGR2_ADR       );
303
wire PACKETLEN_Sel  = (Address == `ETH_PACKETLEN_ADR   );
304
wire COLLCONF_Sel   = (Address == `ETH_COLLCONF_ADR    );
305 21 mohor
 
306 320 igorm
wire CTRLMODER_Sel  = (Address == `ETH_CTRLMODER_ADR   );
307
wire MIIMODER_Sel   = (Address == `ETH_MIIMODER_ADR    );
308
wire MIICOMMAND_Sel = (Address == `ETH_MIICOMMAND_ADR  );
309
wire MIIADDRESS_Sel = (Address == `ETH_MIIADDRESS_ADR  );
310
wire MIITX_DATA_Sel = (Address == `ETH_MIITX_DATA_ADR  );
311
wire MAC_ADDR0_Sel  = (Address == `ETH_MAC_ADDR0_ADR   );
312
wire MAC_ADDR1_Sel  = (Address == `ETH_MAC_ADDR1_ADR   );
313
wire HASH0_Sel      = (Address == `ETH_HASH0_ADR       );
314
wire HASH1_Sel      = (Address == `ETH_HASH1_ADR       );
315
wire TXCTRL_Sel     = (Address == `ETH_TX_CTRL_ADR     );
316
wire RXCTRL_Sel     = (Address == `ETH_RX_CTRL_ADR     );
317 360 olof
wire DBG_REG_Sel    = (Address == `ETH_DBG_ADR         );
318 320 igorm
wire TX_BD_NUM_Sel  = (Address == `ETH_TX_BD_NUM_ADR   );
319 15 mohor
 
320
 
321 320 igorm
wire [2:0] MODER_Wr;
322
wire [0:0] INT_SOURCE_Wr;
323
wire [0:0] INT_MASK_Wr;
324
wire [0:0] IPGT_Wr;
325
wire [0:0] IPGR1_Wr;
326
wire [0:0] IPGR2_Wr;
327
wire [3:0] PACKETLEN_Wr;
328
wire [2:0] COLLCONF_Wr;
329
wire [0:0] CTRLMODER_Wr;
330
wire [1:0] MIIMODER_Wr;
331
wire [0:0] MIICOMMAND_Wr;
332
wire [1:0] MIIADDRESS_Wr;
333
wire [1:0] MIITX_DATA_Wr;
334
wire       MIIRX_DATA_Wr;
335
wire [3:0] MAC_ADDR0_Wr;
336
wire [1:0] MAC_ADDR1_Wr;
337
wire [3:0] HASH0_Wr;
338
wire [3:0] HASH1_Wr;
339
wire [2:0] TXCTRL_Wr;
340 321 igorm
wire [0:0] TX_BD_NUM_Wr;
341 15 mohor
 
342 320 igorm
assign MODER_Wr[0]       = Write[0]  & MODER_Sel;
343
assign MODER_Wr[1]       = Write[1]  & MODER_Sel;
344
assign MODER_Wr[2]       = Write[2]  & MODER_Sel;
345
assign INT_SOURCE_Wr[0]  = Write[0]  & INT_SOURCE_Sel;
346
assign INT_MASK_Wr[0]    = Write[0]  & INT_MASK_Sel;
347
assign IPGT_Wr[0]        = Write[0]  & IPGT_Sel;
348
assign IPGR1_Wr[0]       = Write[0]  & IPGR1_Sel;
349
assign IPGR2_Wr[0]       = Write[0]  & IPGR2_Sel;
350
assign PACKETLEN_Wr[0]   = Write[0]  & PACKETLEN_Sel;
351
assign PACKETLEN_Wr[1]   = Write[1]  & PACKETLEN_Sel;
352
assign PACKETLEN_Wr[2]   = Write[2]  & PACKETLEN_Sel;
353
assign PACKETLEN_Wr[3]   = Write[3]  & PACKETLEN_Sel;
354
assign COLLCONF_Wr[0]    = Write[0]  & COLLCONF_Sel;
355
assign COLLCONF_Wr[1]    = 1'b0;  // Not used
356
assign COLLCONF_Wr[2]    = Write[2]  & COLLCONF_Sel;
357
 
358
assign CTRLMODER_Wr[0]   = Write[0]  & CTRLMODER_Sel;
359
assign MIIMODER_Wr[0]    = Write[0]  & MIIMODER_Sel;
360
assign MIIMODER_Wr[1]    = Write[1]  & MIIMODER_Sel;
361
assign MIICOMMAND_Wr[0]  = Write[0]  & MIICOMMAND_Sel;
362
assign MIIADDRESS_Wr[0]  = Write[0]  & MIIADDRESS_Sel;
363
assign MIIADDRESS_Wr[1]  = Write[1]  & MIIADDRESS_Sel;
364
assign MIITX_DATA_Wr[0]  = Write[0]  & MIITX_DATA_Sel;
365
assign MIITX_DATA_Wr[1]  = Write[1]  & MIITX_DATA_Sel;
366
assign MIIRX_DATA_Wr     = UpdateMIIRX_DATAReg;
367
assign MAC_ADDR0_Wr[0]   = Write[0]  & MAC_ADDR0_Sel;
368
assign MAC_ADDR0_Wr[1]   = Write[1]  & MAC_ADDR0_Sel;
369
assign MAC_ADDR0_Wr[2]   = Write[2]  & MAC_ADDR0_Sel;
370
assign MAC_ADDR0_Wr[3]   = Write[3]  & MAC_ADDR0_Sel;
371
assign MAC_ADDR1_Wr[0]   = Write[0]  & MAC_ADDR1_Sel;
372
assign MAC_ADDR1_Wr[1]   = Write[1]  & MAC_ADDR1_Sel;
373
assign HASH0_Wr[0]       = Write[0]  & HASH0_Sel;
374
assign HASH0_Wr[1]       = Write[1]  & HASH0_Sel;
375
assign HASH0_Wr[2]       = Write[2]  & HASH0_Sel;
376
assign HASH0_Wr[3]       = Write[3]  & HASH0_Sel;
377
assign HASH1_Wr[0]       = Write[0]  & HASH1_Sel;
378
assign HASH1_Wr[1]       = Write[1]  & HASH1_Sel;
379
assign HASH1_Wr[2]       = Write[2]  & HASH1_Sel;
380
assign HASH1_Wr[3]       = Write[3]  & HASH1_Sel;
381
assign TXCTRL_Wr[0]      = Write[0]  & TXCTRL_Sel;
382
assign TXCTRL_Wr[1]      = Write[1]  & TXCTRL_Sel;
383
assign TXCTRL_Wr[2]      = Write[2]  & TXCTRL_Sel;
384 321 igorm
assign TX_BD_NUM_Wr[0]   = Write[0]  & TX_BD_NUM_Sel & (DataIn<='h80);
385 320 igorm
 
386
 
387
 
388 15 mohor
wire [31:0] MODEROut;
389
wire [31:0] INT_SOURCEOut;
390
wire [31:0] INT_MASKOut;
391
wire [31:0] IPGTOut;
392
wire [31:0] IPGR1Out;
393
wire [31:0] IPGR2Out;
394
wire [31:0] PACKETLENOut;
395
wire [31:0] COLLCONFOut;
396
wire [31:0] CTRLMODEROut;
397
wire [31:0] MIIMODEROut;
398
wire [31:0] MIICOMMANDOut;
399
wire [31:0] MIIADDRESSOut;
400
wire [31:0] MIITX_DATAOut;
401
wire [31:0] MIIRX_DATAOut;
402
wire [31:0] MIISTATUSOut;
403
wire [31:0] MAC_ADDR0Out;
404
wire [31:0] MAC_ADDR1Out;
405 34 mohor
wire [31:0] TX_BD_NUMOut;
406 52 billditt
wire [31:0] HASH0Out;
407
wire [31:0] HASH1Out;
408 147 mohor
wire [31:0] TXCTRLOut;
409 360 olof
wire [31:0] DBGOut;
410 15 mohor
 
411 139 mohor
// MODER Register
412 304 tadejm
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0)        MODER_0
413 139 mohor
  (
414 304 tadejm
   .DataIn    (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
415
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]),
416 320 igorm
   .Write     (MODER_Wr[0]),
417 139 mohor
   .Clk       (Clk),
418
   .Reset     (Reset),
419 141 mohor
   .SyncReset (1'b0)
420 139 mohor
  );
421 304 tadejm
eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1)        MODER_1
422
  (
423
   .DataIn    (DataIn[`ETH_MODER_WIDTH_1 + 7:8]),
424
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]),
425 320 igorm
   .Write     (MODER_Wr[1]),
426 304 tadejm
   .Clk       (Clk),
427
   .Reset     (Reset),
428
   .SyncReset (1'b0)
429
  );
430
eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2)        MODER_2
431
  (
432
   .DataIn    (DataIn[`ETH_MODER_WIDTH_2 + 15:16]),
433
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]),
434 320 igorm
   .Write     (MODER_Wr[2]),
435 304 tadejm
   .Clk       (Clk),
436
   .Reset     (Reset),
437
   .SyncReset (1'b0)
438
  );
439
assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0;
440 15 mohor
 
441 139 mohor
// INT_MASK Register
442 304 tadejm
eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0)  INT_MASK_0
443 139 mohor
  (
444 304 tadejm
   .DataIn    (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]),
445
   .DataOut   (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]),
446 320 igorm
   .Write     (INT_MASK_Wr[0]),
447 139 mohor
   .Clk       (Clk),
448
   .Reset     (Reset),
449 141 mohor
   .SyncReset (1'b0)
450 139 mohor
  );
451 304 tadejm
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0;
452 52 billditt
 
453 139 mohor
// IPGT Register
454 304 tadejm
eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0)          IPGT_0
455 139 mohor
  (
456 304 tadejm
   .DataIn    (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]),
457
   .DataOut   (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]),
458 320 igorm
   .Write     (IPGT_Wr[0]),
459 139 mohor
   .Clk       (Clk),
460
   .Reset     (Reset),
461 141 mohor
   .SyncReset (1'b0)
462 139 mohor
  );
463 304 tadejm
assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0;
464 52 billditt
 
465 139 mohor
// IPGR1 Register
466 304 tadejm
eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0)        IPGR1_0
467 139 mohor
  (
468 304 tadejm
   .DataIn    (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]),
469
   .DataOut   (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]),
470 320 igorm
   .Write     (IPGR1_Wr[0]),
471 139 mohor
   .Clk       (Clk),
472
   .Reset     (Reset),
473 141 mohor
   .SyncReset (1'b0)
474 139 mohor
  );
475 304 tadejm
assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0;
476 15 mohor
 
477 139 mohor
// IPGR2 Register
478 304 tadejm
eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0)        IPGR2_0
479 139 mohor
  (
480 304 tadejm
   .DataIn    (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]),
481
   .DataOut   (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]),
482 320 igorm
   .Write     (IPGR2_Wr[0]),
483 139 mohor
   .Clk       (Clk),
484
   .Reset     (Reset),
485 141 mohor
   .SyncReset (1'b0)
486 139 mohor
  );
487 304 tadejm
assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0;
488 15 mohor
 
489 139 mohor
// PACKETLEN Register
490 304 tadejm
eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0
491 139 mohor
  (
492 304 tadejm
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
493
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
494 320 igorm
   .Write     (PACKETLEN_Wr[0]),
495 139 mohor
   .Clk       (Clk),
496
   .Reset     (Reset),
497 141 mohor
   .SyncReset (1'b0)
498 139 mohor
  );
499 304 tadejm
eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1
500
  (
501
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
502
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
503 320 igorm
   .Write     (PACKETLEN_Wr[1]),
504 304 tadejm
   .Clk       (Clk),
505
   .Reset     (Reset),
506
   .SyncReset (1'b0)
507
  );
508
eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2
509
  (
510
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
511
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
512 320 igorm
   .Write     (PACKETLEN_Wr[2]),
513 304 tadejm
   .Clk       (Clk),
514
   .Reset     (Reset),
515
   .SyncReset (1'b0)
516
  );
517
eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3
518
  (
519
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
520
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
521 320 igorm
   .Write     (PACKETLEN_Wr[3]),
522 304 tadejm
   .Clk       (Clk),
523
   .Reset     (Reset),
524
   .SyncReset (1'b0)
525
  );
526 15 mohor
 
527 139 mohor
// COLLCONF Register
528 304 tadejm
eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0)   COLLCONF_0
529 139 mohor
  (
530 304 tadejm
   .DataIn    (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]),
531
   .DataOut   (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]),
532 320 igorm
   .Write     (COLLCONF_Wr[0]),
533 139 mohor
   .Clk       (Clk),
534
   .Reset     (Reset),
535 141 mohor
   .SyncReset (1'b0)
536 139 mohor
  );
537 304 tadejm
eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2)   COLLCONF_2
538 139 mohor
  (
539 304 tadejm
   .DataIn    (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]),
540
   .DataOut   (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]),
541 320 igorm
   .Write     (COLLCONF_Wr[2]),
542 139 mohor
   .Clk       (Clk),
543
   .Reset     (Reset),
544 141 mohor
   .SyncReset (1'b0)
545 139 mohor
  );
546 304 tadejm
assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0;
547
assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0;
548 15 mohor
 
549 139 mohor
// TX_BD_NUM Register
550 304 tadejm
eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0
551 139 mohor
  (
552 304 tadejm
   .DataIn    (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
553
   .DataOut   (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
554 321 igorm
   .Write     (TX_BD_NUM_Wr[0]),
555 139 mohor
   .Clk       (Clk),
556
   .Reset     (Reset),
557 141 mohor
   .SyncReset (1'b0)
558 139 mohor
  );
559 304 tadejm
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0;
560 15 mohor
 
561 139 mohor
// CTRLMODER Register
562 304 tadejm
eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0)  CTRLMODER_0
563 139 mohor
  (
564 304 tadejm
   .DataIn    (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
565
   .DataOut   (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
566 320 igorm
   .Write     (CTRLMODER_Wr[0]),
567 139 mohor
   .Clk       (Clk),
568
   .Reset     (Reset),
569 141 mohor
   .SyncReset (1'b0)
570 139 mohor
  );
571 304 tadejm
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0;
572 15 mohor
 
573 139 mohor
// MIIMODER Register
574 304 tadejm
eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0)    MIIMODER_0
575 139 mohor
  (
576 304 tadejm
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]),
577
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]),
578 320 igorm
   .Write     (MIIMODER_Wr[0]),
579 139 mohor
   .Clk       (Clk),
580
   .Reset     (Reset),
581 141 mohor
   .SyncReset (1'b0)
582 139 mohor
  );
583 304 tadejm
eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1)    MIIMODER_1
584
  (
585
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]),
586
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]),
587 320 igorm
   .Write     (MIIMODER_Wr[1]),
588 304 tadejm
   .Clk       (Clk),
589
   .Reset     (Reset),
590
   .SyncReset (1'b0)
591
  );
592
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0;
593 68 mohor
 
594 139 mohor
// MIICOMMAND Register
595
eth_register #(1, 0)                                      MIICOMMAND0
596
  (
597
   .DataIn    (DataIn[0]),
598
   .DataOut   (MIICOMMANDOut[0]),
599 320 igorm
   .Write     (MIICOMMAND_Wr[0]),
600 139 mohor
   .Clk       (Clk),
601
   .Reset     (Reset),
602 141 mohor
   .SyncReset (1'b0)
603 139 mohor
  );
604
eth_register #(1, 0)                                      MIICOMMAND1
605
  (
606
   .DataIn    (DataIn[1]),
607
   .DataOut   (MIICOMMANDOut[1]),
608 320 igorm
   .Write     (MIICOMMAND_Wr[0]),
609 139 mohor
   .Clk       (Clk),
610
   .Reset     (Reset),
611
   .SyncReset (RStatStart)
612
  );
613
eth_register #(1, 0)                                      MIICOMMAND2
614
  (
615
   .DataIn    (DataIn[2]),
616
   .DataOut   (MIICOMMANDOut[2]),
617 320 igorm
   .Write     (MIICOMMAND_Wr[0]),
618 139 mohor
   .Clk       (Clk),
619
   .Reset     (Reset),
620
   .SyncReset (WCtrlDataStart)
621
  );
622 304 tadejm
assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0;
623 15 mohor
 
624 139 mohor
// MIIADDRESSRegister
625 304 tadejm
eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0
626 139 mohor
  (
627 304 tadejm
   .DataIn    (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
628
   .DataOut   (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
629 320 igorm
   .Write     (MIIADDRESS_Wr[0]),
630 139 mohor
   .Clk       (Clk),
631
   .Reset     (Reset),
632 141 mohor
   .SyncReset (1'b0)
633 139 mohor
  );
634 304 tadejm
eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1
635 139 mohor
  (
636 304 tadejm
   .DataIn    (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
637
   .DataOut   (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
638 320 igorm
   .Write     (MIIADDRESS_Wr[1]),
639 139 mohor
   .Clk       (Clk),
640
   .Reset     (Reset),
641 141 mohor
   .SyncReset (1'b0)
642 139 mohor
  );
643 304 tadejm
assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0;
644
assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0;
645 15 mohor
 
646 139 mohor
// MIITX_DATA Register
647 304 tadejm
eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0
648 139 mohor
  (
649 304 tadejm
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
650
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
651 320 igorm
   .Write     (MIITX_DATA_Wr[0]),
652 139 mohor
   .Clk       (Clk),
653
   .Reset     (Reset),
654 141 mohor
   .SyncReset (1'b0)
655 139 mohor
  );
656 304 tadejm
eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1
657
  (
658
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
659
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
660 320 igorm
   .Write     (MIITX_DATA_Wr[1]),
661 304 tadejm
   .Clk       (Clk),
662
   .Reset     (Reset),
663
   .SyncReset (1'b0)
664
  );
665
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0;
666 15 mohor
 
667 139 mohor
// MIIRX_DATA Register
668
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
669
  (
670
   .DataIn    (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
671
   .DataOut   (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
672 304 tadejm
   .Write     (MIIRX_DATA_Wr), // not written from WB
673 139 mohor
   .Clk       (Clk),
674
   .Reset     (Reset),
675 141 mohor
   .SyncReset (1'b0)
676 139 mohor
  );
677
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
678 15 mohor
 
679 139 mohor
// MAC_ADDR0 Register
680 304 tadejm
eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0)  MAC_ADDR0_0
681 139 mohor
  (
682 304 tadejm
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
683
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
684 320 igorm
   .Write     (MAC_ADDR0_Wr[0]),
685 139 mohor
   .Clk       (Clk),
686
   .Reset     (Reset),
687 141 mohor
   .SyncReset (1'b0)
688 139 mohor
  );
689 304 tadejm
eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1)  MAC_ADDR0_1
690
  (
691
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
692
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
693 320 igorm
   .Write     (MAC_ADDR0_Wr[1]),
694 304 tadejm
   .Clk       (Clk),
695
   .Reset     (Reset),
696
   .SyncReset (1'b0)
697
  );
698
eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2)  MAC_ADDR0_2
699
  (
700
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
701
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
702 320 igorm
   .Write     (MAC_ADDR0_Wr[2]),
703 304 tadejm
   .Clk       (Clk),
704
   .Reset     (Reset),
705
   .SyncReset (1'b0)
706
  );
707
eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3)  MAC_ADDR0_3
708
  (
709
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
710
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
711 320 igorm
   .Write     (MAC_ADDR0_Wr[3]),
712 304 tadejm
   .Clk       (Clk),
713
   .Reset     (Reset),
714
   .SyncReset (1'b0)
715
  );
716 68 mohor
 
717 139 mohor
// MAC_ADDR1 Register
718 304 tadejm
eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0)  MAC_ADDR1_0
719 139 mohor
  (
720 304 tadejm
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
721
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
722 320 igorm
   .Write     (MAC_ADDR1_Wr[0]),
723 139 mohor
   .Clk       (Clk),
724
   .Reset     (Reset),
725 141 mohor
   .SyncReset (1'b0)
726 139 mohor
  );
727 304 tadejm
eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1)  MAC_ADDR1_1
728
  (
729
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
730
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
731 320 igorm
   .Write     (MAC_ADDR1_Wr[1]),
732 304 tadejm
   .Clk       (Clk),
733
   .Reset     (Reset),
734
   .SyncReset (1'b0)
735
  );
736
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0;
737 68 mohor
 
738 139 mohor
// RXHASH0 Register
739 304 tadejm
eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0)          RXHASH0_0
740 139 mohor
  (
741 304 tadejm
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]),
742
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]),
743 320 igorm
   .Write     (HASH0_Wr[0]),
744 139 mohor
   .Clk       (Clk),
745
   .Reset     (Reset),
746 141 mohor
   .SyncReset (1'b0)
747 139 mohor
  );
748 304 tadejm
eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1)          RXHASH0_1
749
  (
750
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]),
751
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]),
752 320 igorm
   .Write     (HASH0_Wr[1]),
753 304 tadejm
   .Clk       (Clk),
754
   .Reset     (Reset),
755
   .SyncReset (1'b0)
756
  );
757
eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2)          RXHASH0_2
758
  (
759
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]),
760
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]),
761 320 igorm
   .Write     (HASH0_Wr[2]),
762 304 tadejm
   .Clk       (Clk),
763
   .Reset     (Reset),
764
   .SyncReset (1'b0)
765
  );
766
eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3)          RXHASH0_3
767
  (
768
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]),
769
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]),
770 320 igorm
   .Write     (HASH0_Wr[3]),
771 304 tadejm
   .Clk       (Clk),
772
   .Reset     (Reset),
773
   .SyncReset (1'b0)
774
  );
775 68 mohor
 
776 139 mohor
// RXHASH1 Register
777 304 tadejm
eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0)          RXHASH1_0
778 139 mohor
  (
779 304 tadejm
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]),
780
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]),
781 320 igorm
   .Write     (HASH1_Wr[0]),
782 139 mohor
   .Clk       (Clk),
783
   .Reset     (Reset),
784 141 mohor
   .SyncReset (1'b0)
785 139 mohor
  );
786 304 tadejm
eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1)          RXHASH1_1
787
  (
788
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]),
789
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]),
790 320 igorm
   .Write     (HASH1_Wr[1]),
791 304 tadejm
   .Clk       (Clk),
792
   .Reset     (Reset),
793
   .SyncReset (1'b0)
794
  );
795
eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2)          RXHASH1_2
796
  (
797
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]),
798
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]),
799 320 igorm
   .Write     (HASH1_Wr[2]),
800 304 tadejm
   .Clk       (Clk),
801
   .Reset     (Reset),
802
   .SyncReset (1'b0)
803
  );
804
eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3)          RXHASH1_3
805
  (
806
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]),
807
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]),
808 320 igorm
   .Write     (HASH1_Wr[3]),
809 304 tadejm
   .Clk       (Clk),
810
   .Reset     (Reset),
811
   .SyncReset (1'b0)
812
  );
813 68 mohor
 
814 147 mohor
// TXCTRL Register
815 304 tadejm
eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0)  TXCTRL_0
816 147 mohor
  (
817 304 tadejm
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
818
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
819 320 igorm
   .Write     (TXCTRL_Wr[0]),
820 147 mohor
   .Clk       (Clk),
821
   .Reset     (Reset),
822
   .SyncReset (1'b0)
823
  );
824 304 tadejm
eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1)  TXCTRL_1
825 147 mohor
  (
826 304 tadejm
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
827
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
828 320 igorm
   .Write     (TXCTRL_Wr[1]),
829 147 mohor
   .Clk       (Clk),
830
   .Reset     (Reset),
831 304 tadejm
   .SyncReset (1'b0)
832
  );
833
eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2)  TXCTRL_2 // Request bit is synchronously reset
834
  (
835
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
836
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
837 320 igorm
   .Write     (TXCTRL_Wr[2]),
838 304 tadejm
   .Clk       (Clk),
839
   .Reset     (Reset),
840 147 mohor
   .SyncReset (RstTxPauseRq)
841
  );
842 304 tadejm
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
843 147 mohor
 
844
 
845
 
846 139 mohor
// Reading data from registers
847
always @ (Address       or Read           or MODEROut       or INT_SOURCEOut  or
848
          INT_MASKOut   or IPGTOut        or IPGR1Out       or IPGR2Out       or
849
          PACKETLENOut  or COLLCONFOut    or CTRLMODEROut   or MIIMODEROut    or
850
          MIICOMMANDOut or MIIADDRESSOut  or MIITX_DATAOut  or MIIRX_DATAOut  or
851
          MIISTATUSOut  or MAC_ADDR0Out   or MAC_ADDR1Out   or TX_BD_NUMOut   or
852 333 igorm
          HASH0Out      or HASH1Out       or TXCTRLOut
853 139 mohor
         )
854 15 mohor
begin
855
  if(Read)  // read
856
    begin
857
      case(Address)
858 357 olof
        `ETH_MODER_ADR        :  DataOut=MODEROut;
859
        `ETH_INT_SOURCE_ADR   :  DataOut=INT_SOURCEOut;
860
        `ETH_INT_MASK_ADR     :  DataOut=INT_MASKOut;
861
        `ETH_IPGT_ADR         :  DataOut=IPGTOut;
862
        `ETH_IPGR1_ADR        :  DataOut=IPGR1Out;
863
        `ETH_IPGR2_ADR        :  DataOut=IPGR2Out;
864
        `ETH_PACKETLEN_ADR    :  DataOut=PACKETLENOut;
865
        `ETH_COLLCONF_ADR     :  DataOut=COLLCONFOut;
866
        `ETH_CTRLMODER_ADR    :  DataOut=CTRLMODEROut;
867
        `ETH_MIIMODER_ADR     :  DataOut=MIIMODEROut;
868
        `ETH_MIICOMMAND_ADR   :  DataOut=MIICOMMANDOut;
869
        `ETH_MIIADDRESS_ADR   :  DataOut=MIIADDRESSOut;
870
        `ETH_MIITX_DATA_ADR   :  DataOut=MIITX_DATAOut;
871
        `ETH_MIIRX_DATA_ADR   :  DataOut=MIIRX_DATAOut;
872
        `ETH_MIISTATUS_ADR    :  DataOut=MIISTATUSOut;
873
        `ETH_MAC_ADDR0_ADR    :  DataOut=MAC_ADDR0Out;
874
        `ETH_MAC_ADDR1_ADR    :  DataOut=MAC_ADDR1Out;
875
        `ETH_TX_BD_NUM_ADR    :  DataOut=TX_BD_NUMOut;
876
        `ETH_HASH0_ADR        :  DataOut=HASH0Out;
877
        `ETH_HASH1_ADR        :  DataOut=HASH1Out;
878
        `ETH_TX_CTRL_ADR      :  DataOut=TXCTRLOut;
879 360 olof
        `ETH_DBG_ADR          :  DataOut=dbg_dat;
880 357 olof
        default:             DataOut=32'h0;
881 15 mohor
      endcase
882
    end
883
  else
884 357 olof
    DataOut=32'h0;
885 15 mohor
end
886
 
887
 
888
assign r_RecSmall         = MODEROut[16];
889
assign r_Pad              = MODEROut[15];
890
assign r_HugEn            = MODEROut[14];
891
assign r_CrcEn            = MODEROut[13];
892
assign r_DlyCrcEn         = MODEROut[12];
893 244 mohor
// assign r_Rst           = MODEROut[11];   This signal is not used any more
894 15 mohor
assign r_FullD            = MODEROut[10];
895
assign r_ExDfrEn          = MODEROut[9];
896
assign r_NoBckof          = MODEROut[8];
897
assign r_LoopBck          = MODEROut[7];
898
assign r_IFG              = MODEROut[6];
899
assign r_Pro              = MODEROut[5];
900
assign r_Iam              = MODEROut[4];
901
assign r_Bro              = MODEROut[3];
902
assign r_NoPre            = MODEROut[2];
903 143 mohor
assign r_TxEn             = MODEROut[1] & (TX_BD_NUMOut>0);     // Transmission is enabled when there is at least one TxBD.
904
assign r_RxEn             = MODEROut[0] & (TX_BD_NUMOut<'h80);  // Reception is enabled when there is  at least one RxBD.
905 15 mohor
 
906
assign r_IPGT[6:0]        = IPGTOut[6:0];
907
 
908
assign r_IPGR1[6:0]       = IPGR1Out[6:0];
909
 
910
assign r_IPGR2[6:0]       = IPGR2Out[6:0];
911
 
912
assign r_MinFL[15:0]      = PACKETLENOut[31:16];
913
assign r_MaxFL[15:0]      = PACKETLENOut[15:0];
914
 
915 56 mohor
assign r_MaxRet[3:0]      = COLLCONFOut[19:16];
916
assign r_CollValid[5:0]   = COLLCONFOut[5:0];
917 15 mohor
 
918
assign r_TxFlow           = CTRLMODEROut[2];
919
assign r_RxFlow           = CTRLMODEROut[1];
920
assign r_PassAll          = CTRLMODEROut[0];
921
 
922
assign r_MiiNoPre         = MIIMODEROut[8];
923
assign r_ClkDiv[7:0]      = MIIMODEROut[7:0];
924
 
925
assign r_WCtrlData        = MIICOMMANDOut[2];
926
assign r_RStat            = MIICOMMANDOut[1];
927
assign r_ScanStat         = MIICOMMANDOut[0];
928
 
929
assign r_RGAD[4:0]        = MIIADDRESSOut[12:8];
930
assign r_FIAD[4:0]        = MIIADDRESSOut[4:0];
931
 
932
assign r_CtrlData[15:0]   = MIITX_DATAOut[15:0];
933
 
934 139 mohor
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
935
assign MIISTATUSOut[2]    = NValid_stat         ;
936
assign MIISTATUSOut[1]    = Busy_stat           ;
937
assign MIISTATUSOut[0]    = LinkFail            ;
938 15 mohor
 
939
assign r_MAC[31:0]        = MAC_ADDR0Out[31:0];
940
assign r_MAC[47:32]       = MAC_ADDR1Out[15:0];
941 52 billditt
assign r_HASH1[31:0]      = HASH1Out;
942
assign r_HASH0[31:0]      = HASH0Out;
943 15 mohor
 
944 147 mohor
assign r_TxBDNum[7:0]     = TX_BD_NUMOut[7:0];
945 15 mohor
 
946 147 mohor
assign r_TxPauseTV[15:0]  = TXCTRLOut[15:0];
947
assign r_TxPauseRq        = TXCTRLOut[16];
948 15 mohor
 
949 147 mohor
 
950
// Synchronizing TxC Interrupt
951
always @ (posedge TxClk or posedge Reset)
952
begin
953
  if(Reset)
954 352 olof
    SetTxCIrq_txclk <= 1'b0;
955 147 mohor
  else
956
  if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
957 352 olof
    SetTxCIrq_txclk <= 1'b1;
958 147 mohor
  else
959
  if(ResetTxCIrq_sync2)
960 352 olof
    SetTxCIrq_txclk <= 1'b0;
961 147 mohor
end
962
 
963
 
964
always @ (posedge Clk or posedge Reset)
965
begin
966
  if(Reset)
967 352 olof
    SetTxCIrq_sync1 <= 1'b0;
968 147 mohor
  else
969 352 olof
    SetTxCIrq_sync1 <= SetTxCIrq_txclk;
970 147 mohor
end
971
 
972
always @ (posedge Clk or posedge Reset)
973
begin
974
  if(Reset)
975 352 olof
    SetTxCIrq_sync2 <= 1'b0;
976 147 mohor
  else
977 352 olof
    SetTxCIrq_sync2 <= SetTxCIrq_sync1;
978 147 mohor
end
979
 
980
always @ (posedge Clk or posedge Reset)
981
begin
982
  if(Reset)
983 352 olof
    SetTxCIrq_sync3 <= 1'b0;
984 147 mohor
  else
985 352 olof
    SetTxCIrq_sync3 <= SetTxCIrq_sync2;
986 147 mohor
end
987
 
988
always @ (posedge Clk or posedge Reset)
989
begin
990
  if(Reset)
991 352 olof
    SetTxCIrq <= 1'b0;
992 147 mohor
  else
993 352 olof
    SetTxCIrq <= SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
994 147 mohor
end
995
 
996
always @ (posedge TxClk or posedge Reset)
997
begin
998
  if(Reset)
999 352 olof
    ResetTxCIrq_sync1 <= 1'b0;
1000 147 mohor
  else
1001 352 olof
    ResetTxCIrq_sync1 <= SetTxCIrq_sync2;
1002 147 mohor
end
1003
 
1004
always @ (posedge TxClk or posedge Reset)
1005
begin
1006
  if(Reset)
1007 352 olof
    ResetTxCIrq_sync2 <= 1'b0;
1008 147 mohor
  else
1009 352 olof
    ResetTxCIrq_sync2 <= SetTxCIrq_sync1;
1010 147 mohor
end
1011
 
1012
 
1013
// Synchronizing RxC Interrupt
1014
always @ (posedge RxClk or posedge Reset)
1015
begin
1016
  if(Reset)
1017 352 olof
    SetRxCIrq_rxclk <= 1'b0;
1018 147 mohor
  else
1019 261 mohor
  if(SetPauseTimer & r_RxFlow)
1020 352 olof
    SetRxCIrq_rxclk <= 1'b1;
1021 147 mohor
  else
1022 261 mohor
  if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
1023 352 olof
    SetRxCIrq_rxclk <= 1'b0;
1024 147 mohor
end
1025
 
1026
 
1027
always @ (posedge Clk or posedge Reset)
1028
begin
1029
  if(Reset)
1030 352 olof
    SetRxCIrq_sync1 <= 1'b0;
1031 147 mohor
  else
1032 352 olof
    SetRxCIrq_sync1 <= SetRxCIrq_rxclk;
1033 147 mohor
end
1034
 
1035
always @ (posedge Clk or posedge Reset)
1036
begin
1037
  if(Reset)
1038 352 olof
    SetRxCIrq_sync2 <= 1'b0;
1039 147 mohor
  else
1040 352 olof
    SetRxCIrq_sync2 <= SetRxCIrq_sync1;
1041 147 mohor
end
1042
 
1043
always @ (posedge Clk or posedge Reset)
1044
begin
1045
  if(Reset)
1046 352 olof
    SetRxCIrq_sync3 <= 1'b0;
1047 147 mohor
  else
1048 352 olof
    SetRxCIrq_sync3 <= SetRxCIrq_sync2;
1049 147 mohor
end
1050
 
1051
always @ (posedge Clk or posedge Reset)
1052
begin
1053
  if(Reset)
1054 352 olof
    SetRxCIrq <= 1'b0;
1055 147 mohor
  else
1056 352 olof
    SetRxCIrq <= SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
1057 147 mohor
end
1058
 
1059
always @ (posedge RxClk or posedge Reset)
1060
begin
1061
  if(Reset)
1062 352 olof
    ResetRxCIrq_sync1 <= 1'b0;
1063 147 mohor
  else
1064 352 olof
    ResetRxCIrq_sync1 <= SetRxCIrq_sync2;
1065 147 mohor
end
1066
 
1067 261 mohor
always @ (posedge RxClk or posedge Reset)
1068 147 mohor
begin
1069
  if(Reset)
1070 352 olof
    ResetRxCIrq_sync2 <= 1'b0;
1071 147 mohor
  else
1072 352 olof
    ResetRxCIrq_sync2 <= ResetRxCIrq_sync1;
1073 147 mohor
end
1074
 
1075 261 mohor
always @ (posedge RxClk or posedge Reset)
1076
begin
1077
  if(Reset)
1078 352 olof
    ResetRxCIrq_sync3 <= 1'b0;
1079 261 mohor
  else
1080 352 olof
    ResetRxCIrq_sync3 <= ResetRxCIrq_sync2;
1081 261 mohor
end
1082 147 mohor
 
1083
 
1084
 
1085 21 mohor
// Interrupt generation
1086
always @ (posedge Clk or posedge Reset)
1087
begin
1088
  if(Reset)
1089
    irq_txb <= 1'b0;
1090
  else
1091 102 mohor
  if(TxB_IRQ)
1092 352 olof
    irq_txb <=  1'b1;
1093 21 mohor
  else
1094 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[0])
1095 352 olof
    irq_txb <=  1'b0;
1096 21 mohor
end
1097
 
1098
always @ (posedge Clk or posedge Reset)
1099
begin
1100
  if(Reset)
1101
    irq_txe <= 1'b0;
1102
  else
1103 102 mohor
  if(TxE_IRQ)
1104 352 olof
    irq_txe <=  1'b1;
1105 21 mohor
  else
1106 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[1])
1107 352 olof
    irq_txe <=  1'b0;
1108 21 mohor
end
1109
 
1110
always @ (posedge Clk or posedge Reset)
1111
begin
1112
  if(Reset)
1113
    irq_rxb <= 1'b0;
1114
  else
1115 102 mohor
  if(RxB_IRQ)
1116 352 olof
    irq_rxb <=  1'b1;
1117 21 mohor
  else
1118 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[2])
1119 352 olof
    irq_rxb <=  1'b0;
1120 21 mohor
end
1121
 
1122
always @ (posedge Clk or posedge Reset)
1123
begin
1124
  if(Reset)
1125 74 mohor
    irq_rxe <= 1'b0;
1126 21 mohor
  else
1127 102 mohor
  if(RxE_IRQ)
1128 352 olof
    irq_rxe <=  1'b1;
1129 21 mohor
  else
1130 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[3])
1131 352 olof
    irq_rxe <=  1'b0;
1132 21 mohor
end
1133
 
1134
always @ (posedge Clk or posedge Reset)
1135
begin
1136
  if(Reset)
1137
    irq_busy <= 1'b0;
1138
  else
1139 102 mohor
  if(Busy_IRQ)
1140 352 olof
    irq_busy <=  1'b1;
1141 21 mohor
  else
1142 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[4])
1143 352 olof
    irq_busy <=  1'b0;
1144 21 mohor
end
1145
 
1146 74 mohor
always @ (posedge Clk or posedge Reset)
1147
begin
1148
  if(Reset)
1149
    irq_txc <= 1'b0;
1150
  else
1151 147 mohor
  if(SetTxCIrq)
1152 352 olof
    irq_txc <=  1'b1;
1153 74 mohor
  else
1154 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[5])
1155 352 olof
    irq_txc <=  1'b0;
1156 74 mohor
end
1157
 
1158
always @ (posedge Clk or posedge Reset)
1159
begin
1160
  if(Reset)
1161
    irq_rxc <= 1'b0;
1162
  else
1163 147 mohor
  if(SetRxCIrq)
1164 352 olof
    irq_rxc <=  1'b1;
1165 74 mohor
  else
1166 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[6])
1167 352 olof
    irq_rxc <=  1'b0;
1168 74 mohor
end
1169
 
1170 21 mohor
// Generating interrupt signal
1171 102 mohor
assign int_o = irq_txb  & INT_MASKOut[0] |
1172
               irq_txe  & INT_MASKOut[1] |
1173
               irq_rxb  & INT_MASKOut[2] |
1174
               irq_rxe  & INT_MASKOut[3] |
1175
               irq_busy & INT_MASKOut[4] |
1176
               irq_txc  & INT_MASKOut[5] |
1177
               irq_rxc  & INT_MASKOut[6] ;
1178 21 mohor
 
1179
// For reading interrupt status
1180 304 tadejm
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
1181 21 mohor
 
1182
 
1183
 
1184 15 mohor
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.