OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxcounters.v] - Blame information for rev 326

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_rxcounters.v                                            ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
11
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
12
////                                                              ////
13
////  All additional information is avaliable in the Readme.txt   ////
14
////  file.                                                       ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2001 Authors                                   ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: not supported by cvs2svn $
46 326 igorm
// Revision 1.5  2002/02/15 11:13:29  mohor
47
// Format of the file changed a bit.
48
//
49 57 mohor
// Revision 1.4  2002/02/14 20:19:41  billditt
50
// Modified for Address Checking,
51
// addition of eth_addrcheck.v
52
//
53 52 billditt
// Revision 1.3  2002/01/23 10:28:16  mohor
54
// Link in the header changed.
55
//
56 37 mohor
// Revision 1.2  2001/10/19 08:43:51  mohor
57
// eth_timescale.v changed to timescale.v This is done because of the
58
// simulation of the few cores in a one joined project.
59
//
60 22 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
61
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
62
// Include files fixed to contain no path.
63
// File names and module names changed ta have a eth_ prologue in the name.
64
// File eth_timescale.v is used to define timescale
65
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
66
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
67
// and Mdo_OE. The bidirectional signal must be created on the top level. This
68
// is done due to the ASIC tools.
69
//
70 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
71
// Directory structure changed. Files checked and joind together.
72
//
73
// Revision 1.1  2001/06/27 21:26:19  mohor
74
// Initial release of the RxEthMAC module.
75
//
76
//
77
//
78
//
79
//
80
//
81
 
82
 
83 22 mohor
`include "timescale.v"
84 15 mohor
 
85
 
86
module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
87
                       MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
88 57 mohor
                       ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
89 326 igorm
                       ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
90 15 mohor
                      );
91
 
92
parameter Tp = 1;
93
 
94
input         MRxClk;
95
input         Reset;
96
input         MRxDV;
97
input         StateSFD;
98
input [1:0]   StateData;
99
input         MRxDEqD;
100
input         StateIdle;
101
input         StateDrop;
102
input         DlyCrcEn;
103
input         StatePreamble;
104
input         Transmitting;
105
input         HugEn;
106
input [15:0]  MaxFL;
107
input         r_IFG;
108
 
109
output        IFGCounterEq24;           // IFG counter reaches 9600 ns (960 ns)
110
output [3:0]  DlyCrcCnt;                // Delayed CRC counter
111
output        ByteCntEq0;               // Byte counter = 0
112
output        ByteCntEq1;               // Byte counter = 1
113 52 billditt
output        ByteCntEq2;               // Byte counter = 2  
114
output        ByteCntEq3;               // Byte counter = 3  
115
output        ByteCntEq4;               // Byte counter = 4  
116
output        ByteCntEq5;               // Byte counter = 5  
117 15 mohor
output        ByteCntEq6;               // Byte counter = 6
118 52 billditt
output        ByteCntEq7;               // Byte counter = 7
119 15 mohor
output        ByteCntGreat2;            // Byte counter > 2
120
output        ByteCntSmall7;            // Byte counter < 7
121
output        ByteCntMaxFrame;          // Byte counter = MaxFL
122 326 igorm
output [15:0] ByteCntOut;               // Byte counter
123 15 mohor
 
124
wire          ResetByteCounter;
125
wire          IncrementByteCounter;
126
wire          ResetIFGCounter;
127
wire          IncrementIFGCounter;
128
wire          ByteCntMax;
129
 
130
reg   [15:0]  ByteCnt;
131
reg   [3:0]   DlyCrcCnt;
132
reg   [4:0]   IFGCounter;
133
 
134 326 igorm
wire  [15:0]  ByteCntDelayed;
135 15 mohor
 
136
 
137 326 igorm
 
138 15 mohor
assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
139
 
140
assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
141
                              (StatePreamble | StateSFD | StateIdle & ~Transmitting |
142
                               StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt)
143
                              );
144
 
145
 
146
always @ (posedge MRxClk or posedge Reset)
147
begin
148
  if(Reset)
149 326 igorm
    ByteCnt[15:0] <= #Tp 16'h0;
150 15 mohor
  else
151
    begin
152
      if(ResetByteCounter)
153 326 igorm
        ByteCnt[15:0] <= #Tp 16'h0;
154 15 mohor
      else
155
      if(IncrementByteCounter)
156
        ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
157
     end
158
end
159
 
160 326 igorm
assign ByteCntDelayed = ByteCnt + 3'h4;
161
assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
162
 
163 15 mohor
assign ByteCntEq0       = ByteCnt == 16'h0;
164
assign ByteCntEq1       = ByteCnt == 16'h1;
165 52 billditt
assign ByteCntEq2       = ByteCnt == 16'h2;
166
assign ByteCntEq3       = ByteCnt == 16'h3;
167
assign ByteCntEq4       = ByteCnt == 16'h4;
168
assign ByteCntEq5       = ByteCnt == 16'h5;
169 15 mohor
assign ByteCntEq6       = ByteCnt == 16'h6;
170 52 billditt
assign ByteCntEq7       = ByteCnt == 16'h7;
171 15 mohor
assign ByteCntGreat2    = ByteCnt >  16'h2;
172
assign ByteCntSmall7    = ByteCnt <  16'h7;
173
assign ByteCntMax       = ByteCnt == 16'hffff;
174
assign ByteCntMaxFrame  = ByteCnt == MaxFL[15:0] & ~HugEn;
175
 
176
 
177
assign ResetIFGCounter = StateSFD  &  MRxDV & MRxDEqD | StateDrop;
178
 
179
assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
180
 
181
always @ (posedge MRxClk or posedge Reset)
182
begin
183
  if(Reset)
184
    IFGCounter[4:0] <= #Tp 5'h0;
185
  else
186
    begin
187
      if(ResetIFGCounter)
188
        IFGCounter[4:0] <= #Tp 5'h0;
189
      else
190
      if(IncrementIFGCounter)
191
        IFGCounter[4:0] <= #Tp IFGCounter[4:0] + 1'b1;
192
    end
193
end
194
 
195
 
196
 
197
assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1
198
 
199
 
200
always @ (posedge MRxClk or posedge Reset)
201
begin
202
  if(Reset)
203
    DlyCrcCnt[3:0] <= #Tp 4'h0;
204
  else
205
    begin
206
      if(DlyCrcCnt[3:0] == 4'h9)
207
        DlyCrcCnt[3:0] <= #Tp 4'h0;
208
      else
209
      if(DlyCrcEn & StateSFD)
210
        DlyCrcCnt[3:0] <= #Tp 4'h1;
211
      else
212
      if(DlyCrcEn & (|DlyCrcCnt[3:0]))
213
        DlyCrcCnt[3:0] <= #Tp DlyCrcCnt[3:0] + 1'b1;
214
    end
215
end
216
 
217
 
218
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.