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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxcounters.v] - Blame information for rev 353

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_rxcounters.v                                            ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/project,ethmac                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
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////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.5  2002/02/15 11:13:29  mohor
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// Format of the file changed a bit.
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//
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// Revision 1.4  2002/02/14 20:19:41  billditt
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// Modified for Address Checking,
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// addition of eth_addrcheck.v
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//
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// Revision 1.3  2002/01/23 10:28:16  mohor
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// Link in the header changed.
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//
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// Revision 1.2  2001/10/19 08:43:51  mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
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// Revision 1.1  2001/08/06 14:44:29  mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.1  2001/07/30 21:23:42  mohor
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// Directory structure changed. Files checked and joind together.
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//
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// Revision 1.1  2001/06/27 21:26:19  mohor
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// Initial release of the RxEthMAC module.
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//
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//
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//
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//
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//
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//
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`include "timescale.v"
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module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
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                       MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
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                       ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
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                       ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
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                      );
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input         MRxClk;
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input         Reset;
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input         MRxDV;
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input         StateSFD;
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input [1:0]   StateData;
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input         MRxDEqD;
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input         StateIdle;
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input         StateDrop;
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input         DlyCrcEn;
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input         StatePreamble;
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input         Transmitting;
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input         HugEn;
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input [15:0]  MaxFL;
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input         r_IFG;
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output        IFGCounterEq24;           // IFG counter reaches 9600 ns (960 ns)
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output [3:0]  DlyCrcCnt;                // Delayed CRC counter
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output        ByteCntEq0;               // Byte counter = 0
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output        ByteCntEq1;               // Byte counter = 1
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output        ByteCntEq2;               // Byte counter = 2  
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output        ByteCntEq3;               // Byte counter = 3  
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output        ByteCntEq4;               // Byte counter = 4  
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output        ByteCntEq5;               // Byte counter = 5  
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output        ByteCntEq6;               // Byte counter = 6
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output        ByteCntEq7;               // Byte counter = 7
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output        ByteCntGreat2;            // Byte counter > 2
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output        ByteCntSmall7;            // Byte counter < 7
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output        ByteCntMaxFrame;          // Byte counter = MaxFL
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output [15:0] ByteCntOut;               // Byte counter
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wire          ResetByteCounter;
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wire          IncrementByteCounter;
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wire          ResetIFGCounter;
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wire          IncrementIFGCounter;
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wire          ByteCntMax;
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reg   [15:0]  ByteCnt;
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reg   [3:0]   DlyCrcCnt;
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reg   [4:0]   IFGCounter;
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wire  [15:0]  ByteCntDelayed;
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assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
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assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
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                              (StatePreamble | StateSFD | StateIdle & ~Transmitting |
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                               StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt)
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                              );
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always @ (posedge MRxClk or posedge Reset)
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begin
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  if(Reset)
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    ByteCnt[15:0] <=  16'd0;
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  else
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    begin
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      if(ResetByteCounter)
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        ByteCnt[15:0] <=  16'd0;
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      else
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      if(IncrementByteCounter)
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        ByteCnt[15:0] <=  ByteCnt[15:0] + 16'd1;
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     end
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end
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assign ByteCntDelayed = ByteCnt + 16'd4;
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assign ByteCntOut = DlyCrcEn ? ByteCntDelayed : ByteCnt;
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assign ByteCntEq0       = ByteCnt == 16'd0;
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assign ByteCntEq1       = ByteCnt == 16'd1;
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assign ByteCntEq2       = ByteCnt == 16'd2;
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assign ByteCntEq3       = ByteCnt == 16'd3;
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assign ByteCntEq4       = ByteCnt == 16'd4;
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assign ByteCntEq5       = ByteCnt == 16'd5;
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assign ByteCntEq6       = ByteCnt == 16'd6;
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assign ByteCntEq7       = ByteCnt == 16'd7;
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assign ByteCntGreat2    = ByteCnt >  16'd2;
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assign ByteCntSmall7    = ByteCnt <  16'd7;
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assign ByteCntMax       = ByteCnt == 16'hffff;
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assign ByteCntMaxFrame  = ByteCnt == MaxFL[15:0] & ~HugEn;
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assign ResetIFGCounter = StateSFD  &  MRxDV & MRxDEqD | StateDrop;
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assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
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always @ (posedge MRxClk or posedge Reset)
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begin
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  if(Reset)
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    IFGCounter[4:0] <=  5'h0;
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  else
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    begin
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      if(ResetIFGCounter)
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        IFGCounter[4:0] <=  5'h0;
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      else
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      if(IncrementIFGCounter)
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        IFGCounter[4:0] <=  IFGCounter[4:0] + 5'd1;
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    end
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end
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assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1
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always @ (posedge MRxClk or posedge Reset)
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begin
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  if(Reset)
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    DlyCrcCnt[3:0] <=  4'h0;
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  else
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    begin
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      if(DlyCrcCnt[3:0] == 4'h9)
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        DlyCrcCnt[3:0] <=  4'h0;
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      else
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      if(DlyCrcEn & StateSFD)
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        DlyCrcCnt[3:0] <=  4'h1;
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      else
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      if(DlyCrcEn & (|DlyCrcCnt[3:0]))
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        DlyCrcCnt[3:0] <=  DlyCrcCnt[3:0] + 4'd1;
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    end
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end
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endmodule

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