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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxethmac.v] - Blame information for rev 352

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1 15 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_rxethmac.v                                              ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
6 341 olof
////  http://www.opencores.org/projects,ethmac/                   ////
7 15 mohor
////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
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////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
12 341 olof
////      - Olof Kindgren (olof@opencores.org                     ////
13 15 mohor
////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
19 341 olof
//// Copyright (C) 2011 Authors                                   ////
20 15 mohor
////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
43
//
44 341 olof
// 2011-07-06 Olof Kindgren <olof@opencores.org>
45
// Add ByteCntEq0 to rxaddrcheck
46
//
47 15 mohor
// CVS Revision History
48
//
49 341 olof
//
50 15 mohor
// $Log: not supported by cvs2svn $
51 330 igorm
// Revision 1.12  2004/04/26 15:26:23  igorm
52
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
53
//   previous update of the core.
54
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
55
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
56
//   register. (thanks to Mathias and Torbjorn)
57
// - Multicast reception was fixed. Thanks to Ulrich Gries
58
//
59 321 igorm
// Revision 1.11  2004/03/17 09:32:15  igorm
60
// Multicast detection fixed. Only the LSB of the first byte is checked.
61
//
62 317 igorm
// Revision 1.10  2002/11/22 01:57:06  mohor
63
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
64
// synchronized.
65
//
66 261 mohor
// Revision 1.9  2002/11/19 17:35:35  mohor
67
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
68
// that a frame was received because of the promiscous mode.
69
//
70 250 mohor
// Revision 1.8  2002/02/16 07:15:27  mohor
71
// Testbench fixed, code simplified, unused signals removed.
72
//
73 65 mohor
// Revision 1.7  2002/02/15 13:44:28  mohor
74
// RxAbort is an output. No need to have is declared as wire.
75
//
76 62 mohor
// Revision 1.6  2002/02/15 11:17:48  mohor
77
// File format changed.
78
//
79 58 mohor
// Revision 1.5  2002/02/14 20:48:43  billditt
80
// Addition  of new module eth_addrcheck.v
81
//
82 53 billditt
// Revision 1.4  2002/01/23 10:28:16  mohor
83
// Link in the header changed.
84
//
85 37 mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
86
// eth_timescale.v changed to timescale.v This is done because of the
87
// simulation of the few cores in a one joined project.
88
//
89 22 mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
90
// Few little NCSIM warnings fixed.
91
//
92 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
93
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
94
// Include files fixed to contain no path.
95
// File names and module names changed ta have a eth_ prologue in the name.
96
// File eth_timescale.v is used to define timescale
97
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
98
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
99
// and Mdo_OE. The bidirectional signal must be created on the top level. This
100
// is done due to the ASIC tools.
101
//
102 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
103
// Directory structure changed. Files checked and joind together.
104
//
105
// Revision 1.1  2001/06/27 21:26:19  mohor
106
// Initial release of the RxEthMAC module.
107
//
108
//
109
//
110
//
111
//
112
 
113 22 mohor
`include "timescale.v"
114 15 mohor
 
115
 
116
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
117 65 mohor
                     RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
118
                     ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
119 261 mohor
                     MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
120 15 mohor
                    );
121
 
122
 
123
 
124
input         MRxClk;
125
input         MRxDV;
126
input   [3:0] MRxD;
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input         Transmitting;
128
input         HugEn;
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input         DlyCrcEn;
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input  [15:0] MaxFL;
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input         r_IFG;
132
input         Reset;
133 53 billditt
input  [47:0] MAC;     //  Station Address  
134
input         r_Bro;   //  broadcast disable
135
input         r_Pro;   //  promiscuous enable 
136
input [31:0]  r_HASH0; //  lower 4 bytes Hash Table
137
input [31:0]  r_HASH1; //  upper 4 bytes Hash Table
138 261 mohor
input         PassAll;
139
input         ControlFrmAddressOK;
140
 
141 15 mohor
output  [7:0] RxData;
142
output        RxValid;
143
output        RxStartFrm;
144
output        RxEndFrm;
145
output [15:0] ByteCnt;
146
output        ByteCntEq0;
147
output        ByteCntGreat2;
148
output        ByteCntMaxFrame;
149
output        CrcError;
150
output        StateIdle;
151
output        StatePreamble;
152
output        StateSFD;
153
output  [1:0] StateData;
154 53 billditt
output        RxAbort;
155 250 mohor
output        AddressMiss;
156 15 mohor
 
157
reg     [7:0] RxData;
158
reg           RxValid;
159
reg           RxStartFrm;
160
reg           RxEndFrm;
161
reg           Broadcast;
162
reg           Multicast;
163 321 igorm
reg     [5:0] CrcHash;
164 15 mohor
reg           CrcHashGood;
165
reg           DelayData;
166
reg     [7:0] LatchedByte;
167
reg     [7:0] RxData_d;
168
reg           RxValid_d;
169
reg           RxStartFrm_d;
170
reg           RxEndFrm_d;
171
 
172
wire          MRxDEqD;
173
wire          MRxDEq5;
174
wire          StateDrop;
175
wire          ByteCntEq1;
176 53 billditt
wire          ByteCntEq2;
177
wire          ByteCntEq3;
178
wire          ByteCntEq4;
179
wire          ByteCntEq5;
180 15 mohor
wire          ByteCntEq6;
181 53 billditt
wire          ByteCntEq7;
182 15 mohor
wire          ByteCntSmall7;
183
wire   [31:0] Crc;
184
wire          Enable_Crc;
185
wire          Initialize_Crc;
186
wire    [3:0] Data_Crc;
187
wire          GenerateRxValid;
188
wire          GenerateRxStartFrm;
189
wire          GenerateRxEndFrm;
190
wire          DribbleRxEndFrm;
191
wire    [3:0] DlyCrcCnt;
192 330 igorm
wire          IFGCounterEq24;
193 15 mohor
 
194
assign MRxDEqD = MRxD == 4'hd;
195
assign MRxDEq5 = MRxD == 4'h5;
196
 
197
 
198
// Rx State Machine module
199 352 olof
eth_rxstatem
200 349 olof
rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
201 15 mohor
                        .ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
202
                        .MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
203
                        .StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
204
                        .StateSFD(StateSFD), .StateDrop(StateDrop)
205
                       );
206
 
207
 
208
// Rx Counters module
209 352 olof
eth_rxcounters
210 349 olof
rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
211 15 mohor
                            .StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
212
                            .StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
213
                            .DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
214
                            .HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
215 58 mohor
                            .ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
216
                            .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
217
                            .ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
218 15 mohor
                            .ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
219 330 igorm
                            .ByteCntOut(ByteCnt)
220 15 mohor
                           );
221
 
222 53 billditt
// Rx Address Check
223 15 mohor
 
224 352 olof
eth_rxaddrcheck
225 349 olof
rxaddrcheck1
226 261 mohor
              (.MRxClk(MRxClk),         .Reset( Reset),             .RxData(RxData),
227
               .Broadcast (Broadcast),  .r_Bro (r_Bro),             .r_Pro(r_Pro),
228
               .ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7),    .ByteCntEq2(ByteCntEq2),
229
               .ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4),    .ByteCntEq5(ByteCntEq5),
230 341 olof
               .HASH0(r_HASH0),         .HASH1(r_HASH1),            .ByteCntEq0(ByteCntEq0),
231 321 igorm
               .CrcHash(CrcHash),       .CrcHashGood(CrcHashGood),  .StateData(StateData),
232 261 mohor
               .Multicast(Multicast),   .MAC(MAC),                  .RxAbort(RxAbort),
233
               .RxEndFrm(RxEndFrm),     .AddressMiss(AddressMiss),  .PassAll(PassAll),
234
               .ControlFrmAddressOK(ControlFrmAddressOK)
235 58 mohor
              );
236 15 mohor
 
237 53 billditt
 
238 15 mohor
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
239
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
240
 
241
assign Data_Crc[0] = MRxD[3];
242
assign Data_Crc[1] = MRxD[2];
243
assign Data_Crc[2] = MRxD[1];
244
assign Data_Crc[3] = MRxD[0];
245
 
246
 
247
// Connecting module Crc
248 352 olof
eth_crc
249 349 olof
crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
250 15 mohor
               .Crc(Crc), .CrcError(CrcError)
251 58 mohor
              );
252 15 mohor
 
253
 
254
 
255
// Latching CRC for use in the hash table
256
 
257
always @ (posedge MRxClk)
258
begin
259 352 olof
  CrcHashGood <=  StateData[0] & ByteCntEq6;
260 15 mohor
end
261
 
262
always @ (posedge MRxClk)
263
begin
264
  if(Reset | StateIdle)
265 352 olof
    CrcHash[5:0] <=  6'h0;
266 15 mohor
  else
267
  if(StateData[0] & ByteCntEq6)
268 352 olof
    CrcHash[5:0] <=  Crc[31:26];
269 15 mohor
end
270
 
271
 
272
// Output byte stream
273
always @ (posedge MRxClk or posedge Reset)
274
begin
275
  if(Reset)
276
    begin
277 352 olof
      RxData_d[7:0]      <=  8'h0;
278
      DelayData          <=  1'b0;
279
      LatchedByte[7:0]   <=  8'h0;
280
      RxData[7:0]        <=  8'h0;
281 15 mohor
    end
282
  else
283
    begin
284 352 olof
      LatchedByte[7:0]   <=  {MRxD[3:0], LatchedByte[7:4]};  // Latched byte
285
      DelayData          <=  StateData[0];
286 15 mohor
 
287
      if(GenerateRxValid)
288 352 olof
        RxData_d[7:0] <=  LatchedByte[7:0] & {8{|StateData}};  // Data goes through only in data state 
289 15 mohor
      else
290
      if(~DelayData)
291 352 olof
        RxData_d[7:0] <=  8'h0;                                // Delaying data to be valid for two cycles. Zero when not active.
292 15 mohor
 
293 352 olof
      RxData[7:0] <=  RxData_d[7:0];                           // Output data byte
294 15 mohor
    end
295
end
296
 
297
 
298
 
299
always @ (posedge MRxClk or posedge Reset)
300
begin
301
  if(Reset)
302 352 olof
    Broadcast <=  1'b0;
303 15 mohor
  else
304
    begin
305
      if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
306 352 olof
        Broadcast <=  1'b0;
307 15 mohor
      else
308 18 mohor
      if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
309 352 olof
        Broadcast <=  1'b1;
310 58 mohor
      else
311
      if(RxAbort | RxEndFrm)
312 352 olof
        Broadcast <=  1'b0;
313 15 mohor
    end
314
end
315
 
316
 
317
always @ (posedge MRxClk or posedge Reset)
318
begin
319
  if(Reset)
320 352 olof
    Multicast <=  1'b0;
321 15 mohor
  else
322
    begin
323 317 igorm
      if(StateData[0] & ByteCntEq1 & LatchedByte[0])
324 352 olof
        Multicast <=  1'b1;
325 317 igorm
      else if(RxAbort | RxEndFrm)
326 352 olof
      Multicast <=  1'b0;
327 15 mohor
    end
328
end
329
 
330
 
331
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
332
 
333
always @ (posedge MRxClk or posedge Reset)
334
begin
335
  if(Reset)
336
    begin
337 352 olof
      RxValid_d <=  1'b0;
338
      RxValid   <=  1'b0;
339 15 mohor
    end
340
  else
341
    begin
342 352 olof
      RxValid_d <=  GenerateRxValid;
343
      RxValid   <=  RxValid_d;
344 15 mohor
    end
345
end
346
 
347
 
348
assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
349
 
350
always @ (posedge MRxClk or posedge Reset)
351
begin
352
  if(Reset)
353
    begin
354 352 olof
      RxStartFrm_d <=  1'b0;
355
      RxStartFrm   <=  1'b0;
356 15 mohor
    end
357
  else
358
    begin
359 352 olof
      RxStartFrm_d <=  GenerateRxStartFrm;
360
      RxStartFrm   <=  RxStartFrm_d;
361 15 mohor
    end
362
end
363
 
364
 
365
assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
366
assign DribbleRxEndFrm  = StateData[1] &  ~MRxDV & ByteCntGreat2;
367
 
368
 
369
always @ (posedge MRxClk or posedge Reset)
370
begin
371
  if(Reset)
372
    begin
373 352 olof
      RxEndFrm_d <=  1'b0;
374
      RxEndFrm   <=  1'b0;
375 15 mohor
    end
376
  else
377
    begin
378 352 olof
      RxEndFrm_d <=  GenerateRxEndFrm;
379
      RxEndFrm   <=  RxEndFrm_d | DribbleRxEndFrm;
380 15 mohor
    end
381
end
382
 
383
 
384
endmodule

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