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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxethmac.v] - Blame information for rev 354

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  eth_rxethmac.v                                              ////
4
////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
6 354 olof
////  http://www.opencores.org/project,ethmac                     ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
11
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
12 341 olof
////      - Olof Kindgren (olof@opencores.org                     ////
13 15 mohor
////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
15
////  file.                                                       ////
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////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19 354 olof
//// Copyright (C) 2001, 2011 Authors                             ////
20 15 mohor
////                                                              ////
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//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
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////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44 341 olof
// 2011-07-06 Olof Kindgren <olof@opencores.org>
45
// Add ByteCntEq0 to rxaddrcheck
46
//
47 15 mohor
// CVS Revision History
48
//
49 341 olof
//
50 15 mohor
// $Log: not supported by cvs2svn $
51 330 igorm
// Revision 1.12  2004/04/26 15:26:23  igorm
52
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
53
//   previous update of the core.
54
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
55
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
56
//   register. (thanks to Mathias and Torbjorn)
57
// - Multicast reception was fixed. Thanks to Ulrich Gries
58
//
59 321 igorm
// Revision 1.11  2004/03/17 09:32:15  igorm
60
// Multicast detection fixed. Only the LSB of the first byte is checked.
61
//
62 317 igorm
// Revision 1.10  2002/11/22 01:57:06  mohor
63
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
64
// synchronized.
65
//
66 261 mohor
// Revision 1.9  2002/11/19 17:35:35  mohor
67
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
68
// that a frame was received because of the promiscous mode.
69
//
70 250 mohor
// Revision 1.8  2002/02/16 07:15:27  mohor
71
// Testbench fixed, code simplified, unused signals removed.
72
//
73 65 mohor
// Revision 1.7  2002/02/15 13:44:28  mohor
74
// RxAbort is an output. No need to have is declared as wire.
75
//
76 62 mohor
// Revision 1.6  2002/02/15 11:17:48  mohor
77
// File format changed.
78
//
79 58 mohor
// Revision 1.5  2002/02/14 20:48:43  billditt
80
// Addition  of new module eth_addrcheck.v
81
//
82 53 billditt
// Revision 1.4  2002/01/23 10:28:16  mohor
83
// Link in the header changed.
84
//
85 37 mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
86
// eth_timescale.v changed to timescale.v This is done because of the
87
// simulation of the few cores in a one joined project.
88
//
89 22 mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
90
// Few little NCSIM warnings fixed.
91
//
92 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
93
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
94
// Include files fixed to contain no path.
95
// File names and module names changed ta have a eth_ prologue in the name.
96
// File eth_timescale.v is used to define timescale
97
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
98
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
99
// and Mdo_OE. The bidirectional signal must be created on the top level. This
100
// is done due to the ASIC tools.
101
//
102 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
103
// Directory structure changed. Files checked and joind together.
104
//
105
// Revision 1.1  2001/06/27 21:26:19  mohor
106
// Initial release of the RxEthMAC module.
107
//
108
//
109
//
110
//
111
//
112
 
113 22 mohor
`include "timescale.v"
114 15 mohor
 
115
 
116 354 olof
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG,
117
                     HugEn, DlyCrcEn, RxData, RxValid, RxStartFrm, RxEndFrm,
118
                     ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,
119
                     CrcError, StateIdle, StatePreamble, StateSFD, StateData,
120
                     MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss,
121
                     PassAll, ControlFrmAddressOK
122 15 mohor
                    );
123
 
124
input         MRxClk;
125
input         MRxDV;
126
input   [3:0] MRxD;
127
input         Transmitting;
128
input         HugEn;
129
input         DlyCrcEn;
130
input  [15:0] MaxFL;
131
input         r_IFG;
132
input         Reset;
133 53 billditt
input  [47:0] MAC;     //  Station Address  
134
input         r_Bro;   //  broadcast disable
135
input         r_Pro;   //  promiscuous enable 
136
input [31:0]  r_HASH0; //  lower 4 bytes Hash Table
137
input [31:0]  r_HASH1; //  upper 4 bytes Hash Table
138 261 mohor
input         PassAll;
139
input         ControlFrmAddressOK;
140
 
141 15 mohor
output  [7:0] RxData;
142
output        RxValid;
143
output        RxStartFrm;
144
output        RxEndFrm;
145
output [15:0] ByteCnt;
146
output        ByteCntEq0;
147
output        ByteCntGreat2;
148
output        ByteCntMaxFrame;
149
output        CrcError;
150
output        StateIdle;
151
output        StatePreamble;
152
output        StateSFD;
153
output  [1:0] StateData;
154 53 billditt
output        RxAbort;
155 250 mohor
output        AddressMiss;
156 15 mohor
 
157
reg     [7:0] RxData;
158
reg           RxValid;
159
reg           RxStartFrm;
160
reg           RxEndFrm;
161
reg           Broadcast;
162
reg           Multicast;
163 321 igorm
reg     [5:0] CrcHash;
164 15 mohor
reg           CrcHashGood;
165
reg           DelayData;
166
reg     [7:0] LatchedByte;
167
reg     [7:0] RxData_d;
168
reg           RxValid_d;
169
reg           RxStartFrm_d;
170
reg           RxEndFrm_d;
171
 
172
wire          MRxDEqD;
173
wire          MRxDEq5;
174
wire          StateDrop;
175
wire          ByteCntEq1;
176 53 billditt
wire          ByteCntEq2;
177
wire          ByteCntEq3;
178
wire          ByteCntEq4;
179
wire          ByteCntEq5;
180 15 mohor
wire          ByteCntEq6;
181 53 billditt
wire          ByteCntEq7;
182 15 mohor
wire          ByteCntSmall7;
183
wire   [31:0] Crc;
184
wire          Enable_Crc;
185
wire          Initialize_Crc;
186
wire    [3:0] Data_Crc;
187
wire          GenerateRxValid;
188
wire          GenerateRxStartFrm;
189
wire          GenerateRxEndFrm;
190
wire          DribbleRxEndFrm;
191
wire    [3:0] DlyCrcCnt;
192 330 igorm
wire          IFGCounterEq24;
193 15 mohor
 
194
assign MRxDEqD = MRxD == 4'hd;
195
assign MRxDEq5 = MRxD == 4'h5;
196
 
197
 
198
// Rx State Machine module
199 354 olof
eth_rxstatem rxstatem1
200
  (.MRxClk(MRxClk),
201
   .Reset(Reset),
202
   .MRxDV(MRxDV),
203
   .ByteCntEq0(ByteCntEq0),
204
   .ByteCntGreat2(ByteCntGreat2),
205
   .Transmitting(Transmitting),
206
   .MRxDEq5(MRxDEq5),
207
   .MRxDEqD(MRxDEqD),
208
   .IFGCounterEq24(IFGCounterEq24),
209
   .ByteCntMaxFrame(ByteCntMaxFrame),
210
   .StateData(StateData),
211
   .StateIdle(StateIdle),
212
   .StatePreamble(StatePreamble),
213
   .StateSFD(StateSFD),
214
   .StateDrop(StateDrop)
215
   );
216 15 mohor
 
217
 
218
// Rx Counters module
219 354 olof
eth_rxcounters rxcounters1
220
  (.MRxClk(MRxClk),
221
   .Reset(Reset),
222
   .MRxDV(MRxDV),
223
   .StateIdle(StateIdle),
224
   .StateSFD(StateSFD),
225
   .StateData(StateData),
226
   .StateDrop(StateDrop),
227
   .StatePreamble(StatePreamble),
228
   .MRxDEqD(MRxDEqD),
229
   .DlyCrcEn(DlyCrcEn),
230
   .DlyCrcCnt(DlyCrcCnt),
231
   .Transmitting(Transmitting),
232
   .MaxFL(MaxFL),
233
   .r_IFG(r_IFG),
234
   .HugEn(HugEn),
235
   .IFGCounterEq24(IFGCounterEq24),
236
   .ByteCntEq0(ByteCntEq0),
237
   .ByteCntEq1(ByteCntEq1),
238
   .ByteCntEq2(ByteCntEq2),
239
   .ByteCntEq3(ByteCntEq3),
240
   .ByteCntEq4(ByteCntEq4),
241
   .ByteCntEq5(ByteCntEq5),
242
   .ByteCntEq6(ByteCntEq6),
243
   .ByteCntEq7(ByteCntEq7),
244
   .ByteCntGreat2(ByteCntGreat2),
245
   .ByteCntSmall7(ByteCntSmall7),
246
   .ByteCntMaxFrame(ByteCntMaxFrame),
247
   .ByteCntOut(ByteCnt)
248
   );
249 15 mohor
 
250 53 billditt
// Rx Address Check
251 15 mohor
 
252 354 olof
eth_rxaddrcheck rxaddrcheck1
253
  (.MRxClk(MRxClk),
254
   .Reset( Reset),
255
   .RxData(RxData),
256
   .Broadcast (Broadcast),
257
   .r_Bro (r_Bro),
258
   .r_Pro(r_Pro),
259
   .ByteCntEq6(ByteCntEq6),
260
   .ByteCntEq7(ByteCntEq7),
261
   .ByteCntEq2(ByteCntEq2),
262
   .ByteCntEq3(ByteCntEq3),
263
   .ByteCntEq4(ByteCntEq4),
264
   .ByteCntEq5(ByteCntEq5),
265
   .HASH0(r_HASH0),
266
   .HASH1(r_HASH1),
267
   .ByteCntEq0(ByteCntEq0),
268
   .CrcHash(CrcHash),
269
   .CrcHashGood(CrcHashGood),
270
   .StateData(StateData),
271
   .Multicast(Multicast),
272
   .MAC(MAC),
273
   .RxAbort(RxAbort),
274
   .RxEndFrm(RxEndFrm),
275
   .AddressMiss(AddressMiss),
276
   .PassAll(PassAll),
277
   .ControlFrmAddressOK(ControlFrmAddressOK)
278
   );
279 15 mohor
 
280 53 billditt
 
281 15 mohor
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
282 354 olof
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) &
283
                        DlyCrcCnt[3:0] < 4'h9;
284 15 mohor
 
285
assign Data_Crc[0] = MRxD[3];
286
assign Data_Crc[1] = MRxD[2];
287
assign Data_Crc[2] = MRxD[1];
288
assign Data_Crc[3] = MRxD[0];
289
 
290
 
291
// Connecting module Crc
292 354 olof
eth_crc crcrx
293
  (.Clk(MRxClk),
294
   .Reset(Reset),
295
   .Data(Data_Crc),
296
   .Enable(Enable_Crc),
297
   .Initialize(Initialize_Crc),
298
   .Crc(Crc),
299
   .CrcError(CrcError)
300
   );
301 15 mohor
 
302
 
303
// Latching CRC for use in the hash table
304
always @ (posedge MRxClk)
305
begin
306 352 olof
  CrcHashGood <=  StateData[0] & ByteCntEq6;
307 15 mohor
end
308
 
309
always @ (posedge MRxClk)
310
begin
311
  if(Reset | StateIdle)
312 352 olof
    CrcHash[5:0] <=  6'h0;
313 15 mohor
  else
314
  if(StateData[0] & ByteCntEq6)
315 352 olof
    CrcHash[5:0] <=  Crc[31:26];
316 15 mohor
end
317
 
318
// Output byte stream
319
always @ (posedge MRxClk or posedge Reset)
320
begin
321
  if(Reset)
322
    begin
323 352 olof
      RxData_d[7:0]      <=  8'h0;
324
      DelayData          <=  1'b0;
325
      LatchedByte[7:0]   <=  8'h0;
326
      RxData[7:0]        <=  8'h0;
327 15 mohor
    end
328
  else
329
    begin
330 354 olof
      // Latched byte
331
      LatchedByte[7:0]   <=  {MRxD[3:0], LatchedByte[7:4]};
332 352 olof
      DelayData          <=  StateData[0];
333 15 mohor
 
334
      if(GenerateRxValid)
335 354 olof
        // Data goes through only in data state 
336
        RxData_d[7:0] <=  LatchedByte[7:0] & {8{|StateData}};
337 15 mohor
      else
338
      if(~DelayData)
339 354 olof
        // Delaying data to be valid for two cycles.
340
        // Zero when not active.
341
        RxData_d[7:0] <=  8'h0;
342 15 mohor
 
343 354 olof
      RxData[7:0] <=  RxData_d[7:0];          // Output data byte
344 15 mohor
    end
345
end
346
 
347
 
348 354 olof
 
349 15 mohor
always @ (posedge MRxClk or posedge Reset)
350
begin
351
  if(Reset)
352 352 olof
    Broadcast <=  1'b0;
353 15 mohor
  else
354
    begin
355
      if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
356 352 olof
        Broadcast <=  1'b0;
357 15 mohor
      else
358 18 mohor
      if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
359 352 olof
        Broadcast <=  1'b1;
360 58 mohor
      else
361
      if(RxAbort | RxEndFrm)
362 352 olof
        Broadcast <=  1'b0;
363 15 mohor
    end
364
end
365
 
366
 
367
always @ (posedge MRxClk or posedge Reset)
368
begin
369
  if(Reset)
370 352 olof
    Multicast <=  1'b0;
371 15 mohor
  else
372
    begin
373 317 igorm
      if(StateData[0] & ByteCntEq1 & LatchedByte[0])
374 352 olof
        Multicast <=  1'b1;
375 317 igorm
      else if(RxAbort | RxEndFrm)
376 352 olof
      Multicast <=  1'b0;
377 15 mohor
    end
378
end
379
 
380
 
381
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
382
 
383
always @ (posedge MRxClk or posedge Reset)
384
begin
385
  if(Reset)
386
    begin
387 352 olof
      RxValid_d <=  1'b0;
388
      RxValid   <=  1'b0;
389 15 mohor
    end
390
  else
391
    begin
392 352 olof
      RxValid_d <=  GenerateRxValid;
393
      RxValid   <=  RxValid_d;
394 15 mohor
    end
395
end
396
 
397
 
398 354 olof
assign GenerateRxStartFrm = StateData[0] &
399
                            ((ByteCntEq1 & ~DlyCrcEn) |
400
                            ((DlyCrcCnt == 4'h3) & DlyCrcEn));
401 15 mohor
 
402
always @ (posedge MRxClk or posedge Reset)
403
begin
404
  if(Reset)
405
    begin
406 352 olof
      RxStartFrm_d <=  1'b0;
407
      RxStartFrm   <=  1'b0;
408 15 mohor
    end
409
  else
410
    begin
411 352 olof
      RxStartFrm_d <=  GenerateRxStartFrm;
412
      RxStartFrm   <=  RxStartFrm_d;
413 15 mohor
    end
414
end
415
 
416
 
417 354 olof
assign GenerateRxEndFrm = StateData[0] &
418
                          (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
419 15 mohor
assign DribbleRxEndFrm  = StateData[1] &  ~MRxDV & ByteCntGreat2;
420
 
421
 
422
always @ (posedge MRxClk or posedge Reset)
423
begin
424
  if(Reset)
425
    begin
426 352 olof
      RxEndFrm_d <=  1'b0;
427
      RxEndFrm   <=  1'b0;
428 15 mohor
    end
429
  else
430
    begin
431 352 olof
      RxEndFrm_d <=  GenerateRxEndFrm;
432
      RxEndFrm   <=  RxEndFrm_d | DribbleRxEndFrm;
433 15 mohor
    end
434
end
435
 
436
 
437
endmodule

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