OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxstatem.v] - Blame information for rev 21

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_rxstatem.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/cores/ethmac/                      ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
11
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
12
////                                                              ////
13
////  All additional information is avaliable in the Readme.txt   ////
14
////  file.                                                       ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2001 Authors                                   ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: not supported by cvs2svn $
46 21 mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
47
// Few little NCSIM warnings fixed.
48
//
49 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
50
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
51
// Include files fixed to contain no path.
52
// File names and module names changed ta have a eth_ prologue in the name.
53
// File eth_timescale.v is used to define timescale
54
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
55
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
56
// and Mdo_OE. The bidirectional signal must be created on the top level. This
57
// is done due to the ASIC tools.
58
//
59 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
60
// Directory structure changed. Files checked and joind together.
61
//
62
// Revision 1.2  2001/07/03 12:55:41  mohor
63
// Minor changes because of the synthesys warnings.
64
//
65
//
66
// Revision 1.1  2001/06/27 21:26:19  mohor
67
// Initial release of the RxEthMAC module.
68
//
69
//
70
//
71
//
72
 
73
 
74
`include "eth_timescale.v"
75
 
76
 
77
module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
78
                     IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,
79
                     StateDrop
80
                    );
81
 
82
parameter Tp = 1;
83
 
84
input         MRxClk;
85
input         Reset;
86
input         MRxDV;
87
input         ByteCntEq0;
88
input         ByteCntGreat2;
89
input         MRxDEq5;
90
input         Transmitting;
91
input         MRxDEqD;
92
input         IFGCounterEq24;
93
input         ByteCntMaxFrame;
94
 
95
output [1:0]  StateData;
96
output        StateIdle;
97
output        StateDrop;
98
output        StatePreamble;
99
output        StateSFD;
100
 
101
reg           StateData0;
102
reg           StateData1;
103
reg           StateIdle;
104
reg           StateDrop;
105
reg           StatePreamble;
106
reg           StateSFD;
107
 
108
wire          StartIdle;
109
wire          StartDrop;
110
wire          StartData0;
111
wire          StartData1;
112
wire          StartPreamble;
113
wire          StartSFD;
114
 
115
 
116
// Defining the next state
117 18 mohor
assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData) & (ByteCntEq0 | ByteCntGreat2));
118 15 mohor
 
119
assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
120
 
121 21 mohor
//assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting);
122
assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);
123 15 mohor
 
124
assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
125
 
126
assign StartData1 = MRxDV & StateData0;
127
 
128
assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 &  MRxDEqD
129
                         |  StateData0 &  ByteCntMaxFrame
130
                           );
131
 
132
// Rx State Machine
133
always @ (posedge MRxClk or posedge Reset)
134
begin
135
  if(Reset)
136
    begin
137
      StateIdle     <= #Tp 1'b0;
138
      StateDrop     <= #Tp 1'b1;
139
      StatePreamble <= #Tp 1'b0;
140
      StateSFD      <= #Tp 1'b0;
141
      StateData0    <= #Tp 1'b0;
142
      StateData1    <= #Tp 1'b0;
143
    end
144
  else
145
    begin
146
      if(StartPreamble | StartSFD | StartDrop)
147
        StateIdle <= #Tp 1'b0;
148
      else
149
      if(StartIdle)
150
        StateIdle <= #Tp 1'b1;
151
 
152
      if(StartIdle)
153
        StateDrop <= #Tp 1'b0;
154
      else
155
      if(StartDrop)
156
        StateDrop <= #Tp 1'b1;
157
 
158
      if(StartSFD | StartIdle | StartDrop)
159
        StatePreamble <= #Tp 1'b0;
160
      else
161
      if(StartPreamble)
162
        StatePreamble <= #Tp 1'b1;
163
 
164
      if(StartPreamble | StartIdle | StartData0 | StartDrop)
165
        StateSFD <= #Tp 1'b0;
166
      else
167
      if(StartSFD)
168
        StateSFD <= #Tp 1'b1;
169
 
170
      if(StartIdle | StartData1 | StartDrop)
171
        StateData0 <= #Tp 1'b0;
172
      else
173
      if(StartData0)
174
        StateData0 <= #Tp 1'b1;
175
 
176
      if(StartIdle | StartData0 | StartDrop)
177
        StateData1 <= #Tp 1'b0;
178
      else
179
      if(StartData1)
180
        StateData1 <= #Tp 1'b1;
181
    end
182
end
183
 
184
assign StateData[1:0] = {StateData1, StateData0};
185
 
186
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.