OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxstatem.v] - Blame information for rev 335

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_rxstatem.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
11
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
12
////                                                              ////
13
////  All additional information is avaliable in the Readme.txt   ////
14
////  file.                                                       ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2001 Authors                                   ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: not supported by cvs2svn $
46 241 tadejm
// Revision 1.5  2002/01/23 10:28:16  mohor
47
// Link in the header changed.
48
//
49 37 mohor
// Revision 1.4  2001/10/19 08:43:51  mohor
50
// eth_timescale.v changed to timescale.v This is done because of the
51
// simulation of the few cores in a one joined project.
52
//
53 22 mohor
// Revision 1.3  2001/10/18 12:07:11  mohor
54
// Status signals changed, Adress decoding changed, interrupt controller
55
// added.
56
//
57 21 mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
58
// Few little NCSIM warnings fixed.
59
//
60 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
61
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
62
// Include files fixed to contain no path.
63
// File names and module names changed ta have a eth_ prologue in the name.
64
// File eth_timescale.v is used to define timescale
65
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
66
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
67
// and Mdo_OE. The bidirectional signal must be created on the top level. This
68
// is done due to the ASIC tools.
69
//
70 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
71
// Directory structure changed. Files checked and joind together.
72
//
73
// Revision 1.2  2001/07/03 12:55:41  mohor
74
// Minor changes because of the synthesys warnings.
75
//
76
//
77
// Revision 1.1  2001/06/27 21:26:19  mohor
78
// Initial release of the RxEthMAC module.
79
//
80
//
81
//
82
//
83
 
84
 
85 22 mohor
`include "timescale.v"
86 15 mohor
 
87
 
88
module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
89
                     IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,
90
                     StateDrop
91
                    );
92
 
93
parameter Tp = 1;
94
 
95
input         MRxClk;
96
input         Reset;
97
input         MRxDV;
98
input         ByteCntEq0;
99
input         ByteCntGreat2;
100
input         MRxDEq5;
101
input         Transmitting;
102
input         MRxDEqD;
103
input         IFGCounterEq24;
104
input         ByteCntMaxFrame;
105
 
106
output [1:0]  StateData;
107
output        StateIdle;
108
output        StateDrop;
109
output        StatePreamble;
110
output        StateSFD;
111
 
112
reg           StateData0;
113
reg           StateData1;
114
reg           StateIdle;
115
reg           StateDrop;
116
reg           StatePreamble;
117
reg           StateSFD;
118
 
119
wire          StartIdle;
120
wire          StartDrop;
121
wire          StartData0;
122
wire          StartData1;
123
wire          StartPreamble;
124
wire          StartSFD;
125
 
126
 
127
// Defining the next state
128 241 tadejm
assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData));
129 15 mohor
 
130
assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
131
 
132 21 mohor
assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);
133 15 mohor
 
134
assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
135
 
136 241 tadejm
assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
137 15 mohor
 
138
assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 &  MRxDEqD
139
                         |  StateData0 &  ByteCntMaxFrame
140
                           );
141
 
142
// Rx State Machine
143
always @ (posedge MRxClk or posedge Reset)
144
begin
145
  if(Reset)
146
    begin
147
      StateIdle     <= #Tp 1'b0;
148
      StateDrop     <= #Tp 1'b1;
149
      StatePreamble <= #Tp 1'b0;
150
      StateSFD      <= #Tp 1'b0;
151
      StateData0    <= #Tp 1'b0;
152
      StateData1    <= #Tp 1'b0;
153
    end
154
  else
155
    begin
156
      if(StartPreamble | StartSFD | StartDrop)
157
        StateIdle <= #Tp 1'b0;
158
      else
159
      if(StartIdle)
160
        StateIdle <= #Tp 1'b1;
161
 
162
      if(StartIdle)
163
        StateDrop <= #Tp 1'b0;
164
      else
165
      if(StartDrop)
166
        StateDrop <= #Tp 1'b1;
167
 
168
      if(StartSFD | StartIdle | StartDrop)
169
        StatePreamble <= #Tp 1'b0;
170
      else
171
      if(StartPreamble)
172
        StatePreamble <= #Tp 1'b1;
173
 
174
      if(StartPreamble | StartIdle | StartData0 | StartDrop)
175
        StateSFD <= #Tp 1'b0;
176
      else
177
      if(StartSFD)
178
        StateSFD <= #Tp 1'b1;
179
 
180
      if(StartIdle | StartData1 | StartDrop)
181
        StateData0 <= #Tp 1'b0;
182
      else
183
      if(StartData0)
184
        StateData0 <= #Tp 1'b1;
185
 
186
      if(StartIdle | StartData0 | StartDrop)
187
        StateData1 <= #Tp 1'b0;
188
      else
189
      if(StartData1)
190
        StateData1 <= #Tp 1'b1;
191
    end
192
end
193
 
194
assign StateData[1:0] = {StateData1, StateData0};
195
 
196
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.