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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxstatem.v] - Blame information for rev 354

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_rxstatem.v                                              ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/project,ethmac                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
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////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.5  2002/01/23 10:28:16  mohor
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// Link in the header changed.
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//
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// Revision 1.4  2001/10/19 08:43:51  mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
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// Revision 1.3  2001/10/18 12:07:11  mohor
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// Status signals changed, Adress decoding changed, interrupt controller
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// added.
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//
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// Revision 1.2  2001/09/11 14:17:00  mohor
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// Few little NCSIM warnings fixed.
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//
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// Revision 1.1  2001/08/06 14:44:29  mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.1  2001/07/30 21:23:42  mohor
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// Directory structure changed. Files checked and joind together.
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//
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// Revision 1.2  2001/07/03 12:55:41  mohor
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// Minor changes because of the synthesys warnings.
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//
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//
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// Revision 1.1  2001/06/27 21:26:19  mohor
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// Initial release of the RxEthMAC module.
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//
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//
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//
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//
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`include "timescale.v"
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module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
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                     IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,
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                     StateDrop
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                    );
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input         MRxClk;
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input         Reset;
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input         MRxDV;
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input         ByteCntEq0;
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input         ByteCntGreat2;
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input         MRxDEq5;
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input         Transmitting;
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input         MRxDEqD;
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input         IFGCounterEq24;
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input         ByteCntMaxFrame;
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output [1:0]  StateData;
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output        StateIdle;
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output        StateDrop;
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output        StatePreamble;
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output        StateSFD;
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reg           StateData0;
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reg           StateData1;
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reg           StateIdle;
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reg           StateDrop;
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reg           StatePreamble;
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reg           StateSFD;
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wire          StartIdle;
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wire          StartDrop;
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wire          StartData0;
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wire          StartData1;
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wire          StartPreamble;
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wire          StartSFD;
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// Defining the next state
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assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData));
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assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
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assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);
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assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
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assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
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assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 &
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                   MRxDEqD |  StateData0 &  ByteCntMaxFrame);
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// Rx State Machine
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always @ (posedge MRxClk or posedge Reset)
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begin
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  if(Reset)
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    begin
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      StateIdle     <=  1'b0;
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      StateDrop     <=  1'b1;
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      StatePreamble <=  1'b0;
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      StateSFD      <=  1'b0;
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      StateData0    <=  1'b0;
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      StateData1    <=  1'b0;
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    end
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  else
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    begin
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      if(StartPreamble | StartSFD | StartDrop)
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        StateIdle <=  1'b0;
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      else
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      if(StartIdle)
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        StateIdle <=  1'b1;
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      if(StartIdle)
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        StateDrop <=  1'b0;
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      else
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      if(StartDrop)
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        StateDrop <=  1'b1;
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      if(StartSFD | StartIdle | StartDrop)
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        StatePreamble <=  1'b0;
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      else
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      if(StartPreamble)
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        StatePreamble <=  1'b1;
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      if(StartPreamble | StartIdle | StartData0 | StartDrop)
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        StateSFD <=  1'b0;
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      else
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      if(StartSFD)
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        StateSFD <=  1'b1;
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      if(StartIdle | StartData1 | StartDrop)
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        StateData0 <=  1'b0;
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      else
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      if(StartData0)
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        StateData0 <=  1'b1;
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      if(StartIdle | StartData0 | StartDrop)
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        StateData1 <=  1'b0;
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      else
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      if(StartData1)
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        StateData1 <=  1'b1;
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    end
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end
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assign StateData[1:0] = {StateData1, StateData0};
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endmodule

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