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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_spram_256x32.v                                          ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/project,ethmac                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is available in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001, 2002 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9  2003/12/05 12:43:06  tadejm
// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.
//
// Revision 1.8  2003/12/04 14:59:13  simons
// Lapsus fixed (!we -> ~we).
//
// Revision 1.7  2003/11/12 18:24:59  tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.6  2003/10/17 07:46:15  markom
// mbist signals updated according to newest convention
//
// Revision 1.5  2003/08/14 16:42:58  simons
// Artisan ram instance added.
//
// Revision 1.4  2002/10/18 17:04:20  tadejm
// Changed BIST scan signals.
//
// Revision 1.3  2002/10/10 16:29:30  mohor
// BIST added.
//
// Revision 1.2  2002/09/23 18:24:31  mohor
// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
//
// Revision 1.1  2002/07/23 16:36:09  mohor
// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
//
//
//
 
`include "ethmac_defines.v"
`include "timescale.v"
 
module eth_spram_256x32(
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
 
`ifdef ETH_BIST
  ,
  // debug chain signals
  mbist_si_i,       // bist scan serial in
  mbist_so_o,       // bist scan serial out
  mbist_ctrl_i        // bist chain shift control
`endif
 
 
 
);
 
   //
   // Generic synchronous single-port RAM interface
   //
   input           clk;  // Clock, rising edge
   input           rst;  // Reset, active high
   input           ce;   // Chip enable input, active high
   input  [3:0]    we;   // Write enable input, active high
   input           oe;   // Output enable input, active high
   input  [7:0]    addr; // address bus inputs
   input  [31:0]   di;   // input data bus
   output [31:0]   do;   // output data bus
 
`ifdef ETH_BIST
   input           mbist_si_i;       // bist scan serial in
   output          mbist_so_o;       // bist scan serial out
   input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
`endif
 
`ifdef ETH_XILINX_RAMB4
 
   /*RAMB4_S16 ram0
    (
    .DO      (do[15:0]),
    .ADDR    (addr),
    .DI      (di[15:0]),
    .EN      (ce),
    .CLK     (clk),
    .WE      (we),
    .RST     (rst)
    );
 
    RAMB4_S16 ram1
    (
    .DO      (do[31:16]),
    .ADDR    (addr),
    .DI      (di[31:16]),
    .EN      (ce),
    .CLK     (clk),
    .WE      (we),
    .RST     (rst)
    );*/
 
   RAMB4_S8 ram0
     (
      .DO      (do[7:0]),
      .ADDR    ({1'b0, addr}),
      .DI      (di[7:0]),
      .EN      (ce),
      .CLK     (clk),
      .WE      (we[0]),
      .RST     (rst)
      );
 
   RAMB4_S8 ram1
     (
      .DO      (do[15:8]),
      .ADDR    ({1'b0, addr}),
      .DI      (di[15:8]),
      .EN      (ce),
      .CLK     (clk),
      .WE      (we[1]),
      .RST     (rst)
      );
 
   RAMB4_S8 ram2
     (
      .DO      (do[23:16]),
      .ADDR    ({1'b0, addr}),
      .DI      (di[23:16]),
      .EN      (ce),
      .CLK     (clk),
      .WE      (we[2]),
      .RST     (rst)
      );
 
   RAMB4_S8 ram3
     (
      .DO      (do[31:24]),
      .ADDR    ({1'b0, addr}),
      .DI      (di[31:24]),
      .EN      (ce),
      .CLK     (clk),
      .WE      (we[3]),
      .RST     (rst)
      );
 
`else   // !ETH_XILINX_RAMB4
 `ifdef  ETH_VIRTUAL_SILICON_RAM
  `ifdef ETH_BIST
   //vs_hdsp_256x32_bist ram0_bist
   vs_hdsp_256x32_bw_bist ram0_bist
  `else
     //vs_hdsp_256x32 ram0
     vs_hdsp_256x32_bw ram0
  `endif
       (
        .CK         (clk),
        .CEN        (!ce),
        .WEN        (~we),
        .OEN        (!oe),
        .ADR        (addr),
        .DI         (di),
        .DOUT       (do)
 
  `ifdef ETH_BIST
        ,
        // debug chain signals
        .mbist_si_i       (mbist_si_i),
        .mbist_so_o       (mbist_so_o),
        .mbist_ctrl_i       (mbist_ctrl_i)
  `endif
       );
 
 `else   // !ETH_VIRTUAL_SILICON_RAM
 
  `ifdef  ETH_ARTISAN_RAM
   `ifdef ETH_BIST
   //art_hssp_256x32_bist ram0_bist
   art_hssp_256x32_bw_bist ram0_bist
   `else
     //art_hssp_256x32 ram0
     art_hssp_256x32_bw ram0
   `endif
       (
        .CLK        (clk),
        .CEN        (!ce),
        .WEN        (~we),
        .OEN        (!oe),
        .A          (addr),
        .D          (di),
        .Q          (do)
 
   `ifdef ETH_BIST
        ,
        // debug chain signals
        .mbist_si_i       (mbist_si_i),
        .mbist_so_o       (mbist_so_o),
        .mbist_ctrl_i     (mbist_ctrl_i)
   `endif
       );
 
  `else   // !ETH_ARTISAN_RAM
   `ifdef ETH_ALTERA_ALTSYNCRAM
 
   altera_spram_256x32  altera_spram_256x32_inst
     (
      .address        (addr),
      .wren           (ce & we),
      .clock          (clk),
      .data           (di),
      .q              (do)
      );  //exemplar attribute altera_spram_256x32_inst NOOPT TRUE
 
   `else   // !ETH_ALTERA_ALTSYNCRAM
 
 
   //
   // Generic single-port synchronous RAM model
   //
 
   //
   // Generic RAM's registers and wires
   //
   reg  [ 7: 0] mem0 [255:0]; // RAM content
   reg  [15: 8] mem1 [255:0]; // RAM content
   reg  [23:16] mem2 [255:0]; // RAM content
   reg  [31:24] mem3 [255:0]; // RAM content
   wire [31:0]  q;            // RAM output
   reg   [7:0]   raddr;        // RAM read address
   //
   // Data output drivers
   //
   assign do = (oe & ce) ? q : {32{1'bz}};
 
   //
   // RAM read and write
   //
 
   // read operation
   always@(posedge clk)
     if (ce)
       raddr <=  addr; // read address needs to be registered to read clock
 
   assign  q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
 
    // write operation
    always@(posedge clk)
    begin
                if (ce && we[3])
                  mem3[addr] <=  di[31:24];
                if (ce && we[2])
                  mem2[addr] <=  di[23:16];
                if (ce && we[1])
                  mem1[addr] <=  di[15: 8];
                if (ce && we[0])
                  mem0[addr] <=  di[ 7: 0];
             end
 
   // Task prints range of memory
   // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations. 
   task print_ram;
      input [7:0] start;
      input [7:0] finish;
      integer     rnum;
      begin
         for (rnum=start;rnum<=finish;rnum=rnum+1)
           $display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
      end
   endtask
 
   `endif  // !ETH_ALTERA_ALTSYNCRAM
  `endif  // !ETH_ARTISAN_RAM
 `endif  // !ETH_VIRTUAL_SILICON_RAM
`endif  // !ETH_XILINX_RAMB4
 
endmodule

Line No.	Rev	Author	Line
1	122	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_spram_256x32.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6	346	olof	`//// http://www.opencores.org/project,ethmac ////`
7	122	mohor	`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11	204	mohor	`//// All additional information is available in the Readme.txt ////`
12	122	mohor	`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001, 2002 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	330	igorm	`// Revision 1.9 2003/12/05 12:43:06 tadejm`
45			`// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.`
46			`//`
47	312	tadejm	`// Revision 1.8 2003/12/04 14:59:13 simons`
48			`// Lapsus fixed (!we -> ~we).`
49			`//`
50	306	simons	`// Revision 1.7 2003/11/12 18:24:59 tadejm`
51			`// WISHBONE slave changed and tested from only 32-bit accesss to byte access.`
52			`//`
53	304	tadejm	`// Revision 1.6 2003/10/17 07:46:15 markom`
54			`// mbist signals updated according to newest convention`
55			`//`
56	302	markom	`// Revision 1.5 2003/08/14 16:42:58 simons`
57			`// Artisan ram instance added.`
58			`//`
59	297	simons	`// Revision 1.4 2002/10/18 17:04:20 tadejm`
60			`// Changed BIST scan signals.`
61			`//`
62	227	tadejm	`// Revision 1.3 2002/10/10 16:29:30 mohor`
63			`// BIST added.`
64			`//`
65	210	mohor	`// Revision 1.2 2002/09/23 18:24:31 mohor`
66			`// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).`
67			`//`
68	204	mohor	`// Revision 1.1 2002/07/23 16:36:09 mohor`
69			`// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.`
70	122	mohor	`//`
71			`//`
72	204	mohor	`//`
73	122	mohor
74	356	olof	`include "ethmac_defines.v"
75	122	mohor	`include "timescale.v"
76
77			`module eth_spram_256x32(`
78			`// Generic synchronous single-port RAM interface`
79			`clk, rst, ce, we, oe, addr, di, do`
80	210	mohor
81			`ifdef ETH_BIST
82	227	tadejm	`,`
83			`// debug chain signals`
84	302	markom	`mbist_si_i, // bist scan serial in`
85			`mbist_so_o, // bist scan serial out`
86			`mbist_ctrl_i // bist chain shift control`
87	210	mohor	`endif
88
89
90
91	122	mohor	`);`
92
93	354	olof	`//`
94			`// Generic synchronous single-port RAM interface`
95			`//`
96			`input clk; // Clock, rising edge`
97			`input rst; // Reset, active high`
98			`input ce; // Chip enable input, active high`
99			`input [3:0] we; // Write enable input, active high`
100			`input oe; // Output enable input, active high`
101			`input [7:0] addr; // address bus inputs`
102			`input [31:0] di; // input data bus`
103			`output [31:0] do; // output data bus`
104	122	mohor
105	210	mohor	`ifdef ETH_BIST
106	354	olof	`input mbist_si_i; // bist scan serial in`
107			`output mbist_so_o; // bist scan serial out`
108			input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
109	210	mohor	`endif
110
111	122	mohor	`ifdef ETH_XILINX_RAMB4
112
113	354	olof	`/*RAMB4_S16 ram0`
114	122	mohor	`(`
115	354	olof	`.DO (do[15:0]),`
116			`.ADDR (addr),`
117			`.DI (di[15:0]),`
118			`.EN (ce),`
119			`.CLK (clk),`
120			`.WE (we),`
121			`.RST (rst)`
122	122	mohor	`);`
123
124			`RAMB4_S16 ram1`
125			`(`
126	354	olof	`.DO (do[31:16]),`
127			`.ADDR (addr),`
128			`.DI (di[31:16]),`
129			`.EN (ce),`
130			`.CLK (clk),`
131			`.WE (we),`
132			`.RST (rst)`
133	304	tadejm	`);*/`
134
135	354	olof	`RAMB4_S8 ram0`
136			`(`
137			`.DO (do[7:0]),`
138			`.ADDR ({1'b0, addr}),`
139			`.DI (di[7:0]),`
140			`.EN (ce),`
141			`.CLK (clk),`
142			`.WE (we[0]),`
143			`.RST (rst)`
144			`);`
145	122	mohor
146	354	olof	`RAMB4_S8 ram1`
147			`(`
148			`.DO (do[15:8]),`
149			`.ADDR ({1'b0, addr}),`
150			`.DI (di[15:8]),`
151			`.EN (ce),`
152			`.CLK (clk),`
153			`.WE (we[1]),`
154			`.RST (rst)`
155			`);`
156	304	tadejm
157	354	olof	`RAMB4_S8 ram2`
158			`(`
159			`.DO (do[23:16]),`
160			`.ADDR ({1'b0, addr}),`
161			`.DI (di[23:16]),`
162			`.EN (ce),`
163			`.CLK (clk),`
164			`.WE (we[2]),`
165			`.RST (rst)`
166			`);`
167	304	tadejm
168	354	olof	`RAMB4_S8 ram3`
169			`(`
170			`.DO (do[31:24]),`
171			`.ADDR ({1'b0, addr}),`
172			`.DI (di[31:24]),`
173			`.EN (ce),`
174			`.CLK (clk),`
175			`.WE (we[3]),`
176			`.RST (rst)`
177			`);`
178	304	tadejm
179	204	mohor	`else // !ETH_XILINX_RAMB4
180	354	olof	`ifdef ETH_VIRTUAL_SILICON_RAM
181	210	mohor	`ifdef ETH_BIST
182	354	olof	`//vs_hdsp_256x32_bist ram0_bist`
183			`vs_hdsp_256x32_bw_bist ram0_bist`
184	210	mohor	`else
185	354	olof	`//vs_hdsp_256x32 ram0`
186			`vs_hdsp_256x32_bw ram0`
187	210	mohor	`endif
188	354	olof	`(`
189	210	mohor	`.CK (clk),`
190			`.CEN (!ce),`
191	306	simons	`.WEN (~we),`
192	210	mohor	`.OEN (!oe),`
193			`.ADR (addr),`
194			`.DI (di),`
195			`.DOUT (do)`
196	122	mohor
197	354	olof	`ifdef ETH_BIST
198	210	mohor	`,`
199			`// debug chain signals`
200	302	markom	`.mbist_si_i (mbist_si_i),`
201			`.mbist_so_o (mbist_so_o),`
202			`.mbist_ctrl_i (mbist_ctrl_i)`
203	354	olof	`endif
204			`);`
205	210	mohor
206	354	olof	`else // !ETH_VIRTUAL_SILICON_RAM
207	204	mohor
208	354	olof	`ifdef ETH_ARTISAN_RAM
209			`ifdef ETH_BIST
210			`//art_hssp_256x32_bist ram0_bist`
211			`art_hssp_256x32_bw_bist ram0_bist`
212			`else
213			`//art_hssp_256x32 ram0`
214			`art_hssp_256x32_bw ram0`
215			`endif
216			`(`
217	297	simons	`.CLK (clk),`
218			`.CEN (!ce),`
219	306	simons	`.WEN (~we),`
220	297	simons	`.OEN (!oe),`
221			`.A (addr),`
222			`.D (di),`
223			`.Q (do)`
224
225	354	olof	`ifdef ETH_BIST
226	297	simons	`,`
227			`// debug chain signals`
228	302	markom	`.mbist_si_i (mbist_si_i),`
229			`.mbist_so_o (mbist_so_o),`
230	330	igorm	`.mbist_ctrl_i (mbist_ctrl_i)`
231	354	olof	`endif
232			`);`
233	297	simons
234	354	olof	`else // !ETH_ARTISAN_RAM
235			`ifdef ETH_ALTERA_ALTSYNCRAM
236	330	igorm
237	354	olof	`altera_spram_256x32 altera_spram_256x32_inst`
238			`(`
239			`.address (addr),`
240			`.wren (ce & we),`
241			`.clock (clk),`
242			`.data (di),`
243			`.q (do)`
244			`); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE`
245	330	igorm
246	354	olof	`else // !ETH_ALTERA_ALTSYNCRAM
247	330	igorm
248
249	354	olof	`//`
250			`// Generic single-port synchronous RAM model`
251			`//`
252	122	mohor
253	354	olof	`//`
254			`// Generic RAM's registers and wires`
255			`//`
256			`reg [ 7: 0] mem0 [255:0]; // RAM content`
257			`reg [15: 8] mem1 [255:0]; // RAM content`
258			`reg [23:16] mem2 [255:0]; // RAM content`
259			`reg [31:24] mem3 [255:0]; // RAM content`
260			`wire [31:0] q; // RAM output`
261			`reg [7:0] raddr; // RAM read address`
262			`//`
263			`// Data output drivers`
264			`//`
265			`assign do = (oe & ce) ? q : {32{1'bz}};`
266	122	mohor
267	354	olof	`//`
268			`// RAM read and write`
269			`//`
270	122	mohor
271	354	olof	`// read operation`
272			`always@(posedge clk)`
273			`if (ce)`
274			`raddr <= addr; // read address needs to be registered to read clock`
275	122	mohor
276	354	olof	`assign q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};`
277	122	mohor
278	354	olof	`// write operation`
279			`always@(posedge clk)`
280			`begin`
281	304	tadejm	`if (ce && we[3])`
282	352	olof	`mem3[addr] <= di[31:24];`
283	304	tadejm	`if (ce && we[2])`
284	352	olof	`mem2[addr] <= di[23:16];`
285	304	tadejm	`if (ce && we[1])`
286	352	olof	`mem1[addr] <= di[15: 8];`
287	304	tadejm	`if (ce && we[0])`
288	352	olof	`mem0[addr] <= di[ 7: 0];`
289			`end`
290	122	mohor
291	354	olof	`// Task prints range of memory`
292			`// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.`
293			`task print_ram;`
294			`input [7:0] start;`
295			`input [7:0] finish;`
296			`integer rnum;`
297			`begin`
298			`for (rnum=start;rnum<=finish;rnum=rnum+1)`
299			`$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);`
300			`end`
301			`endtask`
302	122	mohor
303	354	olof	`endif // !ETH_ALTERA_ALTSYNCRAM
304			`endif // !ETH_ARTISAN_RAM
305			`endif // !ETH_VIRTUAL_SILICON_RAM
306	204	mohor	`endif // !ETH_XILINX_RAMB4
307	122	mohor
308			`endmodule`

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Blame information for rev 356