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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_top.v] - Blame information for rev 366

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1 366 olof
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  ethmac.v                                                    ////
4
////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/project,ethmac                     ////
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////                                                              ////
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////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is available in the Readme.txt   ////
12
////  file.                                                       ////
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////                                                              ////
14
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001, 2002 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
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////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// 2011-08-09 olof@opencores.org
42
// Renamed from eth_top.v to ethmac.v to better fit into the OpenCores
43
// Structure
44
//
45
// CVS Revision History
46
//
47
// $Log: not supported by cvs2svn $
48
// Revision 1.51  2005/02/21 11:13:17  igorm
49
// Defer indication fixed.
50
//
51
// Revision 1.50  2004/04/26 15:26:23  igorm
52
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
53
//   previous update of the core.
54
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
55
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
56
//   register. (thanks to Mathias and Torbjorn)
57
// - Multicast reception was fixed. Thanks to Ulrich Gries
58
//
59
// Revision 1.49  2003/11/12 18:24:59  tadejm
60
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
61
//
62
// Revision 1.48  2003/10/17 07:46:16  markom
63
// mbist signals updated according to newest convention
64
//
65
// Revision 1.47  2003/10/06 15:43:45  knguyen
66
// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
67
//
68
// Revision 1.46  2003/01/30 13:30:22  tadejm
69
// Defer indication changed.
70
//
71
// Revision 1.45  2003/01/22 13:49:26  tadejm
72
// When control packets were received, they were ignored in some cases.
73
//
74
// Revision 1.44  2003/01/21 12:09:40  mohor
75
// When receiving normal data frame and RxFlow control was switched on, RXB
76
// interrupt was not set.
77
//
78
// Revision 1.43  2002/11/22 01:57:06  mohor
79
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
80
// synchronized.
81
//
82
// Revision 1.42  2002/11/21 00:09:19  mohor
83
// TPauseRq synchronized to tx_clk.
84
//
85
// Revision 1.41  2002/11/19 18:13:49  mohor
86
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
87
//
88
// Revision 1.40  2002/11/19 17:34:25  mohor
89
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
90
// that a frame was received because of the promiscous mode.
91
//
92
// Revision 1.39  2002/11/18 17:31:55  mohor
93
// wb_rst_i is used for MIIM reset.
94
//
95
// Revision 1.38  2002/11/14 18:37:20  mohor
96
// r_Rst signal does not reset any module any more and is removed from the design.
97
//
98
// Revision 1.37  2002/11/13 22:25:36  tadejm
99
// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
100
//
101
// Revision 1.36  2002/10/18 17:04:20  tadejm
102
// Changed BIST scan signals.
103
//
104
// Revision 1.35  2002/10/11 13:36:58  mohor
105
// Typo error fixed. (When using Bist)
106
//
107
// Revision 1.34  2002/10/10 16:49:50  mohor
108
// Signals for WISHBONE B3 compliant interface added.
109
//
110
// Revision 1.33  2002/10/10 16:29:30  mohor
111
// BIST added.
112
//
113
// Revision 1.32  2002/09/20 17:12:58  mohor
114
// CsMiss added. When address between 0x800 and 0xfff is accessed within
115
// Ethernet Core, error acknowledge is generated.
116
//
117
// Revision 1.31  2002/09/12 14:50:17  mohor
118
// CarrierSenseLost bug fixed when operating in full duplex mode.
119
//
120
// Revision 1.30  2002/09/10 10:35:23  mohor
121
// Ethernet debug registers removed.
122
//
123
// Revision 1.29  2002/09/09 13:03:13  mohor
124
// Error acknowledge is generated when accessing BDs and RST bit in the
125
// MODER register (r_Rst) is set.
126
//
127
// Revision 1.28  2002/09/04 18:44:10  mohor
128
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
129
// connected.
130
//
131
// Revision 1.27  2002/07/25 18:15:37  mohor
132
// RxAbort changed. Packets received with MRxErr (from PHY) are also
133
// aborted.
134
//
135
// Revision 1.26  2002/07/17 18:51:50  mohor
136
// EXTERNAL_DMA removed. External DMA not supported.
137
//
138
// Revision 1.25  2002/05/03 10:15:50  mohor
139
// Outputs registered. Reset changed for eth_wishbone module.
140
//
141
// Revision 1.24  2002/04/22 14:15:42  mohor
142
// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
143
// selected in eth_defines.v
144
//
145
// Revision 1.23  2002/03/25 13:33:53  mohor
146
// md_padoen_o changed to md_padoe_o. Signal was always active high, just
147
// name was incorrect.
148
//
149
// Revision 1.22  2002/02/26 16:59:54  mohor
150
// Small fixes for external/internal DMA missmatches.
151
//
152
// Revision 1.21  2002/02/26 16:21:00  mohor
153
// Interrupts changed in the top file
154
//
155
// Revision 1.20  2002/02/18 10:40:17  mohor
156
// Small fixes.
157
//
158
// Revision 1.19  2002/02/16 14:03:44  mohor
159
// Registered trimmed. Unused registers removed.
160
//
161
// Revision 1.18  2002/02/16 13:06:33  mohor
162
// EXTERNAL_DMA used instead of WISHBONE_DMA.
163
//
164
// Revision 1.17  2002/02/16 07:15:27  mohor
165
// Testbench fixed, code simplified, unused signals removed.
166
//
167
// Revision 1.16  2002/02/15 13:49:39  mohor
168
// RxAbort is connected differently.
169
//
170
// Revision 1.15  2002/02/15 11:38:26  mohor
171
// Changes that were lost when updating from 1.11 to 1.14 fixed.
172
//
173
// Revision 1.14  2002/02/14 20:19:11  billditt
174
// Modified for Address Checking,
175
// addition of eth_addrcheck.v
176
//
177
// Revision 1.13  2002/02/12 17:03:03  mohor
178
// HASH0 and HASH1 registers added. Registers address width was
179
// changed to 8 bits.
180
//
181
// Revision 1.12  2002/02/11 09:18:22  mohor
182
// Tx status is written back to the BD.
183
//
184
// Revision 1.11  2002/02/08 16:21:54  mohor
185
// Rx status is written back to the BD.
186
//
187
// Revision 1.10  2002/02/06 14:10:21  mohor
188
// non-DMA host interface added. Select the right configutation in eth_defines.
189
//
190
// Revision 1.9  2002/01/23 10:28:16  mohor
191
// Link in the header changed.
192
//
193
// Revision 1.8  2001/12/05 15:00:16  mohor
194
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
195
// instead of the number of RX descriptors).
196
//
197
// Revision 1.7  2001/12/05 10:45:59  mohor
198
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
199
//
200
// Revision 1.6  2001/10/19 11:24:29  mohor
201
// Number of addresses (wb_adr_i) minimized.
202
//
203
// Revision 1.5  2001/10/19 08:43:51  mohor
204
// eth_timescale.v changed to timescale.v This is done because of the
205
// simulation of the few cores in a one joined project.
206
//
207
// Revision 1.4  2001/10/18 12:07:11  mohor
208
// Status signals changed, Adress decoding changed, interrupt controller
209
// added.
210
//
211
// Revision 1.3  2001/09/24 15:02:56  mohor
212
// Defines changed (All precede with ETH_). Small changes because some
213
// tools generate warnings when two operands are together. Synchronization
214
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
215
// demands).
216
//
217
// Revision 1.2  2001/08/15 14:03:59  mohor
218
// Signal names changed on the top level for easier pad insertion (ASIC).
219
//
220
// Revision 1.1  2001/08/06 14:44:29  mohor
221
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
222
// Include files fixed to contain no path.
223
// File names and module names changed ta have a eth_ prologue in the name.
224
// File eth_timescale.v is used to define timescale
225
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
226
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
227
// and Mdo_OE. The bidirectional signal must be created on the top level. This
228
// is done due to the ASIC tools.
229
//
230
// Revision 1.2  2001/08/02 09:25:31  mohor
231
// Unconnected signals are now connected.
232
//
233
// Revision 1.1  2001/07/30 21:23:42  mohor
234
// Directory structure changed. Files checked and joind together.
235
//
236
//
237
//
238
// 
239
 
240
 
241
`include "ethmac_defines.v"
242
`include "timescale.v"
243
 
244
 
245
module eth_top
246
(
247
  // WISHBONE common
248
  wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
249
 
250
  // WISHBONE slave
251
  wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
252
 
253
  // WISHBONE master
254
  m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
255
  m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
256
  m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
257
 
258
`ifdef ETH_WISHBONE_B3
259
  m_wb_cti_o, m_wb_bte_o,
260
`endif
261
 
262
  //TX
263
  mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
264
 
265
  //RX
266
  mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
267
 
268
  // MIIM
269
  mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
270
 
271
  int_o
272
 
273
  // Bist
274
`ifdef ETH_BIST
275
  ,
276
  // debug chain signals
277
  mbist_si_i,       // bist scan serial in
278
  mbist_so_o,       // bist scan serial out
279
  mbist_ctrl_i        // bist chain shift control
280
`endif
281
 
282
);
283
 
284
 
285
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
286
parameter TX_FIFO_DEPTH      = `ETH_TX_FIFO_DEPTH;
287
parameter TX_FIFO_CNT_WIDTH  = `ETH_TX_FIFO_CNT_WIDTH;
288
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
289
parameter RX_FIFO_DEPTH      = `ETH_RX_FIFO_DEPTH;
290
parameter RX_FIFO_CNT_WIDTH  = `ETH_RX_FIFO_CNT_WIDTH;
291
 
292
 
293
// WISHBONE common
294
input           wb_clk_i;     // WISHBONE clock
295
input           wb_rst_i;     // WISHBONE reset
296
input   [31:0]  wb_dat_i;     // WISHBONE data input
297
output  [31:0]  wb_dat_o;     // WISHBONE data output
298
output          wb_err_o;     // WISHBONE error output
299
 
300
// WISHBONE slave
301
input   [11:2]  wb_adr_i;     // WISHBONE address input
302
input    [3:0]  wb_sel_i;     // WISHBONE byte select input
303
input           wb_we_i;      // WISHBONE write enable input
304
input           wb_cyc_i;     // WISHBONE cycle input
305
input           wb_stb_i;     // WISHBONE strobe input
306
output          wb_ack_o;     // WISHBONE acknowledge output
307
 
308
// WISHBONE master
309
output  [31:0]  m_wb_adr_o;
310
output   [3:0]  m_wb_sel_o;
311
output          m_wb_we_o;
312
input   [31:0]  m_wb_dat_i;
313
output  [31:0]  m_wb_dat_o;
314
output          m_wb_cyc_o;
315
output          m_wb_stb_o;
316
input           m_wb_ack_i;
317
input           m_wb_err_i;
318
 
319
wire    [29:0]  m_wb_adr_tmp;
320
 
321
`ifdef ETH_WISHBONE_B3
322
output   [2:0]  m_wb_cti_o;   // Cycle Type Identifier
323
output   [1:0]  m_wb_bte_o;   // Burst Type Extension
324
`endif
325
 
326
// Tx
327
input           mtx_clk_pad_i; // Transmit clock (from PHY)
328
output   [3:0]  mtxd_pad_o;    // Transmit nibble (to PHY)
329
output          mtxen_pad_o;   // Transmit enable (to PHY)
330
output          mtxerr_pad_o;  // Transmit error (to PHY)
331
 
332
// Rx
333
input           mrx_clk_pad_i; // Receive clock (from PHY)
334
input    [3:0]  mrxd_pad_i;    // Receive nibble (from PHY)
335
input           mrxdv_pad_i;   // Receive data valid (from PHY)
336
input           mrxerr_pad_i;  // Receive data error (from PHY)
337
 
338
// Common Tx and Rx
339
input           mcoll_pad_i;   // Collision (from PHY)
340
input           mcrs_pad_i;    // Carrier sense (from PHY)
341
 
342
// MII Management interface
343
input           md_pad_i;      // MII data input (from I/O cell)
344
output          mdc_pad_o;     // MII Management data clock (to PHY)
345
output          md_pad_o;      // MII data output (to I/O cell)
346
output          md_padoe_o;    // MII data output enable (to I/O cell)
347
 
348
output          int_o;         // Interrupt output
349
 
350
// Bist
351
`ifdef ETH_BIST
352
input   mbist_si_i;       // bist scan serial in
353
output  mbist_so_o;       // bist scan serial out
354
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
355
`endif
356
 
357
wire    [31:0]  wb_dbg_dat0;
358
 
359
wire     [7:0]  r_ClkDiv;
360
wire            r_MiiNoPre;
361
wire    [15:0]  r_CtrlData;
362
wire     [4:0]  r_FIAD;
363
wire     [4:0]  r_RGAD;
364
wire            r_WCtrlData;
365
wire            r_RStat;
366
wire            r_ScanStat;
367
wire            NValid_stat;
368
wire            Busy_stat;
369
wire            LinkFail;
370
wire    [15:0]  Prsd;             // Read Status Data (data read from the PHY)
371
wire            WCtrlDataStart;
372
wire            RStatStart;
373
wire            UpdateMIIRX_DATAReg;
374
 
375
wire            TxStartFrm;
376
wire            TxEndFrm;
377
wire            TxUsedData;
378
wire     [7:0]  TxData;
379
wire            TxRetry;
380
wire            TxAbort;
381
wire            TxUnderRun;
382
wire            TxDone;
383
 
384
 
385
reg             WillSendControlFrame_sync1;
386
reg             WillSendControlFrame_sync2;
387
reg             WillSendControlFrame_sync3;
388
reg             RstTxPauseRq;
389
 
390
reg             TxPauseRq_sync1;
391
reg             TxPauseRq_sync2;
392
reg             TxPauseRq_sync3;
393
reg             TPauseRq;
394
 
395
initial
396
begin
397
  $display("          *********************************************");
398
  $display("          =============================================");
399
  $display("          eth_top.v will be removed shortly.");
400
  $display("          Please use ethmac.v as top level file instead");
401
  $display("          =============================================");
402
  $display("          *********************************************");
403
end
404
// Connecting Miim module
405
eth_miim miim1
406
(
407
  .Clk(wb_clk_i),
408
  .Reset(wb_rst_i),
409
  .Divider(r_ClkDiv),
410
  .NoPre(r_MiiNoPre),
411
  .CtrlData(r_CtrlData),
412
  .Rgad(r_RGAD),
413
  .Fiad(r_FIAD),
414
  .WCtrlData(r_WCtrlData),
415
  .RStat(r_RStat),
416
  .ScanStat(r_ScanStat),
417
  .Mdi(md_pad_i),
418
  .Mdo(md_pad_o),
419
  .MdoEn(md_padoe_o),
420
  .Mdc(mdc_pad_o),
421
  .Busy(Busy_stat),
422
  .Prsd(Prsd),
423
  .LinkFail(LinkFail),
424
  .Nvalid(NValid_stat),
425
  .WCtrlDataStart(WCtrlDataStart),
426
  .RStatStart(RStatStart),
427
  .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
428
);
429
 
430
 
431
 
432
 
433
wire  [3:0] RegCs;          // Connected to registers
434
wire [31:0] RegDataOut;     // Multiplexed to wb_dat_o
435
wire        r_RecSmall;     // Receive small frames
436
wire        r_LoopBck;      // Loopback
437
wire        r_TxEn;         // Tx Enable
438
wire        r_RxEn;         // Rx Enable
439
 
440
wire        MRxDV_Lb;       // Muxed MII receive data valid
441
wire        MRxErr_Lb;      // Muxed MII Receive Error
442
wire  [3:0] MRxD_Lb;        // Muxed MII Receive Data
443
wire        Transmitting;   // Indication that TxEthMAC is transmitting
444
wire        r_HugEn;        // Huge packet enable
445
wire        r_DlyCrcEn;     // Delayed CRC enabled
446
wire [15:0] r_MaxFL;        // Maximum frame length
447
 
448
wire [15:0] r_MinFL;        // Minimum frame length
449
wire        ShortFrame;
450
wire        DribbleNibble;  // Extra nibble received
451
wire        ReceivedPacketTooBig; // Received packet is too big
452
wire [47:0] r_MAC;          // MAC address
453
wire        LoadRxStatus;   // Rx status was loaded
454
wire [31:0] r_HASH0;        // HASH table, lower 4 bytes
455
wire [31:0] r_HASH1;        // HASH table, upper 4 bytes
456
wire  [7:0] r_TxBDNum;      // Receive buffer descriptor number
457
wire  [6:0] r_IPGT;         // 
458
wire  [6:0] r_IPGR1;        // 
459
wire  [6:0] r_IPGR2;        // 
460
wire  [5:0] r_CollValid;    // 
461
wire [15:0] r_TxPauseTV;    // Transmit PAUSE value
462
wire        r_TxPauseRq;    // Transmit PAUSE request
463
 
464
wire  [3:0] r_MaxRet;       //
465
wire        r_NoBckof;      // 
466
wire        r_ExDfrEn;      // 
467
wire        r_TxFlow;       // Tx flow control enable
468
wire        r_IFG;          // Minimum interframe gap for incoming packets
469
 
470
wire        TxB_IRQ;        // Interrupt Tx Buffer
471
wire        TxE_IRQ;        // Interrupt Tx Error
472
wire        RxB_IRQ;        // Interrupt Rx Buffer
473
wire        RxE_IRQ;        // Interrupt Rx Error
474
wire        Busy_IRQ;       // Interrupt Busy (lack of buffers)
475
 
476
//wire        DWord;
477
wire        ByteSelected;
478
wire        BDAck;
479
wire [31:0] BD_WB_DAT_O;    // wb_dat_o that comes from the Wishbone module
480
                            //(for buffer descriptors read/write)
481
wire  [3:0] BDCs;           // Buffer descriptor CS
482
wire        CsMiss;         // When access to the address between 0x800
483
                            // and 0xfff occurs, acknowledge is set
484
                            // but data is not valid.
485
wire        r_Pad;
486
wire        r_CrcEn;
487
wire        r_FullD;
488
wire        r_Pro;
489
wire        r_Bro;
490
wire        r_NoPre;
491
wire        r_RxFlow;
492
wire        r_PassAll;
493
wire        TxCtrlEndFrm;
494
wire        StartTxDone;
495
wire        SetPauseTimer;
496
wire        TxUsedDataIn;
497
wire        TxDoneIn;
498
wire        TxAbortIn;
499
wire        PerPacketPad;
500
wire        PadOut;
501
wire        PerPacketCrcEn;
502
wire        CrcEnOut;
503
wire        TxStartFrmOut;
504
wire        TxEndFrmOut;
505
wire        ReceivedPauseFrm;
506
wire        ControlFrmAddressOK;
507
wire        RxStatusWriteLatched_sync2;
508
wire        LateCollision;
509
wire        DeferIndication;
510
wire        LateCollLatched;
511
wire        DeferLatched;
512
wire        RstDeferLatched;
513
wire        CarrierSenseLost;
514
 
515
wire        temp_wb_ack_o;
516
wire [31:0] temp_wb_dat_o;
517
wire        temp_wb_err_o;
518
 
519
`ifdef ETH_REGISTERED_OUTPUTS
520
  reg         temp_wb_ack_o_reg;
521
  reg [31:0]  temp_wb_dat_o_reg;
522
  reg         temp_wb_err_o_reg;
523
`endif
524
 
525
//assign DWord = &wb_sel_i;
526
assign ByteSelected = |wb_sel_i;
527
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3];   // 0x0   - 0x3FF
528
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2];   // 0x0   - 0x3FF
529
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1];   // 0x0   - 0x3FF
530
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0];   // 0x0   - 0x3FF
531
assign BDCs[3]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[3];   // 0x400 - 0x7FF
532
assign BDCs[2]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[2];   // 0x400 - 0x7FF
533
assign BDCs[1]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[1];   // 0x400 - 0x7FF
534
assign BDCs[0]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[0];   // 0x400 - 0x7FF
535
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11];                   // 0x800 - 0xfFF
536
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
537
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
538
 
539
`ifdef ETH_REGISTERED_OUTPUTS
540
  assign wb_ack_o = temp_wb_ack_o_reg;
541
  assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
542
  assign wb_err_o = temp_wb_err_o_reg;
543
`else
544
  assign wb_ack_o = temp_wb_ack_o;
545
  assign wb_dat_o[31:0] = temp_wb_dat_o;
546
  assign wb_err_o = temp_wb_err_o;
547
`endif
548
 
549
`ifdef ETH_AVALON_BUS
550
  // As Avalon has no corresponding "error" signal, I (erroneously) will
551
  // send an ack to Avalon, even when accessing undefined memory. This
552
  // is a grey area in Avalon vs. Wishbone specs: My understanding
553
  // is that Avalon expects all memory addressable by the addr bus feeding
554
  // a slave to be, at the very minimum, readable.
555
  assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
556
`else // WISHBONE
557
  assign temp_wb_ack_o = (|RegCs) | BDAck;
558
`endif
559
 
560
`ifdef ETH_REGISTERED_OUTPUTS
561
  always @ (posedge wb_clk_i or posedge wb_rst_i)
562
  begin
563
    if(wb_rst_i)
564
      begin
565
        temp_wb_ack_o_reg <= 1'b0;
566
        temp_wb_dat_o_reg <= 32'h0;
567
        temp_wb_err_o_reg <= 1'b0;
568
      end
569
    else
570
      begin
571
        temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg;
572
        temp_wb_dat_o_reg <= temp_wb_dat_o;
573
        temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg;
574
      end
575
  end
576
`endif
577
 
578
 
579
// Connecting Ethernet registers
580
eth_registers ethreg1
581
(
582
  .DataIn(wb_dat_i),
583
  .Address(wb_adr_i[9:2]),
584
  .Rw(wb_we_i),
585
  .Cs(RegCs),
586
  .Clk(wb_clk_i),
587
  .Reset(wb_rst_i),
588
  .DataOut(RegDataOut),
589
  .r_RecSmall(r_RecSmall),
590
  .r_Pad(r_Pad),
591
  .r_HugEn(r_HugEn),
592
  .r_CrcEn(r_CrcEn),
593
  .r_DlyCrcEn(r_DlyCrcEn),
594
  .r_FullD(r_FullD),
595
  .r_ExDfrEn(r_ExDfrEn),
596
  .r_NoBckof(r_NoBckof),
597
  .r_LoopBck(r_LoopBck),
598
  .r_IFG(r_IFG),
599
  .r_Pro(r_Pro),
600
  .r_Iam(),
601
  .r_Bro(r_Bro),
602
  .r_NoPre(r_NoPre),
603
  .r_TxEn(r_TxEn),
604
  .r_RxEn(r_RxEn),
605
  .Busy_IRQ(Busy_IRQ),
606
  .RxE_IRQ(RxE_IRQ),
607
  .RxB_IRQ(RxB_IRQ),
608
  .TxE_IRQ(TxE_IRQ),
609
  .TxB_IRQ(TxB_IRQ),
610
  .r_IPGT(r_IPGT),
611
  .r_IPGR1(r_IPGR1),
612
  .r_IPGR2(r_IPGR2),
613
  .r_MinFL(r_MinFL),
614
  .r_MaxFL(r_MaxFL),
615
  .r_MaxRet(r_MaxRet),
616
  .r_CollValid(r_CollValid),
617
  .r_TxFlow(r_TxFlow),
618
  .r_RxFlow(r_RxFlow),
619
  .r_PassAll(r_PassAll),
620
  .r_MiiNoPre(r_MiiNoPre),
621
  .r_ClkDiv(r_ClkDiv),
622
  .r_WCtrlData(r_WCtrlData),
623
  .r_RStat(r_RStat),
624
  .r_ScanStat(r_ScanStat),
625
  .r_RGAD(r_RGAD),
626
  .r_FIAD(r_FIAD),
627
  .r_CtrlData(r_CtrlData),
628
  .NValid_stat(NValid_stat),
629
  .Busy_stat(Busy_stat),
630
  .LinkFail(LinkFail),
631
  .r_MAC(r_MAC),
632
  .WCtrlDataStart(WCtrlDataStart),
633
  .RStatStart(RStatStart),
634
  .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),
635
  .Prsd(Prsd),
636
  .r_TxBDNum(r_TxBDNum),
637
  .int_o(int_o),
638
  .r_HASH0(r_HASH0),
639
  .r_HASH1(r_HASH1),
640
  .r_TxPauseRq(r_TxPauseRq),
641
  .r_TxPauseTV(r_TxPauseTV),
642
  .RstTxPauseRq(RstTxPauseRq),
643
  .TxCtrlEndFrm(TxCtrlEndFrm),
644
  .StartTxDone(StartTxDone),
645
  .TxClk(mtx_clk_pad_i),
646
  .RxClk(mrx_clk_pad_i),
647
  .dbg_dat(wb_dbg_dat0),
648
  .SetPauseTimer(SetPauseTimer)
649
 
650
);
651
 
652
 
653
 
654
wire  [7:0] RxData;
655
wire        RxValid;
656
wire        RxStartFrm;
657
wire        RxEndFrm;
658
wire        RxAbort;
659
 
660
wire        WillTransmit;            // Will transmit (to RxEthMAC)
661
wire        ResetCollision;          // Reset Collision (for synchronizing 
662
                                     // collision)
663
wire  [7:0] TxDataOut;               // Transmit Packet Data (to TxEthMAC)
664
wire        WillSendControlFrame;
665
wire        ReceiveEnd;
666
wire        ReceivedPacketGood;
667
wire        ReceivedLengthOK;
668
wire        InvalidSymbol;
669
wire        LatchedCrcError;
670
wire        RxLateCollision;
671
wire  [3:0] RetryCntLatched;
672
wire  [3:0] RetryCnt;
673
wire        StartTxAbort;
674
wire        MaxCollisionOccured;
675
wire        RetryLimit;
676
wire        StatePreamble;
677
wire  [1:0] StateData;
678
 
679
// Connecting MACControl
680
eth_maccontrol maccontrol1
681
(
682
  .MTxClk(mtx_clk_pad_i),
683
  .TPauseRq(TPauseRq),
684
  .TxPauseTV(r_TxPauseTV),
685
  .TxDataIn(TxData),
686
  .TxStartFrmIn(TxStartFrm),
687
  .TxEndFrmIn(TxEndFrm),
688
  .TxUsedDataIn(TxUsedDataIn),
689
  .TxDoneIn(TxDoneIn),
690
  .TxAbortIn(TxAbortIn),
691
  .MRxClk(mrx_clk_pad_i),
692
  .RxData(RxData),
693
  .RxValid(RxValid),
694
  .RxStartFrm(RxStartFrm),
695
  .RxEndFrm(RxEndFrm),
696
  .ReceiveEnd(ReceiveEnd),
697
  .ReceivedPacketGood(ReceivedPacketGood),
698
  .TxFlow(r_TxFlow),
699
  .RxFlow(r_RxFlow),
700
  .DlyCrcEn(r_DlyCrcEn),
701
  .MAC(r_MAC),
702
  .PadIn(r_Pad | PerPacketPad),
703
  .PadOut(PadOut),
704
  .CrcEnIn(r_CrcEn | PerPacketCrcEn),
705
  .CrcEnOut(CrcEnOut),
706
  .TxReset(wb_rst_i),
707
  .RxReset(wb_rst_i),
708
  .ReceivedLengthOK(ReceivedLengthOK),
709
  .TxDataOut(TxDataOut),
710
  .TxStartFrmOut(TxStartFrmOut),
711
  .TxEndFrmOut(TxEndFrmOut),
712
  .TxUsedDataOut(TxUsedData),
713
  .TxDoneOut(TxDone),
714
  .TxAbortOut(TxAbort),
715
  .WillSendControlFrame(WillSendControlFrame),
716
  .TxCtrlEndFrm(TxCtrlEndFrm),
717
  .ReceivedPauseFrm(ReceivedPauseFrm),
718
  .ControlFrmAddressOK(ControlFrmAddressOK),
719
  .SetPauseTimer(SetPauseTimer),
720
  .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
721
  .r_PassAll(r_PassAll)
722
);
723
 
724
 
725
 
726
wire TxCarrierSense;          // Synchronized CarrierSense (to Tx clock)
727
wire Collision;               // Synchronized Collision
728
 
729
reg CarrierSense_Tx1;
730
reg CarrierSense_Tx2;
731
reg Collision_Tx1;
732
reg Collision_Tx2;
733
 
734
reg RxEnSync;                 // Synchronized Receive Enable
735
reg WillTransmit_q;
736
reg WillTransmit_q2;
737
 
738
 
739
 
740
// Muxed MII receive data valid
741
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
742
 
743
// Muxed MII Receive Error
744
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
745
 
746
// Muxed MII Receive Data
747
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
748
 
749
 
750
 
751
// Connecting TxEthMAC
752
eth_txethmac txethmac1
753
(
754
  .MTxClk(mtx_clk_pad_i),
755
  .Reset(wb_rst_i),
756
  .CarrierSense(TxCarrierSense),
757
  .Collision(Collision),
758
  .TxData(TxDataOut),
759
  .TxStartFrm(TxStartFrmOut),
760
  .TxUnderRun(TxUnderRun),
761
  .TxEndFrm(TxEndFrmOut),
762
  .Pad(PadOut),
763
  .MinFL(r_MinFL),
764
  .CrcEn(CrcEnOut),
765
  .FullD(r_FullD),
766
  .HugEn(r_HugEn),
767
  .DlyCrcEn(r_DlyCrcEn),
768
  .IPGT(r_IPGT),
769
  .IPGR1(r_IPGR1),
770
  .IPGR2(r_IPGR2),
771
  .CollValid(r_CollValid),
772
  .MaxRet(r_MaxRet),
773
  .NoBckof(r_NoBckof),
774
  .ExDfrEn(r_ExDfrEn),
775
  .MaxFL(r_MaxFL),
776
  .MTxEn(mtxen_pad_o),
777
  .MTxD(mtxd_pad_o),
778
  .MTxErr(mtxerr_pad_o),
779
  .TxUsedData(TxUsedDataIn),
780
  .TxDone(TxDoneIn),
781
  .TxRetry(TxRetry),
782
  .TxAbort(TxAbortIn),
783
  .WillTransmit(WillTransmit),
784
  .ResetCollision(ResetCollision),
785
  .RetryCnt(RetryCnt),
786
  .StartTxDone(StartTxDone),
787
  .StartTxAbort(StartTxAbort),
788
  .MaxCollisionOccured(MaxCollisionOccured),
789
  .LateCollision(LateCollision),
790
  .DeferIndication(DeferIndication),
791
  .StatePreamble(StatePreamble),
792
  .StateData(StateData)
793
);
794
 
795
 
796
 
797
 
798
wire  [15:0]  RxByteCnt;
799
wire          RxByteCntEq0;
800
wire          RxByteCntGreat2;
801
wire          RxByteCntMaxFrame;
802
wire          RxCrcError;
803
wire          RxStateIdle;
804
wire          RxStatePreamble;
805
wire          RxStateSFD;
806
wire   [1:0]  RxStateData;
807
wire          AddressMiss;
808
 
809
 
810
 
811
// Connecting RxEthMAC
812
eth_rxethmac rxethmac1
813
(
814
  .MRxClk(mrx_clk_pad_i),
815
  .MRxDV(MRxDV_Lb),
816
  .MRxD(MRxD_Lb),
817
  .Transmitting(Transmitting),
818
  .HugEn(r_HugEn),
819
  .DlyCrcEn(r_DlyCrcEn),
820
  .MaxFL(r_MaxFL),
821
  .r_IFG(r_IFG),
822
  .Reset(wb_rst_i),
823
  .RxData(RxData),
824
  .RxValid(RxValid),
825
  .RxStartFrm(RxStartFrm),
826
  .RxEndFrm(RxEndFrm),
827
  .ByteCnt(RxByteCnt),
828
  .ByteCntEq0(RxByteCntEq0),
829
  .ByteCntGreat2(RxByteCntGreat2),
830
  .ByteCntMaxFrame(RxByteCntMaxFrame),
831
  .CrcError(RxCrcError),
832
  .StateIdle(RxStateIdle),
833
  .StatePreamble(RxStatePreamble),
834
  .StateSFD(RxStateSFD),
835
  .StateData(RxStateData),
836
  .MAC(r_MAC),
837
  .r_Pro(r_Pro),
838
  .r_Bro(r_Bro),
839
  .r_HASH0(r_HASH0),
840
  .r_HASH1(r_HASH1),
841
  .RxAbort(RxAbort),
842
  .AddressMiss(AddressMiss),
843
  .PassAll(r_PassAll),
844
  .ControlFrmAddressOK(ControlFrmAddressOK)
845
);
846
 
847
 
848
// MII Carrier Sense Synchronization
849
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
850
begin
851
  if(wb_rst_i)
852
    begin
853
      CarrierSense_Tx1 <=  1'b0;
854
      CarrierSense_Tx2 <=  1'b0;
855
    end
856
  else
857
    begin
858
      CarrierSense_Tx1 <=  mcrs_pad_i;
859
      CarrierSense_Tx2 <=  CarrierSense_Tx1;
860
    end
861
end
862
 
863
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
864
 
865
 
866
// MII Collision Synchronization
867
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
868
begin
869
  if(wb_rst_i)
870
    begin
871
      Collision_Tx1 <=  1'b0;
872
      Collision_Tx2 <=  1'b0;
873
    end
874
  else
875
    begin
876
      Collision_Tx1 <=  mcoll_pad_i;
877
      if(ResetCollision)
878
        Collision_Tx2 <=  1'b0;
879
      else
880
      if(Collision_Tx1)
881
        Collision_Tx2 <=  1'b1;
882
    end
883
end
884
 
885
 
886
// Synchronized Collision
887
assign Collision = ~r_FullD & Collision_Tx2;
888
 
889
 
890
 
891
// Delayed WillTransmit
892
always @ (posedge mrx_clk_pad_i)
893
begin
894
  WillTransmit_q <=  WillTransmit;
895
  WillTransmit_q2 <=  WillTransmit_q;
896
end
897
 
898
 
899
assign Transmitting = ~r_FullD & WillTransmit_q2;
900
 
901
 
902
 
903
// Synchronized Receive Enable
904
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
905
begin
906
  if(wb_rst_i)
907
    RxEnSync <=  1'b0;
908
  else
909
  if(~mrxdv_pad_i)
910
    RxEnSync <=  r_RxEn;
911
end
912
 
913
 
914
 
915
// Synchronizing WillSendControlFrame to WB_CLK;
916
always @ (posedge wb_clk_i or posedge wb_rst_i)
917
begin
918
  if(wb_rst_i)
919
    WillSendControlFrame_sync1 <= 1'b0;
920
  else
921
    WillSendControlFrame_sync1 <= WillSendControlFrame;
922
end
923
 
924
always @ (posedge wb_clk_i or posedge wb_rst_i)
925
begin
926
  if(wb_rst_i)
927
    WillSendControlFrame_sync2 <= 1'b0;
928
  else
929
    WillSendControlFrame_sync2 <= WillSendControlFrame_sync1;
930
end
931
 
932
always @ (posedge wb_clk_i or posedge wb_rst_i)
933
begin
934
  if(wb_rst_i)
935
    WillSendControlFrame_sync3 <= 1'b0;
936
  else
937
    WillSendControlFrame_sync3 <= WillSendControlFrame_sync2;
938
end
939
 
940
always @ (posedge wb_clk_i or posedge wb_rst_i)
941
begin
942
  if(wb_rst_i)
943
    RstTxPauseRq <= 1'b0;
944
  else
945
    RstTxPauseRq <= WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
946
end
947
 
948
 
949
 
950
 
951
// TX Pause request Synchronization
952
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
953
begin
954
  if(wb_rst_i)
955
    begin
956
      TxPauseRq_sync1 <=  1'b0;
957
      TxPauseRq_sync2 <=  1'b0;
958
      TxPauseRq_sync3 <=  1'b0;
959
    end
960
  else
961
    begin
962
      TxPauseRq_sync1 <=  (r_TxPauseRq & r_TxFlow);
963
      TxPauseRq_sync2 <=  TxPauseRq_sync1;
964
      TxPauseRq_sync3 <=  TxPauseRq_sync2;
965
    end
966
end
967
 
968
 
969
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
970
begin
971
  if(wb_rst_i)
972
    TPauseRq <=  1'b0;
973
  else
974
    TPauseRq <=  TxPauseRq_sync2 & (~TxPauseRq_sync3);
975
end
976
 
977
 
978
wire LatchedMRxErr;
979
reg RxAbort_latch;
980
reg RxAbort_sync1;
981
reg RxAbort_wb;
982
reg RxAbortRst_sync1;
983
reg RxAbortRst;
984
 
985
// Synchronizing RxAbort to the WISHBONE clock
986
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
987
begin
988
  if(wb_rst_i)
989
    RxAbort_latch <=  1'b0;
990
  else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr &
991
          ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
992
    RxAbort_latch <=  1'b1;
993
  else if(RxAbortRst)
994
    RxAbort_latch <=  1'b0;
995
end
996
 
997
always @ (posedge wb_clk_i or posedge wb_rst_i)
998
begin
999
  if(wb_rst_i)
1000
    begin
1001
      RxAbort_sync1 <=  1'b0;
1002
      RxAbort_wb    <=  1'b0;
1003
      RxAbort_wb    <=  1'b0;
1004
    end
1005
  else
1006
    begin
1007
      RxAbort_sync1 <=  RxAbort_latch;
1008
      RxAbort_wb    <=  RxAbort_sync1;
1009
    end
1010
end
1011
 
1012
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
1013
begin
1014
  if(wb_rst_i)
1015
    begin
1016
      RxAbortRst_sync1 <=  1'b0;
1017
      RxAbortRst       <=  1'b0;
1018
    end
1019
  else
1020
    begin
1021
      RxAbortRst_sync1 <=  RxAbort_wb;
1022
      RxAbortRst       <=  RxAbortRst_sync1;
1023
    end
1024
end
1025
 
1026
 
1027
 
1028
// Connecting Wishbone module
1029
eth_wishbone #(.TX_FIFO_DATA_WIDTH(TX_FIFO_DATA_WIDTH),
1030
               .TX_FIFO_DEPTH     (TX_FIFO_DEPTH),
1031
               .TX_FIFO_CNT_WIDTH (TX_FIFO_CNT_WIDTH),
1032
               .RX_FIFO_DATA_WIDTH(RX_FIFO_DATA_WIDTH),
1033
               .RX_FIFO_DEPTH     (RX_FIFO_DEPTH),
1034
               .RX_FIFO_CNT_WIDTH (RX_FIFO_CNT_WIDTH))
1035
wishbone
1036
(
1037
  .WB_CLK_I(wb_clk_i),
1038
  .WB_DAT_I(wb_dat_i),
1039
  .WB_DAT_O(BD_WB_DAT_O),
1040
 
1041
  // WISHBONE slave
1042
  .WB_ADR_I(wb_adr_i[9:2]),
1043
  .WB_WE_I(wb_we_i),
1044
  .BDCs(BDCs),
1045
  .WB_ACK_O(BDAck),
1046
  .Reset(wb_rst_i),
1047
 
1048
  // WISHBONE master
1049
  .m_wb_adr_o(m_wb_adr_tmp),
1050
  .m_wb_sel_o(m_wb_sel_o),
1051
  .m_wb_we_o(m_wb_we_o),
1052
  .m_wb_dat_i(m_wb_dat_i),
1053
  .m_wb_dat_o(m_wb_dat_o),
1054
  .m_wb_cyc_o(m_wb_cyc_o),
1055
  .m_wb_stb_o(m_wb_stb_o),
1056
  .m_wb_ack_i(m_wb_ack_i),
1057
  .m_wb_err_i(m_wb_err_i),
1058
 
1059
`ifdef ETH_WISHBONE_B3
1060
  .m_wb_cti_o(m_wb_cti_o),
1061
  .m_wb_bte_o(m_wb_bte_o),
1062
`endif
1063
 
1064
    //TX
1065
  .MTxClk(mtx_clk_pad_i),
1066
  .TxStartFrm(TxStartFrm),
1067
  .TxEndFrm(TxEndFrm),
1068
  .TxUsedData(TxUsedData),
1069
  .TxData(TxData),
1070
  .TxRetry(TxRetry),
1071
  .TxAbort(TxAbort),
1072
  .TxUnderRun(TxUnderRun),
1073
  .TxDone(TxDone),
1074
  .PerPacketCrcEn(PerPacketCrcEn),
1075
  .PerPacketPad(PerPacketPad),
1076
 
1077
  // Register
1078
  .r_TxEn(r_TxEn),
1079
  .r_RxEn(r_RxEn),
1080
  .r_TxBDNum(r_TxBDNum),
1081
  .r_RxFlow(r_RxFlow),
1082
  .r_PassAll(r_PassAll),
1083
 
1084
  //RX
1085
  .MRxClk(mrx_clk_pad_i),
1086
  .RxData(RxData),
1087
  .RxValid(RxValid),
1088
  .RxStartFrm(RxStartFrm),
1089
  .RxEndFrm(RxEndFrm),
1090
  .Busy_IRQ(Busy_IRQ),
1091
  .RxE_IRQ(RxE_IRQ),
1092
  .RxB_IRQ(RxB_IRQ),
1093
  .TxE_IRQ(TxE_IRQ),
1094
  .TxB_IRQ(TxB_IRQ),
1095
 
1096
  .RxAbort(RxAbort_wb),
1097
  .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
1098
 
1099
  .InvalidSymbol(InvalidSymbol),
1100
  .LatchedCrcError(LatchedCrcError),
1101
  .RxLength(RxByteCnt),
1102
  .RxLateCollision(RxLateCollision),
1103
  .ShortFrame(ShortFrame),
1104
  .DribbleNibble(DribbleNibble),
1105
  .ReceivedPacketTooBig(ReceivedPacketTooBig),
1106
  .LoadRxStatus(LoadRxStatus),
1107
  .RetryCntLatched(RetryCntLatched),
1108
  .RetryLimit(RetryLimit),
1109
  .LateCollLatched(LateCollLatched),
1110
  .DeferLatched(DeferLatched),
1111
  .RstDeferLatched(RstDeferLatched),
1112
  .CarrierSenseLost(CarrierSenseLost),
1113
  .ReceivedPacketGood(ReceivedPacketGood),
1114
  .AddressMiss(AddressMiss),
1115
  .ReceivedPauseFrm(ReceivedPauseFrm)
1116
 
1117
`ifdef ETH_BIST
1118
  ,
1119
  .mbist_si_i       (mbist_si_i),
1120
  .mbist_so_o       (mbist_so_o),
1121
  .mbist_ctrl_i       (mbist_ctrl_i)
1122
`endif
1123
`ifdef WISHBONE_DEBUG
1124
  ,
1125
  .dbg_dat0(wb_dbg_dat0)
1126
`endif
1127
 
1128
);
1129
 
1130
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
1131
 
1132
// Connecting MacStatus module
1133
eth_macstatus macstatus1
1134
(
1135
  .MRxClk(mrx_clk_pad_i),
1136
  .Reset(wb_rst_i),
1137
  .ReceiveEnd(ReceiveEnd),
1138
  .ReceivedPacketGood(ReceivedPacketGood),
1139
     .ReceivedLengthOK(ReceivedLengthOK),
1140
  .RxCrcError(RxCrcError),
1141
  .MRxErr(MRxErr_Lb),
1142
  .MRxDV(MRxDV_Lb),
1143
  .RxStateSFD(RxStateSFD),
1144
  .RxStateData(RxStateData),
1145
  .RxStatePreamble(RxStatePreamble),
1146
  .RxStateIdle(RxStateIdle),
1147
  .Transmitting(Transmitting),
1148
  .RxByteCnt(RxByteCnt),
1149
  .RxByteCntEq0(RxByteCntEq0),
1150
  .RxByteCntGreat2(RxByteCntGreat2),
1151
  .RxByteCntMaxFrame(RxByteCntMaxFrame),
1152
  .InvalidSymbol(InvalidSymbol),
1153
  .MRxD(MRxD_Lb),
1154
  .LatchedCrcError(LatchedCrcError),
1155
  .Collision(mcoll_pad_i),
1156
  .CollValid(r_CollValid),
1157
  .RxLateCollision(RxLateCollision),
1158
  .r_RecSmall(r_RecSmall),
1159
  .r_MinFL(r_MinFL),
1160
  .r_MaxFL(r_MaxFL),
1161
  .ShortFrame(ShortFrame),
1162
  .DribbleNibble(DribbleNibble),
1163
  .ReceivedPacketTooBig(ReceivedPacketTooBig),
1164
  .r_HugEn(r_HugEn),
1165
  .LoadRxStatus(LoadRxStatus),
1166
  .RetryCnt(RetryCnt),
1167
  .StartTxDone(StartTxDone),
1168
  .StartTxAbort(StartTxAbort),
1169
  .RetryCntLatched(RetryCntLatched),
1170
  .MTxClk(mtx_clk_pad_i),
1171
  .MaxCollisionOccured(MaxCollisionOccured),
1172
  .RetryLimit(RetryLimit),
1173
  .LateCollision(LateCollision),
1174
  .LateCollLatched(LateCollLatched),
1175
  .DeferIndication(DeferIndication),
1176
  .DeferLatched(DeferLatched),
1177
  .RstDeferLatched(RstDeferLatched),
1178
  .TxStartFrm(TxStartFrmOut),
1179
  .StatePreamble(StatePreamble),
1180
  .StateData(StateData),
1181
  .CarrierSense(CarrierSense_Tx2),
1182
  .CarrierSenseLost(CarrierSenseLost),
1183
  .TxUsedData(TxUsedDataIn),
1184
  .LatchedMRxErr(LatchedMRxErr),
1185
  .Loopback(r_LoopBck),
1186
  .r_FullD(r_FullD)
1187
);
1188
 
1189
 
1190
endmodule

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