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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_transmitcontrol.v] - Blame information for rev 346

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1 15 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_transmitcontrol.v                                       ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
44 257 mohor
// Revision 1.5  2002/11/19 17:37:32  mohor
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// When control frame (PAUSE) was sent, status was written in the
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// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
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// Only TXC interrupt is set.
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//
49 251 mohor
// Revision 1.4  2002/01/23 10:28:16  mohor
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// Link in the header changed.
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//
52 37 mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
56 22 mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
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// Few little NCSIM warnings fixed.
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//
59 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
69 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
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// Directory structure changed. Files checked and joind together.
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//
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// Revision 1.1  2001/07/03 12:51:54  mohor
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// Initial release of the MAC Control module.
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//
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//
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//
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//
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//
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//
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82 22 mohor
`include "timescale.v"
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module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
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                            TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
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                            TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
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                            ControlData, WillSendControlFrame, BlockTxDone
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                           );
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parameter Tp = 1;
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input         MTxClk;
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input         TxReset;
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input         TxUsedDataIn;
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input         TxUsedDataOut;
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input         TxDoneIn;
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input         TxAbortIn;
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input         TxStartFrmIn;
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input         TPauseRq;
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input         TxUsedDataOutDetected;
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input         TxFlow;
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input         DlyCrcEn;
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input  [15:0] TxPauseTV;
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input  [47:0] MAC;
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output        TxCtrlStartFrm;
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output        TxCtrlEndFrm;
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output        SendingCtrlFrm;
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output        CtrlMux;
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output [7:0]  ControlData;
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output        WillSendControlFrame;
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output        BlockTxDone;
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reg           SendingCtrlFrm;
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reg           CtrlMux;
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reg           WillSendControlFrame;
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reg    [3:0]  DlyCrcCnt;
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reg    [5:0]  ByteCnt;
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reg           ControlEnd_q;
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reg    [7:0]  MuxedCtrlData;
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reg           TxCtrlStartFrm;
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reg           TxCtrlStartFrm_q;
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reg           TxCtrlEndFrm;
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reg    [7:0]  ControlData;
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reg           TxUsedDataIn_q;
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reg           BlockTxDone;
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wire          IncrementDlyCrcCnt;
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wire          ResetByteCnt;
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wire          IncrementByteCnt;
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wire          ControlEnd;
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wire          IncrementByteCntBy2;
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wire          EnableCnt;
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// A command for Sending the control frame is active (latched)
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always @ (posedge MTxClk or posedge TxReset)
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begin
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  if(TxReset)
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    WillSendControlFrame <= #Tp 1'b0;
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  else
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  if(TxCtrlEndFrm & CtrlMux)
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    WillSendControlFrame <= #Tp 1'b0;
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  else
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  if(TPauseRq & TxFlow)
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    WillSendControlFrame <= #Tp 1'b1;
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end
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// Generation of the transmit control packet start frame
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always @ (posedge MTxClk or posedge TxReset)
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begin
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  if(TxReset)
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    TxCtrlStartFrm <= #Tp 1'b0;
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  else
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  if(TxUsedDataIn_q & CtrlMux)
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    TxCtrlStartFrm <= #Tp 1'b0;
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  else
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  if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
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    TxCtrlStartFrm <= #Tp 1'b1;
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end
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// Generation of the transmit control packet end frame
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always @ (posedge MTxClk or posedge TxReset)
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begin
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  if(TxReset)
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    TxCtrlEndFrm <= #Tp 1'b0;
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  else
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  if(ControlEnd | ControlEnd_q)
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    TxCtrlEndFrm <= #Tp 1'b1;
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  else
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    TxCtrlEndFrm <= #Tp 1'b0;
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end
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// Generation of the multiplexer signal (controls muxes for switching between
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// normal and control packets)
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always @ (posedge MTxClk or posedge TxReset)
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begin
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  if(TxReset)
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    CtrlMux <= #Tp 1'b0;
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  else
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  if(WillSendControlFrame & ~TxUsedDataOut)
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    CtrlMux <= #Tp 1'b1;
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  else
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  if(TxDoneIn)
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    CtrlMux <= #Tp 1'b0;
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end
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// Generation of the Sending Control Frame signal (enables padding and CRC)
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always @ (posedge MTxClk or posedge TxReset)
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begin
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  if(TxReset)
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    SendingCtrlFrm <= #Tp 1'b0;
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  else
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  if(WillSendControlFrame & TxCtrlStartFrm)
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    SendingCtrlFrm <= #Tp 1'b1;
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  else
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  if(TxDoneIn)
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    SendingCtrlFrm <= #Tp 1'b0;
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end
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always @ (posedge MTxClk or posedge TxReset)
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begin
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  if(TxReset)
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    TxUsedDataIn_q <= #Tp 1'b0;
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  else
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    TxUsedDataIn_q <= #Tp TxUsedDataIn;
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end
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// Generation of the signal that will block sending the Done signal to the eth_wishbone module
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// While sending the control frame
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always @ (posedge MTxClk or posedge TxReset)
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begin
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  if(TxReset)
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    BlockTxDone <= #Tp 1'b0;
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  else
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  if(TxCtrlStartFrm)
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    BlockTxDone <= #Tp 1'b1;
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  else
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  if(TxStartFrmIn)
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    BlockTxDone <= #Tp 1'b0;
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end
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always @ (posedge MTxClk)
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begin
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  ControlEnd_q     <= #Tp ControlEnd;
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  TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;
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end
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assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn &  ~DlyCrcCnt[2];
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// Delayed CRC counter
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always @ (posedge MTxClk or posedge TxReset)
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begin
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  if(TxReset)
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    DlyCrcCnt <= #Tp 4'h0;
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  else
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  if(ResetByteCnt)
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    DlyCrcCnt <= #Tp 4'h0;
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  else
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  if(IncrementDlyCrcCnt)
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    DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
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end
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assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
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assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
261 257 mohor
assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn;     // When TxUsedDataIn and CtrlMux are set at the same time
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263 257 mohor
assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
264 15 mohor
// Byte counter
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always @ (posedge MTxClk or posedge TxReset)
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begin
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  if(TxReset)
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    ByteCnt <= #Tp 6'h0;
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  else
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  if(ResetByteCnt)
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    ByteCnt <= #Tp 6'h0;
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  else
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  if(IncrementByteCntBy2 & EnableCnt)
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    ByteCnt <= #Tp (ByteCnt[5:0] ) + 2'h2;
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  else
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  if(IncrementByteCnt & EnableCnt)
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    ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;
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end
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assign ControlEnd = ByteCnt[5:0] == 6'h22;
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284
// Control data generation (goes to the TxEthMAC module)
285
always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
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begin
287
  case(ByteCnt)
288 18 mohor
    6'h0:    if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
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               MuxedCtrlData[7:0] = 8'h01;                   // Reserved Multicast Address
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             else
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                                                         MuxedCtrlData[7:0] = 8'h0;
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    6'h2:      MuxedCtrlData[7:0] = 8'h80;
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    6'h4:      MuxedCtrlData[7:0] = 8'hC2;
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    6'h6:      MuxedCtrlData[7:0] = 8'h00;
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    6'h8:      MuxedCtrlData[7:0] = 8'h00;
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    6'hA:      MuxedCtrlData[7:0] = 8'h01;
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    6'hC:      MuxedCtrlData[7:0] = MAC[47:40];
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    6'hE:      MuxedCtrlData[7:0] = MAC[39:32];
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    6'h10:     MuxedCtrlData[7:0] = MAC[31:24];
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    6'h12:     MuxedCtrlData[7:0] = MAC[23:16];
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    6'h14:     MuxedCtrlData[7:0] = MAC[15:8];
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    6'h16:     MuxedCtrlData[7:0] = MAC[7:0];
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    6'h18:     MuxedCtrlData[7:0] = 8'h88;                   // Type/Length
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    6'h1A:     MuxedCtrlData[7:0] = 8'h08;
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    6'h1C:     MuxedCtrlData[7:0] = 8'h00;                   // Opcode
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    6'h1E:     MuxedCtrlData[7:0] = 8'h01;
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    6'h20:     MuxedCtrlData[7:0] = TxPauseTV[15:8];         // Pause timer value
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    6'h22:     MuxedCtrlData[7:0] = TxPauseTV[7:0];
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    default:   MuxedCtrlData[7:0] = 8'h0;
310
  endcase
311
end
312
 
313
 
314
// Latched Control data
315
always @ (posedge MTxClk or posedge TxReset)
316
begin
317
  if(TxReset)
318
    ControlData[7:0] <= #Tp 8'h0;
319
  else
320
  if(~ByteCnt[0])
321
    ControlData[7:0] <= #Tp MuxedCtrlData[7:0];
322
end
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endmodule

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