OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_txethmac.v] - Blame information for rev 353

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_txethmac.v                                              ////
4 353 olof
///                                                               ////
5 15 mohor
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
11
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
12
////                                                              ////
13
////  All additional information is avaliable in the Readme.txt   ////
14
////  file.                                                       ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2001 Authors                                   ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: not supported by cvs2svn $
46 328 igorm
// Revision 1.8  2003/01/30 13:33:24  mohor
47
// When padding was enabled and crc disabled, frame was not ended correctly.
48
//
49 277 mohor
// Revision 1.7  2002/02/26 16:24:01  mohor
50
// RetryCntLatched was unused and removed from design
51
//
52 79 mohor
// Revision 1.6  2002/02/22 12:56:35  mohor
53
// Retry is not activated when a Tx Underrun occured
54
//
55 72 mohor
// Revision 1.5  2002/02/11 09:18:22  mohor
56
// Tx status is written back to the BD.
57
//
58 43 mohor
// Revision 1.4  2002/01/23 10:28:16  mohor
59
// Link in the header changed.
60
//
61 37 mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
62
// eth_timescale.v changed to timescale.v This is done because of the
63
// simulation of the few cores in a one joined project.
64
//
65 22 mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
66
// Few little NCSIM warnings fixed.
67
//
68 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
69
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
70
// Include files fixed to contain no path.
71
// File names and module names changed ta have a eth_ prologue in the name.
72
// File eth_timescale.v is used to define timescale
73
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
74
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
75
// and Mdo_OE. The bidirectional signal must be created on the top level. This
76
// is done due to the ASIC tools.
77
//
78 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
79
// Directory structure changed. Files checked and joind together.
80
//
81
// Revision 1.3  2001/06/19 18:16:40  mohor
82
// TxClk changed to MTxClk (as discribed in the documentation).
83
// Crc changed so only one file can be used instead of two.
84
//
85
// Revision 1.2  2001/06/19 10:38:08  mohor
86
// Minor changes in header.
87
//
88
// Revision 1.1  2001/06/19 10:27:58  mohor
89
// TxEthMAC initial release.
90
//
91
//
92
//
93
 
94 22 mohor
`include "timescale.v"
95 15 mohor
 
96
 
97
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
98
                     Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
99
                     IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
100
                     MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
101 43 mohor
                     ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
102 277 mohor
                     LateCollision, DeferIndication, StatePreamble, StateData
103 43 mohor
 
104 15 mohor
                    );
105
 
106
 
107
input MTxClk;                   // Transmit clock (from PHY)
108
input Reset;                    // Reset
109
input TxStartFrm;               // Transmit packet start frame
110
input TxEndFrm;                 // Transmit packet end frame
111
input TxUnderRun;               // Transmit packet under-run
112
input [7:0] TxData;             // Transmit packet data byte
113
input CarrierSense;             // Carrier sense (synchronized)
114
input Collision;                // Collision (synchronized)
115
input Pad;                      // Pad enable (from register)
116
input CrcEn;                    // Crc enable (from register)
117
input FullD;                    // Full duplex (from register)
118
input HugEn;                    // Huge packets enable (from register)
119
input DlyCrcEn;                 // Delayed Crc enabled (from register)
120
input [15:0] MinFL;             // Minimum frame length (from register)
121
input [15:0] MaxFL;             // Maximum frame length (from register)
122
input [6:0] IPGT;               // Back to back transmit inter packet gap parameter (from register)
123
input [6:0] IPGR1;              // Non back to back transmit inter packet gap parameter IPGR1 (from register)
124
input [6:0] IPGR2;              // Non back to back transmit inter packet gap parameter IPGR2 (from register)
125
input [5:0] CollValid;          // Valid collision window (from register)
126
input [3:0] MaxRet;             // Maximum retry number (from register)
127
input NoBckof;                  // No backoff (from register)
128
input ExDfrEn;                  // Excessive defferal enable (from register)
129
 
130
output [3:0] MTxD;              // Transmit nibble (to PHY)
131
output MTxEn;                   // Transmit enable (to PHY)
132
output MTxErr;                  // Transmit error (to PHY)
133
output TxDone;                  // Transmit packet done (to RISC)
134
output TxRetry;                 // Transmit packet retry (to RISC)
135
output TxAbort;                 // Transmit packet abort (to RISC)
136
output TxUsedData;              // Transmit packet used data (to RISC)
137
output WillTransmit;            // Will transmit (to RxEthMAC)
138
output ResetCollision;          // Reset Collision (for synchronizing collision)
139 43 mohor
output [3:0] RetryCnt;          // Latched Retry Counter for tx status purposes
140
output StartTxDone;
141
output StartTxAbort;
142
output MaxCollisionOccured;
143
output LateCollision;
144 277 mohor
output DeferIndication;
145 43 mohor
output StatePreamble;
146
output [1:0] StateData;
147 15 mohor
 
148
reg [3:0] MTxD;
149
reg MTxEn;
150
reg MTxErr;
151
reg TxDone;
152
reg TxRetry;
153
reg TxAbort;
154
reg TxUsedData;
155
reg WillTransmit;
156
reg ColWindow;
157
reg StopExcessiveDeferOccured;
158
reg [3:0] RetryCnt;
159
reg [3:0] MTxD_d;
160
reg StatusLatch;
161
reg PacketFinished_q;
162
reg PacketFinished;
163
 
164
 
165
wire ExcessiveDeferOccured;
166
wire StartIPG;
167
wire StartPreamble;
168
wire [1:0] StartData;
169
wire StartFCS;
170
wire StartJam;
171 277 mohor
wire StartDefer;
172 15 mohor
wire StartBackoff;
173
wire StateDefer;
174
wire StateIPG;
175
wire StateIdle;
176
wire StatePAD;
177
wire StateFCS;
178
wire StateJam;
179 328 igorm
wire StateJam_q;
180 15 mohor
wire StateBackOff;
181
wire StateSFD;
182
wire StartTxRetry;
183
wire UnderRun;
184
wire TooBig;
185
wire [31:0] Crc;
186
wire CrcError;
187
wire [2:0] DlyCrcCnt;
188
wire [15:0] NibCnt;
189
wire NibCntEq7;
190
wire NibCntEq15;
191
wire NibbleMinFl;
192
wire ExcessiveDefer;
193
wire [15:0] ByteCnt;
194
wire MaxFrame;
195
wire RetryMax;
196
wire RandomEq0;
197
wire RandomEqByteCnt;
198
wire PacketFinished_d;
199
 
200
 
201
 
202 18 mohor
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
203 15 mohor
 
204
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
205
 
206 277 mohor
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
207 15 mohor
 
208
assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
209
 
210
assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
211
 
212 72 mohor
// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
213
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
214 15 mohor
 
215
assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
216
 
217
assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
218
 
219
assign StateSFD = StatePreamble & NibCntEq15;
220
 
221
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
222
 
223
 
224
// StopExcessiveDeferOccured
225
always @ (posedge MTxClk or posedge Reset)
226
begin
227
  if(Reset)
228 352 olof
    StopExcessiveDeferOccured <=  1'b0;
229 15 mohor
  else
230
    begin
231
      if(~TxStartFrm)
232 352 olof
        StopExcessiveDeferOccured <=  1'b0;
233 15 mohor
      else
234
      if(ExcessiveDeferOccured)
235 352 olof
        StopExcessiveDeferOccured <=  1'b1;
236 15 mohor
    end
237
end
238
 
239
 
240
// Collision Window
241
always @ (posedge MTxClk or posedge Reset)
242
begin
243
  if(Reset)
244 352 olof
    ColWindow <=  1'b1;
245 15 mohor
  else
246
    begin
247
      if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
248 352 olof
        ColWindow <=  1'b0;
249 15 mohor
      else
250
      if(StateIdle | StateIPG)
251 352 olof
        ColWindow <=  1'b1;
252 15 mohor
    end
253
end
254
 
255
 
256
// Start Window
257
always @ (posedge MTxClk or posedge Reset)
258
begin
259
  if(Reset)
260 352 olof
    StatusLatch <=  1'b0;
261 15 mohor
  else
262
    begin
263
      if(~TxStartFrm)
264 352 olof
        StatusLatch <=  1'b0;
265 15 mohor
      else
266
      if(ExcessiveDeferOccured | StateIdle)
267 352 olof
        StatusLatch <=  1'b1;
268 15 mohor
     end
269
end
270
 
271
 
272
// Transmit packet used data
273
always @ (posedge MTxClk or posedge Reset)
274
begin
275
  if(Reset)
276 352 olof
    TxUsedData <=  1'b0;
277 15 mohor
  else
278 352 olof
    TxUsedData <=  |StartData;
279 15 mohor
end
280
 
281
 
282
// Transmit packet done
283
always @ (posedge MTxClk or posedge Reset)
284
begin
285
  if(Reset)
286 352 olof
    TxDone <=  1'b0;
287 15 mohor
  else
288
    begin
289
      if(TxStartFrm & ~StatusLatch)
290 352 olof
        TxDone <=  1'b0;
291 15 mohor
      else
292
      if(StartTxDone)
293 352 olof
        TxDone <=  1'b1;
294 15 mohor
    end
295
end
296
 
297
 
298
// Transmit packet retry
299
always @ (posedge MTxClk or posedge Reset)
300
begin
301
  if(Reset)
302 352 olof
    TxRetry <=  1'b0;
303 15 mohor
  else
304
    begin
305
      if(TxStartFrm & ~StatusLatch)
306 352 olof
        TxRetry <=  1'b0;
307 15 mohor
      else
308
      if(StartTxRetry)
309 352 olof
        TxRetry <=  1'b1;
310 15 mohor
     end
311
end
312
 
313
 
314
// Transmit packet abort
315
always @ (posedge MTxClk or posedge Reset)
316
begin
317
  if(Reset)
318 352 olof
    TxAbort <=  1'b0;
319 15 mohor
  else
320
    begin
321
      if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
322 352 olof
        TxAbort <=  1'b0;
323 15 mohor
      else
324
      if(StartTxAbort)
325 352 olof
        TxAbort <=  1'b1;
326 15 mohor
    end
327
end
328
 
329
 
330
// Retry counter
331
always @ (posedge MTxClk or posedge Reset)
332
begin
333
  if(Reset)
334 352 olof
    RetryCnt[3:0] <=  4'h0;
335 15 mohor
  else
336
    begin
337
      if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
338
          | StateJam & NibCntEq7 & (~ColWindow | RetryMax))
339 352 olof
        RetryCnt[3:0] <=  4'h0;
340 15 mohor
      else
341
      if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
342 353 olof
        RetryCnt[3:0] <=  RetryCnt[3:0] + 1;
343 15 mohor
    end
344
end
345
 
346
 
347
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
348
 
349
 
350
// Transmit nibble
351
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
352 328 igorm
          Crc or NibCntEq15)
353 15 mohor
begin
354
  if(StateData[0])
355
    MTxD_d[3:0] = TxData[3:0];                                  // Lower nibble
356
  else
357
  if(StateData[1])
358
    MTxD_d[3:0] = TxData[7:4];                                  // Higher nibble
359
  else
360
  if(StateFCS)
361
    MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]};     // Crc
362
  else
363
  if(StateJam)
364
    MTxD_d[3:0] = 4'h9;                                         // Jam pattern
365
  else
366
  if(StatePreamble)
367
    if(NibCntEq15)
368
      MTxD_d[3:0] = 4'hd;                                       // SFD
369
    else
370
      MTxD_d[3:0] = 4'h5;                                       // Preamble
371
  else
372
    MTxD_d[3:0] = 4'h0;
373
end
374
 
375
 
376
// Transmit Enable
377
always @ (posedge MTxClk or posedge Reset)
378
begin
379
  if(Reset)
380 352 olof
    MTxEn <=  1'b0;
381 15 mohor
  else
382 352 olof
    MTxEn <=  StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
383 15 mohor
end
384
 
385
 
386
// Transmit nibble
387
always @ (posedge MTxClk or posedge Reset)
388
begin
389
  if(Reset)
390 352 olof
    MTxD[3:0] <=  4'h0;
391 15 mohor
  else
392 352 olof
    MTxD[3:0] <=  MTxD_d[3:0];
393 15 mohor
end
394
 
395
 
396
// Transmit error
397
always @ (posedge MTxClk or posedge Reset)
398
begin
399
  if(Reset)
400 352 olof
    MTxErr <=  1'b0;
401 15 mohor
  else
402 352 olof
    MTxErr <=  TooBig | UnderRun;
403 15 mohor
end
404
 
405
 
406
// WillTransmit
407
always @ (posedge MTxClk or posedge Reset)
408
begin
409
  if(Reset)
410 352 olof
    WillTransmit <=   1'b0;
411 15 mohor
  else
412 352 olof
    WillTransmit <=  StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
413 15 mohor
end
414
 
415
 
416
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
417
 
418
 
419
// Packet finished
420
always @ (posedge MTxClk or posedge Reset)
421
begin
422
  if(Reset)
423
    begin
424 352 olof
      PacketFinished <=  1'b0;
425
      PacketFinished_q  <=  1'b0;
426 15 mohor
    end
427
  else
428
    begin
429 352 olof
      PacketFinished <=  PacketFinished_d;
430
      PacketFinished_q  <=  PacketFinished;
431 15 mohor
    end
432
end
433
 
434
 
435
// Connecting module Counters
436 352 olof
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
437 15 mohor
                            .StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
438
                            .StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
439
                            .StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
440
                            .Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
441
                            .PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
442
                            .StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
443
                            .NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
444
                            .DlyCrcCnt(DlyCrcCnt)
445
                           );
446
 
447
 
448
// Connecting module StateM
449 352 olof
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
450 15 mohor
                        .NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
451
                        .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
452
                        .UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
453
                        .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
454
                        .NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
455
                        .NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
456
                        .StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
457
                        .StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
458
                        .StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
459 277 mohor
                        .StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
460 15 mohor
                       );
461
 
462
 
463
wire Enable_Crc;
464
wire [3:0] Data_Crc;
465
wire Initialize_Crc;
466
 
467
assign Enable_Crc = ~StateFCS;
468
 
469
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
470
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
471
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
472
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
473
 
474 18 mohor
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
475 15 mohor
 
476
 
477
// Connecting module Crc
478 352 olof
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
479 15 mohor
               .Crc(Crc), .CrcError(CrcError)
480
              );
481
 
482
 
483
// Connecting module Random
484 352 olof
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
485 15 mohor
                    .NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
486
 
487
 
488
 
489
 
490
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.