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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_txstatem.v] - Blame information for rev 352

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_txstatem.v                                              ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/project,ethmac                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
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////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.5  2002/10/30 12:54:50  mohor
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// State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.
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//
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// Revision 1.4  2002/01/23 10:28:16  mohor
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// Link in the header changed.
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//
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// Revision 1.3  2001/10/19 08:43:51  mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
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// Revision 1.2  2001/09/11 14:17:00  mohor
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// Few little NCSIM warnings fixed.
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//
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// Revision 1.1  2001/08/06 14:44:29  mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.1  2001/07/30 21:23:42  mohor
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// Directory structure changed. Files checked and joind together.
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//
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// Revision 1.3  2001/06/19 18:16:40  mohor
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// TxClk changed to MTxClk (as discribed in the documentation).
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// Crc changed so only one file can be used instead of two.
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//
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// Revision 1.2  2001/06/19 10:38:07  mohor
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// Minor changes in header.
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//
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// Revision 1.1  2001/06/19 10:27:57  mohor
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// TxEthMAC initial release.
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//
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//
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//
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//
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`include "timescale.v"
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module eth_txstatem  (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1,
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                      IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun,
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                      StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn,
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                      NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt,
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                      StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
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                      StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
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                      StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
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                     );
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input MTxClk;
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input Reset;
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input ExcessiveDefer;
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input CarrierSense;
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input [6:0] NibCnt;
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input [6:0] IPGT;
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input [6:0] IPGR1;
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input [6:0] IPGR2;
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input FullD;
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input TxStartFrm;
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input TxEndFrm;
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input TxUnderRun;
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input Collision;
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input UnderRun;
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input StartTxDone;
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input TooBig;
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input NibCntEq7;
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input NibCntEq15;
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input MaxFrame;
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input Pad;
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input CrcEn;
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input NibbleMinFl;
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input RandomEq0;
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input ColWindow;
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input RetryMax;
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input NoBckof;
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input RandomEqByteCnt;
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output StateIdle;         // Idle state
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output StateIPG;          // IPG state
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output StatePreamble;     // Preamble state
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output [1:0] StateData;   // Data state
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output StatePAD;          // PAD state
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output StateFCS;          // FCS state
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output StateJam;          // Jam state
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output StateJam_q;        // Delayed Jam state
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output StateBackOff;      // Backoff state
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output StateDefer;        // Defer state
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output StartFCS;          // FCS state will be activated in next clock
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output StartJam;          // Jam state will be activated in next clock
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output StartBackoff;      // Backoff state will be activated in next clock
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output StartDefer;        // Defer state will be activated in next clock
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output DeferIndication;
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output StartPreamble;     // Preamble state will be activated in next clock
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output [1:0] StartData;   // Data state will be activated in next clock
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output StartIPG;          // IPG state will be activated in next clock
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wire StartIdle;           // Idle state will be activated in next clock
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wire StartPAD;            // PAD state will be activated in next clock
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reg StateIdle;
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reg StateIPG;
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reg StatePreamble;
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reg [1:0] StateData;
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reg StatePAD;
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reg StateFCS;
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reg StateJam;
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reg StateJam_q;
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reg StateBackOff;
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reg StateDefer;
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reg Rule1;
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// Defining the next state
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assign StartIPG = StateDefer & ~ExcessiveDefer & ~CarrierSense;
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assign StartIdle = StateIPG & (Rule1 & NibCnt[6:0] >= IPGT | ~Rule1 & NibCnt[6:0] >= IPGR2);
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assign StartPreamble = StateIdle & TxStartFrm & ~CarrierSense;
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assign StartData[0] = ~Collision & (StatePreamble & NibCntEq15 | StateData[1] & ~TxEndFrm);
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assign StartData[1] = ~Collision & StateData[0] & ~TxUnderRun & ~MaxFrame;
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assign StartPAD = ~Collision & StateData[1] & TxEndFrm & Pad & ~NibbleMinFl;
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assign StartFCS = ~Collision & StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & CrcEn
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                | ~Collision & StatePAD & NibbleMinFl & CrcEn;
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assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (|StateData[1:0]) | StatePAD | StateFCS);
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assign StartBackoff = StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~NoBckof;
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assign StartDefer = StateIPG & ~Rule1 & CarrierSense & NibCnt[6:0] <= IPGR1 & NibCnt[6:0] != IPGR2
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                  | StateIdle & CarrierSense
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                  | StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax)
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                  | StateBackOff & (TxUnderRun | RandomEqByteCnt)
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                  | StartTxDone | TooBig;
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assign DeferIndication = StateIdle & CarrierSense;
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// Tx State Machine
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always @ (posedge MTxClk or posedge Reset)
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begin
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  if(Reset)
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    begin
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      StateIPG        <=  1'b0;
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      StateIdle       <=  1'b0;
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      StatePreamble   <=  1'b0;
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      StateData[1:0]  <=  2'b0;
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      StatePAD        <=  1'b0;
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      StateFCS        <=  1'b0;
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      StateJam        <=  1'b0;
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      StateJam_q      <=  1'b0;
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      StateBackOff    <=  1'b0;
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      StateDefer      <=  1'b1;
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    end
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  else
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    begin
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      StateData[1:0] <=  StartData[1:0];
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      StateJam_q <=  StateJam;
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      if(StartDefer | StartIdle)
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        StateIPG <=  1'b0;
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      else
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      if(StartIPG)
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        StateIPG <=  1'b1;
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      if(StartDefer | StartPreamble)
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        StateIdle <=  1'b0;
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      else
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      if(StartIdle)
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        StateIdle <=  1'b1;
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      if(StartData[0] | StartJam)
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        StatePreamble <=  1'b0;
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      else
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      if(StartPreamble)
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        StatePreamble <=  1'b1;
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      if(StartFCS | StartJam)
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        StatePAD <=  1'b0;
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      else
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      if(StartPAD)
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        StatePAD <=  1'b1;
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      if(StartJam | StartDefer)
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        StateFCS <=  1'b0;
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      else
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      if(StartFCS)
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        StateFCS <=  1'b1;
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      if(StartBackoff | StartDefer)
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        StateJam <=  1'b0;
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      else
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      if(StartJam)
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        StateJam <=  1'b1;
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      if(StartDefer)
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        StateBackOff <=  1'b0;
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      else
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      if(StartBackoff)
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        StateBackOff <=  1'b1;
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      if(StartIPG)
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        StateDefer <=  1'b0;
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      else
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      if(StartDefer)
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        StateDefer <=  1'b1;
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    end
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end
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// This sections defines which interpack gap rule to use
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always @ (posedge MTxClk or posedge Reset)
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begin
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  if(Reset)
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    Rule1 <=  1'b0;
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  else
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    begin
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      if(StateIdle | StateBackOff)
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        Rule1 <=  1'b0;
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      else
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      if(StatePreamble | FullD)
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        Rule1 <=  1'b1;
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    end
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end
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endmodule

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