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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 210

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
45
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
46
//
47 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
48
// Reception is possible after RxPointer is read and not after BD is read. For
49
// that reason RxBDReady is changed to RxReady.
50
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
51
// comes, interrupt is generated.
52
//
53 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
54
// Ethernet debug registers removed.
55
//
56 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
57
// Async reset for WB_ACK_O removed (when core was in reset, it was
58
// impossible to access BDs).
59
// RxPointers and TxPointers names changed to be more descriptive.
60
// TxUnderRun synchronized.
61
//
62 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
63
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
64
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
65
// was not used OK.
66
//
67 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
68
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
69
// need to multiply or devide any more.
70
//
71 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
72
// WriteRxDataToMemory signal changed so end of frame (when last word is
73
// written to fifo) is changed.
74
//
75 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
76
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
77
//
78 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
79
// ShiftEnded synchronization changed.
80
//
81 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
82
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
83
//
84 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
85
// RxPointer bug fixed.
86
//
87 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
88
// Previous bug wasn't succesfully removed. Now fixed.
89
//
90 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
91
// Master state machine had a bug when switching from master write to
92
// master read.
93
//
94 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
95
// m_wb_cyc_o signal released after every single transfer.
96
//
97 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
98
// Outputs registered. Reset changed for eth_wishbone module.
99
//
100 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
101
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
102
// bug fixed.
103
//
104 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
105
// Small typo fixed.
106
//
107 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
108
// Any address can be used for Tx and Rx BD pointers. Address does not need
109
// to be aligned.
110
//
111 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
112
// Comments in Slovene language removed.
113
//
114 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
115
// casex changed with case, fifo reset changed.
116
//
117 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
118
// rx_fifo was not always cleared ok. Fixed.
119
//
120 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
121
// Status was not latched correctly sometimes. Fixed.
122
//
123 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
124
// Big Endian problem when sending frames fixed.
125
//
126 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
127
// Byte ordering changed (Big Endian used). casex changed with case because
128
// Xilinx Foundation had problems. Tested in HW. It WORKS.
129
//
130 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
131
// Small fixes for external/internal DMA missmatches.
132
//
133 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
134
// Interrupts changed
135
//
136 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
137
// Status was not written correctly when frames were discarted because of
138
// address mismatch.
139
//
140 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
141
// RxStartFrm cleared when abort or retry comes.
142
//
143 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
144
// Changes that were lost when updating from 1.5 to 1.8 fixed.
145
//
146 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
147
// Addition  of new module eth_addrcheck.v
148
//
149
// Revision 1.7  2002/02/12 17:03:47  mohor
150
// RxOverRun added to statuses.
151
//
152
// Revision 1.6  2002/02/11 09:18:22  mohor
153
// Tx status is written back to the BD.
154
//
155 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
156
// Rx status is written back to the BD.
157
//
158 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
159
// non-DMA host interface added. Select the right configutation in eth_defines.
160
//
161 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
162
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
163
// MHz. Statuses, overrun, control frame transmission and reception still  need
164
// to be fixed.
165
//
166 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
167
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
168
// added.
169
//
170 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
171
// Initial version. Equals to eth_wishbonedma.v at this moment.
172 38 mohor
//
173
//
174
//
175
 
176
`include "eth_defines.v"
177
`include "timescale.v"
178
 
179
 
180
module eth_wishbone
181
   (
182
 
183
    // WISHBONE common
184 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
185 38 mohor
 
186
    // WISHBONE slave
187 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
188 40 mohor
    BDCs,
189 38 mohor
 
190 40 mohor
    Reset,
191
 
192 39 mohor
    // WISHBONE master
193
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
194
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
195
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
196
 
197 38 mohor
    //TX
198 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
199 150 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
200 38 mohor
    PerPacketPad,
201
 
202
    //RX
203 40 mohor
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
204 38 mohor
 
205
    // Register
206 150 mohor
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr,
207 38 mohor
 
208
    // Interrupts
209 150 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
210 42 mohor
 
211 60 mohor
    // Rx Status
212 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
213 77 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
214 60 mohor
 
215
    // Tx Status
216 164 mohor
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
217
 
218 210 mohor
    // Bist
219
`ifdef ETH_BIST
220
   , trst, SO, SI, shift_DR, capture_DR, extest, tck
221
`endif
222
 
223
 
224
 
225 38 mohor
                );
226
 
227
 
228
parameter Tp = 1;
229
 
230 150 mohor
 
231 38 mohor
// WISHBONE common
232
input           WB_CLK_I;       // WISHBONE clock
233
input  [31:0]   WB_DAT_I;       // WISHBONE data input
234
output [31:0]   WB_DAT_O;       // WISHBONE data output
235
 
236
// WISHBONE slave
237
input   [9:2]   WB_ADR_I;       // WISHBONE address input
238
input           WB_WE_I;        // WISHBONE write enable input
239
input           BDCs;           // Buffer descriptors are selected
240
output          WB_ACK_O;       // WISHBONE acknowledge output
241
 
242 39 mohor
// WISHBONE master
243
output  [31:0]  m_wb_adr_o;     // 
244
output   [3:0]  m_wb_sel_o;     // 
245
output          m_wb_we_o;      // 
246
output  [31:0]  m_wb_dat_o;     // 
247
output          m_wb_cyc_o;     // 
248
output          m_wb_stb_o;     // 
249
input   [31:0]  m_wb_dat_i;     // 
250
input           m_wb_ack_i;     // 
251
input           m_wb_err_i;     // 
252
 
253 40 mohor
input           Reset;       // Reset signal
254 39 mohor
 
255 60 mohor
// Rx Status signals
256 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
257
input           LatchedCrcError;  // CRC error
258
input           RxLateCollision;  // Late collision occured while receiving frame
259
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
260
input           DribbleNibble;    // Extra nibble received
261
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
262
input    [15:0] RxLength;         // Length of the incoming frame
263
input           LoadRxStatus;     // Rx status was loaded
264 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
265 39 mohor
 
266 60 mohor
// Tx Status signals
267
input     [3:0] RetryCntLatched;  // Latched Retry Counter
268
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
269
input           LateCollLatched;  // Late collision occured
270
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
271
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
272
 
273 38 mohor
// Tx
274
input           MTxClk;         // Transmit clock (from PHY)
275
input           TxUsedData;     // Transmit packet used data
276
input           TxRetry;        // Transmit packet retry
277
input           TxAbort;        // Transmit packet abort
278
input           TxDone;         // Transmission ended
279
output          TxStartFrm;     // Transmit packet start frame
280
output          TxEndFrm;       // Transmit packet end frame
281
output  [7:0]   TxData;         // Transmit packet data byte
282
output          TxUnderRun;     // Transmit packet under-run
283
output          PerPacketCrcEn; // Per packet crc enable
284
output          PerPacketPad;   // Per packet pading
285
 
286
// Rx
287
input           MRxClk;         // Receive clock (from PHY)
288
input   [7:0]   RxData;         // Received data byte (from PHY)
289
input           RxValid;        // 
290
input           RxStartFrm;     // 
291
input           RxEndFrm;       // 
292 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
293 38 mohor
 
294
//Register
295
input           r_TxEn;         // Transmit enable
296
input           r_RxEn;         // Receive enable
297
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
298
input           TX_BD_NUM_Wr;   // RxBDNumber written
299
 
300
// Interrupts
301
output TxB_IRQ;
302
output TxE_IRQ;
303
output RxB_IRQ;
304 77 mohor
output RxE_IRQ;
305 38 mohor
output Busy_IRQ;
306
 
307 77 mohor
 
308 210 mohor
// Bist
309
`ifdef ETH_BIST
310
input           trst;
311
input           shift_DR, capture_DR, tck, extest;
312
input           SI;
313
output          SO;
314
`endif
315
 
316 77 mohor
reg TxB_IRQ;
317
reg TxE_IRQ;
318
reg RxB_IRQ;
319
reg RxE_IRQ;
320
 
321 38 mohor
reg             TxStartFrm;
322
reg             TxEndFrm;
323
reg     [7:0]   TxData;
324
 
325
reg             TxUnderRun;
326 60 mohor
reg             TxUnderRun_wb;
327 38 mohor
 
328
reg             TxBDRead;
329 39 mohor
wire            TxStatusWrite;
330 38 mohor
 
331
reg     [1:0]   TxValidBytesLatched;
332
 
333
reg    [15:0]   TxLength;
334 60 mohor
reg    [15:0]   LatchedTxLength;
335
reg   [14:11]   TxStatus;
336 38 mohor
 
337 60 mohor
reg   [14:13]   RxStatus;
338 38 mohor
 
339
reg             TxStartFrm_wb;
340
reg             TxRetry_wb;
341 39 mohor
reg             TxAbort_wb;
342 38 mohor
reg             TxDone_wb;
343
 
344
reg             TxDone_wb_q;
345
reg             TxAbort_wb_q;
346 39 mohor
reg             TxRetry_wb_q;
347 105 mohor
reg             TxDone_wb_q2;
348
reg             TxAbort_wb_q2;
349
reg             TxRetry_wb_q2;
350 38 mohor
reg             RxBDReady;
351 166 mohor
reg             RxReady;
352 38 mohor
reg             TxBDReady;
353
 
354
reg             RxBDRead;
355 40 mohor
wire            RxStatusWrite;
356 38 mohor
 
357
reg    [31:0]   TxDataLatched;
358
reg     [1:0]   TxByteCnt;
359
reg             LastWord;
360 39 mohor
reg             ReadTxDataFromFifo_tck;
361 38 mohor
 
362
reg             BlockingTxStatusWrite;
363
reg             BlockingTxBDRead;
364
 
365 40 mohor
reg             Flop;
366 38 mohor
 
367
reg     [7:0]   TxBDAddress;
368
reg     [7:0]   RxBDAddress;
369
 
370
reg             TxRetrySync1;
371
reg             TxAbortSync1;
372 39 mohor
reg             TxDoneSync1;
373 38 mohor
 
374
reg             TxAbort_q;
375
reg             TxRetry_q;
376
reg             TxUsedData_q;
377
 
378
reg    [31:0]   RxDataLatched2;
379 82 mohor
 
380
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
381
 
382 38 mohor
reg     [1:0]   RxValidBytes;
383
reg     [1:0]   RxByteCnt;
384
reg             LastByteIn;
385
reg             ShiftWillEnd;
386
 
387 40 mohor
reg             WriteRxDataToFifo;
388 42 mohor
reg    [15:0]   LatchedRxLength;
389 64 mohor
reg             RxAbortLatched;
390 38 mohor
 
391 40 mohor
reg             ShiftEnded;
392 60 mohor
reg             RxOverrun;
393 38 mohor
 
394 40 mohor
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
395
reg             BDRead;                     // BD Read access from WISHBONE side
396 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
397
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
398 38 mohor
 
399 39 mohor
reg             TxEndFrm_wb;
400 38 mohor
 
401 39 mohor
wire            TxRetryPulse;
402 38 mohor
wire            TxDonePulse;
403
wire            TxAbortPulse;
404 105 mohor
wire            TxRetryPulse_q;
405
wire            TxDonePulse_q;
406
wire            TxAbortPulse_q;
407 38 mohor
 
408
wire            StartRxBDRead;
409
 
410
wire            StartTxBDRead;
411
 
412
wire            TxIRQEn;
413
wire            WrapTxStatusBit;
414
 
415 77 mohor
wire            RxIRQEn;
416 38 mohor
wire            WrapRxStatusBit;
417
 
418
wire    [1:0]   TxValidBytes;
419
 
420
wire    [7:0]   TempTxBDAddress;
421
wire    [7:0]   TempRxBDAddress;
422
 
423
wire            SetGotData;
424
wire            GotDataEvaluate;
425
 
426 106 mohor
reg             WB_ACK_O;
427 38 mohor
 
428 60 mohor
wire    [6:0]   RxStatusIn;
429
reg     [6:0]   RxStatusInLatched;
430 42 mohor
 
431 39 mohor
reg WbEn, WbEn_q;
432
reg RxEn, RxEn_q;
433
reg TxEn, TxEn_q;
434 38 mohor
 
435 39 mohor
wire ram_ce;
436
wire ram_we;
437
wire ram_oe;
438
reg [7:0]   ram_addr;
439
reg [31:0]  ram_di;
440
wire [31:0] ram_do;
441 38 mohor
 
442 39 mohor
wire StartTxPointerRead;
443
reg  TxPointerRead;
444
reg TxEn_needed;
445 40 mohor
reg RxEn_needed;
446 38 mohor
 
447 40 mohor
wire StartRxPointerRead;
448
reg RxPointerRead;
449 38 mohor
 
450 39 mohor
 
451 159 mohor
always @ (posedge WB_CLK_I)
452 40 mohor
begin
453 159 mohor
  WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
454 40 mohor
end
455 39 mohor
 
456 106 mohor
assign WB_DAT_O = ram_do;
457 39 mohor
 
458 41 mohor
// Generic synchronous single-port RAM interface
459 119 mohor
eth_spram_256x32 bd_ram (
460 210 mohor
  .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
461
`ifdef ETH_BIST
462
  , .trst(trst), .SO(SO), .SI(SI), .shift_DR(.shift_DR), .capture_DR(capture_DR), .extest(extest), .tck(tck)
463
`endif
464 39 mohor
);
465 41 mohor
 
466 39 mohor
assign ram_ce = 1'b1;
467 40 mohor
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
468 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
469 39 mohor
 
470
 
471 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
472 38 mohor
begin
473 40 mohor
  if(Reset)
474 39 mohor
    TxEn_needed <=#Tp 1'b0;
475 38 mohor
  else
476 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
477 39 mohor
    TxEn_needed <=#Tp 1'b1;
478
  else
479
  if(TxPointerRead & TxEn & TxEn_q)
480
    TxEn_needed <=#Tp 1'b0;
481 38 mohor
end
482
 
483 39 mohor
// Enabling access to the RAM for three devices.
484 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
485 39 mohor
begin
486 40 mohor
  if(Reset)
487 39 mohor
    begin
488
      WbEn <=#Tp 1'b1;
489
      RxEn <=#Tp 1'b0;
490
      TxEn <=#Tp 1'b0;
491
      ram_addr <=#Tp 8'h0;
492
      ram_di <=#Tp 32'h0;
493 77 mohor
      BDRead <=#Tp 1'b0;
494
      BDWrite <=#Tp 1'b0;
495 39 mohor
    end
496
  else
497
    begin
498
      // Switching between three stages depends on enable signals
499 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
500
        5'b100_10, 5'b100_11 :
501 39 mohor
          begin
502
            WbEn <=#Tp 1'b0;
503
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
504
            TxEn <=#Tp 1'b0;
505 40 mohor
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
506 39 mohor
            ram_di <=#Tp RxBDDataIn;
507
          end
508
        5'b100_01 :
509
          begin
510
            WbEn <=#Tp 1'b0;
511
            RxEn <=#Tp 1'b0;
512
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
513
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
514
            ram_di <=#Tp TxBDDataIn;
515
          end
516 90 mohor
        5'b010_00, 5'b010_10 :
517 39 mohor
          begin
518
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
519
            RxEn <=#Tp 1'b0;
520
            TxEn <=#Tp 1'b0;
521
            ram_addr <=#Tp WB_ADR_I[9:2];
522
            ram_di <=#Tp WB_DAT_I;
523 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
524
            BDRead <=#Tp BDCs & ~WB_WE_I;
525 39 mohor
          end
526 90 mohor
        5'b010_01, 5'b010_11 :
527 39 mohor
          begin
528
            WbEn <=#Tp 1'b0;
529
            RxEn <=#Tp 1'b0;
530
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
531
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
532
            ram_di <=#Tp TxBDDataIn;
533
          end
534 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
535 39 mohor
          begin
536
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
537
            RxEn <=#Tp 1'b0;
538
            TxEn <=#Tp 1'b0;
539
            ram_addr <=#Tp WB_ADR_I[9:2];
540
            ram_di <=#Tp WB_DAT_I;
541 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
542
            BDRead <=#Tp BDCs & ~WB_WE_I;
543 39 mohor
          end
544
        5'b100_00 :
545
          begin
546
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
547
          end
548
        5'b000_00 :
549
          begin
550
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
551
            RxEn <=#Tp 1'b0;
552
            TxEn <=#Tp 1'b0;
553
            ram_addr <=#Tp WB_ADR_I[9:2];
554
            ram_di <=#Tp WB_DAT_I;
555 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
556
            BDRead <=#Tp BDCs & ~WB_WE_I;
557 39 mohor
          end
558
      endcase
559
    end
560
end
561
 
562
 
563
// Delayed stage signals
564 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
565 39 mohor
begin
566 40 mohor
  if(Reset)
567 39 mohor
    begin
568
      WbEn_q <=#Tp 1'b0;
569
      RxEn_q <=#Tp 1'b0;
570
      TxEn_q <=#Tp 1'b0;
571
    end
572
  else
573
    begin
574
      WbEn_q <=#Tp WbEn;
575
      RxEn_q <=#Tp RxEn;
576
      TxEn_q <=#Tp TxEn;
577
    end
578
end
579
 
580 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
581 40 mohor
always @ (posedge MTxClk or posedge Reset)
582 38 mohor
begin
583 40 mohor
  if(Reset)
584 38 mohor
    Flop <=#Tp 1'b0;
585
  else
586
  if(TxDone | TxAbort | TxRetry_q)
587
    Flop <=#Tp 1'b0;
588
  else
589
  if(TxUsedData)
590
    Flop <=#Tp ~Flop;
591
end
592
 
593 39 mohor
wire ResetTxBDReady;
594
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
595 38 mohor
 
596
// Latching READY status of the Tx buffer descriptor
597 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
598 38 mohor
begin
599 40 mohor
  if(Reset)
600 38 mohor
    TxBDReady <=#Tp 1'b0;
601
  else
602 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
603
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
604
  else                                                // Only packets larger then 4 bytes are transmitted.
605 39 mohor
  if(ResetTxBDReady)
606 38 mohor
    TxBDReady <=#Tp 1'b0;
607
end
608
 
609
 
610 39 mohor
// Reading the Tx buffer descriptor
611 110 mohor
assign StartTxBDRead = (TxRetry_wb | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
612 39 mohor
 
613 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
614 38 mohor
begin
615 40 mohor
  if(Reset)
616 39 mohor
    TxBDRead <=#Tp 1'b1;
617 38 mohor
  else
618 110 mohor
  if(StartTxBDRead)
619 39 mohor
    TxBDRead <=#Tp 1'b1;
620 38 mohor
  else
621 39 mohor
  if(TxBDReady)
622
    TxBDRead <=#Tp 1'b0;
623 38 mohor
end
624
 
625
 
626 39 mohor
// Reading Tx BD pointer
627
assign StartTxPointerRead = TxBDRead & TxBDReady;
628 38 mohor
 
629 39 mohor
// Reading Tx BD Pointer
630 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
631 38 mohor
begin
632 40 mohor
  if(Reset)
633 39 mohor
    TxPointerRead <=#Tp 1'b0;
634 38 mohor
  else
635 39 mohor
  if(StartTxPointerRead)
636
    TxPointerRead <=#Tp 1'b1;
637 38 mohor
  else
638 39 mohor
  if(TxEn_q)
639
    TxPointerRead <=#Tp 1'b0;
640 38 mohor
end
641
 
642
 
643 39 mohor
// Writing status back to the Tx buffer descriptor
644
assign TxStatusWrite = (TxDone_wb | TxAbort_wb) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
645 38 mohor
 
646
 
647
 
648 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
649 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
650 38 mohor
begin
651 40 mohor
  if(Reset)
652 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
653 38 mohor
  else
654 39 mohor
  if(TxStatusWrite)
655
    BlockingTxStatusWrite <=#Tp 1'b1;
656 38 mohor
  else
657 39 mohor
  if(~TxDone_wb & ~TxAbort_wb)
658
    BlockingTxStatusWrite <=#Tp 1'b0;
659 38 mohor
end
660
 
661
 
662 159 mohor
reg BlockingTxStatusWrite_sync1;
663
reg BlockingTxStatusWrite_sync2;
664
 
665
// Synchronizing BlockingTxStatusWrite to MTxClk
666
always @ (posedge MTxClk or posedge Reset)
667
begin
668
  if(Reset)
669
    BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
670
  else
671
    BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
672
end
673
 
674
// Synchronizing BlockingTxStatusWrite to MTxClk
675
always @ (posedge MTxClk or posedge Reset)
676
begin
677
  if(Reset)
678
    BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
679
  else
680
    BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
681
end
682
 
683
 
684 39 mohor
// TxBDRead state is activated only once. 
685 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
686 39 mohor
begin
687 40 mohor
  if(Reset)
688 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
689
  else
690 110 mohor
  if(StartTxBDRead)
691 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
692
  else
693 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
694 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
695
end
696 38 mohor
 
697
 
698 39 mohor
// Latching status from the tx buffer descriptor
699
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
700 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
701 38 mohor
begin
702 40 mohor
  if(Reset)
703 60 mohor
    TxStatus <=#Tp 4'h0;
704 38 mohor
  else
705 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
706 60 mohor
    TxStatus <=#Tp ram_do[14:11];
707 38 mohor
end
708
 
709 40 mohor
reg ReadTxDataFromMemory;
710
wire WriteRxDataToMemory;
711 38 mohor
 
712 39 mohor
reg MasterWbTX;
713
reg MasterWbRX;
714
 
715
reg [31:0] m_wb_adr_o;
716
reg        m_wb_cyc_o;
717
reg        m_wb_stb_o;
718 96 mohor
reg  [3:0] m_wb_sel_o;
719 39 mohor
reg        m_wb_we_o;
720 40 mohor
 
721 39 mohor
wire TxLengthEq0;
722
wire TxLengthLt4;
723
 
724 150 mohor
reg BlockingIncrementTxPointer;
725 159 mohor
reg [31:2] TxPointerMSB;
726
reg [1:0]  TxPointerLSB;
727
reg [1:0]  TxPointerLSB_rst;
728
reg [31:2] RxPointerMSB;
729
reg [1:0]  RxPointerLSB_rst;
730 39 mohor
 
731 150 mohor
wire RxBurstAcc;
732
wire RxWordAcc;
733
wire RxHalfAcc;
734
wire RxByteAcc;
735
 
736 39 mohor
//Latching length from the buffer descriptor;
737 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
738 38 mohor
begin
739 40 mohor
  if(Reset)
740 39 mohor
    TxLength <=#Tp 16'h0;
741 38 mohor
  else
742 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
743
    TxLength <=#Tp ram_do[31:16];
744 38 mohor
  else
745 39 mohor
  if(MasterWbTX & m_wb_ack_i)
746
    begin
747
      if(TxLengthLt4)
748
        TxLength <=#Tp 16'h0;
749 150 mohor
      else
750 159 mohor
      if(TxPointerLSB_rst==2'h0)
751 96 mohor
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
752 39 mohor
      else
753 159 mohor
      if(TxPointerLSB_rst==2'h1)
754 150 mohor
        TxLength <=#Tp TxLength - 3'h3;    // Length is subtracted at the data request
755
      else
756 159 mohor
      if(TxPointerLSB_rst==2'h2)
757 150 mohor
        TxLength <=#Tp TxLength - 3'h2;    // Length is subtracted at the data request
758
      else
759 159 mohor
      if(TxPointerLSB_rst==2'h3)
760 150 mohor
        TxLength <=#Tp TxLength - 3'h1;    // Length is subtracted at the data request
761 39 mohor
    end
762 38 mohor
end
763
 
764 96 mohor
 
765
 
766 60 mohor
//Latching length from the buffer descriptor;
767
always @ (posedge WB_CLK_I or posedge Reset)
768
begin
769
  if(Reset)
770
    LatchedTxLength <=#Tp 16'h0;
771
  else
772
  if(TxEn & TxEn_q & TxBDRead)
773
    LatchedTxLength <=#Tp ram_do[31:16];
774
end
775
 
776 39 mohor
assign TxLengthEq0 = TxLength == 0;
777
assign TxLengthLt4 = TxLength < 4;
778 38 mohor
 
779 150 mohor
reg cyc_cleared;
780
reg IncrTxPointer;
781 39 mohor
 
782
 
783 159 mohor
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
784
// because TxPointerMSB is only used for word-aligned accesses.
785 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
786 38 mohor
begin
787 40 mohor
  if(Reset)
788 159 mohor
    TxPointerMSB <=#Tp 30'h0;
789 38 mohor
  else
790 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
791 159 mohor
    TxPointerMSB <=#Tp ram_do[31:2];
792 38 mohor
  else
793 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
794 159 mohor
    TxPointerMSB <=#Tp TxPointerMSB + 1'b1;     // TxPointer is word-aligned
795 38 mohor
end
796
 
797 96 mohor
 
798 159 mohor
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
799
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
800
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
801
// set by this two bits.
802 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
803
begin
804
  if(Reset)
805 159 mohor
    TxPointerLSB[1:0] <=#Tp 0;
806 96 mohor
  else
807
  if(TxEn & TxEn_q & TxPointerRead)
808 159 mohor
    TxPointerLSB[1:0] <=#Tp ram_do[1:0];
809 96 mohor
end
810
 
811
 
812 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
813
// After the read access, TxLength needs to be decremented for the number of the valid
814
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
815
// valid so this two bits are reset to zero. 
816 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
817
begin
818
  if(Reset)
819 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
820 150 mohor
  else
821
  if(TxEn & TxEn_q & TxPointerRead)
822 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
823 150 mohor
  else
824
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
825 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
826 150 mohor
end
827 96 mohor
 
828 150 mohor
 
829 159 mohor
reg  [3:0] RxByteSel;
830 39 mohor
wire MasterAccessFinished;
831 38 mohor
 
832 39 mohor
 
833 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
834 38 mohor
begin
835 40 mohor
  if(Reset)
836 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
837 38 mohor
  else
838 39 mohor
  if(MasterAccessFinished)
839
    BlockingIncrementTxPointer <=#Tp 0;
840 38 mohor
  else
841 150 mohor
  if(IncrTxPointer)
842 39 mohor
    BlockingIncrementTxPointer <=#Tp 1'b1;
843 38 mohor
end
844
 
845
 
846 39 mohor
wire TxBufferAlmostFull;
847
wire TxBufferFull;
848
wire TxBufferEmpty;
849
wire TxBufferAlmostEmpty;
850 40 mohor
wire ResetReadTxDataFromMemory;
851
wire SetReadTxDataFromMemory;
852 39 mohor
 
853 40 mohor
reg BlockReadTxDataFromMemory;
854 39 mohor
 
855 105 mohor
assign ResetReadTxDataFromMemory = (TxLengthEq0) | TxAbortPulse_q | TxRetryPulse_q;
856 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
857 39 mohor
 
858 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
859 38 mohor
begin
860 40 mohor
  if(Reset)
861
    ReadTxDataFromMemory <=#Tp 1'b0;
862 38 mohor
  else
863 40 mohor
  if(ResetReadTxDataFromMemory)
864
    ReadTxDataFromMemory <=#Tp 1'b0;
865 39 mohor
  else
866 40 mohor
  if(SetReadTxDataFromMemory)
867
    ReadTxDataFromMemory <=#Tp 1'b1;
868 38 mohor
end
869
 
870 40 mohor
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
871 39 mohor
wire [31:0] TxData_wb;
872
wire ReadTxDataFromFifo_wb;
873 38 mohor
 
874 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
875 38 mohor
begin
876 40 mohor
  if(Reset)
877
    BlockReadTxDataFromMemory <=#Tp 1'b0;
878 38 mohor
  else
879 90 mohor
  if(ReadTxDataFromFifo_wb | ResetReadTxDataFromMemory)
880 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b0;
881 38 mohor
  else
882 39 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX)
883 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
884 39 mohor
end
885
 
886
 
887
 
888
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
889 159 mohor
 
890 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
891 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
892 39 mohor
begin
893 40 mohor
  if(Reset)
894 38 mohor
    begin
895 39 mohor
      MasterWbTX <=#Tp 1'b0;
896
      MasterWbRX <=#Tp 1'b0;
897
      m_wb_adr_o <=#Tp 32'h0;
898
      m_wb_cyc_o <=#Tp 1'b0;
899
      m_wb_stb_o <=#Tp 1'b0;
900
      m_wb_we_o  <=#Tp 1'b0;
901 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
902 110 mohor
      cyc_cleared<=#Tp 1'b0;
903 150 mohor
      IncrTxPointer<=#Tp 1'b0;
904 38 mohor
    end
905 39 mohor
  else
906
    begin
907
      // Switching between two stages depends on enable signals
908 110 mohor
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared})  // synopsys parallel_case
909
        6'b00_01_0_x, 6'b00_11_0_x :
910 39 mohor
          begin
911
            MasterWbTX <=#Tp 1'b0;  // idle and master write is needed (data write to rx buffer)
912
            MasterWbRX <=#Tp 1'b1;
913 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
914 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
915
            m_wb_stb_o <=#Tp 1'b1;
916
            m_wb_we_o  <=#Tp 1'b1;
917 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
918 150 mohor
            IncrTxPointer<=#Tp 1'b0;
919 39 mohor
          end
920 110 mohor
        6'b00_10_0_x, 6'b00_10_1_x :
921 39 mohor
          begin
922
            MasterWbTX <=#Tp 1'b1;  // idle and master read is needed (data read from tx buffer)
923
            MasterWbRX <=#Tp 1'b0;
924 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
925 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
926
            m_wb_stb_o <=#Tp 1'b1;
927
            m_wb_we_o  <=#Tp 1'b0;
928 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
929
            IncrTxPointer<=#Tp 1'b1;
930 39 mohor
          end
931 110 mohor
        6'b10_10_0_1 :
932 39 mohor
          begin
933
            MasterWbTX <=#Tp 1'b1;  // master read and master read is needed (data read from tx buffer)
934
            MasterWbRX <=#Tp 1'b0;
935 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
936 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
937
            m_wb_stb_o <=#Tp 1'b1;
938
            m_wb_we_o  <=#Tp 1'b0;
939 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
940 110 mohor
            cyc_cleared<=#Tp 1'b0;
941 150 mohor
            IncrTxPointer<=#Tp 1'b1;
942 39 mohor
          end
943 110 mohor
        6'b01_01_0_1 :
944 39 mohor
          begin
945
            MasterWbTX <=#Tp 1'b0;  // master write and master write is needed (data write to rx buffer)
946
            MasterWbRX <=#Tp 1'b1;
947 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
948 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
949
            m_wb_stb_o <=#Tp 1'b1;
950 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
951 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
952 110 mohor
            cyc_cleared<=#Tp 1'b0;
953 150 mohor
            IncrTxPointer<=#Tp 1'b0;
954 39 mohor
          end
955 110 mohor
        6'b10_01_0_1, 6'b10_11_0_1 :
956 39 mohor
          begin
957
            MasterWbTX <=#Tp 1'b0;  // master read and master write is needed (data write to rx buffer)
958
            MasterWbRX <=#Tp 1'b1;
959 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
960 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
961
            m_wb_stb_o <=#Tp 1'b1;
962 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
963 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
964 110 mohor
            cyc_cleared<=#Tp 1'b0;
965 150 mohor
            IncrTxPointer<=#Tp 1'b0;
966 39 mohor
          end
967 111 mohor
        6'b01_10_0_1, 6'b01_11_0_1 :
968 39 mohor
          begin
969
            MasterWbTX <=#Tp 1'b1;  // master write and master read is needed (data read from tx buffer)
970
            MasterWbRX <=#Tp 1'b0;
971 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
972 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
973
            m_wb_stb_o <=#Tp 1'b1;
974 39 mohor
            m_wb_we_o  <=#Tp 1'b0;
975 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
976 110 mohor
            cyc_cleared<=#Tp 1'b0;
977 150 mohor
            IncrTxPointer<=#Tp 1'b1;
978 39 mohor
          end
979 110 mohor
        6'b10_10_1_0, 6'b01_01_1_0, 6'b10_01_1_0, 6'b10_11_1_0, 6'b01_10_1_0, 6'b01_11_1_0 :
980 39 mohor
          begin
981 110 mohor
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
982
            m_wb_stb_o <=#Tp 1'b0;
983
            cyc_cleared<=#Tp 1'b1;
984 150 mohor
            IncrTxPointer<=#Tp 1'b0;
985 110 mohor
          end
986
        6'b10_00_1_x, 6'b01_00_1_x :
987
          begin
988 39 mohor
            MasterWbTX <=#Tp 1'b0;  // whatever and no master read or write is needed (ack or err comes finishing previous access)
989
            MasterWbRX <=#Tp 1'b0;
990
            m_wb_cyc_o <=#Tp 1'b0;
991
            m_wb_stb_o <=#Tp 1'b0;
992 150 mohor
            IncrTxPointer<=#Tp 1'b0;
993 39 mohor
          end
994 127 mohor
        6'b10_00_0_1, 6'b01_00_0_1 :
995
          begin
996
            MasterWbTX <=#Tp 1'b0;  // Between cyc_cleared request was cleared
997
            MasterWbRX <=#Tp 1'b0;
998
            m_wb_cyc_o <=#Tp 1'b0;
999
            m_wb_stb_o <=#Tp 1'b0;
1000 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1001 127 mohor
          end
1002 82 mohor
        default:                            // Don't touch
1003
          begin
1004
            MasterWbTX <=#Tp MasterWbTX;
1005
            MasterWbRX <=#Tp MasterWbRX;
1006
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
1007
            m_wb_stb_o <=#Tp m_wb_stb_o;
1008 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
1009 150 mohor
            IncrTxPointer<=#Tp IncrTxPointer;
1010 82 mohor
          end
1011 39 mohor
      endcase
1012
    end
1013 38 mohor
end
1014
 
1015 110 mohor
 
1016 39 mohor
wire TxFifoClear;
1017 96 mohor
 
1018 39 mohor
assign TxFifoClear = (TxAbort_wb | TxRetry_wb) & ~TxBDReady;
1019 150 mohor
wire [4:0] txfifo_cnt;
1020 38 mohor
 
1021 40 mohor
eth_fifo #(`TX_FIFO_DATA_WIDTH, `TX_FIFO_DEPTH, `TX_FIFO_CNT_WIDTH)
1022 150 mohor
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
1023 96 mohor
          .clk(WB_CLK_I),                                   .reset(Reset),
1024 150 mohor
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb),
1025 96 mohor
          .clear(TxFifoClear),                              .full(TxBufferFull),
1026
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
1027 150 mohor
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
1028 96 mohor
        );
1029 39 mohor
 
1030
 
1031
reg StartOccured;
1032
reg TxStartFrm_sync1;
1033
reg TxStartFrm_sync2;
1034
reg TxStartFrm_syncb1;
1035
reg TxStartFrm_syncb2;
1036
 
1037
 
1038
 
1039
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1040 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1041 38 mohor
begin
1042 40 mohor
  if(Reset)
1043 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
1044 38 mohor
  else
1045 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1046
    TxStartFrm_wb <=#Tp 1'b1;
1047 38 mohor
  else
1048 39 mohor
  if(TxStartFrm_syncb2)
1049
    TxStartFrm_wb <=#Tp 1'b0;
1050 38 mohor
end
1051
 
1052 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1053 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1054 38 mohor
begin
1055 40 mohor
  if(Reset)
1056 39 mohor
    StartOccured <=#Tp 1'b0;
1057 38 mohor
  else
1058 39 mohor
  if(TxStartFrm_wb)
1059
    StartOccured <=#Tp 1'b1;
1060 38 mohor
  else
1061 39 mohor
  if(ResetTxBDReady)
1062
    StartOccured <=#Tp 1'b0;
1063 38 mohor
end
1064
 
1065 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1066 40 mohor
always @ (posedge MTxClk or posedge Reset)
1067 39 mohor
begin
1068 40 mohor
  if(Reset)
1069 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1070
  else
1071
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1072
end
1073 38 mohor
 
1074 40 mohor
always @ (posedge MTxClk or posedge Reset)
1075 39 mohor
begin
1076 40 mohor
  if(Reset)
1077 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1078
  else
1079
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1080
end
1081
 
1082 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1083 38 mohor
begin
1084 40 mohor
  if(Reset)
1085 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1086 38 mohor
  else
1087 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1088 38 mohor
end
1089
 
1090 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1091 38 mohor
begin
1092 40 mohor
  if(Reset)
1093 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1094 38 mohor
  else
1095 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1096
end
1097
 
1098 40 mohor
always @ (posedge MTxClk or posedge Reset)
1099 39 mohor
begin
1100 40 mohor
  if(Reset)
1101 39 mohor
    TxStartFrm <=#Tp 1'b0;
1102 38 mohor
  else
1103 39 mohor
  if(TxStartFrm_sync2)
1104 61 mohor
    TxStartFrm <=#Tp 1'b1;
1105 39 mohor
  else
1106 61 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry | TxAbort))
1107 39 mohor
    TxStartFrm <=#Tp 1'b0;
1108 38 mohor
end
1109 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1110 38 mohor
 
1111
 
1112 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1113 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1114 38 mohor
begin
1115 40 mohor
  if(Reset)
1116 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1117 38 mohor
  else
1118 39 mohor
  if(TxLengthLt4 & TxBufferAlmostEmpty & TxUsedData)
1119
    TxEndFrm_wb <=#Tp 1'b1;
1120 38 mohor
  else
1121 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1122
    TxEndFrm_wb <=#Tp 1'b0;
1123 38 mohor
end
1124
 
1125
 
1126
// Marks which bytes are valid within the word.
1127 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1128 38 mohor
 
1129 39 mohor
reg LatchValidBytes;
1130
reg LatchValidBytes_q;
1131 38 mohor
 
1132 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1133 38 mohor
begin
1134 40 mohor
  if(Reset)
1135 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1136 38 mohor
  else
1137 39 mohor
  if(TxLengthLt4 & TxBDReady)
1138
    LatchValidBytes <=#Tp 1'b1;
1139 38 mohor
  else
1140 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1141 38 mohor
end
1142
 
1143 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1144 38 mohor
begin
1145 40 mohor
  if(Reset)
1146 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1147 38 mohor
  else
1148 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1149 38 mohor
end
1150
 
1151
 
1152 39 mohor
// Latching valid bytes
1153 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1154 38 mohor
begin
1155 40 mohor
  if(Reset)
1156 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1157 38 mohor
  else
1158 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1159
    TxValidBytesLatched <=#Tp TxValidBytes;
1160
  else
1161
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1162
    TxValidBytesLatched <=#Tp 2'h0;
1163 38 mohor
end
1164
 
1165
 
1166
assign TxIRQEn          = TxStatus[14];
1167 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1168
assign PerPacketPad     = TxStatus[12];
1169
assign PerPacketCrcEn   = TxStatus[11];
1170 38 mohor
 
1171
 
1172 77 mohor
assign RxIRQEn         = RxStatus[14];
1173 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1174 38 mohor
 
1175
 
1176
// Temporary Tx and Rx buffer descriptor address 
1177 39 mohor
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
1178 134 mohor
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1)     | // Using first Rx BD
1179 39 mohor
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
1180 38 mohor
 
1181
 
1182
// Latching Tx buffer descriptor address
1183 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1184 38 mohor
begin
1185 40 mohor
  if(Reset)
1186 38 mohor
    TxBDAddress <=#Tp 8'h0;
1187
  else
1188
  if(TxStatusWrite)
1189
    TxBDAddress <=#Tp TempTxBDAddress;
1190
end
1191
 
1192
 
1193
// Latching Rx buffer descriptor address
1194 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1195 38 mohor
begin
1196 40 mohor
  if(Reset)
1197 134 mohor
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1;
1198 38 mohor
  else
1199 77 mohor
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
1200 134 mohor
    RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
1201 38 mohor
  else
1202
  if(RxStatusWrite)
1203
    RxBDAddress <=#Tp TempRxBDAddress;
1204
end
1205
 
1206 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1207 38 mohor
 
1208 60 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 6'h0, RxStatusInLatched};
1209
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1210 38 mohor
 
1211 60 mohor
 
1212 38 mohor
// Signals used for various purposes
1213 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1214 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1215
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1216 105 mohor
assign TxRetryPulse_q = TxRetry_wb_q & ~TxRetry_wb_q2;
1217
assign TxDonePulse_q  = TxDone_wb_q  & ~TxDone_wb_q2;
1218
assign TxAbortPulse_q = TxAbort_wb_q & ~TxAbort_wb_q2;
1219 38 mohor
 
1220
 
1221
 
1222 39 mohor
// Generating delayed signals
1223 40 mohor
always @ (posedge MTxClk or posedge Reset)
1224 38 mohor
begin
1225 40 mohor
  if(Reset)
1226 39 mohor
    begin
1227
      TxAbort_q      <=#Tp 1'b0;
1228
      TxRetry_q      <=#Tp 1'b0;
1229
      TxUsedData_q   <=#Tp 1'b0;
1230
    end
1231 38 mohor
  else
1232 39 mohor
    begin
1233
      TxAbort_q      <=#Tp TxAbort;
1234
      TxRetry_q      <=#Tp TxRetry;
1235
      TxUsedData_q   <=#Tp TxUsedData;
1236
    end
1237 38 mohor
end
1238
 
1239
// Generating delayed signals
1240 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1241 38 mohor
begin
1242 40 mohor
  if(Reset)
1243 38 mohor
    begin
1244 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1245
      TxAbort_wb_q  <=#Tp 1'b0;
1246 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1247 105 mohor
      TxDone_wb_q2  <=#Tp 1'b0;
1248
      TxAbort_wb_q2 <=#Tp 1'b0;
1249
      TxRetry_wb_q2 <=#Tp 1'b0;
1250 38 mohor
    end
1251
  else
1252
    begin
1253 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1254
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1255 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1256 105 mohor
      TxDone_wb_q2  <=#Tp TxDone_wb_q;
1257
      TxAbort_wb_q2 <=#Tp TxAbort_wb_q;
1258
      TxRetry_wb_q2 <=#Tp TxRetry_wb_q;
1259 38 mohor
    end
1260
end
1261
 
1262
 
1263
// Sinchronizing and evaluating tx data
1264 39 mohor
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
1265
assign SetGotData = (TxStartFrm_wb); // igor namesto zgornje
1266 38 mohor
 
1267
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
1268 40 mohor
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1269
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1270 38 mohor
 
1271
 
1272
// Indication of the last word
1273 40 mohor
always @ (posedge MTxClk or posedge Reset)
1274 38 mohor
begin
1275 40 mohor
  if(Reset)
1276 38 mohor
    LastWord <=#Tp 1'b0;
1277
  else
1278
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1279
    LastWord <=#Tp 1'b0;
1280
  else
1281
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1282 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1283 38 mohor
end
1284
 
1285
 
1286
// Tx end frame generation
1287 40 mohor
always @ (posedge MTxClk or posedge Reset)
1288 38 mohor
begin
1289 40 mohor
  if(Reset)
1290 38 mohor
    TxEndFrm <=#Tp 1'b0;
1291
  else
1292 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1293 38 mohor
    TxEndFrm <=#Tp 1'b0;
1294
  else
1295
  if(Flop & LastWord)
1296
    begin
1297 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1298 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1299
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1300
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1301
 
1302
        default : TxEndFrm <=#Tp 1'b0;
1303
      endcase
1304
    end
1305
end
1306
 
1307
 
1308
// Tx data selection (latching)
1309 40 mohor
always @ (posedge MTxClk or posedge Reset)
1310 38 mohor
begin
1311 40 mohor
  if(Reset)
1312 96 mohor
    TxData <=#Tp 0;
1313 38 mohor
  else
1314 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1315 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1316 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1317
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1318
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1319
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1320
    endcase
1321 38 mohor
  else
1322 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1323 96 mohor
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1324
  else
1325 38 mohor
  if(TxUsedData & Flop)
1326
    begin
1327 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1328 82 mohor
 
1329
        1 : TxData <=#Tp TxDataLatched[23:16];
1330
        2 : TxData <=#Tp TxDataLatched[15:8];
1331
        3 : TxData <=#Tp TxDataLatched[7:0];
1332 38 mohor
      endcase
1333
    end
1334
end
1335
 
1336
 
1337
// Latching tx data
1338 40 mohor
always @ (posedge MTxClk or posedge Reset)
1339 38 mohor
begin
1340 40 mohor
  if(Reset)
1341 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1342
  else
1343 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1344 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1345 38 mohor
end
1346
 
1347
 
1348
// Tx under run
1349 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1350 38 mohor
begin
1351 40 mohor
  if(Reset)
1352 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1353 38 mohor
  else
1354 39 mohor
  if(TxAbortPulse)
1355 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1356
  else
1357
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1358
    TxUnderRun_wb <=#Tp 1'b1;
1359
end
1360
 
1361
 
1362 159 mohor
reg TxUnderRun_sync1;
1363
 
1364 60 mohor
// Tx under run
1365
always @ (posedge MTxClk or posedge Reset)
1366
begin
1367
  if(Reset)
1368 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b0;
1369 43 mohor
  else
1370 60 mohor
  if(TxUnderRun_wb)
1371 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b1;
1372 60 mohor
  else
1373 159 mohor
  if(BlockingTxStatusWrite_sync2)
1374
    TxUnderRun_sync1 <=#Tp 1'b0;
1375
end
1376
 
1377
// Tx under run
1378
always @ (posedge MTxClk or posedge Reset)
1379
begin
1380
  if(Reset)
1381 60 mohor
    TxUnderRun <=#Tp 1'b0;
1382 159 mohor
  else
1383
  if(BlockingTxStatusWrite_sync2)
1384
    TxUnderRun <=#Tp 1'b0;
1385
  else
1386
  if(TxUnderRun_sync1)
1387
    TxUnderRun <=#Tp 1'b1;
1388 38 mohor
end
1389
 
1390
 
1391
// Tx Byte counter
1392 40 mohor
always @ (posedge MTxClk or posedge Reset)
1393 38 mohor
begin
1394 40 mohor
  if(Reset)
1395 38 mohor
    TxByteCnt <=#Tp 2'h0;
1396
  else
1397
  if(TxAbort_q | TxRetry_q)
1398
    TxByteCnt <=#Tp 2'h0;
1399
  else
1400
  if(TxStartFrm & ~TxUsedData)
1401 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1402 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1403
      2'h1 : TxByteCnt <=#Tp 2'h2;
1404
      2'h2 : TxByteCnt <=#Tp 2'h3;
1405
      2'h3 : TxByteCnt <=#Tp 2'h0;
1406
    endcase
1407 38 mohor
  else
1408
  if(TxUsedData & Flop)
1409 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1410 38 mohor
end
1411
 
1412 39 mohor
 
1413 150 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1414
reg ReadTxDataFromFifo_sync1;
1415
reg ReadTxDataFromFifo_sync2;
1416
reg ReadTxDataFromFifo_sync3;
1417
reg ReadTxDataFromFifo_syncb1;
1418
reg ReadTxDataFromFifo_syncb2;
1419
reg ReadTxDataFromFifo_syncb3;
1420
 
1421
 
1422
always @ (posedge MTxClk or posedge Reset)
1423
begin
1424
  if(Reset)
1425
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1426
  else
1427 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1428 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1429 150 mohor
  else
1430
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1431
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1432 38 mohor
end
1433
 
1434 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1435 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1436 38 mohor
begin
1437 40 mohor
  if(Reset)
1438 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1439 38 mohor
  else
1440 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1441
end
1442 38 mohor
 
1443 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1444 38 mohor
begin
1445 40 mohor
  if(Reset)
1446 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1447 38 mohor
  else
1448 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1449 38 mohor
end
1450
 
1451 40 mohor
always @ (posedge MTxClk or posedge Reset)
1452 38 mohor
begin
1453 40 mohor
  if(Reset)
1454 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1455 38 mohor
  else
1456 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1457 38 mohor
end
1458
 
1459 40 mohor
always @ (posedge MTxClk or posedge Reset)
1460 38 mohor
begin
1461 40 mohor
  if(Reset)
1462 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1463 38 mohor
  else
1464 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1465 38 mohor
end
1466
 
1467 150 mohor
always @ (posedge MTxClk or posedge Reset)
1468
begin
1469
  if(Reset)
1470
    ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
1471
  else
1472
    ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
1473
end
1474
 
1475 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1476 38 mohor
begin
1477 40 mohor
  if(Reset)
1478 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1479 38 mohor
  else
1480 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1481 38 mohor
end
1482
 
1483 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1484
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1485 38 mohor
 
1486
 
1487 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1488 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1489 38 mohor
begin
1490 40 mohor
  if(Reset)
1491 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1492 38 mohor
  else
1493 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1494 38 mohor
end
1495
 
1496 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1497 38 mohor
begin
1498 40 mohor
  if(Reset)
1499 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1500 38 mohor
  else
1501 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1502 38 mohor
end
1503
 
1504
 
1505 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1506 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1507 38 mohor
begin
1508 40 mohor
  if(Reset)
1509 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1510 38 mohor
  else
1511 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1512 38 mohor
end
1513
 
1514 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1515 38 mohor
begin
1516 40 mohor
  if(Reset)
1517 39 mohor
    TxDone_wb <=#Tp 1'b0;
1518 38 mohor
  else
1519 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1520 38 mohor
end
1521
 
1522 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1523 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1524 38 mohor
begin
1525 40 mohor
  if(Reset)
1526 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1527 38 mohor
  else
1528 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1529 38 mohor
end
1530
 
1531 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1532 38 mohor
begin
1533 40 mohor
  if(Reset)
1534 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1535
  else
1536 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1537 38 mohor
end
1538
 
1539
 
1540 150 mohor
reg RxAbortSync1;
1541
reg RxAbortSync2;
1542
reg RxAbortSync3;
1543
reg RxAbortSync4;
1544
reg RxAbortSyncb1;
1545
reg RxAbortSyncb2;
1546 39 mohor
 
1547 150 mohor
//assign StartRxBDRead = RxStatusWrite | RxAbortLatched;
1548
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
1549
 
1550 40 mohor
// Reading the Rx buffer descriptor
1551
always @ (posedge WB_CLK_I or posedge Reset)
1552
begin
1553
  if(Reset)
1554
    RxBDRead <=#Tp 1'b1;
1555
  else
1556 166 mohor
  if(StartRxBDRead & ~RxReady)
1557 40 mohor
    RxBDRead <=#Tp 1'b1;
1558
  else
1559
  if(RxBDReady)
1560
    RxBDRead <=#Tp 1'b0;
1561
end
1562 39 mohor
 
1563
 
1564 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1565
// written to the previous one.
1566
 
1567
// Latching READY status of the Rx buffer descriptor
1568 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1569 38 mohor
begin
1570 40 mohor
  if(Reset)
1571 38 mohor
    RxBDReady <=#Tp 1'b0;
1572
  else
1573 166 mohor
  if(RxPointerRead)
1574 150 mohor
    RxBDReady <=#Tp 1'b0;
1575
  else
1576 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1577
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1578 38 mohor
end
1579
 
1580 40 mohor
// Latching Rx buffer descriptor status
1581
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1582
always @ (posedge WB_CLK_I or posedge Reset)
1583 38 mohor
begin
1584 40 mohor
  if(Reset)
1585 60 mohor
    RxStatus <=#Tp 2'h0;
1586 38 mohor
  else
1587 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1588 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1589 38 mohor
end
1590
 
1591
 
1592 166 mohor
// RxReady generation
1593
always @ (posedge WB_CLK_I or posedge Reset)
1594
begin
1595
  if(Reset)
1596
    RxReady <=#Tp 1'b0;
1597
  else
1598
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
1599
    RxReady <=#Tp 1'b0;
1600
  else
1601
  if(RxEn & RxEn_q & RxPointerRead)
1602
    RxReady <=#Tp 1'b1;
1603
end
1604 38 mohor
 
1605
 
1606 40 mohor
// Reading Rx BD pointer
1607
 
1608
 
1609
assign StartRxPointerRead = RxBDRead & RxBDReady;
1610
 
1611
// Reading Tx BD Pointer
1612
always @ (posedge WB_CLK_I or posedge Reset)
1613 38 mohor
begin
1614 40 mohor
  if(Reset)
1615
    RxPointerRead <=#Tp 1'b0;
1616 38 mohor
  else
1617 40 mohor
  if(StartRxPointerRead)
1618
    RxPointerRead <=#Tp 1'b1;
1619 38 mohor
  else
1620 166 mohor
  if(RxEn & RxEn_q)
1621 40 mohor
    RxPointerRead <=#Tp 1'b0;
1622 38 mohor
end
1623
 
1624 113 mohor
 
1625 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1626
always @ (posedge WB_CLK_I or posedge Reset)
1627
begin
1628
  if(Reset)
1629 159 mohor
    RxPointerMSB <=#Tp 30'h0;
1630 40 mohor
  else
1631
  if(RxEn & RxEn_q & RxPointerRead)
1632 159 mohor
    RxPointerMSB <=#Tp ram_do[31:2];
1633 40 mohor
  else
1634 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1635 159 mohor
      RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1636 40 mohor
end
1637 38 mohor
 
1638
 
1639 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1640 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1641
begin
1642
  if(Reset)
1643 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp 0;
1644 96 mohor
  else
1645 159 mohor
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
1646
    RxPointerLSB_rst[1:0] <=#Tp 0;
1647 96 mohor
  else
1648
  if(RxEn & RxEn_q & RxPointerRead)
1649 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
1650 96 mohor
end
1651
 
1652
 
1653 159 mohor
always @ (RxPointerLSB_rst)
1654 96 mohor
begin
1655 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1656
    2'h0 : RxByteSel[3:0] = 4'hf;
1657
    2'h1 : RxByteSel[3:0] = 4'h7;
1658
    2'h2 : RxByteSel[3:0] = 4'h3;
1659
    2'h3 : RxByteSel[3:0] = 4'h1;
1660 96 mohor
  endcase
1661
end
1662
 
1663
 
1664
always @ (posedge WB_CLK_I or posedge Reset)
1665
begin
1666
  if(Reset)
1667 40 mohor
    RxEn_needed <=#Tp 1'b0;
1668 38 mohor
  else
1669 166 mohor
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1670 40 mohor
    RxEn_needed <=#Tp 1'b1;
1671 38 mohor
  else
1672 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1673
    RxEn_needed <=#Tp 1'b0;
1674 38 mohor
end
1675
 
1676
 
1677 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1678
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1679 38 mohor
 
1680 42 mohor
reg RxStatusWriteLatched;
1681
reg RxStatusWrite_rck;
1682
 
1683
always @ (posedge WB_CLK_I or posedge Reset)
1684
begin
1685
  if(Reset)
1686
    RxStatusWriteLatched <=#Tp 1'b0;
1687
  else
1688 87 mohor
  if(RxStatusWrite & ~RxStatusWrite_rck)
1689 42 mohor
    RxStatusWriteLatched <=#Tp 1'b1;
1690
  else
1691
  if(RxStatusWrite_rck)
1692
    RxStatusWriteLatched <=#Tp 1'b0;
1693
end
1694
 
1695
 
1696
always @ (posedge MRxClk or posedge Reset)
1697
begin
1698
  if(Reset)
1699
    RxStatusWrite_rck <=#Tp 1'b0;
1700
  else
1701 87 mohor
  if(RxStatusWriteLatched)
1702
    RxStatusWrite_rck <=#Tp 1'b1;
1703
  else
1704
    RxStatusWrite_rck <=#Tp 1'b0;
1705 42 mohor
end
1706
 
1707
 
1708 40 mohor
reg RxEnableWindow;
1709 38 mohor
 
1710
// Indicating that last byte is being reveived
1711 40 mohor
always @ (posedge MRxClk or posedge Reset)
1712 38 mohor
begin
1713 40 mohor
  if(Reset)
1714 38 mohor
    LastByteIn <=#Tp 1'b0;
1715
  else
1716 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1717 38 mohor
    LastByteIn <=#Tp 1'b0;
1718
  else
1719 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1720 38 mohor
    LastByteIn <=#Tp 1'b1;
1721
end
1722
 
1723 159 mohor
reg ShiftEnded_rck;
1724 40 mohor
reg ShiftEndedSync1;
1725
reg ShiftEndedSync2;
1726 118 mohor
reg ShiftEndedSync3;
1727
reg ShiftEndedSync_c1;
1728
reg ShiftEndedSync_c2;
1729
 
1730 40 mohor
wire StartShiftWillEnd;
1731 96 mohor
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1732 38 mohor
 
1733
// Indicating that data reception will end
1734 40 mohor
always @ (posedge MRxClk or posedge Reset)
1735 38 mohor
begin
1736 40 mohor
  if(Reset)
1737 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1738
  else
1739 159 mohor
  if(ShiftEnded_rck | RxAbort)
1740 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1741
  else
1742 40 mohor
  if(StartShiftWillEnd)
1743 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
1744
end
1745
 
1746
 
1747 40 mohor
 
1748 38 mohor
// Receive byte counter
1749 40 mohor
always @ (posedge MRxClk or posedge Reset)
1750 38 mohor
begin
1751 40 mohor
  if(Reset)
1752 38 mohor
    RxByteCnt <=#Tp 2'h0;
1753
  else
1754 159 mohor
  if(ShiftEnded_rck | RxAbort)
1755 38 mohor
    RxByteCnt <=#Tp 2'h0;
1756 97 lampret
  else
1757 166 mohor
  if(RxValid & RxStartFrm & RxReady)
1758 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
1759 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
1760
      2'h1 : RxByteCnt <=#Tp 2'h2;
1761
      2'h2 : RxByteCnt <=#Tp 2'h3;
1762
      2'h3 : RxByteCnt <=#Tp 2'h0;
1763
    endcase
1764 38 mohor
  else
1765 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
1766 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
1767 38 mohor
end
1768
 
1769
 
1770
// Indicates how many bytes are valid within the last word
1771 40 mohor
always @ (posedge MRxClk or posedge Reset)
1772 38 mohor
begin
1773 40 mohor
  if(Reset)
1774 38 mohor
    RxValidBytes <=#Tp 2'h1;
1775
  else
1776 96 mohor
  if(RxValid & RxStartFrm)
1777 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
1778 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
1779
      2'h1 : RxValidBytes <=#Tp 2'h2;
1780
      2'h2 : RxValidBytes <=#Tp 2'h3;
1781
      2'h3 : RxValidBytes <=#Tp 2'h0;
1782
    endcase
1783 38 mohor
  else
1784 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
1785 38 mohor
    RxValidBytes <=#Tp RxValidBytes + 1;
1786
end
1787
 
1788
 
1789 40 mohor
always @ (posedge MRxClk or posedge Reset)
1790 38 mohor
begin
1791 40 mohor
  if(Reset)
1792
    RxDataLatched1       <=#Tp 24'h0;
1793 38 mohor
  else
1794 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
1795 96 mohor
    if(RxStartFrm)
1796 40 mohor
    begin
1797 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
1798 96 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
1799
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
1800
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
1801
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
1802
      endcase
1803
    end
1804
    else if (RxEnableWindow)
1805
    begin
1806 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
1807 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
1808
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
1809
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
1810 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
1811
      endcase
1812
    end
1813 38 mohor
end
1814
 
1815 40 mohor
wire SetWriteRxDataToFifo;
1816 38 mohor
 
1817 40 mohor
// Assembling data that will be written to the rx_fifo
1818
always @ (posedge MRxClk or posedge Reset)
1819 38 mohor
begin
1820 40 mohor
  if(Reset)
1821
    RxDataLatched2 <=#Tp 32'h0;
1822 38 mohor
  else
1823 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
1824 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
1825 38 mohor
  else
1826 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
1827 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
1828 82 mohor
 
1829
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
1830
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
1831
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
1832 40 mohor
    endcase
1833 38 mohor
end
1834
 
1835
 
1836 40 mohor
reg WriteRxDataToFifoSync1;
1837
reg WriteRxDataToFifoSync2;
1838 150 mohor
reg WriteRxDataToFifoSync3;
1839 38 mohor
 
1840
 
1841 40 mohor
// Indicating start of the reception process
1842 166 mohor
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
1843
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
1844
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
1845 38 mohor
 
1846 150 mohor
always @ (posedge MRxClk or posedge Reset)
1847
begin
1848
  if(Reset)
1849
    WriteRxDataToFifo <=#Tp 1'b0;
1850
  else
1851
  if(SetWriteRxDataToFifo & ~RxAbort)
1852
    WriteRxDataToFifo <=#Tp 1'b1;
1853
  else
1854
  if(WriteRxDataToFifoSync2 | RxAbort)
1855
    WriteRxDataToFifo <=#Tp 1'b0;
1856
end
1857 40 mohor
 
1858 150 mohor
 
1859
 
1860
always @ (posedge WB_CLK_I or posedge Reset)
1861
begin
1862
  if(Reset)
1863
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
1864
  else
1865
  if(WriteRxDataToFifo)
1866
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
1867
  else
1868
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
1869
end
1870
 
1871
always @ (posedge WB_CLK_I or posedge Reset)
1872
begin
1873
  if(Reset)
1874
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
1875
  else
1876
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
1877
end
1878
 
1879
always @ (posedge WB_CLK_I or posedge Reset)
1880
begin
1881
  if(Reset)
1882
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
1883
  else
1884
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
1885
end
1886
 
1887
wire WriteRxDataToFifo_wb;
1888
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
1889
 
1890
 
1891 90 mohor
reg LatchedRxStartFrm;
1892
reg SyncRxStartFrm;
1893
reg SyncRxStartFrm_q;
1894 150 mohor
reg SyncRxStartFrm_q2;
1895 90 mohor
wire RxFifoReset;
1896 40 mohor
 
1897 90 mohor
always @ (posedge MRxClk or posedge Reset)
1898
begin
1899
  if(Reset)
1900
    LatchedRxStartFrm <=#Tp 0;
1901
  else
1902 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
1903 90 mohor
    LatchedRxStartFrm <=#Tp 1;
1904
  else
1905 150 mohor
  if(SyncRxStartFrm_q)
1906 90 mohor
    LatchedRxStartFrm <=#Tp 0;
1907
end
1908
 
1909
 
1910
always @ (posedge WB_CLK_I or posedge Reset)
1911
begin
1912
  if(Reset)
1913
    SyncRxStartFrm <=#Tp 0;
1914
  else
1915
  if(LatchedRxStartFrm)
1916
    SyncRxStartFrm <=#Tp 1;
1917
  else
1918
    SyncRxStartFrm <=#Tp 0;
1919
end
1920
 
1921
 
1922
always @ (posedge WB_CLK_I or posedge Reset)
1923
begin
1924
  if(Reset)
1925
    SyncRxStartFrm_q <=#Tp 0;
1926
  else
1927
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
1928
end
1929
 
1930 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1931
begin
1932
  if(Reset)
1933
    SyncRxStartFrm_q2 <=#Tp 0;
1934
  else
1935
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
1936
end
1937 90 mohor
 
1938
 
1939 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
1940 90 mohor
 
1941 150 mohor
wire [4:0] rxfifo_cnt;
1942
 
1943 40 mohor
eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH)
1944 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
1945
         .clk(WB_CLK_I),                                .reset(Reset),
1946
         .write(WriteRxDataToFifo_wb),                  .read(MasterWbRX & m_wb_ack_i),
1947 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
1948 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
1949 150 mohor
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
1950 88 mohor
        );
1951 40 mohor
 
1952 127 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty & ~MasterWbRX;
1953 40 mohor
 
1954
 
1955
 
1956
// Generation of the end-of-frame signal
1957
always @ (posedge MRxClk or posedge Reset)
1958 38 mohor
begin
1959 40 mohor
  if(Reset)
1960 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
1961 38 mohor
  else
1962 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
1963 159 mohor
    ShiftEnded_rck <=#Tp 1'b1;
1964 38 mohor
  else
1965 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
1966 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
1967 38 mohor
end
1968
 
1969 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1970
begin
1971
  if(Reset)
1972
    ShiftEndedSync1 <=#Tp 1'b0;
1973
  else
1974 159 mohor
    ShiftEndedSync1 <=#Tp ShiftEnded_rck;
1975 40 mohor
end
1976 38 mohor
 
1977 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1978 38 mohor
begin
1979 40 mohor
  if(Reset)
1980
    ShiftEndedSync2 <=#Tp 1'b0;
1981 38 mohor
  else
1982 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
1983 40 mohor
end
1984 38 mohor
 
1985 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1986
begin
1987
  if(Reset)
1988
    ShiftEndedSync3 <=#Tp 1'b0;
1989
  else
1990
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
1991
    ShiftEndedSync3 <=#Tp 1'b1;
1992
  else
1993
  if(ShiftEnded)
1994
    ShiftEndedSync3 <=#Tp 1'b0;
1995
end
1996 38 mohor
 
1997 40 mohor
// Generation of the end-of-frame signal
1998
always @ (posedge WB_CLK_I or posedge Reset)
1999 38 mohor
begin
2000 40 mohor
  if(Reset)
2001
    ShiftEnded <=#Tp 1'b0;
2002 38 mohor
  else
2003 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2004 40 mohor
    ShiftEnded <=#Tp 1'b1;
2005 38 mohor
  else
2006 40 mohor
  if(RxStatusWrite)
2007
    ShiftEnded <=#Tp 1'b0;
2008 38 mohor
end
2009
 
2010 118 mohor
always @ (posedge MRxClk or posedge Reset)
2011
begin
2012
  if(Reset)
2013
    ShiftEndedSync_c1 <=#Tp 1'b0;
2014
  else
2015
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
2016
end
2017 38 mohor
 
2018 118 mohor
always @ (posedge MRxClk or posedge Reset)
2019
begin
2020
  if(Reset)
2021
    ShiftEndedSync_c2 <=#Tp 1'b0;
2022
  else
2023
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
2024
end
2025
 
2026 40 mohor
// Generation of the end-of-frame signal
2027
always @ (posedge MRxClk or posedge Reset)
2028 38 mohor
begin
2029 40 mohor
  if(Reset)
2030
    RxEnableWindow <=#Tp 1'b0;
2031 38 mohor
  else
2032 40 mohor
  if(RxStartFrm)
2033
    RxEnableWindow <=#Tp 1'b1;
2034 38 mohor
  else
2035 40 mohor
  if(RxEndFrm | RxAbort)
2036
    RxEnableWindow <=#Tp 1'b0;
2037 38 mohor
end
2038
 
2039
 
2040 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2041 38 mohor
begin
2042 40 mohor
  if(Reset)
2043
    RxAbortSync1 <=#Tp 1'b0;
2044 38 mohor
  else
2045 150 mohor
//    RxAbortSync1 <=#Tp RxAbort;
2046
    RxAbortSync1 <=#Tp RxAbortLatched;
2047 40 mohor
end
2048
 
2049
always @ (posedge WB_CLK_I or posedge Reset)
2050
begin
2051
  if(Reset)
2052
    RxAbortSync2 <=#Tp 1'b0;
2053 38 mohor
  else
2054 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
2055 38 mohor
end
2056
 
2057 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2058
begin
2059
  if(Reset)
2060
    RxAbortSync3 <=#Tp 1'b0;
2061
  else
2062
    RxAbortSync3 <=#Tp RxAbortSync2;
2063
end
2064
 
2065
always @ (posedge WB_CLK_I or posedge Reset)
2066
begin
2067
  if(Reset)
2068
    RxAbortSync4 <=#Tp 1'b0;
2069
  else
2070
    RxAbortSync4 <=#Tp RxAbortSync3;
2071
end
2072
 
2073 40 mohor
always @ (posedge MRxClk or posedge Reset)
2074
begin
2075
  if(Reset)
2076
    RxAbortSyncb1 <=#Tp 1'b0;
2077
  else
2078
    RxAbortSyncb1 <=#Tp RxAbortSync2;
2079
end
2080 38 mohor
 
2081 40 mohor
always @ (posedge MRxClk or posedge Reset)
2082 38 mohor
begin
2083 40 mohor
  if(Reset)
2084
    RxAbortSyncb2 <=#Tp 1'b0;
2085 38 mohor
  else
2086 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
2087 38 mohor
end
2088
 
2089
 
2090 64 mohor
always @ (posedge MRxClk or posedge Reset)
2091
begin
2092
  if(Reset)
2093
    RxAbortLatched <=#Tp 1'b0;
2094
  else
2095 150 mohor
  if(RxAbortSyncb2)
2096
    RxAbortLatched <=#Tp 1'b0;
2097
  else
2098 64 mohor
  if(RxAbort)
2099
    RxAbortLatched <=#Tp 1'b1;
2100
end
2101 40 mohor
 
2102 64 mohor
 
2103 42 mohor
always @ (posedge MRxClk or posedge Reset)
2104
begin
2105
  if(Reset)
2106
    LatchedRxLength[15:0] <=#Tp 16'h0;
2107
  else
2108 150 mohor
  if(LoadRxStatus)
2109 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
2110
end
2111
 
2112
 
2113 60 mohor
assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2114 42 mohor
 
2115
always @ (posedge MRxClk or posedge Reset)
2116
begin
2117
  if(Reset)
2118
    RxStatusInLatched <=#Tp 'h0;
2119
  else
2120 150 mohor
  if(LoadRxStatus)
2121 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
2122
end
2123
 
2124
 
2125 60 mohor
// Rx overrun
2126
always @ (posedge WB_CLK_I or posedge Reset)
2127
begin
2128
  if(Reset)
2129
    RxOverrun <=#Tp 1'b0;
2130
  else
2131
  if(RxStatusWrite)
2132
    RxOverrun <=#Tp 1'b0;
2133
  else
2134
  if(RxBufferFull & WriteRxDataToFifo_wb)
2135
    RxOverrun <=#Tp 1'b1;
2136
end
2137 48 mohor
 
2138 77 mohor
 
2139
 
2140
wire TxError;
2141
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2142
 
2143
wire RxError;
2144
assign RxError = |RxStatusInLatched[6:0];
2145
 
2146
// Tx Done Interrupt
2147
always @ (posedge WB_CLK_I or posedge Reset)
2148
begin
2149
  if(Reset)
2150
    TxB_IRQ <=#Tp 1'b0;
2151
  else
2152
  if(TxStatusWrite & TxIRQEn)
2153
    TxB_IRQ <=#Tp ~TxError;
2154
  else
2155
    TxB_IRQ <=#Tp 1'b0;
2156
end
2157
 
2158
 
2159
// Tx Error Interrupt
2160
always @ (posedge WB_CLK_I or posedge Reset)
2161
begin
2162
  if(Reset)
2163
    TxE_IRQ <=#Tp 1'b0;
2164
  else
2165
  if(TxStatusWrite & TxIRQEn)
2166
    TxE_IRQ <=#Tp TxError;
2167
  else
2168
    TxE_IRQ <=#Tp 1'b0;
2169
end
2170
 
2171
 
2172
// Rx Done Interrupt
2173
always @ (posedge WB_CLK_I or posedge Reset)
2174
begin
2175
  if(Reset)
2176
    RxB_IRQ <=#Tp 1'b0;
2177
  else
2178
  if(RxStatusWrite & RxIRQEn)
2179 167 mohor
    RxB_IRQ <=#Tp ReceivedPacketGood & ~RxError;
2180 77 mohor
  else
2181
    RxB_IRQ <=#Tp 1'b0;
2182
end
2183
 
2184
 
2185
// Rx Error Interrupt
2186
always @ (posedge WB_CLK_I or posedge Reset)
2187
begin
2188
  if(Reset)
2189
    RxE_IRQ <=#Tp 1'b0;
2190
  else
2191
  if(RxStatusWrite & RxIRQEn)
2192
    RxE_IRQ <=#Tp RxError;
2193
  else
2194
    RxE_IRQ <=#Tp 1'b0;
2195
end
2196
 
2197
 
2198 166 mohor
// Busy Interrupt
2199 77 mohor
 
2200 166 mohor
reg Busy_IRQ_rck;
2201
reg Busy_IRQ_sync1;
2202
reg Busy_IRQ_sync2;
2203
reg Busy_IRQ_sync3;
2204
reg Busy_IRQ_syncb1;
2205
reg Busy_IRQ_syncb2;
2206 77 mohor
 
2207
 
2208 166 mohor
always @ (posedge MRxClk or posedge Reset)
2209
begin
2210
  if(Reset)
2211
    Busy_IRQ_rck <=#Tp 1'b0;
2212
  else
2213
  if(RxValid & RxStartFrm & ~RxReady)
2214
    Busy_IRQ_rck <=#Tp 1'b1;
2215
  else
2216
  if(Busy_IRQ_syncb2)
2217
    Busy_IRQ_rck <=#Tp 1'b0;
2218
end
2219 77 mohor
 
2220 166 mohor
always @ (posedge WB_CLK_I)
2221
begin
2222
    Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
2223
    Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
2224
    Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
2225
end
2226
 
2227
always @ (posedge MRxClk)
2228
begin
2229
    Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
2230
    Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
2231
end
2232
 
2233
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
2234
 
2235
 
2236 60 mohor
 
2237
// TX
2238 61 mohor
// bit 15 ready
2239
// bit 14 interrupt
2240
// bit 13 wrap
2241
// bit 12 pad
2242
// bit 11 crc
2243
// bit 10 last
2244
// bit 9  pause request (control frame)
2245
// bit 8  TxUnderRun          
2246
// bit 7-4 RetryCntLatched    
2247
// bit 3  retransmittion limit
2248
// bit 2  LateCollLatched        
2249
// bit 1  DeferLatched        
2250
// bit 0  CarrierSenseLost    
2251 60 mohor
 
2252
 
2253
// RX
2254
// bit 15 od rx je empty
2255 61 mohor
// bit 14 od rx je interrupt
2256 60 mohor
// bit 13 od rx je wrap
2257
// bit 12 od rx je reserved
2258
// bit 11 od rx je reserved
2259
// bit 10 od rx je reserved
2260
// bit 9  od rx je reserved
2261
// bit 8  od rx je reserved
2262 110 mohor
// bit 7  od rx je Miss
2263 60 mohor
// bit 6  od rx je RxOverrun
2264
// bit 5  od rx je InvalidSymbol
2265
// bit 4  od rx je DribbleNibble
2266
// bit 3  od rx je ReceivedPacketTooBig
2267
// bit 2  od rx je ShortFrame
2268
// bit 1  od rx je LatchedCrcError
2269
// bit 0  od rx je RxLateCollision
2270
 
2271 110 mohor
 
2272 38 mohor
endmodule
2273
 

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