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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 219

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
45
// BIST added.
46
//
47 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
48
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
49
//
50 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
51
// Reception is possible after RxPointer is read and not after BD is read. For
52
// that reason RxBDReady is changed to RxReady.
53
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
54
// comes, interrupt is generated.
55
//
56 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
57
// Ethernet debug registers removed.
58
//
59 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
60
// Async reset for WB_ACK_O removed (when core was in reset, it was
61
// impossible to access BDs).
62
// RxPointers and TxPointers names changed to be more descriptive.
63
// TxUnderRun synchronized.
64
//
65 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
66
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
67
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
68
// was not used OK.
69
//
70 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
71
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
72
// need to multiply or devide any more.
73
//
74 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
75
// WriteRxDataToMemory signal changed so end of frame (when last word is
76
// written to fifo) is changed.
77
//
78 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
79
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
80
//
81 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
82
// ShiftEnded synchronization changed.
83
//
84 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
85
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
86
//
87 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
88
// RxPointer bug fixed.
89
//
90 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
91
// Previous bug wasn't succesfully removed. Now fixed.
92
//
93 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
94
// Master state machine had a bug when switching from master write to
95
// master read.
96
//
97 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
98
// m_wb_cyc_o signal released after every single transfer.
99
//
100 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
101
// Outputs registered. Reset changed for eth_wishbone module.
102
//
103 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
104
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
105
// bug fixed.
106
//
107 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
108
// Small typo fixed.
109
//
110 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
111
// Any address can be used for Tx and Rx BD pointers. Address does not need
112
// to be aligned.
113
//
114 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
115
// Comments in Slovene language removed.
116
//
117 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
118
// casex changed with case, fifo reset changed.
119
//
120 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
121
// rx_fifo was not always cleared ok. Fixed.
122
//
123 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
124
// Status was not latched correctly sometimes. Fixed.
125
//
126 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
127
// Big Endian problem when sending frames fixed.
128
//
129 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
130
// Byte ordering changed (Big Endian used). casex changed with case because
131
// Xilinx Foundation had problems. Tested in HW. It WORKS.
132
//
133 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
134
// Small fixes for external/internal DMA missmatches.
135
//
136 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
137
// Interrupts changed
138
//
139 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
140
// Status was not written correctly when frames were discarted because of
141
// address mismatch.
142
//
143 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
144
// RxStartFrm cleared when abort or retry comes.
145
//
146 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
147
// Changes that were lost when updating from 1.5 to 1.8 fixed.
148
//
149 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
150
// Addition  of new module eth_addrcheck.v
151
//
152
// Revision 1.7  2002/02/12 17:03:47  mohor
153
// RxOverRun added to statuses.
154
//
155
// Revision 1.6  2002/02/11 09:18:22  mohor
156
// Tx status is written back to the BD.
157
//
158 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
159
// Rx status is written back to the BD.
160
//
161 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
162
// non-DMA host interface added. Select the right configutation in eth_defines.
163
//
164 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
165
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
166
// MHz. Statuses, overrun, control frame transmission and reception still  need
167
// to be fixed.
168
//
169 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
170
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
171
// added.
172
//
173 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
174
// Initial version. Equals to eth_wishbonedma.v at this moment.
175 38 mohor
//
176
//
177
//
178
 
179
`include "eth_defines.v"
180
`include "timescale.v"
181
 
182
 
183
module eth_wishbone
184
   (
185
 
186
    // WISHBONE common
187 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
188 38 mohor
 
189
    // WISHBONE slave
190 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
191 40 mohor
    BDCs,
192 38 mohor
 
193 40 mohor
    Reset,
194
 
195 39 mohor
    // WISHBONE master
196
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
197
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
198
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
199
 
200 219 mohor
`ifdef ETH_WISHBONE_B3
201
    m_wb_cti_o, m_wb_bte_o,
202
`endif
203
 
204 38 mohor
    //TX
205 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
206 150 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
207 38 mohor
    PerPacketPad,
208
 
209
    //RX
210 40 mohor
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
211 38 mohor
 
212
    // Register
213 150 mohor
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr,
214 38 mohor
 
215
    // Interrupts
216 150 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
217 42 mohor
 
218 60 mohor
    // Rx Status
219 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
220 77 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
221 60 mohor
 
222
    // Tx Status
223 164 mohor
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
224
 
225 210 mohor
    // Bist
226
`ifdef ETH_BIST
227
   , trst, SO, SI, shift_DR, capture_DR, extest, tck
228
`endif
229
 
230
 
231
 
232 38 mohor
                );
233
 
234
 
235
parameter Tp = 1;
236
 
237 150 mohor
 
238 38 mohor
// WISHBONE common
239
input           WB_CLK_I;       // WISHBONE clock
240
input  [31:0]   WB_DAT_I;       // WISHBONE data input
241
output [31:0]   WB_DAT_O;       // WISHBONE data output
242
 
243
// WISHBONE slave
244
input   [9:2]   WB_ADR_I;       // WISHBONE address input
245
input           WB_WE_I;        // WISHBONE write enable input
246
input           BDCs;           // Buffer descriptors are selected
247
output          WB_ACK_O;       // WISHBONE acknowledge output
248
 
249 39 mohor
// WISHBONE master
250
output  [31:0]  m_wb_adr_o;     // 
251
output   [3:0]  m_wb_sel_o;     // 
252
output          m_wb_we_o;      // 
253
output  [31:0]  m_wb_dat_o;     // 
254
output          m_wb_cyc_o;     // 
255
output          m_wb_stb_o;     // 
256
input   [31:0]  m_wb_dat_i;     // 
257
input           m_wb_ack_i;     // 
258
input           m_wb_err_i;     // 
259
 
260 219 mohor
`ifdef ETH_WISHBONE_B3
261
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
262
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
263
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
264
`endif
265
 
266 40 mohor
input           Reset;       // Reset signal
267 39 mohor
 
268 60 mohor
// Rx Status signals
269 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
270
input           LatchedCrcError;  // CRC error
271
input           RxLateCollision;  // Late collision occured while receiving frame
272
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
273
input           DribbleNibble;    // Extra nibble received
274
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
275
input    [15:0] RxLength;         // Length of the incoming frame
276
input           LoadRxStatus;     // Rx status was loaded
277 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
278 39 mohor
 
279 60 mohor
// Tx Status signals
280
input     [3:0] RetryCntLatched;  // Latched Retry Counter
281
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
282
input           LateCollLatched;  // Late collision occured
283
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
284
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
285
 
286 38 mohor
// Tx
287
input           MTxClk;         // Transmit clock (from PHY)
288
input           TxUsedData;     // Transmit packet used data
289
input           TxRetry;        // Transmit packet retry
290
input           TxAbort;        // Transmit packet abort
291
input           TxDone;         // Transmission ended
292
output          TxStartFrm;     // Transmit packet start frame
293
output          TxEndFrm;       // Transmit packet end frame
294
output  [7:0]   TxData;         // Transmit packet data byte
295
output          TxUnderRun;     // Transmit packet under-run
296
output          PerPacketCrcEn; // Per packet crc enable
297
output          PerPacketPad;   // Per packet pading
298
 
299
// Rx
300
input           MRxClk;         // Receive clock (from PHY)
301
input   [7:0]   RxData;         // Received data byte (from PHY)
302
input           RxValid;        // 
303
input           RxStartFrm;     // 
304
input           RxEndFrm;       // 
305 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
306 38 mohor
 
307
//Register
308
input           r_TxEn;         // Transmit enable
309
input           r_RxEn;         // Receive enable
310
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
311
input           TX_BD_NUM_Wr;   // RxBDNumber written
312
 
313
// Interrupts
314
output TxB_IRQ;
315
output TxE_IRQ;
316
output RxB_IRQ;
317 77 mohor
output RxE_IRQ;
318 38 mohor
output Busy_IRQ;
319
 
320 77 mohor
 
321 210 mohor
// Bist
322
`ifdef ETH_BIST
323
input           trst;
324
input           shift_DR, capture_DR, tck, extest;
325
input           SI;
326
output          SO;
327
`endif
328
 
329 77 mohor
reg TxB_IRQ;
330
reg TxE_IRQ;
331
reg RxB_IRQ;
332
reg RxE_IRQ;
333
 
334 38 mohor
reg             TxStartFrm;
335
reg             TxEndFrm;
336
reg     [7:0]   TxData;
337
 
338
reg             TxUnderRun;
339 60 mohor
reg             TxUnderRun_wb;
340 38 mohor
 
341
reg             TxBDRead;
342 39 mohor
wire            TxStatusWrite;
343 38 mohor
 
344
reg     [1:0]   TxValidBytesLatched;
345
 
346
reg    [15:0]   TxLength;
347 60 mohor
reg    [15:0]   LatchedTxLength;
348
reg   [14:11]   TxStatus;
349 38 mohor
 
350 60 mohor
reg   [14:13]   RxStatus;
351 38 mohor
 
352
reg             TxStartFrm_wb;
353
reg             TxRetry_wb;
354 39 mohor
reg             TxAbort_wb;
355 38 mohor
reg             TxDone_wb;
356
 
357
reg             TxDone_wb_q;
358
reg             TxAbort_wb_q;
359 39 mohor
reg             TxRetry_wb_q;
360 219 mohor
reg             TxRetryPacket;
361
reg             TxDonePulse_q;
362
reg             TxAbortPacket;
363 38 mohor
reg             RxBDReady;
364 166 mohor
reg             RxReady;
365 38 mohor
reg             TxBDReady;
366
 
367
reg             RxBDRead;
368 40 mohor
wire            RxStatusWrite;
369 38 mohor
 
370
reg    [31:0]   TxDataLatched;
371
reg     [1:0]   TxByteCnt;
372
reg             LastWord;
373 39 mohor
reg             ReadTxDataFromFifo_tck;
374 38 mohor
 
375
reg             BlockingTxStatusWrite;
376
reg             BlockingTxBDRead;
377
 
378 40 mohor
reg             Flop;
379 38 mohor
 
380
reg     [7:0]   TxBDAddress;
381
reg     [7:0]   RxBDAddress;
382
 
383
reg             TxRetrySync1;
384
reg             TxAbortSync1;
385 39 mohor
reg             TxDoneSync1;
386 38 mohor
 
387
reg             TxAbort_q;
388
reg             TxRetry_q;
389
reg             TxUsedData_q;
390
 
391
reg    [31:0]   RxDataLatched2;
392 82 mohor
 
393
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
394
 
395 38 mohor
reg     [1:0]   RxValidBytes;
396
reg     [1:0]   RxByteCnt;
397
reg             LastByteIn;
398
reg             ShiftWillEnd;
399
 
400 40 mohor
reg             WriteRxDataToFifo;
401 42 mohor
reg    [15:0]   LatchedRxLength;
402 64 mohor
reg             RxAbortLatched;
403 38 mohor
 
404 40 mohor
reg             ShiftEnded;
405 60 mohor
reg             RxOverrun;
406 38 mohor
 
407 40 mohor
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
408
reg             BDRead;                     // BD Read access from WISHBONE side
409 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
410
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
411 38 mohor
 
412 39 mohor
reg             TxEndFrm_wb;
413 38 mohor
 
414 39 mohor
wire            TxRetryPulse;
415 38 mohor
wire            TxDonePulse;
416
wire            TxAbortPulse;
417
 
418
wire            StartRxBDRead;
419
 
420
wire            StartTxBDRead;
421
 
422
wire            TxIRQEn;
423
wire            WrapTxStatusBit;
424
 
425 77 mohor
wire            RxIRQEn;
426 38 mohor
wire            WrapRxStatusBit;
427
 
428
wire    [1:0]   TxValidBytes;
429
 
430
wire    [7:0]   TempTxBDAddress;
431
wire    [7:0]   TempRxBDAddress;
432
 
433
wire            SetGotData;
434
wire            GotDataEvaluate;
435
 
436 106 mohor
reg             WB_ACK_O;
437 38 mohor
 
438 60 mohor
wire    [6:0]   RxStatusIn;
439
reg     [6:0]   RxStatusInLatched;
440 42 mohor
 
441 39 mohor
reg WbEn, WbEn_q;
442
reg RxEn, RxEn_q;
443
reg TxEn, TxEn_q;
444 38 mohor
 
445 39 mohor
wire ram_ce;
446
wire ram_we;
447
wire ram_oe;
448
reg [7:0]   ram_addr;
449
reg [31:0]  ram_di;
450
wire [31:0] ram_do;
451 38 mohor
 
452 39 mohor
wire StartTxPointerRead;
453
reg  TxPointerRead;
454
reg TxEn_needed;
455 40 mohor
reg RxEn_needed;
456 38 mohor
 
457 40 mohor
wire StartRxPointerRead;
458
reg RxPointerRead;
459 38 mohor
 
460 219 mohor
`ifdef ETH_WISHBONE_B3
461
assign m_wb_bte_o = 2'b00;    // Linear burst
462
`endif
463 39 mohor
 
464 219 mohor
 
465 159 mohor
always @ (posedge WB_CLK_I)
466 40 mohor
begin
467 159 mohor
  WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
468 40 mohor
end
469 39 mohor
 
470 106 mohor
assign WB_DAT_O = ram_do;
471 39 mohor
 
472 41 mohor
// Generic synchronous single-port RAM interface
473 119 mohor
eth_spram_256x32 bd_ram (
474 210 mohor
  .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
475
`ifdef ETH_BIST
476 219 mohor
  , .trst(trst), .SO(SO), .SI(SI), .shift_DR(shift_DR), .capture_DR(capture_DR), .extest(extest), .tck(tck)
477 210 mohor
`endif
478 39 mohor
);
479 41 mohor
 
480 39 mohor
assign ram_ce = 1'b1;
481 40 mohor
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
482 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
483 39 mohor
 
484
 
485 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
486 38 mohor
begin
487 40 mohor
  if(Reset)
488 39 mohor
    TxEn_needed <=#Tp 1'b0;
489 38 mohor
  else
490 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
491 39 mohor
    TxEn_needed <=#Tp 1'b1;
492
  else
493
  if(TxPointerRead & TxEn & TxEn_q)
494
    TxEn_needed <=#Tp 1'b0;
495 38 mohor
end
496
 
497 39 mohor
// Enabling access to the RAM for three devices.
498 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
499 39 mohor
begin
500 40 mohor
  if(Reset)
501 39 mohor
    begin
502
      WbEn <=#Tp 1'b1;
503
      RxEn <=#Tp 1'b0;
504
      TxEn <=#Tp 1'b0;
505
      ram_addr <=#Tp 8'h0;
506
      ram_di <=#Tp 32'h0;
507 77 mohor
      BDRead <=#Tp 1'b0;
508
      BDWrite <=#Tp 1'b0;
509 39 mohor
    end
510
  else
511
    begin
512
      // Switching between three stages depends on enable signals
513 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
514
        5'b100_10, 5'b100_11 :
515 39 mohor
          begin
516
            WbEn <=#Tp 1'b0;
517
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
518
            TxEn <=#Tp 1'b0;
519 40 mohor
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
520 39 mohor
            ram_di <=#Tp RxBDDataIn;
521
          end
522
        5'b100_01 :
523
          begin
524
            WbEn <=#Tp 1'b0;
525
            RxEn <=#Tp 1'b0;
526
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
527
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
528
            ram_di <=#Tp TxBDDataIn;
529
          end
530 90 mohor
        5'b010_00, 5'b010_10 :
531 39 mohor
          begin
532
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
533
            RxEn <=#Tp 1'b0;
534
            TxEn <=#Tp 1'b0;
535
            ram_addr <=#Tp WB_ADR_I[9:2];
536
            ram_di <=#Tp WB_DAT_I;
537 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
538
            BDRead <=#Tp BDCs & ~WB_WE_I;
539 39 mohor
          end
540 90 mohor
        5'b010_01, 5'b010_11 :
541 39 mohor
          begin
542
            WbEn <=#Tp 1'b0;
543
            RxEn <=#Tp 1'b0;
544
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
545
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
546
            ram_di <=#Tp TxBDDataIn;
547
          end
548 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
549 39 mohor
          begin
550
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
551
            RxEn <=#Tp 1'b0;
552
            TxEn <=#Tp 1'b0;
553
            ram_addr <=#Tp WB_ADR_I[9:2];
554
            ram_di <=#Tp WB_DAT_I;
555 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
556
            BDRead <=#Tp BDCs & ~WB_WE_I;
557 39 mohor
          end
558
        5'b100_00 :
559
          begin
560
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
561
          end
562
        5'b000_00 :
563
          begin
564
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
565
            RxEn <=#Tp 1'b0;
566
            TxEn <=#Tp 1'b0;
567
            ram_addr <=#Tp WB_ADR_I[9:2];
568
            ram_di <=#Tp WB_DAT_I;
569 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
570
            BDRead <=#Tp BDCs & ~WB_WE_I;
571 39 mohor
          end
572
      endcase
573
    end
574
end
575
 
576
 
577
// Delayed stage signals
578 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
579 39 mohor
begin
580 40 mohor
  if(Reset)
581 39 mohor
    begin
582
      WbEn_q <=#Tp 1'b0;
583
      RxEn_q <=#Tp 1'b0;
584
      TxEn_q <=#Tp 1'b0;
585
    end
586
  else
587
    begin
588
      WbEn_q <=#Tp WbEn;
589
      RxEn_q <=#Tp RxEn;
590
      TxEn_q <=#Tp TxEn;
591
    end
592
end
593
 
594 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
595 40 mohor
always @ (posedge MTxClk or posedge Reset)
596 38 mohor
begin
597 40 mohor
  if(Reset)
598 38 mohor
    Flop <=#Tp 1'b0;
599
  else
600
  if(TxDone | TxAbort | TxRetry_q)
601
    Flop <=#Tp 1'b0;
602
  else
603
  if(TxUsedData)
604
    Flop <=#Tp ~Flop;
605
end
606
 
607 39 mohor
wire ResetTxBDReady;
608
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
609 38 mohor
 
610
// Latching READY status of the Tx buffer descriptor
611 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
612 38 mohor
begin
613 40 mohor
  if(Reset)
614 38 mohor
    TxBDReady <=#Tp 1'b0;
615
  else
616 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
617
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
618
  else                                                // Only packets larger then 4 bytes are transmitted.
619 39 mohor
  if(ResetTxBDReady)
620 38 mohor
    TxBDReady <=#Tp 1'b0;
621
end
622
 
623
 
624 39 mohor
// Reading the Tx buffer descriptor
625 110 mohor
assign StartTxBDRead = (TxRetry_wb | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
626 39 mohor
 
627 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
628 38 mohor
begin
629 40 mohor
  if(Reset)
630 39 mohor
    TxBDRead <=#Tp 1'b1;
631 38 mohor
  else
632 110 mohor
  if(StartTxBDRead)
633 39 mohor
    TxBDRead <=#Tp 1'b1;
634 38 mohor
  else
635 39 mohor
  if(TxBDReady)
636
    TxBDRead <=#Tp 1'b0;
637 38 mohor
end
638
 
639
 
640 39 mohor
// Reading Tx BD pointer
641
assign StartTxPointerRead = TxBDRead & TxBDReady;
642 38 mohor
 
643 39 mohor
// Reading Tx BD Pointer
644 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
645 38 mohor
begin
646 40 mohor
  if(Reset)
647 39 mohor
    TxPointerRead <=#Tp 1'b0;
648 38 mohor
  else
649 39 mohor
  if(StartTxPointerRead)
650
    TxPointerRead <=#Tp 1'b1;
651 38 mohor
  else
652 39 mohor
  if(TxEn_q)
653
    TxPointerRead <=#Tp 1'b0;
654 38 mohor
end
655
 
656
 
657 39 mohor
// Writing status back to the Tx buffer descriptor
658
assign TxStatusWrite = (TxDone_wb | TxAbort_wb) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
659 38 mohor
 
660
 
661
 
662 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
663 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
664 38 mohor
begin
665 40 mohor
  if(Reset)
666 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
667 38 mohor
  else
668 39 mohor
  if(TxStatusWrite)
669
    BlockingTxStatusWrite <=#Tp 1'b1;
670 38 mohor
  else
671 39 mohor
  if(~TxDone_wb & ~TxAbort_wb)
672
    BlockingTxStatusWrite <=#Tp 1'b0;
673 38 mohor
end
674
 
675
 
676 159 mohor
reg BlockingTxStatusWrite_sync1;
677
reg BlockingTxStatusWrite_sync2;
678
 
679
// Synchronizing BlockingTxStatusWrite to MTxClk
680
always @ (posedge MTxClk or posedge Reset)
681
begin
682
  if(Reset)
683
    BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
684
  else
685
    BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
686
end
687
 
688
// Synchronizing BlockingTxStatusWrite to MTxClk
689
always @ (posedge MTxClk or posedge Reset)
690
begin
691
  if(Reset)
692
    BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
693
  else
694
    BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
695
end
696
 
697
 
698 39 mohor
// TxBDRead state is activated only once. 
699 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
700 39 mohor
begin
701 40 mohor
  if(Reset)
702 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
703
  else
704 110 mohor
  if(StartTxBDRead)
705 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
706
  else
707 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
708 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
709
end
710 38 mohor
 
711
 
712 39 mohor
// Latching status from the tx buffer descriptor
713
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
714 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
715 38 mohor
begin
716 40 mohor
  if(Reset)
717 60 mohor
    TxStatus <=#Tp 4'h0;
718 38 mohor
  else
719 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
720 60 mohor
    TxStatus <=#Tp ram_do[14:11];
721 38 mohor
end
722
 
723 40 mohor
reg ReadTxDataFromMemory;
724
wire WriteRxDataToMemory;
725 38 mohor
 
726 39 mohor
reg MasterWbTX;
727
reg MasterWbRX;
728
 
729
reg [31:0] m_wb_adr_o;
730
reg        m_wb_cyc_o;
731
reg        m_wb_stb_o;
732 96 mohor
reg  [3:0] m_wb_sel_o;
733 39 mohor
reg        m_wb_we_o;
734 40 mohor
 
735 39 mohor
wire TxLengthEq0;
736
wire TxLengthLt4;
737
 
738 150 mohor
reg BlockingIncrementTxPointer;
739 159 mohor
reg [31:2] TxPointerMSB;
740
reg [1:0]  TxPointerLSB;
741
reg [1:0]  TxPointerLSB_rst;
742
reg [31:2] RxPointerMSB;
743
reg [1:0]  RxPointerLSB_rst;
744 39 mohor
 
745 150 mohor
wire RxBurstAcc;
746
wire RxWordAcc;
747
wire RxHalfAcc;
748
wire RxByteAcc;
749
 
750 39 mohor
//Latching length from the buffer descriptor;
751 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
752 38 mohor
begin
753 40 mohor
  if(Reset)
754 39 mohor
    TxLength <=#Tp 16'h0;
755 38 mohor
  else
756 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
757
    TxLength <=#Tp ram_do[31:16];
758 38 mohor
  else
759 39 mohor
  if(MasterWbTX & m_wb_ack_i)
760
    begin
761
      if(TxLengthLt4)
762
        TxLength <=#Tp 16'h0;
763 150 mohor
      else
764 159 mohor
      if(TxPointerLSB_rst==2'h0)
765 96 mohor
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
766 39 mohor
      else
767 159 mohor
      if(TxPointerLSB_rst==2'h1)
768 150 mohor
        TxLength <=#Tp TxLength - 3'h3;    // Length is subtracted at the data request
769
      else
770 159 mohor
      if(TxPointerLSB_rst==2'h2)
771 150 mohor
        TxLength <=#Tp TxLength - 3'h2;    // Length is subtracted at the data request
772
      else
773 159 mohor
      if(TxPointerLSB_rst==2'h3)
774 150 mohor
        TxLength <=#Tp TxLength - 3'h1;    // Length is subtracted at the data request
775 39 mohor
    end
776 38 mohor
end
777
 
778 96 mohor
 
779
 
780 60 mohor
//Latching length from the buffer descriptor;
781
always @ (posedge WB_CLK_I or posedge Reset)
782
begin
783
  if(Reset)
784
    LatchedTxLength <=#Tp 16'h0;
785
  else
786
  if(TxEn & TxEn_q & TxBDRead)
787
    LatchedTxLength <=#Tp ram_do[31:16];
788
end
789
 
790 39 mohor
assign TxLengthEq0 = TxLength == 0;
791
assign TxLengthLt4 = TxLength < 4;
792 38 mohor
 
793 150 mohor
reg cyc_cleared;
794
reg IncrTxPointer;
795 39 mohor
 
796
 
797 159 mohor
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
798
// because TxPointerMSB is only used for word-aligned accesses.
799 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
800 38 mohor
begin
801 40 mohor
  if(Reset)
802 159 mohor
    TxPointerMSB <=#Tp 30'h0;
803 38 mohor
  else
804 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
805 159 mohor
    TxPointerMSB <=#Tp ram_do[31:2];
806 38 mohor
  else
807 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
808 159 mohor
    TxPointerMSB <=#Tp TxPointerMSB + 1'b1;     // TxPointer is word-aligned
809 38 mohor
end
810
 
811 96 mohor
 
812 159 mohor
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
813
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
814
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
815
// set by this two bits.
816 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
817
begin
818
  if(Reset)
819 159 mohor
    TxPointerLSB[1:0] <=#Tp 0;
820 96 mohor
  else
821
  if(TxEn & TxEn_q & TxPointerRead)
822 159 mohor
    TxPointerLSB[1:0] <=#Tp ram_do[1:0];
823 96 mohor
end
824
 
825
 
826 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
827
// After the read access, TxLength needs to be decremented for the number of the valid
828
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
829
// valid so this two bits are reset to zero. 
830 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
831
begin
832
  if(Reset)
833 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
834 150 mohor
  else
835
  if(TxEn & TxEn_q & TxPointerRead)
836 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
837 150 mohor
  else
838
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
839 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
840 150 mohor
end
841 96 mohor
 
842 150 mohor
 
843 159 mohor
reg  [3:0] RxByteSel;
844 39 mohor
wire MasterAccessFinished;
845 38 mohor
 
846 39 mohor
 
847 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
848 38 mohor
begin
849 40 mohor
  if(Reset)
850 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
851 38 mohor
  else
852 39 mohor
  if(MasterAccessFinished)
853
    BlockingIncrementTxPointer <=#Tp 0;
854 38 mohor
  else
855 150 mohor
  if(IncrTxPointer)
856 39 mohor
    BlockingIncrementTxPointer <=#Tp 1'b1;
857 38 mohor
end
858
 
859
 
860 39 mohor
wire TxBufferAlmostFull;
861
wire TxBufferFull;
862
wire TxBufferEmpty;
863
wire TxBufferAlmostEmpty;
864 40 mohor
wire SetReadTxDataFromMemory;
865 39 mohor
 
866 40 mohor
reg BlockReadTxDataFromMemory;
867 39 mohor
 
868 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
869 39 mohor
 
870 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
871 38 mohor
begin
872 40 mohor
  if(Reset)
873
    ReadTxDataFromMemory <=#Tp 1'b0;
874 38 mohor
  else
875 219 mohor
  if(TxLengthEq0 | TxAbortPacket | TxRetryPacket)
876 40 mohor
    ReadTxDataFromMemory <=#Tp 1'b0;
877 39 mohor
  else
878 40 mohor
  if(SetReadTxDataFromMemory)
879
    ReadTxDataFromMemory <=#Tp 1'b1;
880 38 mohor
end
881
 
882 40 mohor
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
883 39 mohor
wire [31:0] TxData_wb;
884
wire ReadTxDataFromFifo_wb;
885 38 mohor
 
886 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
887 38 mohor
begin
888 40 mohor
  if(Reset)
889
    BlockReadTxDataFromMemory <=#Tp 1'b0;
890 38 mohor
  else
891 39 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX)
892 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
893 219 mohor
  else
894
  if(ReadTxDataFromFifo_wb | TxDonePulse_q | TxAbortPacket | TxRetryPacket)
895
    BlockReadTxDataFromMemory <=#Tp 1'b0;
896 39 mohor
end
897
 
898
 
899
 
900
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
901 219 mohor
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
902
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
903 159 mohor
 
904 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
905 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
906 39 mohor
begin
907 40 mohor
  if(Reset)
908 38 mohor
    begin
909 39 mohor
      MasterWbTX <=#Tp 1'b0;
910
      MasterWbRX <=#Tp 1'b0;
911
      m_wb_adr_o <=#Tp 32'h0;
912
      m_wb_cyc_o <=#Tp 1'b0;
913
      m_wb_stb_o <=#Tp 1'b0;
914
      m_wb_we_o  <=#Tp 1'b0;
915 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
916 110 mohor
      cyc_cleared<=#Tp 1'b0;
917 150 mohor
      IncrTxPointer<=#Tp 1'b0;
918 38 mohor
    end
919 39 mohor
  else
920
    begin
921
      // Switching between two stages depends on enable signals
922 110 mohor
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared})  // synopsys parallel_case
923
        6'b00_01_0_x, 6'b00_11_0_x :
924 39 mohor
          begin
925
            MasterWbTX <=#Tp 1'b0;  // idle and master write is needed (data write to rx buffer)
926
            MasterWbRX <=#Tp 1'b1;
927 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
928 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
929
            m_wb_stb_o <=#Tp 1'b1;
930
            m_wb_we_o  <=#Tp 1'b1;
931 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
932 150 mohor
            IncrTxPointer<=#Tp 1'b0;
933 39 mohor
          end
934 110 mohor
        6'b00_10_0_x, 6'b00_10_1_x :
935 39 mohor
          begin
936
            MasterWbTX <=#Tp 1'b1;  // idle and master read is needed (data read from tx buffer)
937
            MasterWbRX <=#Tp 1'b0;
938 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
939 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
940
            m_wb_stb_o <=#Tp 1'b1;
941
            m_wb_we_o  <=#Tp 1'b0;
942 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
943
            IncrTxPointer<=#Tp 1'b1;
944 39 mohor
          end
945 110 mohor
        6'b10_10_0_1 :
946 39 mohor
          begin
947
            MasterWbTX <=#Tp 1'b1;  // master read and master read is needed (data read from tx buffer)
948
            MasterWbRX <=#Tp 1'b0;
949 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
950 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
951
            m_wb_stb_o <=#Tp 1'b1;
952
            m_wb_we_o  <=#Tp 1'b0;
953 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
954 110 mohor
            cyc_cleared<=#Tp 1'b0;
955 150 mohor
            IncrTxPointer<=#Tp 1'b1;
956 39 mohor
          end
957 110 mohor
        6'b01_01_0_1 :
958 39 mohor
          begin
959
            MasterWbTX <=#Tp 1'b0;  // master write and master write is needed (data write to rx buffer)
960
            MasterWbRX <=#Tp 1'b1;
961 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
962 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
963
            m_wb_stb_o <=#Tp 1'b1;
964 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
965 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
966 110 mohor
            cyc_cleared<=#Tp 1'b0;
967 150 mohor
            IncrTxPointer<=#Tp 1'b0;
968 39 mohor
          end
969 110 mohor
        6'b10_01_0_1, 6'b10_11_0_1 :
970 39 mohor
          begin
971
            MasterWbTX <=#Tp 1'b0;  // master read and master write is needed (data write to rx buffer)
972
            MasterWbRX <=#Tp 1'b1;
973 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
974 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
975
            m_wb_stb_o <=#Tp 1'b1;
976 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
977 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
978 110 mohor
            cyc_cleared<=#Tp 1'b0;
979 150 mohor
            IncrTxPointer<=#Tp 1'b0;
980 39 mohor
          end
981 111 mohor
        6'b01_10_0_1, 6'b01_11_0_1 :
982 39 mohor
          begin
983
            MasterWbTX <=#Tp 1'b1;  // master write and master read is needed (data read from tx buffer)
984
            MasterWbRX <=#Tp 1'b0;
985 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
986 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
987
            m_wb_stb_o <=#Tp 1'b1;
988 39 mohor
            m_wb_we_o  <=#Tp 1'b0;
989 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
990 110 mohor
            cyc_cleared<=#Tp 1'b0;
991 150 mohor
            IncrTxPointer<=#Tp 1'b1;
992 39 mohor
          end
993 110 mohor
        6'b10_10_1_0, 6'b01_01_1_0, 6'b10_01_1_0, 6'b10_11_1_0, 6'b01_10_1_0, 6'b01_11_1_0 :
994 39 mohor
          begin
995 110 mohor
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
996
            m_wb_stb_o <=#Tp 1'b0;
997
            cyc_cleared<=#Tp 1'b1;
998 150 mohor
            IncrTxPointer<=#Tp 1'b0;
999 110 mohor
          end
1000
        6'b10_00_1_x, 6'b01_00_1_x :
1001
          begin
1002 39 mohor
            MasterWbTX <=#Tp 1'b0;  // whatever and no master read or write is needed (ack or err comes finishing previous access)
1003
            MasterWbRX <=#Tp 1'b0;
1004
            m_wb_cyc_o <=#Tp 1'b0;
1005
            m_wb_stb_o <=#Tp 1'b0;
1006 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1007 39 mohor
          end
1008 127 mohor
        6'b10_00_0_1, 6'b01_00_0_1 :
1009
          begin
1010
            MasterWbTX <=#Tp 1'b0;  // Between cyc_cleared request was cleared
1011
            MasterWbRX <=#Tp 1'b0;
1012
            m_wb_cyc_o <=#Tp 1'b0;
1013
            m_wb_stb_o <=#Tp 1'b0;
1014 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1015 127 mohor
          end
1016 82 mohor
        default:                            // Don't touch
1017
          begin
1018
            MasterWbTX <=#Tp MasterWbTX;
1019
            MasterWbRX <=#Tp MasterWbRX;
1020
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
1021
            m_wb_stb_o <=#Tp m_wb_stb_o;
1022 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
1023 150 mohor
            IncrTxPointer<=#Tp IncrTxPointer;
1024 82 mohor
          end
1025 39 mohor
      endcase
1026
    end
1027 38 mohor
end
1028
 
1029 110 mohor
 
1030 39 mohor
wire TxFifoClear;
1031 96 mohor
 
1032 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1033 38 mohor
 
1034 219 mohor
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
1035 150 mohor
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
1036 96 mohor
          .clk(WB_CLK_I),                                   .reset(Reset),
1037 219 mohor
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1038 96 mohor
          .clear(TxFifoClear),                              .full(TxBufferFull),
1039
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
1040 150 mohor
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
1041 96 mohor
        );
1042 39 mohor
 
1043
 
1044
reg StartOccured;
1045
reg TxStartFrm_sync1;
1046
reg TxStartFrm_sync2;
1047
reg TxStartFrm_syncb1;
1048
reg TxStartFrm_syncb2;
1049
 
1050
 
1051
 
1052
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1053 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1054 38 mohor
begin
1055 40 mohor
  if(Reset)
1056 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
1057 38 mohor
  else
1058 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1059
    TxStartFrm_wb <=#Tp 1'b1;
1060 38 mohor
  else
1061 39 mohor
  if(TxStartFrm_syncb2)
1062
    TxStartFrm_wb <=#Tp 1'b0;
1063 38 mohor
end
1064
 
1065 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1066 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1067 38 mohor
begin
1068 40 mohor
  if(Reset)
1069 39 mohor
    StartOccured <=#Tp 1'b0;
1070 38 mohor
  else
1071 39 mohor
  if(TxStartFrm_wb)
1072
    StartOccured <=#Tp 1'b1;
1073 38 mohor
  else
1074 39 mohor
  if(ResetTxBDReady)
1075
    StartOccured <=#Tp 1'b0;
1076 38 mohor
end
1077
 
1078 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1079 40 mohor
always @ (posedge MTxClk or posedge Reset)
1080 39 mohor
begin
1081 40 mohor
  if(Reset)
1082 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1083
  else
1084
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1085
end
1086 38 mohor
 
1087 40 mohor
always @ (posedge MTxClk or posedge Reset)
1088 39 mohor
begin
1089 40 mohor
  if(Reset)
1090 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1091
  else
1092
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1093
end
1094
 
1095 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1096 38 mohor
begin
1097 40 mohor
  if(Reset)
1098 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1099 38 mohor
  else
1100 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1101 38 mohor
end
1102
 
1103 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1104 38 mohor
begin
1105 40 mohor
  if(Reset)
1106 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1107 38 mohor
  else
1108 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1109
end
1110
 
1111 40 mohor
always @ (posedge MTxClk or posedge Reset)
1112 39 mohor
begin
1113 40 mohor
  if(Reset)
1114 39 mohor
    TxStartFrm <=#Tp 1'b0;
1115 38 mohor
  else
1116 39 mohor
  if(TxStartFrm_sync2)
1117 61 mohor
    TxStartFrm <=#Tp 1'b1;
1118 39 mohor
  else
1119 61 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry | TxAbort))
1120 39 mohor
    TxStartFrm <=#Tp 1'b0;
1121 38 mohor
end
1122 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1123 38 mohor
 
1124
 
1125 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1126 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1127 38 mohor
begin
1128 40 mohor
  if(Reset)
1129 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1130 38 mohor
  else
1131 39 mohor
  if(TxLengthLt4 & TxBufferAlmostEmpty & TxUsedData)
1132
    TxEndFrm_wb <=#Tp 1'b1;
1133 38 mohor
  else
1134 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1135
    TxEndFrm_wb <=#Tp 1'b0;
1136 38 mohor
end
1137
 
1138
 
1139
// Marks which bytes are valid within the word.
1140 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1141 38 mohor
 
1142 39 mohor
reg LatchValidBytes;
1143
reg LatchValidBytes_q;
1144 38 mohor
 
1145 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1146 38 mohor
begin
1147 40 mohor
  if(Reset)
1148 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1149 38 mohor
  else
1150 39 mohor
  if(TxLengthLt4 & TxBDReady)
1151
    LatchValidBytes <=#Tp 1'b1;
1152 38 mohor
  else
1153 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1154 38 mohor
end
1155
 
1156 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1157 38 mohor
begin
1158 40 mohor
  if(Reset)
1159 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1160 38 mohor
  else
1161 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1162 38 mohor
end
1163
 
1164
 
1165 39 mohor
// Latching valid bytes
1166 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1167 38 mohor
begin
1168 40 mohor
  if(Reset)
1169 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1170 38 mohor
  else
1171 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1172
    TxValidBytesLatched <=#Tp TxValidBytes;
1173
  else
1174
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1175
    TxValidBytesLatched <=#Tp 2'h0;
1176 38 mohor
end
1177
 
1178
 
1179
assign TxIRQEn          = TxStatus[14];
1180 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1181
assign PerPacketPad     = TxStatus[12];
1182
assign PerPacketCrcEn   = TxStatus[11];
1183 38 mohor
 
1184
 
1185 77 mohor
assign RxIRQEn         = RxStatus[14];
1186 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1187 38 mohor
 
1188
 
1189
// Temporary Tx and Rx buffer descriptor address 
1190 39 mohor
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
1191 134 mohor
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1)     | // Using first Rx BD
1192 39 mohor
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
1193 38 mohor
 
1194
 
1195
// Latching Tx buffer descriptor address
1196 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1197 38 mohor
begin
1198 40 mohor
  if(Reset)
1199 38 mohor
    TxBDAddress <=#Tp 8'h0;
1200
  else
1201
  if(TxStatusWrite)
1202
    TxBDAddress <=#Tp TempTxBDAddress;
1203
end
1204
 
1205
 
1206
// Latching Rx buffer descriptor address
1207 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1208 38 mohor
begin
1209 40 mohor
  if(Reset)
1210 134 mohor
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1;
1211 38 mohor
  else
1212 77 mohor
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
1213 134 mohor
    RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
1214 38 mohor
  else
1215
  if(RxStatusWrite)
1216
    RxBDAddress <=#Tp TempRxBDAddress;
1217
end
1218
 
1219 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1220 38 mohor
 
1221 60 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 6'h0, RxStatusInLatched};
1222
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1223 38 mohor
 
1224 60 mohor
 
1225 38 mohor
// Signals used for various purposes
1226 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1227 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1228
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1229
 
1230
 
1231
 
1232 39 mohor
// Generating delayed signals
1233 40 mohor
always @ (posedge MTxClk or posedge Reset)
1234 38 mohor
begin
1235 40 mohor
  if(Reset)
1236 39 mohor
    begin
1237
      TxAbort_q      <=#Tp 1'b0;
1238
      TxRetry_q      <=#Tp 1'b0;
1239
      TxUsedData_q   <=#Tp 1'b0;
1240
    end
1241 38 mohor
  else
1242 39 mohor
    begin
1243
      TxAbort_q      <=#Tp TxAbort;
1244
      TxRetry_q      <=#Tp TxRetry;
1245
      TxUsedData_q   <=#Tp TxUsedData;
1246
    end
1247 38 mohor
end
1248
 
1249
// Generating delayed signals
1250 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1251 38 mohor
begin
1252 40 mohor
  if(Reset)
1253 38 mohor
    begin
1254 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1255
      TxAbort_wb_q  <=#Tp 1'b0;
1256 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1257 219 mohor
      TxDonePulse_q  <=#Tp 1'b0;
1258 38 mohor
    end
1259
  else
1260
    begin
1261 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1262
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1263 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1264 219 mohor
      TxDonePulse_q  <=#Tp TxDonePulse;
1265 38 mohor
    end
1266
end
1267
 
1268
 
1269 219 mohor
reg TxAbortPacketBlocked;
1270
always @ (posedge WB_CLK_I or posedge Reset)
1271
begin
1272
  if(Reset)
1273
    TxAbortPacket <=#Tp 1'b0;
1274
  else
1275
  if(TxAbort_wb & (!TxAbortPacketBlocked) & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
1276
    TxAbortPacket <=#Tp 1'b1;
1277
  else
1278
    TxAbortPacket <=#Tp 1'b0;
1279
end
1280
 
1281
 
1282
always @ (posedge WB_CLK_I or posedge Reset)
1283
begin
1284
  if(Reset)
1285
    TxAbortPacketBlocked <=#Tp 1'b0;
1286
  else
1287
  if(TxAbortPacket)
1288
    TxAbortPacketBlocked <=#Tp 1'b1;
1289
  else
1290
  if(!TxAbort_wb & TxAbort_wb_q)
1291
    TxAbortPacketBlocked <=#Tp 1'b0;
1292
end
1293
 
1294
 
1295
reg TxRetryPacketBlocked;
1296
always @ (posedge WB_CLK_I or posedge Reset)
1297
begin
1298
  if(Reset)
1299
    TxRetryPacket <=#Tp 1'b0;
1300
  else
1301
  if(TxRetry_wb & (!TxRetryPacketBlocked) & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
1302
    TxRetryPacket <=#Tp 1'b1;
1303
  else
1304
    TxRetryPacket <=#Tp 1'b0;
1305
end
1306
 
1307
 
1308
always @ (posedge WB_CLK_I or posedge Reset)
1309
begin
1310
  if(Reset)
1311
    TxRetryPacketBlocked <=#Tp 1'b0;
1312
  else
1313
  if(TxRetryPacket)
1314
    TxRetryPacketBlocked <=#Tp 1'b1;
1315
  else
1316
  if(!TxRetry_wb & TxRetry_wb_q)
1317
    TxRetryPacketBlocked <=#Tp 1'b0;
1318
end
1319
 
1320
 
1321 38 mohor
// Sinchronizing and evaluating tx data
1322 39 mohor
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
1323 219 mohor
assign SetGotData = (TxStartFrm_wb);
1324 38 mohor
 
1325
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
1326 40 mohor
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1327
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1328 38 mohor
 
1329
 
1330
// Indication of the last word
1331 40 mohor
always @ (posedge MTxClk or posedge Reset)
1332 38 mohor
begin
1333 40 mohor
  if(Reset)
1334 38 mohor
    LastWord <=#Tp 1'b0;
1335
  else
1336
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1337
    LastWord <=#Tp 1'b0;
1338
  else
1339
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1340 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1341 38 mohor
end
1342
 
1343
 
1344
// Tx end frame generation
1345 40 mohor
always @ (posedge MTxClk or posedge Reset)
1346 38 mohor
begin
1347 40 mohor
  if(Reset)
1348 38 mohor
    TxEndFrm <=#Tp 1'b0;
1349
  else
1350 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1351 38 mohor
    TxEndFrm <=#Tp 1'b0;
1352
  else
1353
  if(Flop & LastWord)
1354
    begin
1355 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1356 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1357
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1358
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1359
 
1360
        default : TxEndFrm <=#Tp 1'b0;
1361
      endcase
1362
    end
1363
end
1364
 
1365
 
1366
// Tx data selection (latching)
1367 40 mohor
always @ (posedge MTxClk or posedge Reset)
1368 38 mohor
begin
1369 40 mohor
  if(Reset)
1370 96 mohor
    TxData <=#Tp 0;
1371 38 mohor
  else
1372 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1373 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1374 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1375
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1376
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1377
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1378
    endcase
1379 38 mohor
  else
1380 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1381 96 mohor
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1382
  else
1383 38 mohor
  if(TxUsedData & Flop)
1384
    begin
1385 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1386 82 mohor
 
1387
        1 : TxData <=#Tp TxDataLatched[23:16];
1388
        2 : TxData <=#Tp TxDataLatched[15:8];
1389
        3 : TxData <=#Tp TxDataLatched[7:0];
1390 38 mohor
      endcase
1391
    end
1392
end
1393
 
1394
 
1395
// Latching tx data
1396 40 mohor
always @ (posedge MTxClk or posedge Reset)
1397 38 mohor
begin
1398 40 mohor
  if(Reset)
1399 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1400
  else
1401 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1402 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1403 38 mohor
end
1404
 
1405
 
1406
// Tx under run
1407 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1408 38 mohor
begin
1409 40 mohor
  if(Reset)
1410 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1411 38 mohor
  else
1412 39 mohor
  if(TxAbortPulse)
1413 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1414
  else
1415
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1416
    TxUnderRun_wb <=#Tp 1'b1;
1417
end
1418
 
1419
 
1420 159 mohor
reg TxUnderRun_sync1;
1421
 
1422 60 mohor
// Tx under run
1423
always @ (posedge MTxClk or posedge Reset)
1424
begin
1425
  if(Reset)
1426 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b0;
1427 43 mohor
  else
1428 60 mohor
  if(TxUnderRun_wb)
1429 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b1;
1430 60 mohor
  else
1431 159 mohor
  if(BlockingTxStatusWrite_sync2)
1432
    TxUnderRun_sync1 <=#Tp 1'b0;
1433
end
1434
 
1435
// Tx under run
1436
always @ (posedge MTxClk or posedge Reset)
1437
begin
1438
  if(Reset)
1439 60 mohor
    TxUnderRun <=#Tp 1'b0;
1440 159 mohor
  else
1441
  if(BlockingTxStatusWrite_sync2)
1442
    TxUnderRun <=#Tp 1'b0;
1443
  else
1444
  if(TxUnderRun_sync1)
1445
    TxUnderRun <=#Tp 1'b1;
1446 38 mohor
end
1447
 
1448
 
1449
// Tx Byte counter
1450 40 mohor
always @ (posedge MTxClk or posedge Reset)
1451 38 mohor
begin
1452 40 mohor
  if(Reset)
1453 38 mohor
    TxByteCnt <=#Tp 2'h0;
1454
  else
1455
  if(TxAbort_q | TxRetry_q)
1456
    TxByteCnt <=#Tp 2'h0;
1457
  else
1458
  if(TxStartFrm & ~TxUsedData)
1459 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1460 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1461
      2'h1 : TxByteCnt <=#Tp 2'h2;
1462
      2'h2 : TxByteCnt <=#Tp 2'h3;
1463
      2'h3 : TxByteCnt <=#Tp 2'h0;
1464
    endcase
1465 38 mohor
  else
1466
  if(TxUsedData & Flop)
1467 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1468 38 mohor
end
1469
 
1470 39 mohor
 
1471 150 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1472
reg ReadTxDataFromFifo_sync1;
1473
reg ReadTxDataFromFifo_sync2;
1474
reg ReadTxDataFromFifo_sync3;
1475
reg ReadTxDataFromFifo_syncb1;
1476
reg ReadTxDataFromFifo_syncb2;
1477
reg ReadTxDataFromFifo_syncb3;
1478
 
1479
 
1480
always @ (posedge MTxClk or posedge Reset)
1481
begin
1482
  if(Reset)
1483
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1484
  else
1485 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1486 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1487 150 mohor
  else
1488
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1489
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1490 38 mohor
end
1491
 
1492 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1493 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1494 38 mohor
begin
1495 40 mohor
  if(Reset)
1496 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1497 38 mohor
  else
1498 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1499
end
1500 38 mohor
 
1501 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1502 38 mohor
begin
1503 40 mohor
  if(Reset)
1504 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1505 38 mohor
  else
1506 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1507 38 mohor
end
1508
 
1509 40 mohor
always @ (posedge MTxClk or posedge Reset)
1510 38 mohor
begin
1511 40 mohor
  if(Reset)
1512 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1513 38 mohor
  else
1514 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1515 38 mohor
end
1516
 
1517 40 mohor
always @ (posedge MTxClk or posedge Reset)
1518 38 mohor
begin
1519 40 mohor
  if(Reset)
1520 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1521 38 mohor
  else
1522 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1523 38 mohor
end
1524
 
1525 150 mohor
always @ (posedge MTxClk or posedge Reset)
1526
begin
1527
  if(Reset)
1528
    ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
1529
  else
1530
    ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
1531
end
1532
 
1533 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1534 38 mohor
begin
1535 40 mohor
  if(Reset)
1536 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1537 38 mohor
  else
1538 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1539 38 mohor
end
1540
 
1541 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1542
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1543 38 mohor
 
1544
 
1545 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1546 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1547 38 mohor
begin
1548 40 mohor
  if(Reset)
1549 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1550 38 mohor
  else
1551 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1552 38 mohor
end
1553
 
1554 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1555 38 mohor
begin
1556 40 mohor
  if(Reset)
1557 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1558 38 mohor
  else
1559 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1560 38 mohor
end
1561
 
1562
 
1563 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1564 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1565 38 mohor
begin
1566 40 mohor
  if(Reset)
1567 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1568 38 mohor
  else
1569 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1570 38 mohor
end
1571
 
1572 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1573 38 mohor
begin
1574 40 mohor
  if(Reset)
1575 39 mohor
    TxDone_wb <=#Tp 1'b0;
1576 38 mohor
  else
1577 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1578 38 mohor
end
1579
 
1580 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1581 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1582 38 mohor
begin
1583 40 mohor
  if(Reset)
1584 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1585 38 mohor
  else
1586 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1587 38 mohor
end
1588
 
1589 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1590 38 mohor
begin
1591 40 mohor
  if(Reset)
1592 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1593
  else
1594 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1595 38 mohor
end
1596
 
1597
 
1598 150 mohor
reg RxAbortSync1;
1599
reg RxAbortSync2;
1600
reg RxAbortSync3;
1601
reg RxAbortSync4;
1602
reg RxAbortSyncb1;
1603
reg RxAbortSyncb2;
1604 39 mohor
 
1605 150 mohor
//assign StartRxBDRead = RxStatusWrite | RxAbortLatched;
1606
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
1607
 
1608 40 mohor
// Reading the Rx buffer descriptor
1609
always @ (posedge WB_CLK_I or posedge Reset)
1610
begin
1611
  if(Reset)
1612
    RxBDRead <=#Tp 1'b1;
1613
  else
1614 166 mohor
  if(StartRxBDRead & ~RxReady)
1615 40 mohor
    RxBDRead <=#Tp 1'b1;
1616
  else
1617
  if(RxBDReady)
1618
    RxBDRead <=#Tp 1'b0;
1619
end
1620 39 mohor
 
1621
 
1622 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1623
// written to the previous one.
1624
 
1625
// Latching READY status of the Rx buffer descriptor
1626 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1627 38 mohor
begin
1628 40 mohor
  if(Reset)
1629 38 mohor
    RxBDReady <=#Tp 1'b0;
1630
  else
1631 166 mohor
  if(RxPointerRead)
1632 150 mohor
    RxBDReady <=#Tp 1'b0;
1633
  else
1634 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1635
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1636 38 mohor
end
1637
 
1638 40 mohor
// Latching Rx buffer descriptor status
1639
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1640
always @ (posedge WB_CLK_I or posedge Reset)
1641 38 mohor
begin
1642 40 mohor
  if(Reset)
1643 60 mohor
    RxStatus <=#Tp 2'h0;
1644 38 mohor
  else
1645 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1646 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1647 38 mohor
end
1648
 
1649
 
1650 166 mohor
// RxReady generation
1651
always @ (posedge WB_CLK_I or posedge Reset)
1652
begin
1653
  if(Reset)
1654
    RxReady <=#Tp 1'b0;
1655
  else
1656
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
1657
    RxReady <=#Tp 1'b0;
1658
  else
1659
  if(RxEn & RxEn_q & RxPointerRead)
1660
    RxReady <=#Tp 1'b1;
1661
end
1662 38 mohor
 
1663
 
1664 40 mohor
// Reading Rx BD pointer
1665
 
1666
 
1667
assign StartRxPointerRead = RxBDRead & RxBDReady;
1668
 
1669
// Reading Tx BD Pointer
1670
always @ (posedge WB_CLK_I or posedge Reset)
1671 38 mohor
begin
1672 40 mohor
  if(Reset)
1673
    RxPointerRead <=#Tp 1'b0;
1674 38 mohor
  else
1675 40 mohor
  if(StartRxPointerRead)
1676
    RxPointerRead <=#Tp 1'b1;
1677 38 mohor
  else
1678 166 mohor
  if(RxEn & RxEn_q)
1679 40 mohor
    RxPointerRead <=#Tp 1'b0;
1680 38 mohor
end
1681
 
1682 113 mohor
 
1683 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1684
always @ (posedge WB_CLK_I or posedge Reset)
1685
begin
1686
  if(Reset)
1687 159 mohor
    RxPointerMSB <=#Tp 30'h0;
1688 40 mohor
  else
1689
  if(RxEn & RxEn_q & RxPointerRead)
1690 159 mohor
    RxPointerMSB <=#Tp ram_do[31:2];
1691 40 mohor
  else
1692 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1693 159 mohor
      RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1694 40 mohor
end
1695 38 mohor
 
1696
 
1697 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1698 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1699
begin
1700
  if(Reset)
1701 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp 0;
1702 96 mohor
  else
1703 159 mohor
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
1704
    RxPointerLSB_rst[1:0] <=#Tp 0;
1705 96 mohor
  else
1706
  if(RxEn & RxEn_q & RxPointerRead)
1707 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
1708 96 mohor
end
1709
 
1710
 
1711 159 mohor
always @ (RxPointerLSB_rst)
1712 96 mohor
begin
1713 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1714
    2'h0 : RxByteSel[3:0] = 4'hf;
1715
    2'h1 : RxByteSel[3:0] = 4'h7;
1716
    2'h2 : RxByteSel[3:0] = 4'h3;
1717
    2'h3 : RxByteSel[3:0] = 4'h1;
1718 96 mohor
  endcase
1719
end
1720
 
1721
 
1722
always @ (posedge WB_CLK_I or posedge Reset)
1723
begin
1724
  if(Reset)
1725 40 mohor
    RxEn_needed <=#Tp 1'b0;
1726 38 mohor
  else
1727 166 mohor
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1728 40 mohor
    RxEn_needed <=#Tp 1'b1;
1729 38 mohor
  else
1730 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1731
    RxEn_needed <=#Tp 1'b0;
1732 38 mohor
end
1733
 
1734
 
1735 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1736
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1737 38 mohor
 
1738 42 mohor
reg RxStatusWriteLatched;
1739
reg RxStatusWrite_rck;
1740
 
1741
always @ (posedge WB_CLK_I or posedge Reset)
1742
begin
1743
  if(Reset)
1744
    RxStatusWriteLatched <=#Tp 1'b0;
1745
  else
1746 87 mohor
  if(RxStatusWrite & ~RxStatusWrite_rck)
1747 42 mohor
    RxStatusWriteLatched <=#Tp 1'b1;
1748
  else
1749
  if(RxStatusWrite_rck)
1750
    RxStatusWriteLatched <=#Tp 1'b0;
1751
end
1752
 
1753
 
1754
always @ (posedge MRxClk or posedge Reset)
1755
begin
1756
  if(Reset)
1757
    RxStatusWrite_rck <=#Tp 1'b0;
1758
  else
1759 87 mohor
  if(RxStatusWriteLatched)
1760
    RxStatusWrite_rck <=#Tp 1'b1;
1761
  else
1762
    RxStatusWrite_rck <=#Tp 1'b0;
1763 42 mohor
end
1764
 
1765
 
1766 40 mohor
reg RxEnableWindow;
1767 38 mohor
 
1768
// Indicating that last byte is being reveived
1769 40 mohor
always @ (posedge MRxClk or posedge Reset)
1770 38 mohor
begin
1771 40 mohor
  if(Reset)
1772 38 mohor
    LastByteIn <=#Tp 1'b0;
1773
  else
1774 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1775 38 mohor
    LastByteIn <=#Tp 1'b0;
1776
  else
1777 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1778 38 mohor
    LastByteIn <=#Tp 1'b1;
1779
end
1780
 
1781 159 mohor
reg ShiftEnded_rck;
1782 40 mohor
reg ShiftEndedSync1;
1783
reg ShiftEndedSync2;
1784 118 mohor
reg ShiftEndedSync3;
1785
reg ShiftEndedSync_c1;
1786
reg ShiftEndedSync_c2;
1787
 
1788 40 mohor
wire StartShiftWillEnd;
1789 96 mohor
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1790 38 mohor
 
1791
// Indicating that data reception will end
1792 40 mohor
always @ (posedge MRxClk or posedge Reset)
1793 38 mohor
begin
1794 40 mohor
  if(Reset)
1795 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1796
  else
1797 159 mohor
  if(ShiftEnded_rck | RxAbort)
1798 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1799
  else
1800 40 mohor
  if(StartShiftWillEnd)
1801 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
1802
end
1803
 
1804
 
1805 40 mohor
 
1806 38 mohor
// Receive byte counter
1807 40 mohor
always @ (posedge MRxClk or posedge Reset)
1808 38 mohor
begin
1809 40 mohor
  if(Reset)
1810 38 mohor
    RxByteCnt <=#Tp 2'h0;
1811
  else
1812 159 mohor
  if(ShiftEnded_rck | RxAbort)
1813 38 mohor
    RxByteCnt <=#Tp 2'h0;
1814 97 lampret
  else
1815 166 mohor
  if(RxValid & RxStartFrm & RxReady)
1816 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
1817 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
1818
      2'h1 : RxByteCnt <=#Tp 2'h2;
1819
      2'h2 : RxByteCnt <=#Tp 2'h3;
1820
      2'h3 : RxByteCnt <=#Tp 2'h0;
1821
    endcase
1822 38 mohor
  else
1823 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
1824 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
1825 38 mohor
end
1826
 
1827
 
1828
// Indicates how many bytes are valid within the last word
1829 40 mohor
always @ (posedge MRxClk or posedge Reset)
1830 38 mohor
begin
1831 40 mohor
  if(Reset)
1832 38 mohor
    RxValidBytes <=#Tp 2'h1;
1833
  else
1834 96 mohor
  if(RxValid & RxStartFrm)
1835 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
1836 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
1837
      2'h1 : RxValidBytes <=#Tp 2'h2;
1838
      2'h2 : RxValidBytes <=#Tp 2'h3;
1839
      2'h3 : RxValidBytes <=#Tp 2'h0;
1840
    endcase
1841 38 mohor
  else
1842 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
1843 38 mohor
    RxValidBytes <=#Tp RxValidBytes + 1;
1844
end
1845
 
1846
 
1847 40 mohor
always @ (posedge MRxClk or posedge Reset)
1848 38 mohor
begin
1849 40 mohor
  if(Reset)
1850
    RxDataLatched1       <=#Tp 24'h0;
1851 38 mohor
  else
1852 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
1853 96 mohor
    if(RxStartFrm)
1854 40 mohor
    begin
1855 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
1856 96 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
1857
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
1858
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
1859
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
1860
      endcase
1861
    end
1862
    else if (RxEnableWindow)
1863
    begin
1864 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
1865 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
1866
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
1867
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
1868 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
1869
      endcase
1870
    end
1871 38 mohor
end
1872
 
1873 40 mohor
wire SetWriteRxDataToFifo;
1874 38 mohor
 
1875 40 mohor
// Assembling data that will be written to the rx_fifo
1876
always @ (posedge MRxClk or posedge Reset)
1877 38 mohor
begin
1878 40 mohor
  if(Reset)
1879
    RxDataLatched2 <=#Tp 32'h0;
1880 38 mohor
  else
1881 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
1882 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
1883 38 mohor
  else
1884 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
1885 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
1886 82 mohor
 
1887
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
1888
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
1889
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
1890 40 mohor
    endcase
1891 38 mohor
end
1892
 
1893
 
1894 40 mohor
reg WriteRxDataToFifoSync1;
1895
reg WriteRxDataToFifoSync2;
1896 150 mohor
reg WriteRxDataToFifoSync3;
1897 38 mohor
 
1898
 
1899 40 mohor
// Indicating start of the reception process
1900 166 mohor
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
1901
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
1902
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
1903 38 mohor
 
1904 150 mohor
always @ (posedge MRxClk or posedge Reset)
1905
begin
1906
  if(Reset)
1907
    WriteRxDataToFifo <=#Tp 1'b0;
1908
  else
1909
  if(SetWriteRxDataToFifo & ~RxAbort)
1910
    WriteRxDataToFifo <=#Tp 1'b1;
1911
  else
1912
  if(WriteRxDataToFifoSync2 | RxAbort)
1913
    WriteRxDataToFifo <=#Tp 1'b0;
1914
end
1915 40 mohor
 
1916 150 mohor
 
1917
 
1918
always @ (posedge WB_CLK_I or posedge Reset)
1919
begin
1920
  if(Reset)
1921
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
1922
  else
1923
  if(WriteRxDataToFifo)
1924
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
1925
  else
1926
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
1927
end
1928
 
1929
always @ (posedge WB_CLK_I or posedge Reset)
1930
begin
1931
  if(Reset)
1932
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
1933
  else
1934
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
1935
end
1936
 
1937
always @ (posedge WB_CLK_I or posedge Reset)
1938
begin
1939
  if(Reset)
1940
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
1941
  else
1942
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
1943
end
1944
 
1945
wire WriteRxDataToFifo_wb;
1946
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
1947
 
1948
 
1949 90 mohor
reg LatchedRxStartFrm;
1950
reg SyncRxStartFrm;
1951
reg SyncRxStartFrm_q;
1952 150 mohor
reg SyncRxStartFrm_q2;
1953 90 mohor
wire RxFifoReset;
1954 40 mohor
 
1955 90 mohor
always @ (posedge MRxClk or posedge Reset)
1956
begin
1957
  if(Reset)
1958
    LatchedRxStartFrm <=#Tp 0;
1959
  else
1960 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
1961 90 mohor
    LatchedRxStartFrm <=#Tp 1;
1962
  else
1963 150 mohor
  if(SyncRxStartFrm_q)
1964 90 mohor
    LatchedRxStartFrm <=#Tp 0;
1965
end
1966
 
1967
 
1968
always @ (posedge WB_CLK_I or posedge Reset)
1969
begin
1970
  if(Reset)
1971
    SyncRxStartFrm <=#Tp 0;
1972
  else
1973
  if(LatchedRxStartFrm)
1974
    SyncRxStartFrm <=#Tp 1;
1975
  else
1976
    SyncRxStartFrm <=#Tp 0;
1977
end
1978
 
1979
 
1980
always @ (posedge WB_CLK_I or posedge Reset)
1981
begin
1982
  if(Reset)
1983
    SyncRxStartFrm_q <=#Tp 0;
1984
  else
1985
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
1986
end
1987
 
1988 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1989
begin
1990
  if(Reset)
1991
    SyncRxStartFrm_q2 <=#Tp 0;
1992
  else
1993
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
1994
end
1995 90 mohor
 
1996
 
1997 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
1998 90 mohor
 
1999 150 mohor
 
2000 219 mohor
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
2001 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
2002
         .clk(WB_CLK_I),                                .reset(Reset),
2003 219 mohor
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
2004 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
2005 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
2006 150 mohor
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
2007 88 mohor
        );
2008 40 mohor
 
2009 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2010 40 mohor
 
2011
 
2012
 
2013
// Generation of the end-of-frame signal
2014
always @ (posedge MRxClk or posedge Reset)
2015 38 mohor
begin
2016 40 mohor
  if(Reset)
2017 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2018 38 mohor
  else
2019 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2020 159 mohor
    ShiftEnded_rck <=#Tp 1'b1;
2021 38 mohor
  else
2022 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2023 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2024 38 mohor
end
2025
 
2026 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2027
begin
2028
  if(Reset)
2029
    ShiftEndedSync1 <=#Tp 1'b0;
2030
  else
2031 159 mohor
    ShiftEndedSync1 <=#Tp ShiftEnded_rck;
2032 40 mohor
end
2033 38 mohor
 
2034 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2035 38 mohor
begin
2036 40 mohor
  if(Reset)
2037
    ShiftEndedSync2 <=#Tp 1'b0;
2038 38 mohor
  else
2039 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
2040 40 mohor
end
2041 38 mohor
 
2042 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2043
begin
2044
  if(Reset)
2045
    ShiftEndedSync3 <=#Tp 1'b0;
2046
  else
2047
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2048
    ShiftEndedSync3 <=#Tp 1'b1;
2049
  else
2050
  if(ShiftEnded)
2051
    ShiftEndedSync3 <=#Tp 1'b0;
2052
end
2053 38 mohor
 
2054 40 mohor
// Generation of the end-of-frame signal
2055
always @ (posedge WB_CLK_I or posedge Reset)
2056 38 mohor
begin
2057 40 mohor
  if(Reset)
2058
    ShiftEnded <=#Tp 1'b0;
2059 38 mohor
  else
2060 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2061 40 mohor
    ShiftEnded <=#Tp 1'b1;
2062 38 mohor
  else
2063 40 mohor
  if(RxStatusWrite)
2064
    ShiftEnded <=#Tp 1'b0;
2065 38 mohor
end
2066
 
2067 118 mohor
always @ (posedge MRxClk or posedge Reset)
2068
begin
2069
  if(Reset)
2070
    ShiftEndedSync_c1 <=#Tp 1'b0;
2071
  else
2072
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
2073
end
2074 38 mohor
 
2075 118 mohor
always @ (posedge MRxClk or posedge Reset)
2076
begin
2077
  if(Reset)
2078
    ShiftEndedSync_c2 <=#Tp 1'b0;
2079
  else
2080
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
2081
end
2082
 
2083 40 mohor
// Generation of the end-of-frame signal
2084
always @ (posedge MRxClk or posedge Reset)
2085 38 mohor
begin
2086 40 mohor
  if(Reset)
2087
    RxEnableWindow <=#Tp 1'b0;
2088 38 mohor
  else
2089 40 mohor
  if(RxStartFrm)
2090
    RxEnableWindow <=#Tp 1'b1;
2091 38 mohor
  else
2092 40 mohor
  if(RxEndFrm | RxAbort)
2093
    RxEnableWindow <=#Tp 1'b0;
2094 38 mohor
end
2095
 
2096
 
2097 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2098 38 mohor
begin
2099 40 mohor
  if(Reset)
2100
    RxAbortSync1 <=#Tp 1'b0;
2101 38 mohor
  else
2102 150 mohor
    RxAbortSync1 <=#Tp RxAbortLatched;
2103 40 mohor
end
2104
 
2105
always @ (posedge WB_CLK_I or posedge Reset)
2106
begin
2107
  if(Reset)
2108
    RxAbortSync2 <=#Tp 1'b0;
2109 38 mohor
  else
2110 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
2111 38 mohor
end
2112
 
2113 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2114
begin
2115
  if(Reset)
2116
    RxAbortSync3 <=#Tp 1'b0;
2117
  else
2118
    RxAbortSync3 <=#Tp RxAbortSync2;
2119
end
2120
 
2121
always @ (posedge WB_CLK_I or posedge Reset)
2122
begin
2123
  if(Reset)
2124
    RxAbortSync4 <=#Tp 1'b0;
2125
  else
2126
    RxAbortSync4 <=#Tp RxAbortSync3;
2127
end
2128
 
2129 40 mohor
always @ (posedge MRxClk or posedge Reset)
2130
begin
2131
  if(Reset)
2132
    RxAbortSyncb1 <=#Tp 1'b0;
2133
  else
2134
    RxAbortSyncb1 <=#Tp RxAbortSync2;
2135
end
2136 38 mohor
 
2137 40 mohor
always @ (posedge MRxClk or posedge Reset)
2138 38 mohor
begin
2139 40 mohor
  if(Reset)
2140
    RxAbortSyncb2 <=#Tp 1'b0;
2141 38 mohor
  else
2142 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
2143 38 mohor
end
2144
 
2145
 
2146 64 mohor
always @ (posedge MRxClk or posedge Reset)
2147
begin
2148
  if(Reset)
2149
    RxAbortLatched <=#Tp 1'b0;
2150
  else
2151 150 mohor
  if(RxAbortSyncb2)
2152
    RxAbortLatched <=#Tp 1'b0;
2153
  else
2154 64 mohor
  if(RxAbort)
2155
    RxAbortLatched <=#Tp 1'b1;
2156
end
2157 40 mohor
 
2158 64 mohor
 
2159 42 mohor
always @ (posedge MRxClk or posedge Reset)
2160
begin
2161
  if(Reset)
2162
    LatchedRxLength[15:0] <=#Tp 16'h0;
2163
  else
2164 150 mohor
  if(LoadRxStatus)
2165 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
2166
end
2167
 
2168
 
2169 60 mohor
assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2170 42 mohor
 
2171
always @ (posedge MRxClk or posedge Reset)
2172
begin
2173
  if(Reset)
2174
    RxStatusInLatched <=#Tp 'h0;
2175
  else
2176 150 mohor
  if(LoadRxStatus)
2177 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
2178
end
2179
 
2180
 
2181 60 mohor
// Rx overrun
2182
always @ (posedge WB_CLK_I or posedge Reset)
2183
begin
2184
  if(Reset)
2185
    RxOverrun <=#Tp 1'b0;
2186
  else
2187
  if(RxStatusWrite)
2188
    RxOverrun <=#Tp 1'b0;
2189
  else
2190
  if(RxBufferFull & WriteRxDataToFifo_wb)
2191
    RxOverrun <=#Tp 1'b1;
2192
end
2193 48 mohor
 
2194 77 mohor
 
2195
 
2196
wire TxError;
2197
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2198
 
2199
wire RxError;
2200
assign RxError = |RxStatusInLatched[6:0];
2201
 
2202
// Tx Done Interrupt
2203
always @ (posedge WB_CLK_I or posedge Reset)
2204
begin
2205
  if(Reset)
2206
    TxB_IRQ <=#Tp 1'b0;
2207
  else
2208
  if(TxStatusWrite & TxIRQEn)
2209
    TxB_IRQ <=#Tp ~TxError;
2210
  else
2211
    TxB_IRQ <=#Tp 1'b0;
2212
end
2213
 
2214
 
2215
// Tx Error Interrupt
2216
always @ (posedge WB_CLK_I or posedge Reset)
2217
begin
2218
  if(Reset)
2219
    TxE_IRQ <=#Tp 1'b0;
2220
  else
2221
  if(TxStatusWrite & TxIRQEn)
2222
    TxE_IRQ <=#Tp TxError;
2223
  else
2224
    TxE_IRQ <=#Tp 1'b0;
2225
end
2226
 
2227
 
2228
// Rx Done Interrupt
2229
always @ (posedge WB_CLK_I or posedge Reset)
2230
begin
2231
  if(Reset)
2232
    RxB_IRQ <=#Tp 1'b0;
2233
  else
2234
  if(RxStatusWrite & RxIRQEn)
2235 167 mohor
    RxB_IRQ <=#Tp ReceivedPacketGood & ~RxError;
2236 77 mohor
  else
2237
    RxB_IRQ <=#Tp 1'b0;
2238
end
2239
 
2240
 
2241
// Rx Error Interrupt
2242
always @ (posedge WB_CLK_I or posedge Reset)
2243
begin
2244
  if(Reset)
2245
    RxE_IRQ <=#Tp 1'b0;
2246
  else
2247
  if(RxStatusWrite & RxIRQEn)
2248
    RxE_IRQ <=#Tp RxError;
2249
  else
2250
    RxE_IRQ <=#Tp 1'b0;
2251
end
2252
 
2253
 
2254 166 mohor
// Busy Interrupt
2255 77 mohor
 
2256 166 mohor
reg Busy_IRQ_rck;
2257
reg Busy_IRQ_sync1;
2258
reg Busy_IRQ_sync2;
2259
reg Busy_IRQ_sync3;
2260
reg Busy_IRQ_syncb1;
2261
reg Busy_IRQ_syncb2;
2262 77 mohor
 
2263
 
2264 166 mohor
always @ (posedge MRxClk or posedge Reset)
2265
begin
2266
  if(Reset)
2267
    Busy_IRQ_rck <=#Tp 1'b0;
2268
  else
2269
  if(RxValid & RxStartFrm & ~RxReady)
2270
    Busy_IRQ_rck <=#Tp 1'b1;
2271
  else
2272
  if(Busy_IRQ_syncb2)
2273
    Busy_IRQ_rck <=#Tp 1'b0;
2274
end
2275 77 mohor
 
2276 166 mohor
always @ (posedge WB_CLK_I)
2277
begin
2278
    Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
2279
    Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
2280
    Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
2281
end
2282
 
2283
always @ (posedge MRxClk)
2284
begin
2285
    Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
2286
    Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
2287
end
2288
 
2289
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
2290
 
2291
 
2292 60 mohor
 
2293
// TX
2294 61 mohor
// bit 15 ready
2295
// bit 14 interrupt
2296
// bit 13 wrap
2297
// bit 12 pad
2298
// bit 11 crc
2299
// bit 10 last
2300
// bit 9  pause request (control frame)
2301
// bit 8  TxUnderRun          
2302
// bit 7-4 RetryCntLatched    
2303
// bit 3  retransmittion limit
2304
// bit 2  LateCollLatched        
2305
// bit 1  DeferLatched        
2306
// bit 0  CarrierSenseLost    
2307 60 mohor
 
2308
 
2309
// RX
2310
// bit 15 od rx je empty
2311 61 mohor
// bit 14 od rx je interrupt
2312 60 mohor
// bit 13 od rx je wrap
2313
// bit 12 od rx je reserved
2314
// bit 11 od rx je reserved
2315
// bit 10 od rx je reserved
2316
// bit 9  od rx je reserved
2317
// bit 8  od rx je reserved
2318 110 mohor
// bit 7  od rx je Miss
2319 60 mohor
// bit 6  od rx je RxOverrun
2320
// bit 5  od rx je InvalidSymbol
2321
// bit 4  od rx je DribbleNibble
2322
// bit 3  od rx je ReceivedPacketTooBig
2323
// bit 2  od rx je ShortFrame
2324
// bit 1  od rx je LatchedCrcError
2325
// bit 0  od rx je RxLateCollision
2326
 
2327 110 mohor
 
2328 38 mohor
endmodule
2329
 

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