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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 221

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
45
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
46
// TxDone and TxRetry are generated after the current WISHBONE access is
47
// finished.
48
//
49 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
50
// BIST added.
51
//
52 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
53
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
54
//
55 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
56
// Reception is possible after RxPointer is read and not after BD is read. For
57
// that reason RxBDReady is changed to RxReady.
58
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
59
// comes, interrupt is generated.
60
//
61 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
62
// Ethernet debug registers removed.
63
//
64 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
65
// Async reset for WB_ACK_O removed (when core was in reset, it was
66
// impossible to access BDs).
67
// RxPointers and TxPointers names changed to be more descriptive.
68
// TxUnderRun synchronized.
69
//
70 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
71
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
72
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
73
// was not used OK.
74
//
75 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
76
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
77
// need to multiply or devide any more.
78
//
79 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
80
// WriteRxDataToMemory signal changed so end of frame (when last word is
81
// written to fifo) is changed.
82
//
83 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
84
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
85
//
86 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
87
// ShiftEnded synchronization changed.
88
//
89 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
90
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
91
//
92 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
93
// RxPointer bug fixed.
94
//
95 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
96
// Previous bug wasn't succesfully removed. Now fixed.
97
//
98 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
99
// Master state machine had a bug when switching from master write to
100
// master read.
101
//
102 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
103
// m_wb_cyc_o signal released after every single transfer.
104
//
105 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
106
// Outputs registered. Reset changed for eth_wishbone module.
107
//
108 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
109
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
110
// bug fixed.
111
//
112 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
113
// Small typo fixed.
114
//
115 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
116
// Any address can be used for Tx and Rx BD pointers. Address does not need
117
// to be aligned.
118
//
119 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
120
// Comments in Slovene language removed.
121
//
122 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
123
// casex changed with case, fifo reset changed.
124
//
125 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
126
// rx_fifo was not always cleared ok. Fixed.
127
//
128 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
129
// Status was not latched correctly sometimes. Fixed.
130
//
131 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
132
// Big Endian problem when sending frames fixed.
133
//
134 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
135
// Byte ordering changed (Big Endian used). casex changed with case because
136
// Xilinx Foundation had problems. Tested in HW. It WORKS.
137
//
138 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
139
// Small fixes for external/internal DMA missmatches.
140
//
141 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
142
// Interrupts changed
143
//
144 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
145
// Status was not written correctly when frames were discarted because of
146
// address mismatch.
147
//
148 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
149
// RxStartFrm cleared when abort or retry comes.
150
//
151 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
152
// Changes that were lost when updating from 1.5 to 1.8 fixed.
153
//
154 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
155
// Addition  of new module eth_addrcheck.v
156
//
157
// Revision 1.7  2002/02/12 17:03:47  mohor
158
// RxOverRun added to statuses.
159
//
160
// Revision 1.6  2002/02/11 09:18:22  mohor
161
// Tx status is written back to the BD.
162
//
163 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
164
// Rx status is written back to the BD.
165
//
166 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
167
// non-DMA host interface added. Select the right configutation in eth_defines.
168
//
169 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
170
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
171
// MHz. Statuses, overrun, control frame transmission and reception still  need
172
// to be fixed.
173
//
174 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
175
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
176
// added.
177
//
178 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
179
// Initial version. Equals to eth_wishbonedma.v at this moment.
180 38 mohor
//
181
//
182
//
183
 
184
`include "eth_defines.v"
185
`include "timescale.v"
186
 
187
 
188
module eth_wishbone
189
   (
190
 
191
    // WISHBONE common
192 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
193 38 mohor
 
194
    // WISHBONE slave
195 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
196 40 mohor
    BDCs,
197 38 mohor
 
198 40 mohor
    Reset,
199
 
200 39 mohor
    // WISHBONE master
201
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
202
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
203
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
204
 
205 219 mohor
`ifdef ETH_WISHBONE_B3
206
    m_wb_cti_o, m_wb_bte_o,
207
`endif
208
 
209 38 mohor
    //TX
210 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
211 150 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
212 38 mohor
    PerPacketPad,
213
 
214
    //RX
215 40 mohor
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
216 38 mohor
 
217
    // Register
218 150 mohor
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr,
219 38 mohor
 
220
    // Interrupts
221 150 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
222 42 mohor
 
223 60 mohor
    // Rx Status
224 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
225 77 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
226 60 mohor
 
227
    // Tx Status
228 164 mohor
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
229
 
230 210 mohor
    // Bist
231
`ifdef ETH_BIST
232
   , trst, SO, SI, shift_DR, capture_DR, extest, tck
233
`endif
234
 
235
 
236
 
237 38 mohor
                );
238
 
239
 
240
parameter Tp = 1;
241
 
242 150 mohor
 
243 38 mohor
// WISHBONE common
244
input           WB_CLK_I;       // WISHBONE clock
245
input  [31:0]   WB_DAT_I;       // WISHBONE data input
246
output [31:0]   WB_DAT_O;       // WISHBONE data output
247
 
248
// WISHBONE slave
249
input   [9:2]   WB_ADR_I;       // WISHBONE address input
250
input           WB_WE_I;        // WISHBONE write enable input
251
input           BDCs;           // Buffer descriptors are selected
252
output          WB_ACK_O;       // WISHBONE acknowledge output
253
 
254 39 mohor
// WISHBONE master
255
output  [31:0]  m_wb_adr_o;     // 
256
output   [3:0]  m_wb_sel_o;     // 
257
output          m_wb_we_o;      // 
258
output  [31:0]  m_wb_dat_o;     // 
259
output          m_wb_cyc_o;     // 
260
output          m_wb_stb_o;     // 
261
input   [31:0]  m_wb_dat_i;     // 
262
input           m_wb_ack_i;     // 
263
input           m_wb_err_i;     // 
264
 
265 219 mohor
`ifdef ETH_WISHBONE_B3
266
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
267
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
268
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
269
`endif
270
 
271 40 mohor
input           Reset;       // Reset signal
272 39 mohor
 
273 60 mohor
// Rx Status signals
274 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
275
input           LatchedCrcError;  // CRC error
276
input           RxLateCollision;  // Late collision occured while receiving frame
277
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
278
input           DribbleNibble;    // Extra nibble received
279
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
280
input    [15:0] RxLength;         // Length of the incoming frame
281
input           LoadRxStatus;     // Rx status was loaded
282 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
283 39 mohor
 
284 60 mohor
// Tx Status signals
285
input     [3:0] RetryCntLatched;  // Latched Retry Counter
286
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
287
input           LateCollLatched;  // Late collision occured
288
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
289
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
290
 
291 38 mohor
// Tx
292
input           MTxClk;         // Transmit clock (from PHY)
293
input           TxUsedData;     // Transmit packet used data
294
input           TxRetry;        // Transmit packet retry
295
input           TxAbort;        // Transmit packet abort
296
input           TxDone;         // Transmission ended
297
output          TxStartFrm;     // Transmit packet start frame
298
output          TxEndFrm;       // Transmit packet end frame
299
output  [7:0]   TxData;         // Transmit packet data byte
300
output          TxUnderRun;     // Transmit packet under-run
301
output          PerPacketCrcEn; // Per packet crc enable
302
output          PerPacketPad;   // Per packet pading
303
 
304
// Rx
305
input           MRxClk;         // Receive clock (from PHY)
306
input   [7:0]   RxData;         // Received data byte (from PHY)
307
input           RxValid;        // 
308
input           RxStartFrm;     // 
309
input           RxEndFrm;       // 
310 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
311 38 mohor
 
312
//Register
313
input           r_TxEn;         // Transmit enable
314
input           r_RxEn;         // Receive enable
315
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
316
input           TX_BD_NUM_Wr;   // RxBDNumber written
317
 
318
// Interrupts
319
output TxB_IRQ;
320
output TxE_IRQ;
321
output RxB_IRQ;
322 77 mohor
output RxE_IRQ;
323 38 mohor
output Busy_IRQ;
324
 
325 77 mohor
 
326 210 mohor
// Bist
327
`ifdef ETH_BIST
328
input           trst;
329
input           shift_DR, capture_DR, tck, extest;
330
input           SI;
331
output          SO;
332
`endif
333
 
334 77 mohor
reg TxB_IRQ;
335
reg TxE_IRQ;
336
reg RxB_IRQ;
337
reg RxE_IRQ;
338
 
339 38 mohor
reg             TxStartFrm;
340
reg             TxEndFrm;
341
reg     [7:0]   TxData;
342
 
343
reg             TxUnderRun;
344 60 mohor
reg             TxUnderRun_wb;
345 38 mohor
 
346
reg             TxBDRead;
347 39 mohor
wire            TxStatusWrite;
348 38 mohor
 
349
reg     [1:0]   TxValidBytesLatched;
350
 
351
reg    [15:0]   TxLength;
352 60 mohor
reg    [15:0]   LatchedTxLength;
353
reg   [14:11]   TxStatus;
354 38 mohor
 
355 60 mohor
reg   [14:13]   RxStatus;
356 38 mohor
 
357
reg             TxStartFrm_wb;
358
reg             TxRetry_wb;
359 39 mohor
reg             TxAbort_wb;
360 38 mohor
reg             TxDone_wb;
361
 
362
reg             TxDone_wb_q;
363
reg             TxAbort_wb_q;
364 39 mohor
reg             TxRetry_wb_q;
365 219 mohor
reg             TxRetryPacket;
366 221 mohor
reg             TxRetryPacket_NotCleared;
367
reg             TxDonePacket;
368
reg             TxDonePacket_NotCleared;
369 219 mohor
reg             TxAbortPacket;
370 221 mohor
reg             TxAbortPacket_NotCleared;
371 38 mohor
reg             RxBDReady;
372 166 mohor
reg             RxReady;
373 38 mohor
reg             TxBDReady;
374
 
375
reg             RxBDRead;
376 40 mohor
wire            RxStatusWrite;
377 38 mohor
 
378
reg    [31:0]   TxDataLatched;
379
reg     [1:0]   TxByteCnt;
380
reg             LastWord;
381 39 mohor
reg             ReadTxDataFromFifo_tck;
382 38 mohor
 
383
reg             BlockingTxStatusWrite;
384
reg             BlockingTxBDRead;
385
 
386 40 mohor
reg             Flop;
387 38 mohor
 
388
reg     [7:0]   TxBDAddress;
389
reg     [7:0]   RxBDAddress;
390
 
391
reg             TxRetrySync1;
392
reg             TxAbortSync1;
393 39 mohor
reg             TxDoneSync1;
394 38 mohor
 
395
reg             TxAbort_q;
396
reg             TxRetry_q;
397
reg             TxUsedData_q;
398
 
399
reg    [31:0]   RxDataLatched2;
400 82 mohor
 
401
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
402
 
403 38 mohor
reg     [1:0]   RxValidBytes;
404
reg     [1:0]   RxByteCnt;
405
reg             LastByteIn;
406
reg             ShiftWillEnd;
407
 
408 40 mohor
reg             WriteRxDataToFifo;
409 42 mohor
reg    [15:0]   LatchedRxLength;
410 64 mohor
reg             RxAbortLatched;
411 38 mohor
 
412 40 mohor
reg             ShiftEnded;
413 60 mohor
reg             RxOverrun;
414 38 mohor
 
415 40 mohor
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
416
reg             BDRead;                     // BD Read access from WISHBONE side
417 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
418
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
419 38 mohor
 
420 39 mohor
reg             TxEndFrm_wb;
421 38 mohor
 
422 39 mohor
wire            TxRetryPulse;
423 38 mohor
wire            TxDonePulse;
424
wire            TxAbortPulse;
425
 
426
wire            StartRxBDRead;
427
 
428
wire            StartTxBDRead;
429
 
430
wire            TxIRQEn;
431
wire            WrapTxStatusBit;
432
 
433 77 mohor
wire            RxIRQEn;
434 38 mohor
wire            WrapRxStatusBit;
435
 
436
wire    [1:0]   TxValidBytes;
437
 
438
wire    [7:0]   TempTxBDAddress;
439
wire    [7:0]   TempRxBDAddress;
440
 
441
wire            SetGotData;
442
wire            GotDataEvaluate;
443
 
444 106 mohor
reg             WB_ACK_O;
445 38 mohor
 
446 60 mohor
wire    [6:0]   RxStatusIn;
447
reg     [6:0]   RxStatusInLatched;
448 42 mohor
 
449 39 mohor
reg WbEn, WbEn_q;
450
reg RxEn, RxEn_q;
451
reg TxEn, TxEn_q;
452 38 mohor
 
453 39 mohor
wire ram_ce;
454
wire ram_we;
455
wire ram_oe;
456
reg [7:0]   ram_addr;
457
reg [31:0]  ram_di;
458
wire [31:0] ram_do;
459 38 mohor
 
460 39 mohor
wire StartTxPointerRead;
461
reg  TxPointerRead;
462
reg TxEn_needed;
463 40 mohor
reg RxEn_needed;
464 38 mohor
 
465 40 mohor
wire StartRxPointerRead;
466
reg RxPointerRead;
467 38 mohor
 
468 219 mohor
`ifdef ETH_WISHBONE_B3
469
assign m_wb_bte_o = 2'b00;    // Linear burst
470
`endif
471 39 mohor
 
472 219 mohor
 
473 159 mohor
always @ (posedge WB_CLK_I)
474 40 mohor
begin
475 159 mohor
  WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
476 40 mohor
end
477 39 mohor
 
478 106 mohor
assign WB_DAT_O = ram_do;
479 39 mohor
 
480 41 mohor
// Generic synchronous single-port RAM interface
481 119 mohor
eth_spram_256x32 bd_ram (
482 210 mohor
  .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
483
`ifdef ETH_BIST
484 219 mohor
  , .trst(trst), .SO(SO), .SI(SI), .shift_DR(shift_DR), .capture_DR(capture_DR), .extest(extest), .tck(tck)
485 210 mohor
`endif
486 39 mohor
);
487 41 mohor
 
488 39 mohor
assign ram_ce = 1'b1;
489 40 mohor
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
490 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
491 39 mohor
 
492
 
493 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
494 38 mohor
begin
495 40 mohor
  if(Reset)
496 39 mohor
    TxEn_needed <=#Tp 1'b0;
497 38 mohor
  else
498 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
499 39 mohor
    TxEn_needed <=#Tp 1'b1;
500
  else
501
  if(TxPointerRead & TxEn & TxEn_q)
502
    TxEn_needed <=#Tp 1'b0;
503 38 mohor
end
504
 
505 39 mohor
// Enabling access to the RAM for three devices.
506 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
507 39 mohor
begin
508 40 mohor
  if(Reset)
509 39 mohor
    begin
510
      WbEn <=#Tp 1'b1;
511
      RxEn <=#Tp 1'b0;
512
      TxEn <=#Tp 1'b0;
513
      ram_addr <=#Tp 8'h0;
514
      ram_di <=#Tp 32'h0;
515 77 mohor
      BDRead <=#Tp 1'b0;
516
      BDWrite <=#Tp 1'b0;
517 39 mohor
    end
518
  else
519
    begin
520
      // Switching between three stages depends on enable signals
521 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
522
        5'b100_10, 5'b100_11 :
523 39 mohor
          begin
524
            WbEn <=#Tp 1'b0;
525
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
526
            TxEn <=#Tp 1'b0;
527 40 mohor
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
528 39 mohor
            ram_di <=#Tp RxBDDataIn;
529
          end
530
        5'b100_01 :
531
          begin
532
            WbEn <=#Tp 1'b0;
533
            RxEn <=#Tp 1'b0;
534
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
535
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
536
            ram_di <=#Tp TxBDDataIn;
537
          end
538 90 mohor
        5'b010_00, 5'b010_10 :
539 39 mohor
          begin
540
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
541
            RxEn <=#Tp 1'b0;
542
            TxEn <=#Tp 1'b0;
543
            ram_addr <=#Tp WB_ADR_I[9:2];
544
            ram_di <=#Tp WB_DAT_I;
545 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
546
            BDRead <=#Tp BDCs & ~WB_WE_I;
547 39 mohor
          end
548 90 mohor
        5'b010_01, 5'b010_11 :
549 39 mohor
          begin
550
            WbEn <=#Tp 1'b0;
551
            RxEn <=#Tp 1'b0;
552
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
553
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
554
            ram_di <=#Tp TxBDDataIn;
555
          end
556 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
557 39 mohor
          begin
558
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
559
            RxEn <=#Tp 1'b0;
560
            TxEn <=#Tp 1'b0;
561
            ram_addr <=#Tp WB_ADR_I[9:2];
562
            ram_di <=#Tp WB_DAT_I;
563 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
564
            BDRead <=#Tp BDCs & ~WB_WE_I;
565 39 mohor
          end
566
        5'b100_00 :
567
          begin
568
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
569
          end
570
        5'b000_00 :
571
          begin
572
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
573
            RxEn <=#Tp 1'b0;
574
            TxEn <=#Tp 1'b0;
575
            ram_addr <=#Tp WB_ADR_I[9:2];
576
            ram_di <=#Tp WB_DAT_I;
577 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
578
            BDRead <=#Tp BDCs & ~WB_WE_I;
579 39 mohor
          end
580
      endcase
581
    end
582
end
583
 
584
 
585
// Delayed stage signals
586 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
587 39 mohor
begin
588 40 mohor
  if(Reset)
589 39 mohor
    begin
590
      WbEn_q <=#Tp 1'b0;
591
      RxEn_q <=#Tp 1'b0;
592
      TxEn_q <=#Tp 1'b0;
593
    end
594
  else
595
    begin
596
      WbEn_q <=#Tp WbEn;
597
      RxEn_q <=#Tp RxEn;
598
      TxEn_q <=#Tp TxEn;
599
    end
600
end
601
 
602 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
603 40 mohor
always @ (posedge MTxClk or posedge Reset)
604 38 mohor
begin
605 40 mohor
  if(Reset)
606 38 mohor
    Flop <=#Tp 1'b0;
607
  else
608
  if(TxDone | TxAbort | TxRetry_q)
609
    Flop <=#Tp 1'b0;
610
  else
611
  if(TxUsedData)
612
    Flop <=#Tp ~Flop;
613
end
614
 
615 39 mohor
wire ResetTxBDReady;
616
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
617 38 mohor
 
618
// Latching READY status of the Tx buffer descriptor
619 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
620 38 mohor
begin
621 40 mohor
  if(Reset)
622 38 mohor
    TxBDReady <=#Tp 1'b0;
623
  else
624 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
625
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
626
  else                                                // Only packets larger then 4 bytes are transmitted.
627 39 mohor
  if(ResetTxBDReady)
628 38 mohor
    TxBDReady <=#Tp 1'b0;
629
end
630
 
631
 
632 39 mohor
// Reading the Tx buffer descriptor
633 221 mohor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
634 39 mohor
 
635 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
636 38 mohor
begin
637 40 mohor
  if(Reset)
638 39 mohor
    TxBDRead <=#Tp 1'b1;
639 38 mohor
  else
640 110 mohor
  if(StartTxBDRead)
641 39 mohor
    TxBDRead <=#Tp 1'b1;
642 38 mohor
  else
643 39 mohor
  if(TxBDReady)
644
    TxBDRead <=#Tp 1'b0;
645 38 mohor
end
646
 
647
 
648 39 mohor
// Reading Tx BD pointer
649
assign StartTxPointerRead = TxBDRead & TxBDReady;
650 38 mohor
 
651 39 mohor
// Reading Tx BD Pointer
652 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
653 38 mohor
begin
654 40 mohor
  if(Reset)
655 39 mohor
    TxPointerRead <=#Tp 1'b0;
656 38 mohor
  else
657 39 mohor
  if(StartTxPointerRead)
658
    TxPointerRead <=#Tp 1'b1;
659 38 mohor
  else
660 39 mohor
  if(TxEn_q)
661
    TxPointerRead <=#Tp 1'b0;
662 38 mohor
end
663
 
664
 
665 39 mohor
// Writing status back to the Tx buffer descriptor
666 221 mohor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
667 38 mohor
 
668
 
669
 
670 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
671 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
672 38 mohor
begin
673 40 mohor
  if(Reset)
674 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
675 38 mohor
  else
676 39 mohor
  if(TxStatusWrite)
677
    BlockingTxStatusWrite <=#Tp 1'b1;
678 38 mohor
  else
679 39 mohor
  if(~TxDone_wb & ~TxAbort_wb)
680
    BlockingTxStatusWrite <=#Tp 1'b0;
681 38 mohor
end
682
 
683
 
684 159 mohor
reg BlockingTxStatusWrite_sync1;
685
reg BlockingTxStatusWrite_sync2;
686
 
687
// Synchronizing BlockingTxStatusWrite to MTxClk
688
always @ (posedge MTxClk or posedge Reset)
689
begin
690
  if(Reset)
691
    BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
692
  else
693
    BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
694
end
695
 
696
// Synchronizing BlockingTxStatusWrite to MTxClk
697
always @ (posedge MTxClk or posedge Reset)
698
begin
699
  if(Reset)
700
    BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
701
  else
702
    BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
703
end
704
 
705
 
706 39 mohor
// TxBDRead state is activated only once. 
707 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
708 39 mohor
begin
709 40 mohor
  if(Reset)
710 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
711
  else
712 110 mohor
  if(StartTxBDRead)
713 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
714
  else
715 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
716 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
717
end
718 38 mohor
 
719
 
720 39 mohor
// Latching status from the tx buffer descriptor
721
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
722 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
723 38 mohor
begin
724 40 mohor
  if(Reset)
725 60 mohor
    TxStatus <=#Tp 4'h0;
726 38 mohor
  else
727 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
728 60 mohor
    TxStatus <=#Tp ram_do[14:11];
729 38 mohor
end
730
 
731 40 mohor
reg ReadTxDataFromMemory;
732
wire WriteRxDataToMemory;
733 38 mohor
 
734 39 mohor
reg MasterWbTX;
735
reg MasterWbRX;
736
 
737
reg [31:0] m_wb_adr_o;
738
reg        m_wb_cyc_o;
739
reg        m_wb_stb_o;
740 96 mohor
reg  [3:0] m_wb_sel_o;
741 39 mohor
reg        m_wb_we_o;
742 40 mohor
 
743 39 mohor
wire TxLengthEq0;
744
wire TxLengthLt4;
745
 
746 150 mohor
reg BlockingIncrementTxPointer;
747 159 mohor
reg [31:2] TxPointerMSB;
748
reg [1:0]  TxPointerLSB;
749
reg [1:0]  TxPointerLSB_rst;
750
reg [31:2] RxPointerMSB;
751
reg [1:0]  RxPointerLSB_rst;
752 39 mohor
 
753 150 mohor
wire RxBurstAcc;
754
wire RxWordAcc;
755
wire RxHalfAcc;
756
wire RxByteAcc;
757
 
758 39 mohor
//Latching length from the buffer descriptor;
759 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
760 38 mohor
begin
761 40 mohor
  if(Reset)
762 39 mohor
    TxLength <=#Tp 16'h0;
763 38 mohor
  else
764 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
765
    TxLength <=#Tp ram_do[31:16];
766 38 mohor
  else
767 39 mohor
  if(MasterWbTX & m_wb_ack_i)
768
    begin
769
      if(TxLengthLt4)
770
        TxLength <=#Tp 16'h0;
771 150 mohor
      else
772 159 mohor
      if(TxPointerLSB_rst==2'h0)
773 96 mohor
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
774 39 mohor
      else
775 159 mohor
      if(TxPointerLSB_rst==2'h1)
776 150 mohor
        TxLength <=#Tp TxLength - 3'h3;    // Length is subtracted at the data request
777
      else
778 159 mohor
      if(TxPointerLSB_rst==2'h2)
779 150 mohor
        TxLength <=#Tp TxLength - 3'h2;    // Length is subtracted at the data request
780
      else
781 159 mohor
      if(TxPointerLSB_rst==2'h3)
782 150 mohor
        TxLength <=#Tp TxLength - 3'h1;    // Length is subtracted at the data request
783 39 mohor
    end
784 38 mohor
end
785
 
786 96 mohor
 
787
 
788 60 mohor
//Latching length from the buffer descriptor;
789
always @ (posedge WB_CLK_I or posedge Reset)
790
begin
791
  if(Reset)
792
    LatchedTxLength <=#Tp 16'h0;
793
  else
794
  if(TxEn & TxEn_q & TxBDRead)
795
    LatchedTxLength <=#Tp ram_do[31:16];
796
end
797
 
798 39 mohor
assign TxLengthEq0 = TxLength == 0;
799
assign TxLengthLt4 = TxLength < 4;
800 38 mohor
 
801 150 mohor
reg cyc_cleared;
802
reg IncrTxPointer;
803 39 mohor
 
804
 
805 159 mohor
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
806
// because TxPointerMSB is only used for word-aligned accesses.
807 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
808 38 mohor
begin
809 40 mohor
  if(Reset)
810 159 mohor
    TxPointerMSB <=#Tp 30'h0;
811 38 mohor
  else
812 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
813 159 mohor
    TxPointerMSB <=#Tp ram_do[31:2];
814 38 mohor
  else
815 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
816 159 mohor
    TxPointerMSB <=#Tp TxPointerMSB + 1'b1;     // TxPointer is word-aligned
817 38 mohor
end
818
 
819 96 mohor
 
820 159 mohor
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
821
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
822
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
823
// set by this two bits.
824 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
825
begin
826
  if(Reset)
827 159 mohor
    TxPointerLSB[1:0] <=#Tp 0;
828 96 mohor
  else
829
  if(TxEn & TxEn_q & TxPointerRead)
830 159 mohor
    TxPointerLSB[1:0] <=#Tp ram_do[1:0];
831 96 mohor
end
832
 
833
 
834 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
835
// After the read access, TxLength needs to be decremented for the number of the valid
836
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
837
// valid so this two bits are reset to zero. 
838 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
839
begin
840
  if(Reset)
841 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
842 150 mohor
  else
843
  if(TxEn & TxEn_q & TxPointerRead)
844 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
845 150 mohor
  else
846
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
847 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
848 150 mohor
end
849 96 mohor
 
850 150 mohor
 
851 159 mohor
reg  [3:0] RxByteSel;
852 39 mohor
wire MasterAccessFinished;
853 38 mohor
 
854 39 mohor
 
855 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
856 38 mohor
begin
857 40 mohor
  if(Reset)
858 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
859 38 mohor
  else
860 39 mohor
  if(MasterAccessFinished)
861
    BlockingIncrementTxPointer <=#Tp 0;
862 38 mohor
  else
863 150 mohor
  if(IncrTxPointer)
864 39 mohor
    BlockingIncrementTxPointer <=#Tp 1'b1;
865 38 mohor
end
866
 
867
 
868 39 mohor
wire TxBufferAlmostFull;
869
wire TxBufferFull;
870
wire TxBufferEmpty;
871
wire TxBufferAlmostEmpty;
872 40 mohor
wire SetReadTxDataFromMemory;
873 39 mohor
 
874 40 mohor
reg BlockReadTxDataFromMemory;
875 39 mohor
 
876 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
877 39 mohor
 
878 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
879 38 mohor
begin
880 40 mohor
  if(Reset)
881
    ReadTxDataFromMemory <=#Tp 1'b0;
882 38 mohor
  else
883 219 mohor
  if(TxLengthEq0 | TxAbortPacket | TxRetryPacket)
884 40 mohor
    ReadTxDataFromMemory <=#Tp 1'b0;
885 39 mohor
  else
886 40 mohor
  if(SetReadTxDataFromMemory)
887
    ReadTxDataFromMemory <=#Tp 1'b1;
888 38 mohor
end
889
 
890 221 mohor
reg BlockingLastReadOn_Abort_Retry;
891
 
892
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory & ~BlockingLastReadOn_Abort_Retry;
893
 
894 39 mohor
wire [31:0] TxData_wb;
895
wire ReadTxDataFromFifo_wb;
896 38 mohor
 
897 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
898 38 mohor
begin
899 40 mohor
  if(Reset)
900
    BlockReadTxDataFromMemory <=#Tp 1'b0;
901 38 mohor
  else
902 221 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (!(TxAbortPacket | TxRetryPacket)))
903 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
904 219 mohor
  else
905 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
906 219 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b0;
907 39 mohor
end
908
 
909
 
910 221 mohor
always @ (posedge WB_CLK_I or posedge Reset)
911
begin
912
  if(Reset)
913
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
914
  else
915
  if(TxAbortPacket | TxRetryPacket)
916
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
917
  else
918
  if(((TxAbort_wb & !TxAbortPacket_NotCleared) | (TxRetry_wb & !TxRetryPacket_NotCleared)) & !TxBDReady)
919
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b1;
920
end
921 39 mohor
 
922 221 mohor
 
923
 
924
 
925 39 mohor
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
926 219 mohor
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
927
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
928 159 mohor
 
929 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
930 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
931 39 mohor
begin
932 40 mohor
  if(Reset)
933 38 mohor
    begin
934 39 mohor
      MasterWbTX <=#Tp 1'b0;
935
      MasterWbRX <=#Tp 1'b0;
936
      m_wb_adr_o <=#Tp 32'h0;
937
      m_wb_cyc_o <=#Tp 1'b0;
938
      m_wb_stb_o <=#Tp 1'b0;
939
      m_wb_we_o  <=#Tp 1'b0;
940 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
941 110 mohor
      cyc_cleared<=#Tp 1'b0;
942 150 mohor
      IncrTxPointer<=#Tp 1'b0;
943 38 mohor
    end
944 39 mohor
  else
945
    begin
946
      // Switching between two stages depends on enable signals
947 110 mohor
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared})  // synopsys parallel_case
948
        6'b00_01_0_x, 6'b00_11_0_x :
949 39 mohor
          begin
950
            MasterWbTX <=#Tp 1'b0;  // idle and master write is needed (data write to rx buffer)
951
            MasterWbRX <=#Tp 1'b1;
952 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
953 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
954
            m_wb_stb_o <=#Tp 1'b1;
955
            m_wb_we_o  <=#Tp 1'b1;
956 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
957 150 mohor
            IncrTxPointer<=#Tp 1'b0;
958 39 mohor
          end
959 110 mohor
        6'b00_10_0_x, 6'b00_10_1_x :
960 39 mohor
          begin
961
            MasterWbTX <=#Tp 1'b1;  // idle and master read is needed (data read from tx buffer)
962
            MasterWbRX <=#Tp 1'b0;
963 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
964 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
965
            m_wb_stb_o <=#Tp 1'b1;
966
            m_wb_we_o  <=#Tp 1'b0;
967 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
968
            IncrTxPointer<=#Tp 1'b1;
969 39 mohor
          end
970 110 mohor
        6'b10_10_0_1 :
971 39 mohor
          begin
972
            MasterWbTX <=#Tp 1'b1;  // master read and master read is needed (data read from tx buffer)
973
            MasterWbRX <=#Tp 1'b0;
974 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
975 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
976
            m_wb_stb_o <=#Tp 1'b1;
977
            m_wb_we_o  <=#Tp 1'b0;
978 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
979 110 mohor
            cyc_cleared<=#Tp 1'b0;
980 150 mohor
            IncrTxPointer<=#Tp 1'b1;
981 39 mohor
          end
982 110 mohor
        6'b01_01_0_1 :
983 39 mohor
          begin
984
            MasterWbTX <=#Tp 1'b0;  // master write and master write is needed (data write to rx buffer)
985
            MasterWbRX <=#Tp 1'b1;
986 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
987 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
988
            m_wb_stb_o <=#Tp 1'b1;
989 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
990 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
991 110 mohor
            cyc_cleared<=#Tp 1'b0;
992 150 mohor
            IncrTxPointer<=#Tp 1'b0;
993 39 mohor
          end
994 110 mohor
        6'b10_01_0_1, 6'b10_11_0_1 :
995 39 mohor
          begin
996
            MasterWbTX <=#Tp 1'b0;  // master read and master write is needed (data write to rx buffer)
997
            MasterWbRX <=#Tp 1'b1;
998 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
999 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1000
            m_wb_stb_o <=#Tp 1'b1;
1001 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
1002 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1003 110 mohor
            cyc_cleared<=#Tp 1'b0;
1004 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1005 39 mohor
          end
1006 111 mohor
        6'b01_10_0_1, 6'b01_11_0_1 :
1007 39 mohor
          begin
1008
            MasterWbTX <=#Tp 1'b1;  // master write and master read is needed (data read from tx buffer)
1009
            MasterWbRX <=#Tp 1'b0;
1010 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1011 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1012
            m_wb_stb_o <=#Tp 1'b1;
1013 39 mohor
            m_wb_we_o  <=#Tp 1'b0;
1014 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1015 110 mohor
            cyc_cleared<=#Tp 1'b0;
1016 150 mohor
            IncrTxPointer<=#Tp 1'b1;
1017 39 mohor
          end
1018 110 mohor
        6'b10_10_1_0, 6'b01_01_1_0, 6'b10_01_1_0, 6'b10_11_1_0, 6'b01_10_1_0, 6'b01_11_1_0 :
1019 39 mohor
          begin
1020 110 mohor
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
1021
            m_wb_stb_o <=#Tp 1'b0;
1022
            cyc_cleared<=#Tp 1'b1;
1023 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1024 110 mohor
          end
1025
        6'b10_00_1_x, 6'b01_00_1_x :
1026
          begin
1027 39 mohor
            MasterWbTX <=#Tp 1'b0;  // whatever and no master read or write is needed (ack or err comes finishing previous access)
1028
            MasterWbRX <=#Tp 1'b0;
1029
            m_wb_cyc_o <=#Tp 1'b0;
1030
            m_wb_stb_o <=#Tp 1'b0;
1031 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1032 39 mohor
          end
1033 127 mohor
        6'b10_00_0_1, 6'b01_00_0_1 :
1034
          begin
1035
            MasterWbTX <=#Tp 1'b0;  // Between cyc_cleared request was cleared
1036
            MasterWbRX <=#Tp 1'b0;
1037
            m_wb_cyc_o <=#Tp 1'b0;
1038
            m_wb_stb_o <=#Tp 1'b0;
1039 221 mohor
            cyc_cleared<=#Tp 1'b0;
1040 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1041 127 mohor
          end
1042 82 mohor
        default:                            // Don't touch
1043
          begin
1044
            MasterWbTX <=#Tp MasterWbTX;
1045
            MasterWbRX <=#Tp MasterWbRX;
1046
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
1047
            m_wb_stb_o <=#Tp m_wb_stb_o;
1048 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
1049 150 mohor
            IncrTxPointer<=#Tp IncrTxPointer;
1050 82 mohor
          end
1051 39 mohor
      endcase
1052
    end
1053 38 mohor
end
1054
 
1055 110 mohor
 
1056 39 mohor
wire TxFifoClear;
1057 96 mohor
 
1058 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1059 38 mohor
 
1060 219 mohor
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
1061 150 mohor
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
1062 96 mohor
          .clk(WB_CLK_I),                                   .reset(Reset),
1063 219 mohor
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1064 96 mohor
          .clear(TxFifoClear),                              .full(TxBufferFull),
1065
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
1066 150 mohor
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
1067 96 mohor
        );
1068 39 mohor
 
1069
 
1070
reg StartOccured;
1071
reg TxStartFrm_sync1;
1072
reg TxStartFrm_sync2;
1073
reg TxStartFrm_syncb1;
1074
reg TxStartFrm_syncb2;
1075
 
1076
 
1077
 
1078
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1079 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1080 38 mohor
begin
1081 40 mohor
  if(Reset)
1082 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
1083 38 mohor
  else
1084 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1085
    TxStartFrm_wb <=#Tp 1'b1;
1086 38 mohor
  else
1087 39 mohor
  if(TxStartFrm_syncb2)
1088
    TxStartFrm_wb <=#Tp 1'b0;
1089 38 mohor
end
1090
 
1091 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1092 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1093 38 mohor
begin
1094 40 mohor
  if(Reset)
1095 39 mohor
    StartOccured <=#Tp 1'b0;
1096 38 mohor
  else
1097 39 mohor
  if(TxStartFrm_wb)
1098
    StartOccured <=#Tp 1'b1;
1099 38 mohor
  else
1100 39 mohor
  if(ResetTxBDReady)
1101
    StartOccured <=#Tp 1'b0;
1102 38 mohor
end
1103
 
1104 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1105 40 mohor
always @ (posedge MTxClk or posedge Reset)
1106 39 mohor
begin
1107 40 mohor
  if(Reset)
1108 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1109
  else
1110
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1111
end
1112 38 mohor
 
1113 40 mohor
always @ (posedge MTxClk or posedge Reset)
1114 39 mohor
begin
1115 40 mohor
  if(Reset)
1116 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1117
  else
1118
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1119
end
1120
 
1121 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1122 38 mohor
begin
1123 40 mohor
  if(Reset)
1124 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1125 38 mohor
  else
1126 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1127 38 mohor
end
1128
 
1129 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1130 38 mohor
begin
1131 40 mohor
  if(Reset)
1132 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1133 38 mohor
  else
1134 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1135
end
1136
 
1137 40 mohor
always @ (posedge MTxClk or posedge Reset)
1138 39 mohor
begin
1139 40 mohor
  if(Reset)
1140 39 mohor
    TxStartFrm <=#Tp 1'b0;
1141 38 mohor
  else
1142 39 mohor
  if(TxStartFrm_sync2)
1143 61 mohor
    TxStartFrm <=#Tp 1'b1;
1144 39 mohor
  else
1145 61 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry | TxAbort))
1146 39 mohor
    TxStartFrm <=#Tp 1'b0;
1147 38 mohor
end
1148 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1149 38 mohor
 
1150
 
1151 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1152 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1153 38 mohor
begin
1154 40 mohor
  if(Reset)
1155 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1156 38 mohor
  else
1157 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1158 39 mohor
    TxEndFrm_wb <=#Tp 1'b1;
1159 38 mohor
  else
1160 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1161
    TxEndFrm_wb <=#Tp 1'b0;
1162 38 mohor
end
1163
 
1164
 
1165
// Marks which bytes are valid within the word.
1166 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1167 38 mohor
 
1168 39 mohor
reg LatchValidBytes;
1169
reg LatchValidBytes_q;
1170 38 mohor
 
1171 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1172 38 mohor
begin
1173 40 mohor
  if(Reset)
1174 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1175 38 mohor
  else
1176 39 mohor
  if(TxLengthLt4 & TxBDReady)
1177
    LatchValidBytes <=#Tp 1'b1;
1178 38 mohor
  else
1179 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1180 38 mohor
end
1181
 
1182 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1183 38 mohor
begin
1184 40 mohor
  if(Reset)
1185 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1186 38 mohor
  else
1187 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1188 38 mohor
end
1189
 
1190
 
1191 39 mohor
// Latching valid bytes
1192 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1193 38 mohor
begin
1194 40 mohor
  if(Reset)
1195 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1196 38 mohor
  else
1197 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1198
    TxValidBytesLatched <=#Tp TxValidBytes;
1199
  else
1200
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1201
    TxValidBytesLatched <=#Tp 2'h0;
1202 38 mohor
end
1203
 
1204
 
1205
assign TxIRQEn          = TxStatus[14];
1206 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1207
assign PerPacketPad     = TxStatus[12];
1208
assign PerPacketCrcEn   = TxStatus[11];
1209 38 mohor
 
1210
 
1211 77 mohor
assign RxIRQEn         = RxStatus[14];
1212 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1213 38 mohor
 
1214
 
1215
// Temporary Tx and Rx buffer descriptor address 
1216 39 mohor
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
1217 134 mohor
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1)     | // Using first Rx BD
1218 39 mohor
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
1219 38 mohor
 
1220
 
1221
// Latching Tx buffer descriptor address
1222 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1223 38 mohor
begin
1224 40 mohor
  if(Reset)
1225 38 mohor
    TxBDAddress <=#Tp 8'h0;
1226
  else
1227
  if(TxStatusWrite)
1228
    TxBDAddress <=#Tp TempTxBDAddress;
1229
end
1230
 
1231
 
1232
// Latching Rx buffer descriptor address
1233 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1234 38 mohor
begin
1235 40 mohor
  if(Reset)
1236 134 mohor
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1;
1237 38 mohor
  else
1238 77 mohor
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
1239 134 mohor
    RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
1240 38 mohor
  else
1241
  if(RxStatusWrite)
1242
    RxBDAddress <=#Tp TempRxBDAddress;
1243
end
1244
 
1245 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1246 38 mohor
 
1247 60 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 6'h0, RxStatusInLatched};
1248
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1249 38 mohor
 
1250 60 mohor
 
1251 38 mohor
// Signals used for various purposes
1252 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1253 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1254
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1255
 
1256
 
1257
 
1258 39 mohor
// Generating delayed signals
1259 40 mohor
always @ (posedge MTxClk or posedge Reset)
1260 38 mohor
begin
1261 40 mohor
  if(Reset)
1262 39 mohor
    begin
1263
      TxAbort_q      <=#Tp 1'b0;
1264
      TxRetry_q      <=#Tp 1'b0;
1265
      TxUsedData_q   <=#Tp 1'b0;
1266
    end
1267 38 mohor
  else
1268 39 mohor
    begin
1269
      TxAbort_q      <=#Tp TxAbort;
1270
      TxRetry_q      <=#Tp TxRetry;
1271
      TxUsedData_q   <=#Tp TxUsedData;
1272
    end
1273 38 mohor
end
1274
 
1275
// Generating delayed signals
1276 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1277 38 mohor
begin
1278 40 mohor
  if(Reset)
1279 38 mohor
    begin
1280 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1281
      TxAbort_wb_q  <=#Tp 1'b0;
1282 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1283 38 mohor
    end
1284
  else
1285
    begin
1286 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1287
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1288 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1289 38 mohor
    end
1290
end
1291
 
1292
 
1293 219 mohor
reg TxAbortPacketBlocked;
1294
always @ (posedge WB_CLK_I or posedge Reset)
1295
begin
1296
  if(Reset)
1297
    TxAbortPacket <=#Tp 1'b0;
1298
  else
1299
  if(TxAbort_wb & (!TxAbortPacketBlocked) & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
1300
    TxAbortPacket <=#Tp 1'b1;
1301
  else
1302
    TxAbortPacket <=#Tp 1'b0;
1303
end
1304
 
1305
 
1306
always @ (posedge WB_CLK_I or posedge Reset)
1307
begin
1308
  if(Reset)
1309 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1310
  else
1311
  if(TxAbort_wb & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
1312
    TxAbortPacket_NotCleared <=#Tp 1'b1;
1313
  else
1314
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1315
end
1316
 
1317
 
1318
always @ (posedge WB_CLK_I or posedge Reset)
1319
begin
1320
  if(Reset)
1321 219 mohor
    TxAbortPacketBlocked <=#Tp 1'b0;
1322
  else
1323
  if(TxAbortPacket)
1324
    TxAbortPacketBlocked <=#Tp 1'b1;
1325
  else
1326
  if(!TxAbort_wb & TxAbort_wb_q)
1327
    TxAbortPacketBlocked <=#Tp 1'b0;
1328
end
1329
 
1330
 
1331
reg TxRetryPacketBlocked;
1332
always @ (posedge WB_CLK_I or posedge Reset)
1333
begin
1334
  if(Reset)
1335
    TxRetryPacket <=#Tp 1'b0;
1336
  else
1337
  if(TxRetry_wb & (!TxRetryPacketBlocked) & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
1338
    TxRetryPacket <=#Tp 1'b1;
1339
  else
1340
    TxRetryPacket <=#Tp 1'b0;
1341
end
1342
 
1343
 
1344
always @ (posedge WB_CLK_I or posedge Reset)
1345
begin
1346
  if(Reset)
1347 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1348
  else
1349
  if(TxRetry_wb & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
1350
    TxRetryPacket_NotCleared <=#Tp 1'b1;
1351
  else
1352
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1353
end
1354
 
1355
 
1356
always @ (posedge WB_CLK_I or posedge Reset)
1357
begin
1358
  if(Reset)
1359 219 mohor
    TxRetryPacketBlocked <=#Tp 1'b0;
1360
  else
1361
  if(TxRetryPacket)
1362
    TxRetryPacketBlocked <=#Tp 1'b1;
1363
  else
1364
  if(!TxRetry_wb & TxRetry_wb_q)
1365
    TxRetryPacketBlocked <=#Tp 1'b0;
1366
end
1367
 
1368
 
1369 221 mohor
reg TxDonePacketBlocked;
1370
always @ (posedge WB_CLK_I or posedge Reset)
1371
begin
1372
  if(Reset)
1373
    TxDonePacket <=#Tp 1'b0;
1374
  else
1375
  if(TxDone_wb & (!TxDonePacketBlocked) & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
1376
    TxDonePacket <=#Tp 1'b1;
1377
  else
1378
    TxDonePacket <=#Tp 1'b0;
1379
end
1380
 
1381
 
1382
always @ (posedge WB_CLK_I or posedge Reset)
1383
begin
1384
  if(Reset)
1385
    TxDonePacket_NotCleared <=#Tp 1'b0;
1386
  else
1387
  if(TxDone_wb & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
1388
    TxDonePacket_NotCleared <=#Tp 1'b1;
1389
  else
1390
    TxDonePacket_NotCleared <=#Tp 1'b0;
1391
end
1392
 
1393
 
1394
always @ (posedge WB_CLK_I or posedge Reset)
1395
begin
1396
  if(Reset)
1397
    TxDonePacketBlocked <=#Tp 1'b0;
1398
  else
1399
  if(TxDonePacket)
1400
    TxDonePacketBlocked <=#Tp 1'b1;
1401
  else
1402
  if(!TxDone_wb & TxDone_wb_q)
1403
    TxDonePacketBlocked <=#Tp 1'b0;
1404
end
1405
 
1406
 
1407 38 mohor
// Sinchronizing and evaluating tx data
1408 39 mohor
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
1409 219 mohor
assign SetGotData = (TxStartFrm_wb);
1410 38 mohor
 
1411
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
1412 40 mohor
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1413
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1414 38 mohor
 
1415
 
1416
// Indication of the last word
1417 40 mohor
always @ (posedge MTxClk or posedge Reset)
1418 38 mohor
begin
1419 40 mohor
  if(Reset)
1420 38 mohor
    LastWord <=#Tp 1'b0;
1421
  else
1422
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1423
    LastWord <=#Tp 1'b0;
1424
  else
1425
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1426 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1427 38 mohor
end
1428
 
1429
 
1430
// Tx end frame generation
1431 40 mohor
always @ (posedge MTxClk or posedge Reset)
1432 38 mohor
begin
1433 40 mohor
  if(Reset)
1434 38 mohor
    TxEndFrm <=#Tp 1'b0;
1435
  else
1436 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1437 38 mohor
    TxEndFrm <=#Tp 1'b0;
1438
  else
1439
  if(Flop & LastWord)
1440
    begin
1441 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1442 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1443
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1444
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1445
 
1446
        default : TxEndFrm <=#Tp 1'b0;
1447
      endcase
1448
    end
1449
end
1450
 
1451
 
1452
// Tx data selection (latching)
1453 40 mohor
always @ (posedge MTxClk or posedge Reset)
1454 38 mohor
begin
1455 40 mohor
  if(Reset)
1456 96 mohor
    TxData <=#Tp 0;
1457 38 mohor
  else
1458 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1459 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1460 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1461
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1462
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1463
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1464
    endcase
1465 38 mohor
  else
1466 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1467 96 mohor
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1468
  else
1469 38 mohor
  if(TxUsedData & Flop)
1470
    begin
1471 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1472 82 mohor
 
1473
        1 : TxData <=#Tp TxDataLatched[23:16];
1474
        2 : TxData <=#Tp TxDataLatched[15:8];
1475
        3 : TxData <=#Tp TxDataLatched[7:0];
1476 38 mohor
      endcase
1477
    end
1478
end
1479
 
1480
 
1481
// Latching tx data
1482 40 mohor
always @ (posedge MTxClk or posedge Reset)
1483 38 mohor
begin
1484 40 mohor
  if(Reset)
1485 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1486
  else
1487 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1488 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1489 38 mohor
end
1490
 
1491
 
1492
// Tx under run
1493 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1494 38 mohor
begin
1495 40 mohor
  if(Reset)
1496 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1497 38 mohor
  else
1498 39 mohor
  if(TxAbortPulse)
1499 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1500
  else
1501
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1502
    TxUnderRun_wb <=#Tp 1'b1;
1503
end
1504
 
1505
 
1506 159 mohor
reg TxUnderRun_sync1;
1507
 
1508 60 mohor
// Tx under run
1509
always @ (posedge MTxClk or posedge Reset)
1510
begin
1511
  if(Reset)
1512 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b0;
1513 43 mohor
  else
1514 60 mohor
  if(TxUnderRun_wb)
1515 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b1;
1516 60 mohor
  else
1517 159 mohor
  if(BlockingTxStatusWrite_sync2)
1518
    TxUnderRun_sync1 <=#Tp 1'b0;
1519
end
1520
 
1521
// Tx under run
1522
always @ (posedge MTxClk or posedge Reset)
1523
begin
1524
  if(Reset)
1525 60 mohor
    TxUnderRun <=#Tp 1'b0;
1526 159 mohor
  else
1527
  if(BlockingTxStatusWrite_sync2)
1528
    TxUnderRun <=#Tp 1'b0;
1529
  else
1530
  if(TxUnderRun_sync1)
1531
    TxUnderRun <=#Tp 1'b1;
1532 38 mohor
end
1533
 
1534
 
1535
// Tx Byte counter
1536 40 mohor
always @ (posedge MTxClk or posedge Reset)
1537 38 mohor
begin
1538 40 mohor
  if(Reset)
1539 38 mohor
    TxByteCnt <=#Tp 2'h0;
1540
  else
1541
  if(TxAbort_q | TxRetry_q)
1542
    TxByteCnt <=#Tp 2'h0;
1543
  else
1544
  if(TxStartFrm & ~TxUsedData)
1545 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1546 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1547
      2'h1 : TxByteCnt <=#Tp 2'h2;
1548
      2'h2 : TxByteCnt <=#Tp 2'h3;
1549
      2'h3 : TxByteCnt <=#Tp 2'h0;
1550
    endcase
1551 38 mohor
  else
1552
  if(TxUsedData & Flop)
1553 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1554 38 mohor
end
1555
 
1556 39 mohor
 
1557 150 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1558
reg ReadTxDataFromFifo_sync1;
1559
reg ReadTxDataFromFifo_sync2;
1560
reg ReadTxDataFromFifo_sync3;
1561
reg ReadTxDataFromFifo_syncb1;
1562
reg ReadTxDataFromFifo_syncb2;
1563
reg ReadTxDataFromFifo_syncb3;
1564
 
1565
 
1566
always @ (posedge MTxClk or posedge Reset)
1567
begin
1568
  if(Reset)
1569
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1570
  else
1571 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1572 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1573 150 mohor
  else
1574
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1575
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1576 38 mohor
end
1577
 
1578 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1579 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1580 38 mohor
begin
1581 40 mohor
  if(Reset)
1582 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1583 38 mohor
  else
1584 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1585
end
1586 38 mohor
 
1587 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1588 38 mohor
begin
1589 40 mohor
  if(Reset)
1590 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1591 38 mohor
  else
1592 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1593 38 mohor
end
1594
 
1595 40 mohor
always @ (posedge MTxClk or posedge Reset)
1596 38 mohor
begin
1597 40 mohor
  if(Reset)
1598 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1599 38 mohor
  else
1600 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1601 38 mohor
end
1602
 
1603 40 mohor
always @ (posedge MTxClk or posedge Reset)
1604 38 mohor
begin
1605 40 mohor
  if(Reset)
1606 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1607 38 mohor
  else
1608 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1609 38 mohor
end
1610
 
1611 150 mohor
always @ (posedge MTxClk or posedge Reset)
1612
begin
1613
  if(Reset)
1614
    ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
1615
  else
1616
    ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
1617
end
1618
 
1619 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1620 38 mohor
begin
1621 40 mohor
  if(Reset)
1622 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1623 38 mohor
  else
1624 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1625 38 mohor
end
1626
 
1627 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1628
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1629 38 mohor
 
1630
 
1631 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1632 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1633 38 mohor
begin
1634 40 mohor
  if(Reset)
1635 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1636 38 mohor
  else
1637 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1638 38 mohor
end
1639
 
1640 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1641 38 mohor
begin
1642 40 mohor
  if(Reset)
1643 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1644 38 mohor
  else
1645 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1646 38 mohor
end
1647
 
1648
 
1649 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1650 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1651 38 mohor
begin
1652 40 mohor
  if(Reset)
1653 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1654 38 mohor
  else
1655 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1656 38 mohor
end
1657
 
1658 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1659 38 mohor
begin
1660 40 mohor
  if(Reset)
1661 39 mohor
    TxDone_wb <=#Tp 1'b0;
1662 38 mohor
  else
1663 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1664 38 mohor
end
1665
 
1666 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1667 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1668 38 mohor
begin
1669 40 mohor
  if(Reset)
1670 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1671 38 mohor
  else
1672 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1673 38 mohor
end
1674
 
1675 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1676 38 mohor
begin
1677 40 mohor
  if(Reset)
1678 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1679
  else
1680 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1681 38 mohor
end
1682
 
1683
 
1684 150 mohor
reg RxAbortSync1;
1685
reg RxAbortSync2;
1686
reg RxAbortSync3;
1687
reg RxAbortSync4;
1688
reg RxAbortSyncb1;
1689
reg RxAbortSyncb2;
1690 39 mohor
 
1691 150 mohor
//assign StartRxBDRead = RxStatusWrite | RxAbortLatched;
1692
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
1693
 
1694 40 mohor
// Reading the Rx buffer descriptor
1695
always @ (posedge WB_CLK_I or posedge Reset)
1696
begin
1697
  if(Reset)
1698
    RxBDRead <=#Tp 1'b1;
1699
  else
1700 166 mohor
  if(StartRxBDRead & ~RxReady)
1701 40 mohor
    RxBDRead <=#Tp 1'b1;
1702
  else
1703
  if(RxBDReady)
1704
    RxBDRead <=#Tp 1'b0;
1705
end
1706 39 mohor
 
1707
 
1708 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1709
// written to the previous one.
1710
 
1711
// Latching READY status of the Rx buffer descriptor
1712 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1713 38 mohor
begin
1714 40 mohor
  if(Reset)
1715 38 mohor
    RxBDReady <=#Tp 1'b0;
1716
  else
1717 166 mohor
  if(RxPointerRead)
1718 150 mohor
    RxBDReady <=#Tp 1'b0;
1719
  else
1720 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1721
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1722 38 mohor
end
1723
 
1724 40 mohor
// Latching Rx buffer descriptor status
1725
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1726
always @ (posedge WB_CLK_I or posedge Reset)
1727 38 mohor
begin
1728 40 mohor
  if(Reset)
1729 60 mohor
    RxStatus <=#Tp 2'h0;
1730 38 mohor
  else
1731 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1732 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1733 38 mohor
end
1734
 
1735
 
1736 166 mohor
// RxReady generation
1737
always @ (posedge WB_CLK_I or posedge Reset)
1738
begin
1739
  if(Reset)
1740
    RxReady <=#Tp 1'b0;
1741
  else
1742
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
1743
    RxReady <=#Tp 1'b0;
1744
  else
1745
  if(RxEn & RxEn_q & RxPointerRead)
1746
    RxReady <=#Tp 1'b1;
1747
end
1748 38 mohor
 
1749
 
1750 40 mohor
// Reading Rx BD pointer
1751
 
1752
 
1753
assign StartRxPointerRead = RxBDRead & RxBDReady;
1754
 
1755
// Reading Tx BD Pointer
1756
always @ (posedge WB_CLK_I or posedge Reset)
1757 38 mohor
begin
1758 40 mohor
  if(Reset)
1759
    RxPointerRead <=#Tp 1'b0;
1760 38 mohor
  else
1761 40 mohor
  if(StartRxPointerRead)
1762
    RxPointerRead <=#Tp 1'b1;
1763 38 mohor
  else
1764 166 mohor
  if(RxEn & RxEn_q)
1765 40 mohor
    RxPointerRead <=#Tp 1'b0;
1766 38 mohor
end
1767
 
1768 113 mohor
 
1769 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1770
always @ (posedge WB_CLK_I or posedge Reset)
1771
begin
1772
  if(Reset)
1773 159 mohor
    RxPointerMSB <=#Tp 30'h0;
1774 40 mohor
  else
1775
  if(RxEn & RxEn_q & RxPointerRead)
1776 159 mohor
    RxPointerMSB <=#Tp ram_do[31:2];
1777 40 mohor
  else
1778 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1779 159 mohor
      RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1780 40 mohor
end
1781 38 mohor
 
1782
 
1783 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1784 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1785
begin
1786
  if(Reset)
1787 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp 0;
1788 96 mohor
  else
1789 159 mohor
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
1790
    RxPointerLSB_rst[1:0] <=#Tp 0;
1791 96 mohor
  else
1792
  if(RxEn & RxEn_q & RxPointerRead)
1793 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
1794 96 mohor
end
1795
 
1796
 
1797 159 mohor
always @ (RxPointerLSB_rst)
1798 96 mohor
begin
1799 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1800
    2'h0 : RxByteSel[3:0] = 4'hf;
1801
    2'h1 : RxByteSel[3:0] = 4'h7;
1802
    2'h2 : RxByteSel[3:0] = 4'h3;
1803
    2'h3 : RxByteSel[3:0] = 4'h1;
1804 96 mohor
  endcase
1805
end
1806
 
1807
 
1808
always @ (posedge WB_CLK_I or posedge Reset)
1809
begin
1810
  if(Reset)
1811 40 mohor
    RxEn_needed <=#Tp 1'b0;
1812 38 mohor
  else
1813 166 mohor
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1814 40 mohor
    RxEn_needed <=#Tp 1'b1;
1815 38 mohor
  else
1816 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1817
    RxEn_needed <=#Tp 1'b0;
1818 38 mohor
end
1819
 
1820
 
1821 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1822
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1823 38 mohor
 
1824 42 mohor
reg RxStatusWriteLatched;
1825
reg RxStatusWrite_rck;
1826
 
1827
always @ (posedge WB_CLK_I or posedge Reset)
1828
begin
1829
  if(Reset)
1830
    RxStatusWriteLatched <=#Tp 1'b0;
1831
  else
1832 87 mohor
  if(RxStatusWrite & ~RxStatusWrite_rck)
1833 42 mohor
    RxStatusWriteLatched <=#Tp 1'b1;
1834
  else
1835
  if(RxStatusWrite_rck)
1836
    RxStatusWriteLatched <=#Tp 1'b0;
1837
end
1838
 
1839
 
1840
always @ (posedge MRxClk or posedge Reset)
1841
begin
1842
  if(Reset)
1843
    RxStatusWrite_rck <=#Tp 1'b0;
1844
  else
1845 87 mohor
  if(RxStatusWriteLatched)
1846
    RxStatusWrite_rck <=#Tp 1'b1;
1847
  else
1848
    RxStatusWrite_rck <=#Tp 1'b0;
1849 42 mohor
end
1850
 
1851
 
1852 40 mohor
reg RxEnableWindow;
1853 38 mohor
 
1854
// Indicating that last byte is being reveived
1855 40 mohor
always @ (posedge MRxClk or posedge Reset)
1856 38 mohor
begin
1857 40 mohor
  if(Reset)
1858 38 mohor
    LastByteIn <=#Tp 1'b0;
1859
  else
1860 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1861 38 mohor
    LastByteIn <=#Tp 1'b0;
1862
  else
1863 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1864 38 mohor
    LastByteIn <=#Tp 1'b1;
1865
end
1866
 
1867 159 mohor
reg ShiftEnded_rck;
1868 40 mohor
reg ShiftEndedSync1;
1869
reg ShiftEndedSync2;
1870 118 mohor
reg ShiftEndedSync3;
1871
reg ShiftEndedSync_c1;
1872
reg ShiftEndedSync_c2;
1873
 
1874 40 mohor
wire StartShiftWillEnd;
1875 96 mohor
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1876 38 mohor
 
1877
// Indicating that data reception will end
1878 40 mohor
always @ (posedge MRxClk or posedge Reset)
1879 38 mohor
begin
1880 40 mohor
  if(Reset)
1881 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1882
  else
1883 159 mohor
  if(ShiftEnded_rck | RxAbort)
1884 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1885
  else
1886 40 mohor
  if(StartShiftWillEnd)
1887 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
1888
end
1889
 
1890
 
1891 40 mohor
 
1892 38 mohor
// Receive byte counter
1893 40 mohor
always @ (posedge MRxClk or posedge Reset)
1894 38 mohor
begin
1895 40 mohor
  if(Reset)
1896 38 mohor
    RxByteCnt <=#Tp 2'h0;
1897
  else
1898 159 mohor
  if(ShiftEnded_rck | RxAbort)
1899 38 mohor
    RxByteCnt <=#Tp 2'h0;
1900 97 lampret
  else
1901 166 mohor
  if(RxValid & RxStartFrm & RxReady)
1902 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
1903 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
1904
      2'h1 : RxByteCnt <=#Tp 2'h2;
1905
      2'h2 : RxByteCnt <=#Tp 2'h3;
1906
      2'h3 : RxByteCnt <=#Tp 2'h0;
1907
    endcase
1908 38 mohor
  else
1909 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
1910 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
1911 38 mohor
end
1912
 
1913
 
1914
// Indicates how many bytes are valid within the last word
1915 40 mohor
always @ (posedge MRxClk or posedge Reset)
1916 38 mohor
begin
1917 40 mohor
  if(Reset)
1918 38 mohor
    RxValidBytes <=#Tp 2'h1;
1919
  else
1920 96 mohor
  if(RxValid & RxStartFrm)
1921 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
1922 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
1923
      2'h1 : RxValidBytes <=#Tp 2'h2;
1924
      2'h2 : RxValidBytes <=#Tp 2'h3;
1925
      2'h3 : RxValidBytes <=#Tp 2'h0;
1926
    endcase
1927 38 mohor
  else
1928 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
1929 38 mohor
    RxValidBytes <=#Tp RxValidBytes + 1;
1930
end
1931
 
1932
 
1933 40 mohor
always @ (posedge MRxClk or posedge Reset)
1934 38 mohor
begin
1935 40 mohor
  if(Reset)
1936
    RxDataLatched1       <=#Tp 24'h0;
1937 38 mohor
  else
1938 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
1939 96 mohor
    if(RxStartFrm)
1940 40 mohor
    begin
1941 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
1942 96 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
1943
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
1944
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
1945
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
1946
      endcase
1947
    end
1948
    else if (RxEnableWindow)
1949
    begin
1950 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
1951 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
1952
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
1953
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
1954 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
1955
      endcase
1956
    end
1957 38 mohor
end
1958
 
1959 40 mohor
wire SetWriteRxDataToFifo;
1960 38 mohor
 
1961 40 mohor
// Assembling data that will be written to the rx_fifo
1962
always @ (posedge MRxClk or posedge Reset)
1963 38 mohor
begin
1964 40 mohor
  if(Reset)
1965
    RxDataLatched2 <=#Tp 32'h0;
1966 38 mohor
  else
1967 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
1968 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
1969 38 mohor
  else
1970 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
1971 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
1972 82 mohor
 
1973
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
1974
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
1975
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
1976 40 mohor
    endcase
1977 38 mohor
end
1978
 
1979
 
1980 40 mohor
reg WriteRxDataToFifoSync1;
1981
reg WriteRxDataToFifoSync2;
1982 150 mohor
reg WriteRxDataToFifoSync3;
1983 38 mohor
 
1984
 
1985 40 mohor
// Indicating start of the reception process
1986 166 mohor
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
1987
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
1988
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
1989 38 mohor
 
1990 150 mohor
always @ (posedge MRxClk or posedge Reset)
1991
begin
1992
  if(Reset)
1993
    WriteRxDataToFifo <=#Tp 1'b0;
1994
  else
1995
  if(SetWriteRxDataToFifo & ~RxAbort)
1996
    WriteRxDataToFifo <=#Tp 1'b1;
1997
  else
1998
  if(WriteRxDataToFifoSync2 | RxAbort)
1999
    WriteRxDataToFifo <=#Tp 1'b0;
2000
end
2001 40 mohor
 
2002 150 mohor
 
2003
 
2004
always @ (posedge WB_CLK_I or posedge Reset)
2005
begin
2006
  if(Reset)
2007
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2008
  else
2009
  if(WriteRxDataToFifo)
2010
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
2011
  else
2012
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2013
end
2014
 
2015
always @ (posedge WB_CLK_I or posedge Reset)
2016
begin
2017
  if(Reset)
2018
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
2019
  else
2020
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
2021
end
2022
 
2023
always @ (posedge WB_CLK_I or posedge Reset)
2024
begin
2025
  if(Reset)
2026
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
2027
  else
2028
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
2029
end
2030
 
2031
wire WriteRxDataToFifo_wb;
2032
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
2033
 
2034
 
2035 90 mohor
reg LatchedRxStartFrm;
2036
reg SyncRxStartFrm;
2037
reg SyncRxStartFrm_q;
2038 150 mohor
reg SyncRxStartFrm_q2;
2039 90 mohor
wire RxFifoReset;
2040 40 mohor
 
2041 90 mohor
always @ (posedge MRxClk or posedge Reset)
2042
begin
2043
  if(Reset)
2044
    LatchedRxStartFrm <=#Tp 0;
2045
  else
2046 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2047 90 mohor
    LatchedRxStartFrm <=#Tp 1;
2048
  else
2049 150 mohor
  if(SyncRxStartFrm_q)
2050 90 mohor
    LatchedRxStartFrm <=#Tp 0;
2051
end
2052
 
2053
 
2054
always @ (posedge WB_CLK_I or posedge Reset)
2055
begin
2056
  if(Reset)
2057
    SyncRxStartFrm <=#Tp 0;
2058
  else
2059
  if(LatchedRxStartFrm)
2060
    SyncRxStartFrm <=#Tp 1;
2061
  else
2062
    SyncRxStartFrm <=#Tp 0;
2063
end
2064
 
2065
 
2066
always @ (posedge WB_CLK_I or posedge Reset)
2067
begin
2068
  if(Reset)
2069
    SyncRxStartFrm_q <=#Tp 0;
2070
  else
2071
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
2072
end
2073
 
2074 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2075
begin
2076
  if(Reset)
2077
    SyncRxStartFrm_q2 <=#Tp 0;
2078
  else
2079
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
2080
end
2081 90 mohor
 
2082
 
2083 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2084 90 mohor
 
2085 150 mohor
 
2086 219 mohor
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
2087 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
2088
         .clk(WB_CLK_I),                                .reset(Reset),
2089 219 mohor
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
2090 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
2091 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
2092 150 mohor
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
2093 88 mohor
        );
2094 40 mohor
 
2095 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2096 40 mohor
 
2097
 
2098
// Generation of the end-of-frame signal
2099
always @ (posedge MRxClk or posedge Reset)
2100 38 mohor
begin
2101 40 mohor
  if(Reset)
2102 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2103 38 mohor
  else
2104 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2105 159 mohor
    ShiftEnded_rck <=#Tp 1'b1;
2106 38 mohor
  else
2107 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2108 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2109 38 mohor
end
2110
 
2111 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2112
begin
2113
  if(Reset)
2114
    ShiftEndedSync1 <=#Tp 1'b0;
2115
  else
2116 159 mohor
    ShiftEndedSync1 <=#Tp ShiftEnded_rck;
2117 40 mohor
end
2118 38 mohor
 
2119 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2120 38 mohor
begin
2121 40 mohor
  if(Reset)
2122
    ShiftEndedSync2 <=#Tp 1'b0;
2123 38 mohor
  else
2124 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
2125 40 mohor
end
2126 38 mohor
 
2127 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2128
begin
2129
  if(Reset)
2130
    ShiftEndedSync3 <=#Tp 1'b0;
2131
  else
2132
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2133
    ShiftEndedSync3 <=#Tp 1'b1;
2134
  else
2135
  if(ShiftEnded)
2136
    ShiftEndedSync3 <=#Tp 1'b0;
2137
end
2138 38 mohor
 
2139 40 mohor
// Generation of the end-of-frame signal
2140
always @ (posedge WB_CLK_I or posedge Reset)
2141 38 mohor
begin
2142 40 mohor
  if(Reset)
2143
    ShiftEnded <=#Tp 1'b0;
2144 38 mohor
  else
2145 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2146 40 mohor
    ShiftEnded <=#Tp 1'b1;
2147 38 mohor
  else
2148 40 mohor
  if(RxStatusWrite)
2149
    ShiftEnded <=#Tp 1'b0;
2150 38 mohor
end
2151
 
2152 118 mohor
always @ (posedge MRxClk or posedge Reset)
2153
begin
2154
  if(Reset)
2155
    ShiftEndedSync_c1 <=#Tp 1'b0;
2156
  else
2157
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
2158
end
2159 38 mohor
 
2160 118 mohor
always @ (posedge MRxClk or posedge Reset)
2161
begin
2162
  if(Reset)
2163
    ShiftEndedSync_c2 <=#Tp 1'b0;
2164
  else
2165
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
2166
end
2167
 
2168 40 mohor
// Generation of the end-of-frame signal
2169
always @ (posedge MRxClk or posedge Reset)
2170 38 mohor
begin
2171 40 mohor
  if(Reset)
2172
    RxEnableWindow <=#Tp 1'b0;
2173 38 mohor
  else
2174 40 mohor
  if(RxStartFrm)
2175
    RxEnableWindow <=#Tp 1'b1;
2176 38 mohor
  else
2177 40 mohor
  if(RxEndFrm | RxAbort)
2178
    RxEnableWindow <=#Tp 1'b0;
2179 38 mohor
end
2180
 
2181
 
2182 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2183 38 mohor
begin
2184 40 mohor
  if(Reset)
2185
    RxAbortSync1 <=#Tp 1'b0;
2186 38 mohor
  else
2187 150 mohor
    RxAbortSync1 <=#Tp RxAbortLatched;
2188 40 mohor
end
2189
 
2190
always @ (posedge WB_CLK_I or posedge Reset)
2191
begin
2192
  if(Reset)
2193
    RxAbortSync2 <=#Tp 1'b0;
2194 38 mohor
  else
2195 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
2196 38 mohor
end
2197
 
2198 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2199
begin
2200
  if(Reset)
2201
    RxAbortSync3 <=#Tp 1'b0;
2202
  else
2203
    RxAbortSync3 <=#Tp RxAbortSync2;
2204
end
2205
 
2206
always @ (posedge WB_CLK_I or posedge Reset)
2207
begin
2208
  if(Reset)
2209
    RxAbortSync4 <=#Tp 1'b0;
2210
  else
2211
    RxAbortSync4 <=#Tp RxAbortSync3;
2212
end
2213
 
2214 40 mohor
always @ (posedge MRxClk or posedge Reset)
2215
begin
2216
  if(Reset)
2217
    RxAbortSyncb1 <=#Tp 1'b0;
2218
  else
2219
    RxAbortSyncb1 <=#Tp RxAbortSync2;
2220
end
2221 38 mohor
 
2222 40 mohor
always @ (posedge MRxClk or posedge Reset)
2223 38 mohor
begin
2224 40 mohor
  if(Reset)
2225
    RxAbortSyncb2 <=#Tp 1'b0;
2226 38 mohor
  else
2227 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
2228 38 mohor
end
2229
 
2230
 
2231 64 mohor
always @ (posedge MRxClk or posedge Reset)
2232
begin
2233
  if(Reset)
2234
    RxAbortLatched <=#Tp 1'b0;
2235
  else
2236 150 mohor
  if(RxAbortSyncb2)
2237
    RxAbortLatched <=#Tp 1'b0;
2238
  else
2239 64 mohor
  if(RxAbort)
2240
    RxAbortLatched <=#Tp 1'b1;
2241
end
2242 40 mohor
 
2243 64 mohor
 
2244 42 mohor
always @ (posedge MRxClk or posedge Reset)
2245
begin
2246
  if(Reset)
2247
    LatchedRxLength[15:0] <=#Tp 16'h0;
2248
  else
2249 150 mohor
  if(LoadRxStatus)
2250 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
2251
end
2252
 
2253
 
2254 60 mohor
assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2255 42 mohor
 
2256
always @ (posedge MRxClk or posedge Reset)
2257
begin
2258
  if(Reset)
2259
    RxStatusInLatched <=#Tp 'h0;
2260
  else
2261 150 mohor
  if(LoadRxStatus)
2262 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
2263
end
2264
 
2265
 
2266 60 mohor
// Rx overrun
2267
always @ (posedge WB_CLK_I or posedge Reset)
2268
begin
2269
  if(Reset)
2270
    RxOverrun <=#Tp 1'b0;
2271
  else
2272
  if(RxStatusWrite)
2273
    RxOverrun <=#Tp 1'b0;
2274
  else
2275
  if(RxBufferFull & WriteRxDataToFifo_wb)
2276
    RxOverrun <=#Tp 1'b1;
2277
end
2278 48 mohor
 
2279 77 mohor
 
2280
 
2281
wire TxError;
2282
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2283
 
2284
wire RxError;
2285
assign RxError = |RxStatusInLatched[6:0];
2286
 
2287
// Tx Done Interrupt
2288
always @ (posedge WB_CLK_I or posedge Reset)
2289
begin
2290
  if(Reset)
2291
    TxB_IRQ <=#Tp 1'b0;
2292
  else
2293
  if(TxStatusWrite & TxIRQEn)
2294
    TxB_IRQ <=#Tp ~TxError;
2295
  else
2296
    TxB_IRQ <=#Tp 1'b0;
2297
end
2298
 
2299
 
2300
// Tx Error Interrupt
2301
always @ (posedge WB_CLK_I or posedge Reset)
2302
begin
2303
  if(Reset)
2304
    TxE_IRQ <=#Tp 1'b0;
2305
  else
2306
  if(TxStatusWrite & TxIRQEn)
2307
    TxE_IRQ <=#Tp TxError;
2308
  else
2309
    TxE_IRQ <=#Tp 1'b0;
2310
end
2311
 
2312
 
2313
// Rx Done Interrupt
2314
always @ (posedge WB_CLK_I or posedge Reset)
2315
begin
2316
  if(Reset)
2317
    RxB_IRQ <=#Tp 1'b0;
2318
  else
2319
  if(RxStatusWrite & RxIRQEn)
2320 167 mohor
    RxB_IRQ <=#Tp ReceivedPacketGood & ~RxError;
2321 77 mohor
  else
2322
    RxB_IRQ <=#Tp 1'b0;
2323
end
2324
 
2325
 
2326
// Rx Error Interrupt
2327
always @ (posedge WB_CLK_I or posedge Reset)
2328
begin
2329
  if(Reset)
2330
    RxE_IRQ <=#Tp 1'b0;
2331
  else
2332
  if(RxStatusWrite & RxIRQEn)
2333
    RxE_IRQ <=#Tp RxError;
2334
  else
2335
    RxE_IRQ <=#Tp 1'b0;
2336
end
2337
 
2338
 
2339 166 mohor
// Busy Interrupt
2340 77 mohor
 
2341 166 mohor
reg Busy_IRQ_rck;
2342
reg Busy_IRQ_sync1;
2343
reg Busy_IRQ_sync2;
2344
reg Busy_IRQ_sync3;
2345
reg Busy_IRQ_syncb1;
2346
reg Busy_IRQ_syncb2;
2347 77 mohor
 
2348
 
2349 166 mohor
always @ (posedge MRxClk or posedge Reset)
2350
begin
2351
  if(Reset)
2352
    Busy_IRQ_rck <=#Tp 1'b0;
2353
  else
2354
  if(RxValid & RxStartFrm & ~RxReady)
2355
    Busy_IRQ_rck <=#Tp 1'b1;
2356
  else
2357
  if(Busy_IRQ_syncb2)
2358
    Busy_IRQ_rck <=#Tp 1'b0;
2359
end
2360 77 mohor
 
2361 166 mohor
always @ (posedge WB_CLK_I)
2362
begin
2363
    Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
2364
    Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
2365
    Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
2366
end
2367
 
2368
always @ (posedge MRxClk)
2369
begin
2370
    Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
2371
    Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
2372
end
2373
 
2374
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
2375
 
2376
 
2377 60 mohor
 
2378
// TX
2379 61 mohor
// bit 15 ready
2380
// bit 14 interrupt
2381
// bit 13 wrap
2382
// bit 12 pad
2383
// bit 11 crc
2384
// bit 10 last
2385
// bit 9  pause request (control frame)
2386
// bit 8  TxUnderRun          
2387
// bit 7-4 RetryCntLatched    
2388
// bit 3  retransmittion limit
2389
// bit 2  LateCollLatched        
2390
// bit 1  DeferLatched        
2391
// bit 0  CarrierSenseLost    
2392 60 mohor
 
2393
 
2394
// RX
2395
// bit 15 od rx je empty
2396 61 mohor
// bit 14 od rx je interrupt
2397 60 mohor
// bit 13 od rx je wrap
2398
// bit 12 od rx je reserved
2399
// bit 11 od rx je reserved
2400
// bit 10 od rx je reserved
2401
// bit 9  od rx je reserved
2402
// bit 8  od rx je reserved
2403 110 mohor
// bit 7  od rx je Miss
2404 60 mohor
// bit 6  od rx je RxOverrun
2405
// bit 5  od rx je InvalidSymbol
2406
// bit 4  od rx je DribbleNibble
2407
// bit 3  od rx je ReceivedPacketTooBig
2408
// bit 2  od rx je ShortFrame
2409
// bit 1  od rx je LatchedCrcError
2410
// bit 0  od rx je RxLateCollision
2411
 
2412 110 mohor
 
2413 38 mohor
endmodule
2414
 

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