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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 227

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
45
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
46
//
47 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
48
// TxStatus is written after last access to the TX fifo is finished (in case of abort
49
// or retry). TxDone is fixed.
50
//
51 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
52
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
53
// TxDone and TxRetry are generated after the current WISHBONE access is
54
// finished.
55
//
56 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
57
// BIST added.
58
//
59 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
60
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
61
//
62 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
63
// Reception is possible after RxPointer is read and not after BD is read. For
64
// that reason RxBDReady is changed to RxReady.
65
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
66
// comes, interrupt is generated.
67
//
68 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
69
// Ethernet debug registers removed.
70
//
71 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
72
// Async reset for WB_ACK_O removed (when core was in reset, it was
73
// impossible to access BDs).
74
// RxPointers and TxPointers names changed to be more descriptive.
75
// TxUnderRun synchronized.
76
//
77 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
78
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
79
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
80
// was not used OK.
81
//
82 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
83
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
84
// need to multiply or devide any more.
85
//
86 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
87
// WriteRxDataToMemory signal changed so end of frame (when last word is
88
// written to fifo) is changed.
89
//
90 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
91
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
92
//
93 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
94
// ShiftEnded synchronization changed.
95
//
96 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
97
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
98
//
99 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
100
// RxPointer bug fixed.
101
//
102 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
103
// Previous bug wasn't succesfully removed. Now fixed.
104
//
105 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
106
// Master state machine had a bug when switching from master write to
107
// master read.
108
//
109 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
110
// m_wb_cyc_o signal released after every single transfer.
111
//
112 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
113
// Outputs registered. Reset changed for eth_wishbone module.
114
//
115 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
116
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
117
// bug fixed.
118
//
119 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
120
// Small typo fixed.
121
//
122 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
123
// Any address can be used for Tx and Rx BD pointers. Address does not need
124
// to be aligned.
125
//
126 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
127
// Comments in Slovene language removed.
128
//
129 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
130
// casex changed with case, fifo reset changed.
131
//
132 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
133
// rx_fifo was not always cleared ok. Fixed.
134
//
135 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
136
// Status was not latched correctly sometimes. Fixed.
137
//
138 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
139
// Big Endian problem when sending frames fixed.
140
//
141 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
142
// Byte ordering changed (Big Endian used). casex changed with case because
143
// Xilinx Foundation had problems. Tested in HW. It WORKS.
144
//
145 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
146
// Small fixes for external/internal DMA missmatches.
147
//
148 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
149
// Interrupts changed
150
//
151 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
152
// Status was not written correctly when frames were discarted because of
153
// address mismatch.
154
//
155 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
156
// RxStartFrm cleared when abort or retry comes.
157
//
158 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
159
// Changes that were lost when updating from 1.5 to 1.8 fixed.
160
//
161 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
162
// Addition  of new module eth_addrcheck.v
163
//
164
// Revision 1.7  2002/02/12 17:03:47  mohor
165
// RxOverRun added to statuses.
166
//
167
// Revision 1.6  2002/02/11 09:18:22  mohor
168
// Tx status is written back to the BD.
169
//
170 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
171
// Rx status is written back to the BD.
172
//
173 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
174
// non-DMA host interface added. Select the right configutation in eth_defines.
175
//
176 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
177
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
178
// MHz. Statuses, overrun, control frame transmission and reception still  need
179
// to be fixed.
180
//
181 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
182
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
183
// added.
184
//
185 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
186
// Initial version. Equals to eth_wishbonedma.v at this moment.
187 38 mohor
//
188
//
189
//
190
 
191
`include "eth_defines.v"
192
`include "timescale.v"
193
 
194
 
195
module eth_wishbone
196
   (
197
 
198
    // WISHBONE common
199 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
200 38 mohor
 
201
    // WISHBONE slave
202 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
203 40 mohor
    BDCs,
204 38 mohor
 
205 40 mohor
    Reset,
206
 
207 39 mohor
    // WISHBONE master
208
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
209
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
210
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
211
 
212 219 mohor
`ifdef ETH_WISHBONE_B3
213
    m_wb_cti_o, m_wb_bte_o,
214
`endif
215
 
216 38 mohor
    //TX
217 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
218 150 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
219 38 mohor
    PerPacketPad,
220
 
221
    //RX
222 40 mohor
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
223 38 mohor
 
224
    // Register
225 150 mohor
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr,
226 38 mohor
 
227
    // Interrupts
228 150 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
229 42 mohor
 
230 60 mohor
    // Rx Status
231 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
232 77 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
233 60 mohor
 
234
    // Tx Status
235 164 mohor
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
236
 
237 210 mohor
    // Bist
238
`ifdef ETH_BIST
239 227 tadejm
    ,
240
    // debug chain signals
241
    scanb_rst,      // bist scan reset
242
    scanb_clk,      // bist scan clock
243
    scanb_si,       // bist scan serial in
244
    scanb_so,       // bist scan serial out
245
    scanb_en        // bist scan shift enable
246 210 mohor
`endif
247
 
248
 
249
 
250 38 mohor
                );
251
 
252
 
253
parameter Tp = 1;
254
 
255 150 mohor
 
256 38 mohor
// WISHBONE common
257
input           WB_CLK_I;       // WISHBONE clock
258
input  [31:0]   WB_DAT_I;       // WISHBONE data input
259
output [31:0]   WB_DAT_O;       // WISHBONE data output
260
 
261
// WISHBONE slave
262
input   [9:2]   WB_ADR_I;       // WISHBONE address input
263
input           WB_WE_I;        // WISHBONE write enable input
264
input           BDCs;           // Buffer descriptors are selected
265
output          WB_ACK_O;       // WISHBONE acknowledge output
266
 
267 39 mohor
// WISHBONE master
268
output  [31:0]  m_wb_adr_o;     // 
269
output   [3:0]  m_wb_sel_o;     // 
270
output          m_wb_we_o;      // 
271
output  [31:0]  m_wb_dat_o;     // 
272
output          m_wb_cyc_o;     // 
273
output          m_wb_stb_o;     // 
274
input   [31:0]  m_wb_dat_i;     // 
275
input           m_wb_ack_i;     // 
276
input           m_wb_err_i;     // 
277
 
278 219 mohor
`ifdef ETH_WISHBONE_B3
279
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
280
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
281
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
282
`endif
283
 
284 40 mohor
input           Reset;       // Reset signal
285 39 mohor
 
286 60 mohor
// Rx Status signals
287 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
288
input           LatchedCrcError;  // CRC error
289
input           RxLateCollision;  // Late collision occured while receiving frame
290
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
291
input           DribbleNibble;    // Extra nibble received
292
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
293
input    [15:0] RxLength;         // Length of the incoming frame
294
input           LoadRxStatus;     // Rx status was loaded
295 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
296 39 mohor
 
297 60 mohor
// Tx Status signals
298
input     [3:0] RetryCntLatched;  // Latched Retry Counter
299
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
300
input           LateCollLatched;  // Late collision occured
301
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
302
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
303
 
304 38 mohor
// Tx
305
input           MTxClk;         // Transmit clock (from PHY)
306
input           TxUsedData;     // Transmit packet used data
307
input           TxRetry;        // Transmit packet retry
308
input           TxAbort;        // Transmit packet abort
309
input           TxDone;         // Transmission ended
310
output          TxStartFrm;     // Transmit packet start frame
311
output          TxEndFrm;       // Transmit packet end frame
312
output  [7:0]   TxData;         // Transmit packet data byte
313
output          TxUnderRun;     // Transmit packet under-run
314
output          PerPacketCrcEn; // Per packet crc enable
315
output          PerPacketPad;   // Per packet pading
316
 
317
// Rx
318
input           MRxClk;         // Receive clock (from PHY)
319
input   [7:0]   RxData;         // Received data byte (from PHY)
320
input           RxValid;        // 
321
input           RxStartFrm;     // 
322
input           RxEndFrm;       // 
323 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
324 38 mohor
 
325
//Register
326
input           r_TxEn;         // Transmit enable
327
input           r_RxEn;         // Receive enable
328
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
329
input           TX_BD_NUM_Wr;   // RxBDNumber written
330
 
331
// Interrupts
332
output TxB_IRQ;
333
output TxE_IRQ;
334
output RxB_IRQ;
335 77 mohor
output RxE_IRQ;
336 38 mohor
output Busy_IRQ;
337
 
338 77 mohor
 
339 210 mohor
// Bist
340
`ifdef ETH_BIST
341 227 tadejm
input   scanb_rst;      // bist scan reset
342
input   scanb_clk;      // bist scan clock
343
input   scanb_si;       // bist scan serial in
344
output  scanb_so;       // bist scan serial out
345
input   scanb_en;       // bist scan shift enable
346 210 mohor
`endif
347
 
348 77 mohor
reg TxB_IRQ;
349
reg TxE_IRQ;
350
reg RxB_IRQ;
351
reg RxE_IRQ;
352
 
353 38 mohor
reg             TxStartFrm;
354
reg             TxEndFrm;
355
reg     [7:0]   TxData;
356
 
357
reg             TxUnderRun;
358 60 mohor
reg             TxUnderRun_wb;
359 38 mohor
 
360
reg             TxBDRead;
361 39 mohor
wire            TxStatusWrite;
362 38 mohor
 
363
reg     [1:0]   TxValidBytesLatched;
364
 
365
reg    [15:0]   TxLength;
366 60 mohor
reg    [15:0]   LatchedTxLength;
367
reg   [14:11]   TxStatus;
368 38 mohor
 
369 60 mohor
reg   [14:13]   RxStatus;
370 38 mohor
 
371
reg             TxStartFrm_wb;
372
reg             TxRetry_wb;
373 39 mohor
reg             TxAbort_wb;
374 38 mohor
reg             TxDone_wb;
375
 
376
reg             TxDone_wb_q;
377
reg             TxAbort_wb_q;
378 39 mohor
reg             TxRetry_wb_q;
379 219 mohor
reg             TxRetryPacket;
380 221 mohor
reg             TxRetryPacket_NotCleared;
381
reg             TxDonePacket;
382
reg             TxDonePacket_NotCleared;
383 219 mohor
reg             TxAbortPacket;
384 221 mohor
reg             TxAbortPacket_NotCleared;
385 38 mohor
reg             RxBDReady;
386 166 mohor
reg             RxReady;
387 38 mohor
reg             TxBDReady;
388
 
389
reg             RxBDRead;
390 40 mohor
wire            RxStatusWrite;
391 38 mohor
 
392
reg    [31:0]   TxDataLatched;
393
reg     [1:0]   TxByteCnt;
394
reg             LastWord;
395 39 mohor
reg             ReadTxDataFromFifo_tck;
396 38 mohor
 
397
reg             BlockingTxStatusWrite;
398
reg             BlockingTxBDRead;
399
 
400 40 mohor
reg             Flop;
401 38 mohor
 
402
reg     [7:0]   TxBDAddress;
403
reg     [7:0]   RxBDAddress;
404
 
405
reg             TxRetrySync1;
406
reg             TxAbortSync1;
407 39 mohor
reg             TxDoneSync1;
408 38 mohor
 
409
reg             TxAbort_q;
410
reg             TxRetry_q;
411
reg             TxUsedData_q;
412
 
413
reg    [31:0]   RxDataLatched2;
414 82 mohor
 
415
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
416
 
417 38 mohor
reg     [1:0]   RxValidBytes;
418
reg     [1:0]   RxByteCnt;
419
reg             LastByteIn;
420
reg             ShiftWillEnd;
421
 
422 40 mohor
reg             WriteRxDataToFifo;
423 42 mohor
reg    [15:0]   LatchedRxLength;
424 64 mohor
reg             RxAbortLatched;
425 38 mohor
 
426 40 mohor
reg             ShiftEnded;
427 60 mohor
reg             RxOverrun;
428 38 mohor
 
429 40 mohor
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
430
reg             BDRead;                     // BD Read access from WISHBONE side
431 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
432
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
433 38 mohor
 
434 39 mohor
reg             TxEndFrm_wb;
435 38 mohor
 
436 39 mohor
wire            TxRetryPulse;
437 38 mohor
wire            TxDonePulse;
438
wire            TxAbortPulse;
439
 
440
wire            StartRxBDRead;
441
 
442
wire            StartTxBDRead;
443
 
444
wire            TxIRQEn;
445
wire            WrapTxStatusBit;
446
 
447 77 mohor
wire            RxIRQEn;
448 38 mohor
wire            WrapRxStatusBit;
449
 
450
wire    [1:0]   TxValidBytes;
451
 
452
wire    [7:0]   TempTxBDAddress;
453
wire    [7:0]   TempRxBDAddress;
454
 
455
wire            SetGotData;
456
wire            GotDataEvaluate;
457
 
458 106 mohor
reg             WB_ACK_O;
459 38 mohor
 
460 60 mohor
wire    [6:0]   RxStatusIn;
461
reg     [6:0]   RxStatusInLatched;
462 42 mohor
 
463 39 mohor
reg WbEn, WbEn_q;
464
reg RxEn, RxEn_q;
465
reg TxEn, TxEn_q;
466 38 mohor
 
467 39 mohor
wire ram_ce;
468
wire ram_we;
469
wire ram_oe;
470
reg [7:0]   ram_addr;
471
reg [31:0]  ram_di;
472
wire [31:0] ram_do;
473 38 mohor
 
474 39 mohor
wire StartTxPointerRead;
475
reg  TxPointerRead;
476
reg TxEn_needed;
477 40 mohor
reg RxEn_needed;
478 38 mohor
 
479 40 mohor
wire StartRxPointerRead;
480
reg RxPointerRead;
481 38 mohor
 
482 219 mohor
`ifdef ETH_WISHBONE_B3
483
assign m_wb_bte_o = 2'b00;    // Linear burst
484
`endif
485 39 mohor
 
486 219 mohor
 
487 159 mohor
always @ (posedge WB_CLK_I)
488 40 mohor
begin
489 159 mohor
  WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
490 40 mohor
end
491 39 mohor
 
492 106 mohor
assign WB_DAT_O = ram_do;
493 39 mohor
 
494 41 mohor
// Generic synchronous single-port RAM interface
495 119 mohor
eth_spram_256x32 bd_ram (
496 226 tadejm
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
497 210 mohor
`ifdef ETH_BIST
498 227 tadejm
  ,
499
  .scanb_rst      (scanb_rst),
500
  .scanb_clk      (scanb_clk),
501
  .scanb_si       (scanb_si),
502
  .scanb_so       (scanb_so),
503
  .scanb_en       (scanb_en)
504 210 mohor
`endif
505 39 mohor
);
506 41 mohor
 
507 39 mohor
assign ram_ce = 1'b1;
508 40 mohor
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
509 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
510 39 mohor
 
511
 
512 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
513 38 mohor
begin
514 40 mohor
  if(Reset)
515 39 mohor
    TxEn_needed <=#Tp 1'b0;
516 38 mohor
  else
517 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
518 39 mohor
    TxEn_needed <=#Tp 1'b1;
519
  else
520
  if(TxPointerRead & TxEn & TxEn_q)
521
    TxEn_needed <=#Tp 1'b0;
522 38 mohor
end
523
 
524 39 mohor
// Enabling access to the RAM for three devices.
525 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
526 39 mohor
begin
527 40 mohor
  if(Reset)
528 39 mohor
    begin
529
      WbEn <=#Tp 1'b1;
530
      RxEn <=#Tp 1'b0;
531
      TxEn <=#Tp 1'b0;
532
      ram_addr <=#Tp 8'h0;
533
      ram_di <=#Tp 32'h0;
534 77 mohor
      BDRead <=#Tp 1'b0;
535
      BDWrite <=#Tp 1'b0;
536 39 mohor
    end
537
  else
538
    begin
539
      // Switching between three stages depends on enable signals
540 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
541
        5'b100_10, 5'b100_11 :
542 39 mohor
          begin
543
            WbEn <=#Tp 1'b0;
544
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
545
            TxEn <=#Tp 1'b0;
546 40 mohor
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
547 39 mohor
            ram_di <=#Tp RxBDDataIn;
548
          end
549
        5'b100_01 :
550
          begin
551
            WbEn <=#Tp 1'b0;
552
            RxEn <=#Tp 1'b0;
553
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
554
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
555
            ram_di <=#Tp TxBDDataIn;
556
          end
557 90 mohor
        5'b010_00, 5'b010_10 :
558 39 mohor
          begin
559
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
560
            RxEn <=#Tp 1'b0;
561
            TxEn <=#Tp 1'b0;
562
            ram_addr <=#Tp WB_ADR_I[9:2];
563
            ram_di <=#Tp WB_DAT_I;
564 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
565
            BDRead <=#Tp BDCs & ~WB_WE_I;
566 39 mohor
          end
567 90 mohor
        5'b010_01, 5'b010_11 :
568 39 mohor
          begin
569
            WbEn <=#Tp 1'b0;
570
            RxEn <=#Tp 1'b0;
571
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
572
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
573
            ram_di <=#Tp TxBDDataIn;
574
          end
575 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
576 39 mohor
          begin
577
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
578
            RxEn <=#Tp 1'b0;
579
            TxEn <=#Tp 1'b0;
580
            ram_addr <=#Tp WB_ADR_I[9:2];
581
            ram_di <=#Tp WB_DAT_I;
582 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
583
            BDRead <=#Tp BDCs & ~WB_WE_I;
584 39 mohor
          end
585
        5'b100_00 :
586
          begin
587
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
588
          end
589
        5'b000_00 :
590
          begin
591
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
592
            RxEn <=#Tp 1'b0;
593
            TxEn <=#Tp 1'b0;
594
            ram_addr <=#Tp WB_ADR_I[9:2];
595
            ram_di <=#Tp WB_DAT_I;
596 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
597
            BDRead <=#Tp BDCs & ~WB_WE_I;
598 39 mohor
          end
599
      endcase
600
    end
601
end
602
 
603
 
604
// Delayed stage signals
605 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
606 39 mohor
begin
607 40 mohor
  if(Reset)
608 39 mohor
    begin
609
      WbEn_q <=#Tp 1'b0;
610
      RxEn_q <=#Tp 1'b0;
611
      TxEn_q <=#Tp 1'b0;
612
    end
613
  else
614
    begin
615
      WbEn_q <=#Tp WbEn;
616
      RxEn_q <=#Tp RxEn;
617
      TxEn_q <=#Tp TxEn;
618
    end
619
end
620
 
621 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
622 40 mohor
always @ (posedge MTxClk or posedge Reset)
623 38 mohor
begin
624 40 mohor
  if(Reset)
625 38 mohor
    Flop <=#Tp 1'b0;
626
  else
627
  if(TxDone | TxAbort | TxRetry_q)
628
    Flop <=#Tp 1'b0;
629
  else
630
  if(TxUsedData)
631
    Flop <=#Tp ~Flop;
632
end
633
 
634 39 mohor
wire ResetTxBDReady;
635
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
636 38 mohor
 
637
// Latching READY status of the Tx buffer descriptor
638 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
639 38 mohor
begin
640 40 mohor
  if(Reset)
641 38 mohor
    TxBDReady <=#Tp 1'b0;
642
  else
643 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
644
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
645
  else                                                // Only packets larger then 4 bytes are transmitted.
646 39 mohor
  if(ResetTxBDReady)
647 38 mohor
    TxBDReady <=#Tp 1'b0;
648
end
649
 
650
 
651 39 mohor
// Reading the Tx buffer descriptor
652 221 mohor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
653 39 mohor
 
654 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
655 38 mohor
begin
656 40 mohor
  if(Reset)
657 39 mohor
    TxBDRead <=#Tp 1'b1;
658 38 mohor
  else
659 110 mohor
  if(StartTxBDRead)
660 39 mohor
    TxBDRead <=#Tp 1'b1;
661 38 mohor
  else
662 39 mohor
  if(TxBDReady)
663
    TxBDRead <=#Tp 1'b0;
664 38 mohor
end
665
 
666
 
667 39 mohor
// Reading Tx BD pointer
668
assign StartTxPointerRead = TxBDRead & TxBDReady;
669 38 mohor
 
670 39 mohor
// Reading Tx BD Pointer
671 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
672 38 mohor
begin
673 40 mohor
  if(Reset)
674 39 mohor
    TxPointerRead <=#Tp 1'b0;
675 38 mohor
  else
676 39 mohor
  if(StartTxPointerRead)
677
    TxPointerRead <=#Tp 1'b1;
678 38 mohor
  else
679 39 mohor
  if(TxEn_q)
680
    TxPointerRead <=#Tp 1'b0;
681 38 mohor
end
682
 
683
 
684 39 mohor
// Writing status back to the Tx buffer descriptor
685 221 mohor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
686 38 mohor
 
687
 
688
 
689 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
690 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
691 38 mohor
begin
692 40 mohor
  if(Reset)
693 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
694 38 mohor
  else
695 39 mohor
  if(TxStatusWrite)
696
    BlockingTxStatusWrite <=#Tp 1'b1;
697 38 mohor
  else
698 39 mohor
  if(~TxDone_wb & ~TxAbort_wb)
699
    BlockingTxStatusWrite <=#Tp 1'b0;
700 38 mohor
end
701
 
702
 
703 159 mohor
reg BlockingTxStatusWrite_sync1;
704
reg BlockingTxStatusWrite_sync2;
705
 
706
// Synchronizing BlockingTxStatusWrite to MTxClk
707
always @ (posedge MTxClk or posedge Reset)
708
begin
709
  if(Reset)
710
    BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
711
  else
712
    BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
713
end
714
 
715
// Synchronizing BlockingTxStatusWrite to MTxClk
716
always @ (posedge MTxClk or posedge Reset)
717
begin
718
  if(Reset)
719
    BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
720
  else
721
    BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
722
end
723
 
724
 
725 39 mohor
// TxBDRead state is activated only once. 
726 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
727 39 mohor
begin
728 40 mohor
  if(Reset)
729 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
730
  else
731 110 mohor
  if(StartTxBDRead)
732 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
733
  else
734 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
735 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
736
end
737 38 mohor
 
738
 
739 39 mohor
// Latching status from the tx buffer descriptor
740
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
741 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
742 38 mohor
begin
743 40 mohor
  if(Reset)
744 60 mohor
    TxStatus <=#Tp 4'h0;
745 38 mohor
  else
746 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
747 60 mohor
    TxStatus <=#Tp ram_do[14:11];
748 38 mohor
end
749
 
750 40 mohor
reg ReadTxDataFromMemory;
751
wire WriteRxDataToMemory;
752 38 mohor
 
753 39 mohor
reg MasterWbTX;
754
reg MasterWbRX;
755
 
756
reg [31:0] m_wb_adr_o;
757
reg        m_wb_cyc_o;
758
reg        m_wb_stb_o;
759 96 mohor
reg  [3:0] m_wb_sel_o;
760 39 mohor
reg        m_wb_we_o;
761 40 mohor
 
762 39 mohor
wire TxLengthEq0;
763
wire TxLengthLt4;
764
 
765 150 mohor
reg BlockingIncrementTxPointer;
766 159 mohor
reg [31:2] TxPointerMSB;
767
reg [1:0]  TxPointerLSB;
768
reg [1:0]  TxPointerLSB_rst;
769
reg [31:2] RxPointerMSB;
770
reg [1:0]  RxPointerLSB_rst;
771 39 mohor
 
772 150 mohor
wire RxBurstAcc;
773
wire RxWordAcc;
774
wire RxHalfAcc;
775
wire RxByteAcc;
776
 
777 39 mohor
//Latching length from the buffer descriptor;
778 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
779 38 mohor
begin
780 40 mohor
  if(Reset)
781 39 mohor
    TxLength <=#Tp 16'h0;
782 38 mohor
  else
783 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
784
    TxLength <=#Tp ram_do[31:16];
785 38 mohor
  else
786 39 mohor
  if(MasterWbTX & m_wb_ack_i)
787
    begin
788
      if(TxLengthLt4)
789
        TxLength <=#Tp 16'h0;
790 150 mohor
      else
791 159 mohor
      if(TxPointerLSB_rst==2'h0)
792 96 mohor
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
793 39 mohor
      else
794 159 mohor
      if(TxPointerLSB_rst==2'h1)
795 150 mohor
        TxLength <=#Tp TxLength - 3'h3;    // Length is subtracted at the data request
796
      else
797 159 mohor
      if(TxPointerLSB_rst==2'h2)
798 150 mohor
        TxLength <=#Tp TxLength - 3'h2;    // Length is subtracted at the data request
799
      else
800 159 mohor
      if(TxPointerLSB_rst==2'h3)
801 150 mohor
        TxLength <=#Tp TxLength - 3'h1;    // Length is subtracted at the data request
802 39 mohor
    end
803 38 mohor
end
804
 
805 96 mohor
 
806
 
807 60 mohor
//Latching length from the buffer descriptor;
808
always @ (posedge WB_CLK_I or posedge Reset)
809
begin
810
  if(Reset)
811
    LatchedTxLength <=#Tp 16'h0;
812
  else
813
  if(TxEn & TxEn_q & TxBDRead)
814
    LatchedTxLength <=#Tp ram_do[31:16];
815
end
816
 
817 39 mohor
assign TxLengthEq0 = TxLength == 0;
818
assign TxLengthLt4 = TxLength < 4;
819 38 mohor
 
820 150 mohor
reg cyc_cleared;
821
reg IncrTxPointer;
822 39 mohor
 
823
 
824 159 mohor
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
825
// because TxPointerMSB is only used for word-aligned accesses.
826 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
827 38 mohor
begin
828 40 mohor
  if(Reset)
829 159 mohor
    TxPointerMSB <=#Tp 30'h0;
830 38 mohor
  else
831 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
832 159 mohor
    TxPointerMSB <=#Tp ram_do[31:2];
833 38 mohor
  else
834 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
835 159 mohor
    TxPointerMSB <=#Tp TxPointerMSB + 1'b1;     // TxPointer is word-aligned
836 38 mohor
end
837
 
838 96 mohor
 
839 159 mohor
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
840
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
841
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
842
// set by this two bits.
843 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
844
begin
845
  if(Reset)
846 159 mohor
    TxPointerLSB[1:0] <=#Tp 0;
847 96 mohor
  else
848
  if(TxEn & TxEn_q & TxPointerRead)
849 159 mohor
    TxPointerLSB[1:0] <=#Tp ram_do[1:0];
850 96 mohor
end
851
 
852
 
853 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
854
// After the read access, TxLength needs to be decremented for the number of the valid
855
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
856
// valid so this two bits are reset to zero. 
857 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
858
begin
859
  if(Reset)
860 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
861 150 mohor
  else
862
  if(TxEn & TxEn_q & TxPointerRead)
863 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
864 150 mohor
  else
865
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
866 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
867 150 mohor
end
868 96 mohor
 
869 150 mohor
 
870 159 mohor
reg  [3:0] RxByteSel;
871 39 mohor
wire MasterAccessFinished;
872 38 mohor
 
873 39 mohor
 
874 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
875 38 mohor
begin
876 40 mohor
  if(Reset)
877 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
878 38 mohor
  else
879 39 mohor
  if(MasterAccessFinished)
880
    BlockingIncrementTxPointer <=#Tp 0;
881 38 mohor
  else
882 150 mohor
  if(IncrTxPointer)
883 39 mohor
    BlockingIncrementTxPointer <=#Tp 1'b1;
884 38 mohor
end
885
 
886
 
887 39 mohor
wire TxBufferAlmostFull;
888
wire TxBufferFull;
889
wire TxBufferEmpty;
890
wire TxBufferAlmostEmpty;
891 40 mohor
wire SetReadTxDataFromMemory;
892 39 mohor
 
893 40 mohor
reg BlockReadTxDataFromMemory;
894 39 mohor
 
895 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
896 39 mohor
 
897 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
898 38 mohor
begin
899 40 mohor
  if(Reset)
900
    ReadTxDataFromMemory <=#Tp 1'b0;
901 38 mohor
  else
902 219 mohor
  if(TxLengthEq0 | TxAbortPacket | TxRetryPacket)
903 40 mohor
    ReadTxDataFromMemory <=#Tp 1'b0;
904 39 mohor
  else
905 40 mohor
  if(SetReadTxDataFromMemory)
906
    ReadTxDataFromMemory <=#Tp 1'b1;
907 38 mohor
end
908
 
909 226 tadejm
reg tx_burst_en;
910
reg rx_burst_en;
911 221 mohor
reg BlockingLastReadOn_Abort_Retry;
912
 
913
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory & ~BlockingLastReadOn_Abort_Retry;
914 226 tadejm
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
915 221 mohor
 
916 39 mohor
wire [31:0] TxData_wb;
917
wire ReadTxDataFromFifo_wb;
918 38 mohor
 
919 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
920 38 mohor
begin
921 40 mohor
  if(Reset)
922
    BlockReadTxDataFromMemory <=#Tp 1'b0;
923 38 mohor
  else
924 221 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (!(TxAbortPacket | TxRetryPacket)))
925 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
926 219 mohor
  else
927 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
928 219 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b0;
929 39 mohor
end
930
 
931
 
932 221 mohor
always @ (posedge WB_CLK_I or posedge Reset)
933
begin
934
  if(Reset)
935
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
936
  else
937
  if(TxAbortPacket | TxRetryPacket)
938
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
939
  else
940
  if(((TxAbort_wb & !TxAbortPacket_NotCleared) | (TxRetry_wb & !TxRetryPacket_NotCleared)) & !TxBDReady)
941
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b1;
942
end
943 39 mohor
 
944 221 mohor
 
945
 
946
 
947 39 mohor
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
948 219 mohor
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
949
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
950 226 tadejm
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
951
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
952 159 mohor
 
953 226 tadejm
wire rx_burst;
954
wire enough_data_in_rxfifo_for_burst;
955
wire enough_data_in_rxfifo_for_burst_plus1;
956
reg [3:0] StateM;
957 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
958 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
959 39 mohor
begin
960 40 mohor
  if(Reset)
961 38 mohor
    begin
962 226 tadejm
StateM<=#Tp 4'h0;
963 39 mohor
      MasterWbTX <=#Tp 1'b0;
964
      MasterWbRX <=#Tp 1'b0;
965
      m_wb_adr_o <=#Tp 32'h0;
966
      m_wb_cyc_o <=#Tp 1'b0;
967
      m_wb_stb_o <=#Tp 1'b0;
968
      m_wb_we_o  <=#Tp 1'b0;
969 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
970 110 mohor
      cyc_cleared<=#Tp 1'b0;
971 226 tadejm
      tx_burst_cnt<=#Tp 0;
972
      rx_burst_cnt<=#Tp 0;
973 150 mohor
      IncrTxPointer<=#Tp 1'b0;
974 226 tadejm
      tx_burst_en<=#Tp 1'b1;
975
      rx_burst_en<=#Tp 1'b0;
976
      `ifdef ETH_WISHBONE_B3
977
        m_wb_cti_o <=#Tp 3'b0;
978
      `endif
979 38 mohor
    end
980 39 mohor
  else
981
    begin
982
      // Switching between two stages depends on enable signals
983 226 tadejm
//      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst})  // synopsys parallel_case
984
      case ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst})  // synopsys parallel_case
985
        8'b00_10_00_10,             // Idle and MRB needed
986
 
987
//        8'b10_1x_10_1x,             // MRB continues
988
        8'b10_10_10_10,             // MRB continues
989
        8'b10_10_10_11,             // MRB continues
990
        8'b10_11_10_10,             // MRB continues
991
        8'b10_11_10_11,             // MRB continues
992
 
993
        8'b10_10_01_10,             // Clear (previously MR) and MRB needed
994
 
995
//        8'b01_1x_01_1x :            // Clear (previously MW) and MRB needed
996
        8'b01_10_01_10 ,            // Clear (previously MW) and MRB needed
997
        8'b01_10_01_11 ,            // Clear (previously MW) and MRB needed
998
        8'b01_11_01_10 ,            // Clear (previously MW) and MRB needed
999
        8'b01_11_01_11 :            // Clear (previously MW) and MRB needed
1000 39 mohor
          begin
1001 226 tadejm
StateM<=#Tp 4'h1;
1002
            MasterWbTX <=#Tp 1'b1;  // tx burst
1003
            MasterWbRX <=#Tp 1'b0;
1004
            m_wb_cyc_o <=#Tp 1'b1;
1005
            m_wb_stb_o <=#Tp 1'b1;
1006
            m_wb_we_o  <=#Tp 1'b0;
1007
            m_wb_sel_o <=#Tp 4'hf;
1008
            cyc_cleared<=#Tp 1'b0;
1009
            IncrTxPointer<=#Tp 1'b1;
1010
            tx_burst_cnt <=#Tp tx_burst_cnt+1;
1011
            if(tx_burst_cnt==0)
1012
              m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1013
            else
1014
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1015
 
1016
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1017
              begin
1018
                tx_burst_en<=#Tp 1'b0;
1019
              `ifdef ETH_WISHBONE_B3
1020
                m_wb_cti_o <=#Tp 3'b111;
1021
              `endif
1022
              end
1023
            else
1024
              begin
1025
              `ifdef ETH_WISHBONE_B3
1026
                m_wb_cti_o <=#Tp 3'b010;
1027
              `endif
1028
              end
1029
          end
1030
//        8'b00_x1_00_x1,             // Idle and MWB needed
1031
        8'b00_01_00_01,             // Idle and MWB needed
1032
        8'b00_01_00_11,             // Idle and MWB needed
1033
        8'b00_11_00_01,             // Idle and MWB needed
1034
        8'b00_11_00_11,             // Idle and MWB needed
1035
 
1036
//        8'b01_x1_10_x1,             // MWB continues
1037
        8'b01_01_10_01,             // MWB continues
1038
        8'b01_01_10_11,             // MWB continues
1039
        8'b01_11_10_01,             // MWB continues
1040
        8'b01_11_10_11,             // MWB continues
1041
 
1042
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1043
 
1044
//        8'b10_x1_01_x1 :            // Clear (previously MR) and MWB needed
1045
        8'b10_01_01_01 ,            // Clear (previously MR) and MWB needed
1046
        8'b10_01_01_11 ,            // Clear (previously MR) and MWB needed
1047
        8'b10_11_01_01 ,            // Clear (previously MR) and MWB needed
1048
        8'b10_11_01_11 :            // Clear (previously MR) and MWB needed
1049
          begin
1050
StateM<=#Tp 4'h2;
1051
            MasterWbTX <=#Tp 1'b0;  // rx burst
1052 39 mohor
            MasterWbRX <=#Tp 1'b1;
1053 226 tadejm
            m_wb_cyc_o <=#Tp 1'b1;
1054
            m_wb_stb_o <=#Tp 1'b1;
1055
            m_wb_we_o  <=#Tp 1'b1;
1056
            m_wb_sel_o <=#Tp RxByteSel;
1057
            IncrTxPointer<=#Tp 1'b0;
1058
            cyc_cleared<=#Tp 1'b0;
1059
            rx_burst_cnt <=#Tp rx_burst_cnt+1;
1060
 
1061
            if(rx_burst_cnt==0)
1062
              m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1063
            else
1064
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1065
 
1066
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1067
              begin
1068
                rx_burst_en<=#Tp 1'b0;
1069
              `ifdef ETH_WISHBONE_B3
1070
                m_wb_cti_o <=#Tp 3'b111;
1071
              `endif
1072
              end
1073
            else
1074
              begin
1075
              `ifdef ETH_WISHBONE_B3
1076
                m_wb_cti_o <=#Tp 3'b010;
1077
              `endif
1078
              end
1079
          end
1080
//        8'b00_x1_00_x0 :            // idle and MW is needed (data write to rx buffer)
1081
        8'b00_01_00_00 ,            // idle and MW is needed (data write to rx buffer)
1082
        8'b00_01_00_10 ,            // idle and MW is needed (data write to rx buffer)
1083
        8'b00_11_00_00 ,            // idle and MW is needed (data write to rx buffer)
1084
        8'b00_11_00_10 :            // idle and MW is needed (data write to rx buffer)
1085
          begin
1086
StateM<=#Tp 4'h3;
1087
            MasterWbTX <=#Tp 1'b0;
1088
            MasterWbRX <=#Tp 1'b1;
1089 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1090 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1091
            m_wb_stb_o <=#Tp 1'b1;
1092
            m_wb_we_o  <=#Tp 1'b1;
1093 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1094 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1095 39 mohor
          end
1096 226 tadejm
        8'b00_10_00_00 :            // idle and MR is needed (data read from tx buffer)
1097 39 mohor
          begin
1098 226 tadejm
StateM<=#Tp 4'h4;
1099
            MasterWbTX <=#Tp 1'b1;
1100 39 mohor
            MasterWbRX <=#Tp 1'b0;
1101 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1102 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1103
            m_wb_stb_o <=#Tp 1'b1;
1104
            m_wb_we_o  <=#Tp 1'b0;
1105 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1106
            IncrTxPointer<=#Tp 1'b1;
1107 39 mohor
          end
1108 226 tadejm
        8'b10_10_01_00,             // MR and MR is needed (data read from tx buffer)
1109
 
1110
//        8'b01_1x_01_0x  :           // MW and MR is needed (data read from tx buffer)
1111
        8'b01_10_01_00  ,           // MW and MR is needed (data read from tx buffer)
1112
        8'b01_10_01_01  ,           // MW and MR is needed (data read from tx buffer)
1113
        8'b01_11_01_00  ,           // MW and MR is needed (data read from tx buffer)
1114
        8'b01_11_01_01  :           // MW and MR is needed (data read from tx buffer)
1115 39 mohor
          begin
1116 226 tadejm
StateM<=#Tp 4'h5;
1117
            MasterWbTX <=#Tp 1'b1;
1118 39 mohor
            MasterWbRX <=#Tp 1'b0;
1119 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1120 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1121
            m_wb_stb_o <=#Tp 1'b1;
1122
            m_wb_we_o  <=#Tp 1'b0;
1123 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1124 110 mohor
            cyc_cleared<=#Tp 1'b0;
1125 150 mohor
            IncrTxPointer<=#Tp 1'b1;
1126 39 mohor
          end
1127 226 tadejm
        8'b01_01_01_00,             // MW and MW needed (data write to rx buffer)
1128
 
1129
//        8'b10_x1_01_x0  :           // MR and MW is needed (data write to rx buffer)
1130
        8'b10_01_01_00  ,           // MR and MW is needed (data write to rx buffer)
1131
        8'b10_01_01_10  ,           // MR and MW is needed (data write to rx buffer)
1132
        8'b10_11_01_00  ,           // MR and MW is needed (data write to rx buffer)
1133
        8'b10_11_01_10  :           // MR and MW is needed (data write to rx buffer)
1134 39 mohor
          begin
1135 226 tadejm
StateM<=#Tp 4'h6;
1136
            MasterWbTX <=#Tp 1'b0;
1137 39 mohor
            MasterWbRX <=#Tp 1'b1;
1138 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1139 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1140
            m_wb_stb_o <=#Tp 1'b1;
1141 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
1142 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1143 110 mohor
            cyc_cleared<=#Tp 1'b0;
1144 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1145 39 mohor
          end
1146 226 tadejm
        8'b01_01_10_00,             // MW and MW needed (cycle is cleared between previous and next access)
1147
 
1148
//        8'b01_1x_10_x0,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1149
        8'b01_10_10_00,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1150
        8'b01_10_10_10,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1151
        8'b01_11_10_00,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1152
        8'b01_11_10_10,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1153
 
1154
        8'b10_10_10_00,             // MR and MR needed (cycle is cleared between previous and next access)
1155
 
1156
//        8'b10_x1_10_0x :            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1157
        8'b10_01_10_00 ,            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1158
        8'b10_01_10_01 ,            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1159
        8'b10_11_10_00 ,            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1160
        8'b10_11_10_01 :            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1161 39 mohor
          begin
1162 226 tadejm
StateM<=#Tp 4'h7;
1163 110 mohor
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
1164
            m_wb_stb_o <=#Tp 1'b0;
1165
            cyc_cleared<=#Tp 1'b1;
1166 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1167 226 tadejm
            tx_burst_cnt<=#Tp 0;
1168
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1169
            rx_burst_cnt<=#Tp 0;
1170
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1171
            `ifdef ETH_WISHBONE_B3
1172
              m_wb_cti_o <=#Tp 3'b0;
1173
            `endif
1174 110 mohor
          end
1175 226 tadejm
//        8'bxx_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1176
        8'b00_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1177
        8'b01_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1178
        8'b10_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1179
        8'b11_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1180
 
1181
//        8'bxx_00_01_00 :            // Between cyc_cleared request was cleared
1182
        8'b00_00_01_00 ,            // Between cyc_cleared request was cleared
1183
        8'b01_00_01_00 ,            // Between cyc_cleared request was cleared
1184
        8'b10_00_01_00 ,            // Between cyc_cleared request was cleared
1185
        8'b11_00_01_00 :            // Between cyc_cleared request was cleared
1186 110 mohor
          begin
1187 226 tadejm
StateM<=#Tp 4'h8;
1188
            MasterWbTX <=#Tp 1'b0;
1189 39 mohor
            MasterWbRX <=#Tp 1'b0;
1190
            m_wb_cyc_o <=#Tp 1'b0;
1191
            m_wb_stb_o <=#Tp 1'b0;
1192 226 tadejm
            cyc_cleared<=#Tp 1'b0;
1193 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1194 226 tadejm
            rx_burst_cnt<=#Tp 0;
1195
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1196
            `ifdef ETH_WISHBONE_B3
1197
              m_wb_cti_o <=#Tp 3'b0;
1198
            `endif
1199 39 mohor
          end
1200 226 tadejm
        8'b00_00_00_00:             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1201 127 mohor
          begin
1202 226 tadejm
StateM<=#Tp 4'h9;
1203
            tx_burst_cnt<=#Tp 0;
1204
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1205 127 mohor
          end
1206 226 tadejm
        default:                    // Don't touch
1207 82 mohor
          begin
1208
            MasterWbTX <=#Tp MasterWbTX;
1209
            MasterWbRX <=#Tp MasterWbRX;
1210
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
1211
            m_wb_stb_o <=#Tp m_wb_stb_o;
1212 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
1213 150 mohor
            IncrTxPointer<=#Tp IncrTxPointer;
1214 82 mohor
          end
1215 39 mohor
      endcase
1216
    end
1217 38 mohor
end
1218
 
1219 110 mohor
 
1220 39 mohor
wire TxFifoClear;
1221 96 mohor
 
1222 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1223 38 mohor
 
1224 219 mohor
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
1225 150 mohor
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
1226 96 mohor
          .clk(WB_CLK_I),                                   .reset(Reset),
1227 226 tadejm
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1228 96 mohor
          .clear(TxFifoClear),                              .full(TxBufferFull),
1229
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
1230 150 mohor
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
1231 96 mohor
        );
1232 39 mohor
 
1233
 
1234
reg StartOccured;
1235
reg TxStartFrm_sync1;
1236
reg TxStartFrm_sync2;
1237
reg TxStartFrm_syncb1;
1238
reg TxStartFrm_syncb2;
1239
 
1240
 
1241
 
1242
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1243 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1244 38 mohor
begin
1245 40 mohor
  if(Reset)
1246 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
1247 38 mohor
  else
1248 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1249
    TxStartFrm_wb <=#Tp 1'b1;
1250 38 mohor
  else
1251 39 mohor
  if(TxStartFrm_syncb2)
1252
    TxStartFrm_wb <=#Tp 1'b0;
1253 38 mohor
end
1254
 
1255 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1256 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1257 38 mohor
begin
1258 40 mohor
  if(Reset)
1259 39 mohor
    StartOccured <=#Tp 1'b0;
1260 38 mohor
  else
1261 39 mohor
  if(TxStartFrm_wb)
1262
    StartOccured <=#Tp 1'b1;
1263 38 mohor
  else
1264 39 mohor
  if(ResetTxBDReady)
1265
    StartOccured <=#Tp 1'b0;
1266 38 mohor
end
1267
 
1268 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1269 40 mohor
always @ (posedge MTxClk or posedge Reset)
1270 39 mohor
begin
1271 40 mohor
  if(Reset)
1272 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1273
  else
1274
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1275
end
1276 38 mohor
 
1277 40 mohor
always @ (posedge MTxClk or posedge Reset)
1278 39 mohor
begin
1279 40 mohor
  if(Reset)
1280 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1281
  else
1282
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1283
end
1284
 
1285 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1286 38 mohor
begin
1287 40 mohor
  if(Reset)
1288 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1289 38 mohor
  else
1290 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1291 38 mohor
end
1292
 
1293 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1294 38 mohor
begin
1295 40 mohor
  if(Reset)
1296 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1297 38 mohor
  else
1298 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1299
end
1300
 
1301 40 mohor
always @ (posedge MTxClk or posedge Reset)
1302 39 mohor
begin
1303 40 mohor
  if(Reset)
1304 39 mohor
    TxStartFrm <=#Tp 1'b0;
1305 38 mohor
  else
1306 39 mohor
  if(TxStartFrm_sync2)
1307 61 mohor
    TxStartFrm <=#Tp 1'b1;
1308 39 mohor
  else
1309 61 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry | TxAbort))
1310 39 mohor
    TxStartFrm <=#Tp 1'b0;
1311 38 mohor
end
1312 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1313 38 mohor
 
1314
 
1315 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1316 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1317 38 mohor
begin
1318 40 mohor
  if(Reset)
1319 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1320 38 mohor
  else
1321 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1322 39 mohor
    TxEndFrm_wb <=#Tp 1'b1;
1323 38 mohor
  else
1324 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1325
    TxEndFrm_wb <=#Tp 1'b0;
1326 38 mohor
end
1327
 
1328
 
1329
// Marks which bytes are valid within the word.
1330 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1331 38 mohor
 
1332 39 mohor
reg LatchValidBytes;
1333
reg LatchValidBytes_q;
1334 38 mohor
 
1335 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1336 38 mohor
begin
1337 40 mohor
  if(Reset)
1338 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1339 38 mohor
  else
1340 39 mohor
  if(TxLengthLt4 & TxBDReady)
1341
    LatchValidBytes <=#Tp 1'b1;
1342 38 mohor
  else
1343 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1344 38 mohor
end
1345
 
1346 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1347 38 mohor
begin
1348 40 mohor
  if(Reset)
1349 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1350 38 mohor
  else
1351 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1352 38 mohor
end
1353
 
1354
 
1355 39 mohor
// Latching valid bytes
1356 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1357 38 mohor
begin
1358 40 mohor
  if(Reset)
1359 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1360 38 mohor
  else
1361 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1362
    TxValidBytesLatched <=#Tp TxValidBytes;
1363
  else
1364
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1365
    TxValidBytesLatched <=#Tp 2'h0;
1366 38 mohor
end
1367
 
1368
 
1369
assign TxIRQEn          = TxStatus[14];
1370 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1371
assign PerPacketPad     = TxStatus[12];
1372
assign PerPacketCrcEn   = TxStatus[11];
1373 38 mohor
 
1374
 
1375 77 mohor
assign RxIRQEn         = RxStatus[14];
1376 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1377 38 mohor
 
1378
 
1379
// Temporary Tx and Rx buffer descriptor address 
1380 39 mohor
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
1381 134 mohor
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1)     | // Using first Rx BD
1382 39 mohor
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
1383 38 mohor
 
1384
 
1385
// Latching Tx buffer descriptor address
1386 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1387 38 mohor
begin
1388 40 mohor
  if(Reset)
1389 38 mohor
    TxBDAddress <=#Tp 8'h0;
1390
  else
1391
  if(TxStatusWrite)
1392
    TxBDAddress <=#Tp TempTxBDAddress;
1393
end
1394
 
1395
 
1396
// Latching Rx buffer descriptor address
1397 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1398 38 mohor
begin
1399 40 mohor
  if(Reset)
1400 134 mohor
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1;
1401 38 mohor
  else
1402 77 mohor
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
1403 134 mohor
    RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
1404 38 mohor
  else
1405
  if(RxStatusWrite)
1406
    RxBDAddress <=#Tp TempRxBDAddress;
1407
end
1408
 
1409 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1410 38 mohor
 
1411 60 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 6'h0, RxStatusInLatched};
1412
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1413 38 mohor
 
1414 60 mohor
 
1415 38 mohor
// Signals used for various purposes
1416 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1417 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1418
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1419
 
1420
 
1421
 
1422 39 mohor
// Generating delayed signals
1423 40 mohor
always @ (posedge MTxClk or posedge Reset)
1424 38 mohor
begin
1425 40 mohor
  if(Reset)
1426 39 mohor
    begin
1427
      TxAbort_q      <=#Tp 1'b0;
1428
      TxRetry_q      <=#Tp 1'b0;
1429
      TxUsedData_q   <=#Tp 1'b0;
1430
    end
1431 38 mohor
  else
1432 39 mohor
    begin
1433
      TxAbort_q      <=#Tp TxAbort;
1434
      TxRetry_q      <=#Tp TxRetry;
1435
      TxUsedData_q   <=#Tp TxUsedData;
1436
    end
1437 38 mohor
end
1438
 
1439
// Generating delayed signals
1440 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1441 38 mohor
begin
1442 40 mohor
  if(Reset)
1443 38 mohor
    begin
1444 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1445
      TxAbort_wb_q  <=#Tp 1'b0;
1446 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1447 38 mohor
    end
1448
  else
1449
    begin
1450 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1451
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1452 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1453 38 mohor
    end
1454
end
1455
 
1456
 
1457 219 mohor
reg TxAbortPacketBlocked;
1458
always @ (posedge WB_CLK_I or posedge Reset)
1459
begin
1460
  if(Reset)
1461
    TxAbortPacket <=#Tp 1'b0;
1462
  else
1463 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxAbortPacketBlocked |
1464
     TxAbort_wb & !MasterWbTX & !TxAbortPacketBlocked)
1465 219 mohor
    TxAbortPacket <=#Tp 1'b1;
1466
  else
1467
    TxAbortPacket <=#Tp 1'b0;
1468
end
1469
 
1470
 
1471
always @ (posedge WB_CLK_I or posedge Reset)
1472
begin
1473
  if(Reset)
1474 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1475
  else
1476 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1477
     TxAbort_wb & !MasterWbTX)
1478 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b1;
1479
  else
1480
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1481
end
1482
 
1483
 
1484
always @ (posedge WB_CLK_I or posedge Reset)
1485
begin
1486
  if(Reset)
1487 219 mohor
    TxAbortPacketBlocked <=#Tp 1'b0;
1488
  else
1489
  if(TxAbortPacket)
1490
    TxAbortPacketBlocked <=#Tp 1'b1;
1491
  else
1492
  if(!TxAbort_wb & TxAbort_wb_q)
1493
    TxAbortPacketBlocked <=#Tp 1'b0;
1494
end
1495
 
1496
 
1497
reg TxRetryPacketBlocked;
1498
always @ (posedge WB_CLK_I or posedge Reset)
1499
begin
1500
  if(Reset)
1501
    TxRetryPacket <=#Tp 1'b0;
1502
  else
1503 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1504
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1505 219 mohor
    TxRetryPacket <=#Tp 1'b1;
1506
  else
1507
    TxRetryPacket <=#Tp 1'b0;
1508
end
1509
 
1510
 
1511
always @ (posedge WB_CLK_I or posedge Reset)
1512
begin
1513
  if(Reset)
1514 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1515
  else
1516 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1517
     TxRetry_wb & !MasterWbTX)
1518 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b1;
1519
  else
1520
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1521
end
1522
 
1523
 
1524
always @ (posedge WB_CLK_I or posedge Reset)
1525
begin
1526
  if(Reset)
1527 219 mohor
    TxRetryPacketBlocked <=#Tp 1'b0;
1528
  else
1529
  if(TxRetryPacket)
1530
    TxRetryPacketBlocked <=#Tp 1'b1;
1531
  else
1532
  if(!TxRetry_wb & TxRetry_wb_q)
1533
    TxRetryPacketBlocked <=#Tp 1'b0;
1534
end
1535
 
1536
 
1537 221 mohor
reg TxDonePacketBlocked;
1538
always @ (posedge WB_CLK_I or posedge Reset)
1539
begin
1540
  if(Reset)
1541
    TxDonePacket <=#Tp 1'b0;
1542
  else
1543 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
1544
     TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1545 221 mohor
    TxDonePacket <=#Tp 1'b1;
1546
  else
1547
    TxDonePacket <=#Tp 1'b0;
1548
end
1549
 
1550
 
1551
always @ (posedge WB_CLK_I or posedge Reset)
1552
begin
1553
  if(Reset)
1554
    TxDonePacket_NotCleared <=#Tp 1'b0;
1555
  else
1556 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1557
     TxDone_wb & !MasterWbTX)
1558 221 mohor
    TxDonePacket_NotCleared <=#Tp 1'b1;
1559
  else
1560
    TxDonePacket_NotCleared <=#Tp 1'b0;
1561
end
1562
 
1563
 
1564
always @ (posedge WB_CLK_I or posedge Reset)
1565
begin
1566
  if(Reset)
1567
    TxDonePacketBlocked <=#Tp 1'b0;
1568
  else
1569
  if(TxDonePacket)
1570
    TxDonePacketBlocked <=#Tp 1'b1;
1571
  else
1572
  if(!TxDone_wb & TxDone_wb_q)
1573
    TxDonePacketBlocked <=#Tp 1'b0;
1574
end
1575
 
1576
 
1577 38 mohor
// Sinchronizing and evaluating tx data
1578 39 mohor
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
1579 219 mohor
assign SetGotData = (TxStartFrm_wb);
1580 38 mohor
 
1581
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
1582 40 mohor
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1583
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1584 38 mohor
 
1585
 
1586
// Indication of the last word
1587 40 mohor
always @ (posedge MTxClk or posedge Reset)
1588 38 mohor
begin
1589 40 mohor
  if(Reset)
1590 38 mohor
    LastWord <=#Tp 1'b0;
1591
  else
1592
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1593
    LastWord <=#Tp 1'b0;
1594
  else
1595
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1596 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1597 38 mohor
end
1598
 
1599
 
1600
// Tx end frame generation
1601 40 mohor
always @ (posedge MTxClk or posedge Reset)
1602 38 mohor
begin
1603 40 mohor
  if(Reset)
1604 38 mohor
    TxEndFrm <=#Tp 1'b0;
1605
  else
1606 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1607 38 mohor
    TxEndFrm <=#Tp 1'b0;
1608
  else
1609
  if(Flop & LastWord)
1610
    begin
1611 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1612 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1613
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1614
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1615
 
1616
        default : TxEndFrm <=#Tp 1'b0;
1617
      endcase
1618
    end
1619
end
1620
 
1621
 
1622
// Tx data selection (latching)
1623 40 mohor
always @ (posedge MTxClk or posedge Reset)
1624 38 mohor
begin
1625 40 mohor
  if(Reset)
1626 96 mohor
    TxData <=#Tp 0;
1627 38 mohor
  else
1628 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1629 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1630 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1631
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1632
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1633
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1634
    endcase
1635 38 mohor
  else
1636 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1637 96 mohor
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1638
  else
1639 38 mohor
  if(TxUsedData & Flop)
1640
    begin
1641 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1642 226 tadejm
 
1643 82 mohor
        1 : TxData <=#Tp TxDataLatched[23:16];
1644
        2 : TxData <=#Tp TxDataLatched[15:8];
1645
        3 : TxData <=#Tp TxDataLatched[7:0];
1646 38 mohor
      endcase
1647
    end
1648
end
1649
 
1650
 
1651
// Latching tx data
1652 40 mohor
always @ (posedge MTxClk or posedge Reset)
1653 38 mohor
begin
1654 40 mohor
  if(Reset)
1655 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1656
  else
1657 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1658 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1659 38 mohor
end
1660
 
1661
 
1662
// Tx under run
1663 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1664 38 mohor
begin
1665 40 mohor
  if(Reset)
1666 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1667 38 mohor
  else
1668 39 mohor
  if(TxAbortPulse)
1669 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1670
  else
1671
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1672
    TxUnderRun_wb <=#Tp 1'b1;
1673
end
1674
 
1675
 
1676 159 mohor
reg TxUnderRun_sync1;
1677
 
1678 60 mohor
// Tx under run
1679
always @ (posedge MTxClk or posedge Reset)
1680
begin
1681
  if(Reset)
1682 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b0;
1683 43 mohor
  else
1684 60 mohor
  if(TxUnderRun_wb)
1685 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b1;
1686 60 mohor
  else
1687 159 mohor
  if(BlockingTxStatusWrite_sync2)
1688
    TxUnderRun_sync1 <=#Tp 1'b0;
1689
end
1690
 
1691
// Tx under run
1692
always @ (posedge MTxClk or posedge Reset)
1693
begin
1694
  if(Reset)
1695 60 mohor
    TxUnderRun <=#Tp 1'b0;
1696 159 mohor
  else
1697
  if(BlockingTxStatusWrite_sync2)
1698
    TxUnderRun <=#Tp 1'b0;
1699
  else
1700
  if(TxUnderRun_sync1)
1701
    TxUnderRun <=#Tp 1'b1;
1702 38 mohor
end
1703
 
1704
 
1705
// Tx Byte counter
1706 40 mohor
always @ (posedge MTxClk or posedge Reset)
1707 38 mohor
begin
1708 40 mohor
  if(Reset)
1709 38 mohor
    TxByteCnt <=#Tp 2'h0;
1710
  else
1711
  if(TxAbort_q | TxRetry_q)
1712
    TxByteCnt <=#Tp 2'h0;
1713
  else
1714
  if(TxStartFrm & ~TxUsedData)
1715 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1716 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1717
      2'h1 : TxByteCnt <=#Tp 2'h2;
1718
      2'h2 : TxByteCnt <=#Tp 2'h3;
1719
      2'h3 : TxByteCnt <=#Tp 2'h0;
1720
    endcase
1721 38 mohor
  else
1722
  if(TxUsedData & Flop)
1723 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1724 38 mohor
end
1725
 
1726 39 mohor
 
1727 150 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1728
reg ReadTxDataFromFifo_sync1;
1729
reg ReadTxDataFromFifo_sync2;
1730
reg ReadTxDataFromFifo_sync3;
1731
reg ReadTxDataFromFifo_syncb1;
1732
reg ReadTxDataFromFifo_syncb2;
1733
reg ReadTxDataFromFifo_syncb3;
1734
 
1735
 
1736
always @ (posedge MTxClk or posedge Reset)
1737
begin
1738
  if(Reset)
1739
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1740
  else
1741 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1742 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1743 150 mohor
  else
1744
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1745
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1746 38 mohor
end
1747
 
1748 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1749 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1750 38 mohor
begin
1751 40 mohor
  if(Reset)
1752 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1753 38 mohor
  else
1754 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1755
end
1756 38 mohor
 
1757 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1758 38 mohor
begin
1759 40 mohor
  if(Reset)
1760 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1761 38 mohor
  else
1762 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1763 38 mohor
end
1764
 
1765 40 mohor
always @ (posedge MTxClk or posedge Reset)
1766 38 mohor
begin
1767 40 mohor
  if(Reset)
1768 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1769 38 mohor
  else
1770 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1771 38 mohor
end
1772
 
1773 40 mohor
always @ (posedge MTxClk or posedge Reset)
1774 38 mohor
begin
1775 40 mohor
  if(Reset)
1776 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1777 38 mohor
  else
1778 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1779 38 mohor
end
1780
 
1781 150 mohor
always @ (posedge MTxClk or posedge Reset)
1782
begin
1783
  if(Reset)
1784
    ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
1785
  else
1786
    ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
1787
end
1788
 
1789 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1790 38 mohor
begin
1791 40 mohor
  if(Reset)
1792 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1793 38 mohor
  else
1794 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1795 38 mohor
end
1796
 
1797 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1798
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1799 38 mohor
 
1800
 
1801 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1802 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1803 38 mohor
begin
1804 40 mohor
  if(Reset)
1805 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1806 38 mohor
  else
1807 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1808 38 mohor
end
1809
 
1810 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1811 38 mohor
begin
1812 40 mohor
  if(Reset)
1813 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1814 38 mohor
  else
1815 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1816 38 mohor
end
1817
 
1818
 
1819 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1820 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1821 38 mohor
begin
1822 40 mohor
  if(Reset)
1823 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1824 38 mohor
  else
1825 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1826 38 mohor
end
1827
 
1828 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1829 38 mohor
begin
1830 40 mohor
  if(Reset)
1831 39 mohor
    TxDone_wb <=#Tp 1'b0;
1832 38 mohor
  else
1833 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1834 38 mohor
end
1835
 
1836 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1837 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1838 38 mohor
begin
1839 40 mohor
  if(Reset)
1840 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1841 38 mohor
  else
1842 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1843 38 mohor
end
1844
 
1845 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1846 38 mohor
begin
1847 40 mohor
  if(Reset)
1848 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1849
  else
1850 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1851 38 mohor
end
1852
 
1853
 
1854 150 mohor
reg RxAbortSync1;
1855
reg RxAbortSync2;
1856
reg RxAbortSync3;
1857
reg RxAbortSync4;
1858
reg RxAbortSyncb1;
1859
reg RxAbortSyncb2;
1860 39 mohor
 
1861 150 mohor
//assign StartRxBDRead = RxStatusWrite | RxAbortLatched;
1862
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
1863
 
1864 40 mohor
// Reading the Rx buffer descriptor
1865
always @ (posedge WB_CLK_I or posedge Reset)
1866
begin
1867
  if(Reset)
1868
    RxBDRead <=#Tp 1'b1;
1869
  else
1870 166 mohor
  if(StartRxBDRead & ~RxReady)
1871 40 mohor
    RxBDRead <=#Tp 1'b1;
1872
  else
1873
  if(RxBDReady)
1874
    RxBDRead <=#Tp 1'b0;
1875
end
1876 39 mohor
 
1877
 
1878 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1879
// written to the previous one.
1880
 
1881
// Latching READY status of the Rx buffer descriptor
1882 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1883 38 mohor
begin
1884 40 mohor
  if(Reset)
1885 38 mohor
    RxBDReady <=#Tp 1'b0;
1886
  else
1887 166 mohor
  if(RxPointerRead)
1888 150 mohor
    RxBDReady <=#Tp 1'b0;
1889
  else
1890 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1891
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1892 38 mohor
end
1893
 
1894 40 mohor
// Latching Rx buffer descriptor status
1895
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1896
always @ (posedge WB_CLK_I or posedge Reset)
1897 38 mohor
begin
1898 40 mohor
  if(Reset)
1899 60 mohor
    RxStatus <=#Tp 2'h0;
1900 38 mohor
  else
1901 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1902 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1903 38 mohor
end
1904
 
1905
 
1906 166 mohor
// RxReady generation
1907
always @ (posedge WB_CLK_I or posedge Reset)
1908
begin
1909
  if(Reset)
1910
    RxReady <=#Tp 1'b0;
1911
  else
1912
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
1913
    RxReady <=#Tp 1'b0;
1914
  else
1915
  if(RxEn & RxEn_q & RxPointerRead)
1916
    RxReady <=#Tp 1'b1;
1917
end
1918 38 mohor
 
1919
 
1920 40 mohor
// Reading Rx BD pointer
1921
 
1922
 
1923
assign StartRxPointerRead = RxBDRead & RxBDReady;
1924
 
1925
// Reading Tx BD Pointer
1926
always @ (posedge WB_CLK_I or posedge Reset)
1927 38 mohor
begin
1928 40 mohor
  if(Reset)
1929
    RxPointerRead <=#Tp 1'b0;
1930 38 mohor
  else
1931 40 mohor
  if(StartRxPointerRead)
1932
    RxPointerRead <=#Tp 1'b1;
1933 38 mohor
  else
1934 166 mohor
  if(RxEn & RxEn_q)
1935 40 mohor
    RxPointerRead <=#Tp 1'b0;
1936 38 mohor
end
1937
 
1938 113 mohor
 
1939 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1940
always @ (posedge WB_CLK_I or posedge Reset)
1941
begin
1942
  if(Reset)
1943 159 mohor
    RxPointerMSB <=#Tp 30'h0;
1944 40 mohor
  else
1945
  if(RxEn & RxEn_q & RxPointerRead)
1946 159 mohor
    RxPointerMSB <=#Tp ram_do[31:2];
1947 40 mohor
  else
1948 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1949 159 mohor
      RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1950 40 mohor
end
1951 38 mohor
 
1952
 
1953 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1954 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1955
begin
1956
  if(Reset)
1957 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp 0;
1958 96 mohor
  else
1959 159 mohor
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
1960
    RxPointerLSB_rst[1:0] <=#Tp 0;
1961 96 mohor
  else
1962
  if(RxEn & RxEn_q & RxPointerRead)
1963 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
1964 96 mohor
end
1965
 
1966
 
1967 159 mohor
always @ (RxPointerLSB_rst)
1968 96 mohor
begin
1969 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1970
    2'h0 : RxByteSel[3:0] = 4'hf;
1971
    2'h1 : RxByteSel[3:0] = 4'h7;
1972
    2'h2 : RxByteSel[3:0] = 4'h3;
1973
    2'h3 : RxByteSel[3:0] = 4'h1;
1974 96 mohor
  endcase
1975
end
1976
 
1977
 
1978
always @ (posedge WB_CLK_I or posedge Reset)
1979
begin
1980
  if(Reset)
1981 40 mohor
    RxEn_needed <=#Tp 1'b0;
1982 38 mohor
  else
1983 166 mohor
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1984 40 mohor
    RxEn_needed <=#Tp 1'b1;
1985 38 mohor
  else
1986 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1987
    RxEn_needed <=#Tp 1'b0;
1988 38 mohor
end
1989
 
1990
 
1991 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1992
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1993 38 mohor
 
1994 42 mohor
reg RxStatusWriteLatched;
1995
reg RxStatusWrite_rck;
1996
 
1997
always @ (posedge WB_CLK_I or posedge Reset)
1998
begin
1999
  if(Reset)
2000
    RxStatusWriteLatched <=#Tp 1'b0;
2001
  else
2002 87 mohor
  if(RxStatusWrite & ~RxStatusWrite_rck)
2003 42 mohor
    RxStatusWriteLatched <=#Tp 1'b1;
2004
  else
2005
  if(RxStatusWrite_rck)
2006
    RxStatusWriteLatched <=#Tp 1'b0;
2007
end
2008
 
2009
 
2010
always @ (posedge MRxClk or posedge Reset)
2011
begin
2012
  if(Reset)
2013
    RxStatusWrite_rck <=#Tp 1'b0;
2014
  else
2015 87 mohor
  if(RxStatusWriteLatched)
2016
    RxStatusWrite_rck <=#Tp 1'b1;
2017
  else
2018
    RxStatusWrite_rck <=#Tp 1'b0;
2019 42 mohor
end
2020
 
2021
 
2022 40 mohor
reg RxEnableWindow;
2023 38 mohor
 
2024
// Indicating that last byte is being reveived
2025 40 mohor
always @ (posedge MRxClk or posedge Reset)
2026 38 mohor
begin
2027 40 mohor
  if(Reset)
2028 38 mohor
    LastByteIn <=#Tp 1'b0;
2029
  else
2030 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
2031 38 mohor
    LastByteIn <=#Tp 1'b0;
2032
  else
2033 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
2034 38 mohor
    LastByteIn <=#Tp 1'b1;
2035
end
2036
 
2037 159 mohor
reg ShiftEnded_rck;
2038 40 mohor
reg ShiftEndedSync1;
2039
reg ShiftEndedSync2;
2040 118 mohor
reg ShiftEndedSync3;
2041
reg ShiftEndedSync_c1;
2042
reg ShiftEndedSync_c2;
2043
 
2044 40 mohor
wire StartShiftWillEnd;
2045 96 mohor
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
2046 38 mohor
 
2047
// Indicating that data reception will end
2048 40 mohor
always @ (posedge MRxClk or posedge Reset)
2049 38 mohor
begin
2050 40 mohor
  if(Reset)
2051 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
2052
  else
2053 159 mohor
  if(ShiftEnded_rck | RxAbort)
2054 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
2055
  else
2056 40 mohor
  if(StartShiftWillEnd)
2057 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
2058
end
2059
 
2060
 
2061 40 mohor
 
2062 38 mohor
// Receive byte counter
2063 40 mohor
always @ (posedge MRxClk or posedge Reset)
2064 38 mohor
begin
2065 40 mohor
  if(Reset)
2066 38 mohor
    RxByteCnt <=#Tp 2'h0;
2067
  else
2068 159 mohor
  if(ShiftEnded_rck | RxAbort)
2069 38 mohor
    RxByteCnt <=#Tp 2'h0;
2070 97 lampret
  else
2071 166 mohor
  if(RxValid & RxStartFrm & RxReady)
2072 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2073 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
2074
      2'h1 : RxByteCnt <=#Tp 2'h2;
2075
      2'h2 : RxByteCnt <=#Tp 2'h3;
2076
      2'h3 : RxByteCnt <=#Tp 2'h0;
2077
    endcase
2078 38 mohor
  else
2079 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
2080 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
2081 38 mohor
end
2082
 
2083
 
2084
// Indicates how many bytes are valid within the last word
2085 40 mohor
always @ (posedge MRxClk or posedge Reset)
2086 38 mohor
begin
2087 40 mohor
  if(Reset)
2088 38 mohor
    RxValidBytes <=#Tp 2'h1;
2089
  else
2090 96 mohor
  if(RxValid & RxStartFrm)
2091 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2092 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
2093
      2'h1 : RxValidBytes <=#Tp 2'h2;
2094
      2'h2 : RxValidBytes <=#Tp 2'h3;
2095
      2'h3 : RxValidBytes <=#Tp 2'h0;
2096
    endcase
2097 38 mohor
  else
2098 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2099 38 mohor
    RxValidBytes <=#Tp RxValidBytes + 1;
2100
end
2101
 
2102
 
2103 40 mohor
always @ (posedge MRxClk or posedge Reset)
2104 38 mohor
begin
2105 40 mohor
  if(Reset)
2106
    RxDataLatched1       <=#Tp 24'h0;
2107 38 mohor
  else
2108 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2109 96 mohor
    if(RxStartFrm)
2110 40 mohor
    begin
2111 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2112 96 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2113
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2114
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2115
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2116
      endcase
2117
    end
2118
    else if (RxEnableWindow)
2119
    begin
2120 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2121 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2122
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2123
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2124 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2125
      endcase
2126
    end
2127 38 mohor
end
2128
 
2129 40 mohor
wire SetWriteRxDataToFifo;
2130 38 mohor
 
2131 40 mohor
// Assembling data that will be written to the rx_fifo
2132
always @ (posedge MRxClk or posedge Reset)
2133 38 mohor
begin
2134 40 mohor
  if(Reset)
2135
    RxDataLatched2 <=#Tp 32'h0;
2136 38 mohor
  else
2137 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2138 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
2139 38 mohor
  else
2140 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2141 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2142 82 mohor
 
2143
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2144
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
2145
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
2146 40 mohor
    endcase
2147 38 mohor
end
2148
 
2149
 
2150 40 mohor
reg WriteRxDataToFifoSync1;
2151
reg WriteRxDataToFifoSync2;
2152 150 mohor
reg WriteRxDataToFifoSync3;
2153 38 mohor
 
2154
 
2155 40 mohor
// Indicating start of the reception process
2156 166 mohor
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
2157
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
2158
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
2159 38 mohor
 
2160 150 mohor
always @ (posedge MRxClk or posedge Reset)
2161
begin
2162
  if(Reset)
2163
    WriteRxDataToFifo <=#Tp 1'b0;
2164
  else
2165
  if(SetWriteRxDataToFifo & ~RxAbort)
2166
    WriteRxDataToFifo <=#Tp 1'b1;
2167
  else
2168
  if(WriteRxDataToFifoSync2 | RxAbort)
2169
    WriteRxDataToFifo <=#Tp 1'b0;
2170
end
2171 40 mohor
 
2172 150 mohor
 
2173
 
2174
always @ (posedge WB_CLK_I or posedge Reset)
2175
begin
2176
  if(Reset)
2177
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2178
  else
2179
  if(WriteRxDataToFifo)
2180
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
2181
  else
2182
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2183
end
2184
 
2185
always @ (posedge WB_CLK_I or posedge Reset)
2186
begin
2187
  if(Reset)
2188
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
2189
  else
2190
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
2191
end
2192
 
2193
always @ (posedge WB_CLK_I or posedge Reset)
2194
begin
2195
  if(Reset)
2196
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
2197
  else
2198
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
2199
end
2200
 
2201
wire WriteRxDataToFifo_wb;
2202
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
2203
 
2204
 
2205 90 mohor
reg LatchedRxStartFrm;
2206
reg SyncRxStartFrm;
2207
reg SyncRxStartFrm_q;
2208 150 mohor
reg SyncRxStartFrm_q2;
2209 90 mohor
wire RxFifoReset;
2210 40 mohor
 
2211 90 mohor
always @ (posedge MRxClk or posedge Reset)
2212
begin
2213
  if(Reset)
2214
    LatchedRxStartFrm <=#Tp 0;
2215
  else
2216 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2217 90 mohor
    LatchedRxStartFrm <=#Tp 1;
2218
  else
2219 150 mohor
  if(SyncRxStartFrm_q)
2220 90 mohor
    LatchedRxStartFrm <=#Tp 0;
2221
end
2222
 
2223
 
2224
always @ (posedge WB_CLK_I or posedge Reset)
2225
begin
2226
  if(Reset)
2227
    SyncRxStartFrm <=#Tp 0;
2228
  else
2229
  if(LatchedRxStartFrm)
2230
    SyncRxStartFrm <=#Tp 1;
2231
  else
2232
    SyncRxStartFrm <=#Tp 0;
2233
end
2234
 
2235
 
2236
always @ (posedge WB_CLK_I or posedge Reset)
2237
begin
2238
  if(Reset)
2239
    SyncRxStartFrm_q <=#Tp 0;
2240
  else
2241
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
2242
end
2243
 
2244 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2245
begin
2246
  if(Reset)
2247
    SyncRxStartFrm_q2 <=#Tp 0;
2248
  else
2249
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
2250
end
2251 90 mohor
 
2252
 
2253 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2254 90 mohor
 
2255 150 mohor
 
2256 219 mohor
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
2257 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
2258
         .clk(WB_CLK_I),                                .reset(Reset),
2259 219 mohor
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
2260 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
2261 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
2262 150 mohor
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
2263 88 mohor
        );
2264 40 mohor
 
2265 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2266
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2267 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2268 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2269 40 mohor
 
2270
 
2271
// Generation of the end-of-frame signal
2272
always @ (posedge MRxClk or posedge Reset)
2273 38 mohor
begin
2274 40 mohor
  if(Reset)
2275 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2276 38 mohor
  else
2277 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2278 159 mohor
    ShiftEnded_rck <=#Tp 1'b1;
2279 38 mohor
  else
2280 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2281 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2282 38 mohor
end
2283
 
2284 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2285
begin
2286
  if(Reset)
2287
    ShiftEndedSync1 <=#Tp 1'b0;
2288
  else
2289 159 mohor
    ShiftEndedSync1 <=#Tp ShiftEnded_rck;
2290 40 mohor
end
2291 38 mohor
 
2292 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2293 38 mohor
begin
2294 40 mohor
  if(Reset)
2295
    ShiftEndedSync2 <=#Tp 1'b0;
2296 38 mohor
  else
2297 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
2298 40 mohor
end
2299 38 mohor
 
2300 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2301
begin
2302
  if(Reset)
2303
    ShiftEndedSync3 <=#Tp 1'b0;
2304
  else
2305
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2306
    ShiftEndedSync3 <=#Tp 1'b1;
2307
  else
2308
  if(ShiftEnded)
2309
    ShiftEndedSync3 <=#Tp 1'b0;
2310
end
2311 38 mohor
 
2312 40 mohor
// Generation of the end-of-frame signal
2313
always @ (posedge WB_CLK_I or posedge Reset)
2314 38 mohor
begin
2315 40 mohor
  if(Reset)
2316
    ShiftEnded <=#Tp 1'b0;
2317 38 mohor
  else
2318 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2319 40 mohor
    ShiftEnded <=#Tp 1'b1;
2320 38 mohor
  else
2321 40 mohor
  if(RxStatusWrite)
2322
    ShiftEnded <=#Tp 1'b0;
2323 38 mohor
end
2324
 
2325 118 mohor
always @ (posedge MRxClk or posedge Reset)
2326
begin
2327
  if(Reset)
2328
    ShiftEndedSync_c1 <=#Tp 1'b0;
2329
  else
2330
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
2331
end
2332 38 mohor
 
2333 118 mohor
always @ (posedge MRxClk or posedge Reset)
2334
begin
2335
  if(Reset)
2336
    ShiftEndedSync_c2 <=#Tp 1'b0;
2337
  else
2338
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
2339
end
2340
 
2341 40 mohor
// Generation of the end-of-frame signal
2342
always @ (posedge MRxClk or posedge Reset)
2343 38 mohor
begin
2344 40 mohor
  if(Reset)
2345
    RxEnableWindow <=#Tp 1'b0;
2346 38 mohor
  else
2347 40 mohor
  if(RxStartFrm)
2348
    RxEnableWindow <=#Tp 1'b1;
2349 38 mohor
  else
2350 40 mohor
  if(RxEndFrm | RxAbort)
2351
    RxEnableWindow <=#Tp 1'b0;
2352 38 mohor
end
2353
 
2354
 
2355 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2356 38 mohor
begin
2357 40 mohor
  if(Reset)
2358
    RxAbortSync1 <=#Tp 1'b0;
2359 38 mohor
  else
2360 150 mohor
    RxAbortSync1 <=#Tp RxAbortLatched;
2361 40 mohor
end
2362
 
2363
always @ (posedge WB_CLK_I or posedge Reset)
2364
begin
2365
  if(Reset)
2366
    RxAbortSync2 <=#Tp 1'b0;
2367 38 mohor
  else
2368 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
2369 38 mohor
end
2370
 
2371 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2372
begin
2373
  if(Reset)
2374
    RxAbortSync3 <=#Tp 1'b0;
2375
  else
2376
    RxAbortSync3 <=#Tp RxAbortSync2;
2377
end
2378
 
2379
always @ (posedge WB_CLK_I or posedge Reset)
2380
begin
2381
  if(Reset)
2382
    RxAbortSync4 <=#Tp 1'b0;
2383
  else
2384
    RxAbortSync4 <=#Tp RxAbortSync3;
2385
end
2386
 
2387 40 mohor
always @ (posedge MRxClk or posedge Reset)
2388
begin
2389
  if(Reset)
2390
    RxAbortSyncb1 <=#Tp 1'b0;
2391
  else
2392
    RxAbortSyncb1 <=#Tp RxAbortSync2;
2393
end
2394 38 mohor
 
2395 40 mohor
always @ (posedge MRxClk or posedge Reset)
2396 38 mohor
begin
2397 40 mohor
  if(Reset)
2398
    RxAbortSyncb2 <=#Tp 1'b0;
2399 38 mohor
  else
2400 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
2401 38 mohor
end
2402
 
2403
 
2404 64 mohor
always @ (posedge MRxClk or posedge Reset)
2405
begin
2406
  if(Reset)
2407
    RxAbortLatched <=#Tp 1'b0;
2408
  else
2409 150 mohor
  if(RxAbortSyncb2)
2410
    RxAbortLatched <=#Tp 1'b0;
2411
  else
2412 64 mohor
  if(RxAbort)
2413
    RxAbortLatched <=#Tp 1'b1;
2414
end
2415 40 mohor
 
2416 64 mohor
 
2417 42 mohor
always @ (posedge MRxClk or posedge Reset)
2418
begin
2419
  if(Reset)
2420
    LatchedRxLength[15:0] <=#Tp 16'h0;
2421
  else
2422 150 mohor
  if(LoadRxStatus)
2423 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
2424
end
2425
 
2426
 
2427 60 mohor
assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2428 42 mohor
 
2429
always @ (posedge MRxClk or posedge Reset)
2430
begin
2431
  if(Reset)
2432
    RxStatusInLatched <=#Tp 'h0;
2433
  else
2434 150 mohor
  if(LoadRxStatus)
2435 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
2436
end
2437
 
2438
 
2439 60 mohor
// Rx overrun
2440
always @ (posedge WB_CLK_I or posedge Reset)
2441
begin
2442
  if(Reset)
2443
    RxOverrun <=#Tp 1'b0;
2444
  else
2445
  if(RxStatusWrite)
2446
    RxOverrun <=#Tp 1'b0;
2447
  else
2448
  if(RxBufferFull & WriteRxDataToFifo_wb)
2449
    RxOverrun <=#Tp 1'b1;
2450
end
2451 48 mohor
 
2452 77 mohor
 
2453
 
2454
wire TxError;
2455
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2456
 
2457
wire RxError;
2458
assign RxError = |RxStatusInLatched[6:0];
2459
 
2460
// Tx Done Interrupt
2461
always @ (posedge WB_CLK_I or posedge Reset)
2462
begin
2463
  if(Reset)
2464
    TxB_IRQ <=#Tp 1'b0;
2465
  else
2466
  if(TxStatusWrite & TxIRQEn)
2467
    TxB_IRQ <=#Tp ~TxError;
2468
  else
2469
    TxB_IRQ <=#Tp 1'b0;
2470
end
2471
 
2472
 
2473
// Tx Error Interrupt
2474
always @ (posedge WB_CLK_I or posedge Reset)
2475
begin
2476
  if(Reset)
2477
    TxE_IRQ <=#Tp 1'b0;
2478
  else
2479
  if(TxStatusWrite & TxIRQEn)
2480
    TxE_IRQ <=#Tp TxError;
2481
  else
2482
    TxE_IRQ <=#Tp 1'b0;
2483
end
2484
 
2485
 
2486
// Rx Done Interrupt
2487
always @ (posedge WB_CLK_I or posedge Reset)
2488
begin
2489
  if(Reset)
2490
    RxB_IRQ <=#Tp 1'b0;
2491
  else
2492
  if(RxStatusWrite & RxIRQEn)
2493 167 mohor
    RxB_IRQ <=#Tp ReceivedPacketGood & ~RxError;
2494 77 mohor
  else
2495
    RxB_IRQ <=#Tp 1'b0;
2496
end
2497
 
2498
 
2499
// Rx Error Interrupt
2500
always @ (posedge WB_CLK_I or posedge Reset)
2501
begin
2502
  if(Reset)
2503
    RxE_IRQ <=#Tp 1'b0;
2504
  else
2505
  if(RxStatusWrite & RxIRQEn)
2506
    RxE_IRQ <=#Tp RxError;
2507
  else
2508
    RxE_IRQ <=#Tp 1'b0;
2509
end
2510
 
2511
 
2512 166 mohor
// Busy Interrupt
2513 77 mohor
 
2514 166 mohor
reg Busy_IRQ_rck;
2515
reg Busy_IRQ_sync1;
2516
reg Busy_IRQ_sync2;
2517
reg Busy_IRQ_sync3;
2518
reg Busy_IRQ_syncb1;
2519
reg Busy_IRQ_syncb2;
2520 77 mohor
 
2521
 
2522 166 mohor
always @ (posedge MRxClk or posedge Reset)
2523
begin
2524
  if(Reset)
2525
    Busy_IRQ_rck <=#Tp 1'b0;
2526
  else
2527
  if(RxValid & RxStartFrm & ~RxReady)
2528
    Busy_IRQ_rck <=#Tp 1'b1;
2529
  else
2530
  if(Busy_IRQ_syncb2)
2531
    Busy_IRQ_rck <=#Tp 1'b0;
2532
end
2533 77 mohor
 
2534 166 mohor
always @ (posedge WB_CLK_I)
2535
begin
2536
    Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
2537
    Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
2538
    Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
2539
end
2540
 
2541
always @ (posedge MRxClk)
2542
begin
2543
    Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
2544
    Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
2545
end
2546
 
2547
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
2548
 
2549
 
2550 60 mohor
 
2551
// TX
2552 61 mohor
// bit 15 ready
2553
// bit 14 interrupt
2554
// bit 13 wrap
2555
// bit 12 pad
2556
// bit 11 crc
2557
// bit 10 last
2558
// bit 9  pause request (control frame)
2559
// bit 8  TxUnderRun          
2560
// bit 7-4 RetryCntLatched    
2561
// bit 3  retransmittion limit
2562
// bit 2  LateCollLatched        
2563
// bit 1  DeferLatched        
2564
// bit 0  CarrierSenseLost    
2565 60 mohor
 
2566
 
2567
// RX
2568
// bit 15 od rx je empty
2569 61 mohor
// bit 14 od rx je interrupt
2570 60 mohor
// bit 13 od rx je wrap
2571
// bit 12 od rx je reserved
2572
// bit 11 od rx je reserved
2573
// bit 10 od rx je reserved
2574
// bit 9  od rx je reserved
2575
// bit 8  od rx je reserved
2576 110 mohor
// bit 7  od rx je Miss
2577 60 mohor
// bit 6  od rx je RxOverrun
2578
// bit 5  od rx je InvalidSymbol
2579
// bit 4  od rx je DribbleNibble
2580
// bit 3  od rx je ReceivedPacketTooBig
2581
// bit 2  od rx je ShortFrame
2582
// bit 1  od rx je LatchedCrcError
2583
// bit 0  od rx je RxLateCollision
2584
 
2585 110 mohor
 
2586 38 mohor
endmodule
2587
 

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