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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 250

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 250 mohor
// Revision 1.44  2002/11/13 22:21:40  tadejm
45
// RxError is not generated when small frame reception is enabled and small
46
// frames are received.
47
//
48 239 tadejm
// Revision 1.43  2002/10/18 20:53:34  mohor
49
// case changed to casex.
50
//
51 229 mohor
// Revision 1.42  2002/10/18 17:04:20  tadejm
52
// Changed BIST scan signals.
53
//
54 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
55
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
56
//
57 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
58
// TxStatus is written after last access to the TX fifo is finished (in case of abort
59
// or retry). TxDone is fixed.
60
//
61 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
62
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
63
// TxDone and TxRetry are generated after the current WISHBONE access is
64
// finished.
65
//
66 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
67
// BIST added.
68
//
69 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
70
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
71
//
72 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
73
// Reception is possible after RxPointer is read and not after BD is read. For
74
// that reason RxBDReady is changed to RxReady.
75
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
76
// comes, interrupt is generated.
77
//
78 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
79
// Ethernet debug registers removed.
80
//
81 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
82
// Async reset for WB_ACK_O removed (when core was in reset, it was
83
// impossible to access BDs).
84
// RxPointers and TxPointers names changed to be more descriptive.
85
// TxUnderRun synchronized.
86
//
87 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
88
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
89
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
90
// was not used OK.
91
//
92 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
93
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
94
// need to multiply or devide any more.
95
//
96 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
97
// WriteRxDataToMemory signal changed so end of frame (when last word is
98
// written to fifo) is changed.
99
//
100 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
101
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
102
//
103 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
104
// ShiftEnded synchronization changed.
105
//
106 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
107
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
108
//
109 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
110
// RxPointer bug fixed.
111
//
112 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
113
// Previous bug wasn't succesfully removed. Now fixed.
114
//
115 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
116
// Master state machine had a bug when switching from master write to
117
// master read.
118
//
119 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
120
// m_wb_cyc_o signal released after every single transfer.
121
//
122 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
123
// Outputs registered. Reset changed for eth_wishbone module.
124
//
125 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
126
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
127
// bug fixed.
128
//
129 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
130
// Small typo fixed.
131
//
132 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
133
// Any address can be used for Tx and Rx BD pointers. Address does not need
134
// to be aligned.
135
//
136 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
137
// Comments in Slovene language removed.
138
//
139 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
140
// casex changed with case, fifo reset changed.
141
//
142 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
143
// rx_fifo was not always cleared ok. Fixed.
144
//
145 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
146
// Status was not latched correctly sometimes. Fixed.
147
//
148 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
149
// Big Endian problem when sending frames fixed.
150
//
151 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
152
// Byte ordering changed (Big Endian used). casex changed with case because
153
// Xilinx Foundation had problems. Tested in HW. It WORKS.
154
//
155 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
156
// Small fixes for external/internal DMA missmatches.
157
//
158 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
159
// Interrupts changed
160
//
161 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
162
// Status was not written correctly when frames were discarted because of
163
// address mismatch.
164
//
165 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
166
// RxStartFrm cleared when abort or retry comes.
167
//
168 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
169
// Changes that were lost when updating from 1.5 to 1.8 fixed.
170
//
171 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
172
// Addition  of new module eth_addrcheck.v
173
//
174
// Revision 1.7  2002/02/12 17:03:47  mohor
175
// RxOverRun added to statuses.
176
//
177
// Revision 1.6  2002/02/11 09:18:22  mohor
178
// Tx status is written back to the BD.
179
//
180 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
181
// Rx status is written back to the BD.
182
//
183 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
184
// non-DMA host interface added. Select the right configutation in eth_defines.
185
//
186 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
187
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
188
// MHz. Statuses, overrun, control frame transmission and reception still  need
189
// to be fixed.
190
//
191 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
192
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
193
// added.
194
//
195 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
196
// Initial version. Equals to eth_wishbonedma.v at this moment.
197 38 mohor
//
198
//
199
//
200
 
201
`include "eth_defines.v"
202
`include "timescale.v"
203
 
204
 
205
module eth_wishbone
206
   (
207
 
208
    // WISHBONE common
209 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
210 38 mohor
 
211
    // WISHBONE slave
212 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
213 40 mohor
    BDCs,
214 38 mohor
 
215 40 mohor
    Reset,
216
 
217 39 mohor
    // WISHBONE master
218
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
219
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
220
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
221
 
222 219 mohor
`ifdef ETH_WISHBONE_B3
223
    m_wb_cti_o, m_wb_bte_o,
224
`endif
225
 
226 38 mohor
    //TX
227 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
228 150 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
229 38 mohor
    PerPacketPad,
230
 
231
    //RX
232 40 mohor
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
233 38 mohor
 
234
    // Register
235 150 mohor
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr,
236 38 mohor
 
237
    // Interrupts
238 150 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
239 42 mohor
 
240 60 mohor
    // Rx Status
241 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
242 250 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
243 60 mohor
 
244
    // Tx Status
245 164 mohor
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
246
 
247 210 mohor
    // Bist
248
`ifdef ETH_BIST
249 227 tadejm
    ,
250
    // debug chain signals
251
    scanb_rst,      // bist scan reset
252
    scanb_clk,      // bist scan clock
253
    scanb_si,       // bist scan serial in
254
    scanb_so,       // bist scan serial out
255
    scanb_en        // bist scan shift enable
256 210 mohor
`endif
257
 
258
 
259
 
260 38 mohor
                );
261
 
262
 
263
parameter Tp = 1;
264
 
265 150 mohor
 
266 38 mohor
// WISHBONE common
267
input           WB_CLK_I;       // WISHBONE clock
268
input  [31:0]   WB_DAT_I;       // WISHBONE data input
269
output [31:0]   WB_DAT_O;       // WISHBONE data output
270
 
271
// WISHBONE slave
272
input   [9:2]   WB_ADR_I;       // WISHBONE address input
273
input           WB_WE_I;        // WISHBONE write enable input
274
input           BDCs;           // Buffer descriptors are selected
275
output          WB_ACK_O;       // WISHBONE acknowledge output
276
 
277 39 mohor
// WISHBONE master
278
output  [31:0]  m_wb_adr_o;     // 
279
output   [3:0]  m_wb_sel_o;     // 
280
output          m_wb_we_o;      // 
281
output  [31:0]  m_wb_dat_o;     // 
282
output          m_wb_cyc_o;     // 
283
output          m_wb_stb_o;     // 
284
input   [31:0]  m_wb_dat_i;     // 
285
input           m_wb_ack_i;     // 
286
input           m_wb_err_i;     // 
287
 
288 219 mohor
`ifdef ETH_WISHBONE_B3
289
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
290
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
291
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
292
`endif
293
 
294 40 mohor
input           Reset;       // Reset signal
295 39 mohor
 
296 60 mohor
// Rx Status signals
297 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
298
input           LatchedCrcError;  // CRC error
299
input           RxLateCollision;  // Late collision occured while receiving frame
300
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
301
input           DribbleNibble;    // Extra nibble received
302
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
303
input    [15:0] RxLength;         // Length of the incoming frame
304
input           LoadRxStatus;     // Rx status was loaded
305 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
306 250 mohor
input           AddressMiss;      // When a packet is received AddressMiss status is written to the Rx BD
307 39 mohor
 
308 60 mohor
// Tx Status signals
309
input     [3:0] RetryCntLatched;  // Latched Retry Counter
310
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
311
input           LateCollLatched;  // Late collision occured
312
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
313
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
314
 
315 38 mohor
// Tx
316
input           MTxClk;         // Transmit clock (from PHY)
317
input           TxUsedData;     // Transmit packet used data
318
input           TxRetry;        // Transmit packet retry
319
input           TxAbort;        // Transmit packet abort
320
input           TxDone;         // Transmission ended
321
output          TxStartFrm;     // Transmit packet start frame
322
output          TxEndFrm;       // Transmit packet end frame
323
output  [7:0]   TxData;         // Transmit packet data byte
324
output          TxUnderRun;     // Transmit packet under-run
325
output          PerPacketCrcEn; // Per packet crc enable
326
output          PerPacketPad;   // Per packet pading
327
 
328
// Rx
329
input           MRxClk;         // Receive clock (from PHY)
330
input   [7:0]   RxData;         // Received data byte (from PHY)
331
input           RxValid;        // 
332
input           RxStartFrm;     // 
333
input           RxEndFrm;       // 
334 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
335 38 mohor
 
336
//Register
337
input           r_TxEn;         // Transmit enable
338
input           r_RxEn;         // Receive enable
339
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
340
input           TX_BD_NUM_Wr;   // RxBDNumber written
341
 
342
// Interrupts
343
output TxB_IRQ;
344
output TxE_IRQ;
345
output RxB_IRQ;
346 77 mohor
output RxE_IRQ;
347 38 mohor
output Busy_IRQ;
348
 
349 77 mohor
 
350 210 mohor
// Bist
351
`ifdef ETH_BIST
352 227 tadejm
input   scanb_rst;      // bist scan reset
353
input   scanb_clk;      // bist scan clock
354
input   scanb_si;       // bist scan serial in
355
output  scanb_so;       // bist scan serial out
356
input   scanb_en;       // bist scan shift enable
357 210 mohor
`endif
358
 
359 77 mohor
reg TxB_IRQ;
360
reg TxE_IRQ;
361
reg RxB_IRQ;
362
reg RxE_IRQ;
363
 
364 38 mohor
reg             TxStartFrm;
365
reg             TxEndFrm;
366
reg     [7:0]   TxData;
367
 
368
reg             TxUnderRun;
369 60 mohor
reg             TxUnderRun_wb;
370 38 mohor
 
371
reg             TxBDRead;
372 39 mohor
wire            TxStatusWrite;
373 38 mohor
 
374
reg     [1:0]   TxValidBytesLatched;
375
 
376
reg    [15:0]   TxLength;
377 60 mohor
reg    [15:0]   LatchedTxLength;
378
reg   [14:11]   TxStatus;
379 38 mohor
 
380 60 mohor
reg   [14:13]   RxStatus;
381 38 mohor
 
382
reg             TxStartFrm_wb;
383
reg             TxRetry_wb;
384 39 mohor
reg             TxAbort_wb;
385 38 mohor
reg             TxDone_wb;
386
 
387
reg             TxDone_wb_q;
388
reg             TxAbort_wb_q;
389 39 mohor
reg             TxRetry_wb_q;
390 219 mohor
reg             TxRetryPacket;
391 221 mohor
reg             TxRetryPacket_NotCleared;
392
reg             TxDonePacket;
393
reg             TxDonePacket_NotCleared;
394 219 mohor
reg             TxAbortPacket;
395 221 mohor
reg             TxAbortPacket_NotCleared;
396 38 mohor
reg             RxBDReady;
397 166 mohor
reg             RxReady;
398 38 mohor
reg             TxBDReady;
399
 
400
reg             RxBDRead;
401 40 mohor
wire            RxStatusWrite;
402 38 mohor
 
403
reg    [31:0]   TxDataLatched;
404
reg     [1:0]   TxByteCnt;
405
reg             LastWord;
406 39 mohor
reg             ReadTxDataFromFifo_tck;
407 38 mohor
 
408
reg             BlockingTxStatusWrite;
409
reg             BlockingTxBDRead;
410
 
411 40 mohor
reg             Flop;
412 38 mohor
 
413
reg     [7:0]   TxBDAddress;
414
reg     [7:0]   RxBDAddress;
415
 
416
reg             TxRetrySync1;
417
reg             TxAbortSync1;
418 39 mohor
reg             TxDoneSync1;
419 38 mohor
 
420
reg             TxAbort_q;
421
reg             TxRetry_q;
422
reg             TxUsedData_q;
423
 
424
reg    [31:0]   RxDataLatched2;
425 82 mohor
 
426
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
427
 
428 38 mohor
reg     [1:0]   RxValidBytes;
429
reg     [1:0]   RxByteCnt;
430
reg             LastByteIn;
431
reg             ShiftWillEnd;
432
 
433 40 mohor
reg             WriteRxDataToFifo;
434 42 mohor
reg    [15:0]   LatchedRxLength;
435 64 mohor
reg             RxAbortLatched;
436 38 mohor
 
437 40 mohor
reg             ShiftEnded;
438 60 mohor
reg             RxOverrun;
439 38 mohor
 
440 40 mohor
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
441
reg             BDRead;                     // BD Read access from WISHBONE side
442 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
443
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
444 38 mohor
 
445 39 mohor
reg             TxEndFrm_wb;
446 38 mohor
 
447 39 mohor
wire            TxRetryPulse;
448 38 mohor
wire            TxDonePulse;
449
wire            TxAbortPulse;
450
 
451
wire            StartRxBDRead;
452
 
453
wire            StartTxBDRead;
454
 
455
wire            TxIRQEn;
456
wire            WrapTxStatusBit;
457
 
458 77 mohor
wire            RxIRQEn;
459 38 mohor
wire            WrapRxStatusBit;
460
 
461
wire    [1:0]   TxValidBytes;
462
 
463
wire    [7:0]   TempTxBDAddress;
464
wire    [7:0]   TempRxBDAddress;
465
 
466
wire            SetGotData;
467
wire            GotDataEvaluate;
468
 
469 106 mohor
reg             WB_ACK_O;
470 38 mohor
 
471 250 mohor
wire    [7:0]   RxStatusIn;
472
reg     [7:0]   RxStatusInLatched;
473 42 mohor
 
474 39 mohor
reg WbEn, WbEn_q;
475
reg RxEn, RxEn_q;
476
reg TxEn, TxEn_q;
477 38 mohor
 
478 39 mohor
wire ram_ce;
479
wire ram_we;
480
wire ram_oe;
481
reg [7:0]   ram_addr;
482
reg [31:0]  ram_di;
483
wire [31:0] ram_do;
484 38 mohor
 
485 39 mohor
wire StartTxPointerRead;
486
reg  TxPointerRead;
487
reg TxEn_needed;
488 40 mohor
reg RxEn_needed;
489 38 mohor
 
490 40 mohor
wire StartRxPointerRead;
491
reg RxPointerRead;
492 38 mohor
 
493 219 mohor
`ifdef ETH_WISHBONE_B3
494
assign m_wb_bte_o = 2'b00;    // Linear burst
495
`endif
496 39 mohor
 
497 219 mohor
 
498 159 mohor
always @ (posedge WB_CLK_I)
499 40 mohor
begin
500 159 mohor
  WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
501 40 mohor
end
502 39 mohor
 
503 106 mohor
assign WB_DAT_O = ram_do;
504 39 mohor
 
505 41 mohor
// Generic synchronous single-port RAM interface
506 119 mohor
eth_spram_256x32 bd_ram (
507 226 tadejm
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
508 210 mohor
`ifdef ETH_BIST
509 227 tadejm
  ,
510
  .scanb_rst      (scanb_rst),
511
  .scanb_clk      (scanb_clk),
512
  .scanb_si       (scanb_si),
513
  .scanb_so       (scanb_so),
514
  .scanb_en       (scanb_en)
515 210 mohor
`endif
516 39 mohor
);
517 41 mohor
 
518 39 mohor
assign ram_ce = 1'b1;
519 40 mohor
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
520 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
521 39 mohor
 
522
 
523 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
524 38 mohor
begin
525 40 mohor
  if(Reset)
526 39 mohor
    TxEn_needed <=#Tp 1'b0;
527 38 mohor
  else
528 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
529 39 mohor
    TxEn_needed <=#Tp 1'b1;
530
  else
531
  if(TxPointerRead & TxEn & TxEn_q)
532
    TxEn_needed <=#Tp 1'b0;
533 38 mohor
end
534
 
535 39 mohor
// Enabling access to the RAM for three devices.
536 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
537 39 mohor
begin
538 40 mohor
  if(Reset)
539 39 mohor
    begin
540
      WbEn <=#Tp 1'b1;
541
      RxEn <=#Tp 1'b0;
542
      TxEn <=#Tp 1'b0;
543
      ram_addr <=#Tp 8'h0;
544
      ram_di <=#Tp 32'h0;
545 77 mohor
      BDRead <=#Tp 1'b0;
546
      BDWrite <=#Tp 1'b0;
547 39 mohor
    end
548
  else
549
    begin
550
      // Switching between three stages depends on enable signals
551 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
552
        5'b100_10, 5'b100_11 :
553 39 mohor
          begin
554
            WbEn <=#Tp 1'b0;
555
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
556
            TxEn <=#Tp 1'b0;
557 40 mohor
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
558 39 mohor
            ram_di <=#Tp RxBDDataIn;
559
          end
560
        5'b100_01 :
561
          begin
562
            WbEn <=#Tp 1'b0;
563
            RxEn <=#Tp 1'b0;
564
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
565
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
566
            ram_di <=#Tp TxBDDataIn;
567
          end
568 90 mohor
        5'b010_00, 5'b010_10 :
569 39 mohor
          begin
570
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
571
            RxEn <=#Tp 1'b0;
572
            TxEn <=#Tp 1'b0;
573
            ram_addr <=#Tp WB_ADR_I[9:2];
574
            ram_di <=#Tp WB_DAT_I;
575 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
576
            BDRead <=#Tp BDCs & ~WB_WE_I;
577 39 mohor
          end
578 90 mohor
        5'b010_01, 5'b010_11 :
579 39 mohor
          begin
580
            WbEn <=#Tp 1'b0;
581
            RxEn <=#Tp 1'b0;
582
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
583
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
584
            ram_di <=#Tp TxBDDataIn;
585
          end
586 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
587 39 mohor
          begin
588
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
589
            RxEn <=#Tp 1'b0;
590
            TxEn <=#Tp 1'b0;
591
            ram_addr <=#Tp WB_ADR_I[9:2];
592
            ram_di <=#Tp WB_DAT_I;
593 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
594
            BDRead <=#Tp BDCs & ~WB_WE_I;
595 39 mohor
          end
596
        5'b100_00 :
597
          begin
598
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
599
          end
600
        5'b000_00 :
601
          begin
602
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
603
            RxEn <=#Tp 1'b0;
604
            TxEn <=#Tp 1'b0;
605
            ram_addr <=#Tp WB_ADR_I[9:2];
606
            ram_di <=#Tp WB_DAT_I;
607 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
608
            BDRead <=#Tp BDCs & ~WB_WE_I;
609 39 mohor
          end
610
      endcase
611
    end
612
end
613
 
614
 
615
// Delayed stage signals
616 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
617 39 mohor
begin
618 40 mohor
  if(Reset)
619 39 mohor
    begin
620
      WbEn_q <=#Tp 1'b0;
621
      RxEn_q <=#Tp 1'b0;
622
      TxEn_q <=#Tp 1'b0;
623
    end
624
  else
625
    begin
626
      WbEn_q <=#Tp WbEn;
627
      RxEn_q <=#Tp RxEn;
628
      TxEn_q <=#Tp TxEn;
629
    end
630
end
631
 
632 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
633 40 mohor
always @ (posedge MTxClk or posedge Reset)
634 38 mohor
begin
635 40 mohor
  if(Reset)
636 38 mohor
    Flop <=#Tp 1'b0;
637
  else
638
  if(TxDone | TxAbort | TxRetry_q)
639
    Flop <=#Tp 1'b0;
640
  else
641
  if(TxUsedData)
642
    Flop <=#Tp ~Flop;
643
end
644
 
645 39 mohor
wire ResetTxBDReady;
646
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
647 38 mohor
 
648
// Latching READY status of the Tx buffer descriptor
649 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
650 38 mohor
begin
651 40 mohor
  if(Reset)
652 38 mohor
    TxBDReady <=#Tp 1'b0;
653
  else
654 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
655
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
656
  else                                                // Only packets larger then 4 bytes are transmitted.
657 39 mohor
  if(ResetTxBDReady)
658 38 mohor
    TxBDReady <=#Tp 1'b0;
659
end
660
 
661
 
662 39 mohor
// Reading the Tx buffer descriptor
663 221 mohor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
664 39 mohor
 
665 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
666 38 mohor
begin
667 40 mohor
  if(Reset)
668 39 mohor
    TxBDRead <=#Tp 1'b1;
669 38 mohor
  else
670 110 mohor
  if(StartTxBDRead)
671 39 mohor
    TxBDRead <=#Tp 1'b1;
672 38 mohor
  else
673 39 mohor
  if(TxBDReady)
674
    TxBDRead <=#Tp 1'b0;
675 38 mohor
end
676
 
677
 
678 39 mohor
// Reading Tx BD pointer
679
assign StartTxPointerRead = TxBDRead & TxBDReady;
680 38 mohor
 
681 39 mohor
// Reading Tx BD Pointer
682 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
683 38 mohor
begin
684 40 mohor
  if(Reset)
685 39 mohor
    TxPointerRead <=#Tp 1'b0;
686 38 mohor
  else
687 39 mohor
  if(StartTxPointerRead)
688
    TxPointerRead <=#Tp 1'b1;
689 38 mohor
  else
690 39 mohor
  if(TxEn_q)
691
    TxPointerRead <=#Tp 1'b0;
692 38 mohor
end
693
 
694
 
695 39 mohor
// Writing status back to the Tx buffer descriptor
696 221 mohor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
697 38 mohor
 
698
 
699
 
700 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
701 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
702 38 mohor
begin
703 40 mohor
  if(Reset)
704 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
705 38 mohor
  else
706 39 mohor
  if(TxStatusWrite)
707
    BlockingTxStatusWrite <=#Tp 1'b1;
708 38 mohor
  else
709 39 mohor
  if(~TxDone_wb & ~TxAbort_wb)
710
    BlockingTxStatusWrite <=#Tp 1'b0;
711 38 mohor
end
712
 
713
 
714 159 mohor
reg BlockingTxStatusWrite_sync1;
715
reg BlockingTxStatusWrite_sync2;
716
 
717
// Synchronizing BlockingTxStatusWrite to MTxClk
718
always @ (posedge MTxClk or posedge Reset)
719
begin
720
  if(Reset)
721
    BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
722
  else
723
    BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
724
end
725
 
726
// Synchronizing BlockingTxStatusWrite to MTxClk
727
always @ (posedge MTxClk or posedge Reset)
728
begin
729
  if(Reset)
730
    BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
731
  else
732
    BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
733
end
734
 
735
 
736 39 mohor
// TxBDRead state is activated only once. 
737 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
738 39 mohor
begin
739 40 mohor
  if(Reset)
740 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
741
  else
742 110 mohor
  if(StartTxBDRead)
743 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
744
  else
745 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
746 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
747
end
748 38 mohor
 
749
 
750 39 mohor
// Latching status from the tx buffer descriptor
751
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
752 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
753 38 mohor
begin
754 40 mohor
  if(Reset)
755 60 mohor
    TxStatus <=#Tp 4'h0;
756 38 mohor
  else
757 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
758 60 mohor
    TxStatus <=#Tp ram_do[14:11];
759 38 mohor
end
760
 
761 40 mohor
reg ReadTxDataFromMemory;
762
wire WriteRxDataToMemory;
763 38 mohor
 
764 39 mohor
reg MasterWbTX;
765
reg MasterWbRX;
766
 
767
reg [31:0] m_wb_adr_o;
768
reg        m_wb_cyc_o;
769
reg        m_wb_stb_o;
770 96 mohor
reg  [3:0] m_wb_sel_o;
771 39 mohor
reg        m_wb_we_o;
772 40 mohor
 
773 39 mohor
wire TxLengthEq0;
774
wire TxLengthLt4;
775
 
776 150 mohor
reg BlockingIncrementTxPointer;
777 159 mohor
reg [31:2] TxPointerMSB;
778
reg [1:0]  TxPointerLSB;
779
reg [1:0]  TxPointerLSB_rst;
780
reg [31:2] RxPointerMSB;
781
reg [1:0]  RxPointerLSB_rst;
782 39 mohor
 
783 150 mohor
wire RxBurstAcc;
784
wire RxWordAcc;
785
wire RxHalfAcc;
786
wire RxByteAcc;
787
 
788 39 mohor
//Latching length from the buffer descriptor;
789 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
790 38 mohor
begin
791 40 mohor
  if(Reset)
792 39 mohor
    TxLength <=#Tp 16'h0;
793 38 mohor
  else
794 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
795
    TxLength <=#Tp ram_do[31:16];
796 38 mohor
  else
797 39 mohor
  if(MasterWbTX & m_wb_ack_i)
798
    begin
799
      if(TxLengthLt4)
800
        TxLength <=#Tp 16'h0;
801 150 mohor
      else
802 159 mohor
      if(TxPointerLSB_rst==2'h0)
803 96 mohor
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
804 39 mohor
      else
805 159 mohor
      if(TxPointerLSB_rst==2'h1)
806 150 mohor
        TxLength <=#Tp TxLength - 3'h3;    // Length is subtracted at the data request
807
      else
808 159 mohor
      if(TxPointerLSB_rst==2'h2)
809 150 mohor
        TxLength <=#Tp TxLength - 3'h2;    // Length is subtracted at the data request
810
      else
811 159 mohor
      if(TxPointerLSB_rst==2'h3)
812 150 mohor
        TxLength <=#Tp TxLength - 3'h1;    // Length is subtracted at the data request
813 39 mohor
    end
814 38 mohor
end
815
 
816 96 mohor
 
817
 
818 60 mohor
//Latching length from the buffer descriptor;
819
always @ (posedge WB_CLK_I or posedge Reset)
820
begin
821
  if(Reset)
822
    LatchedTxLength <=#Tp 16'h0;
823
  else
824
  if(TxEn & TxEn_q & TxBDRead)
825
    LatchedTxLength <=#Tp ram_do[31:16];
826
end
827
 
828 39 mohor
assign TxLengthEq0 = TxLength == 0;
829
assign TxLengthLt4 = TxLength < 4;
830 38 mohor
 
831 150 mohor
reg cyc_cleared;
832
reg IncrTxPointer;
833 39 mohor
 
834
 
835 159 mohor
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
836
// because TxPointerMSB is only used for word-aligned accesses.
837 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
838 38 mohor
begin
839 40 mohor
  if(Reset)
840 159 mohor
    TxPointerMSB <=#Tp 30'h0;
841 38 mohor
  else
842 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
843 159 mohor
    TxPointerMSB <=#Tp ram_do[31:2];
844 38 mohor
  else
845 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
846 159 mohor
    TxPointerMSB <=#Tp TxPointerMSB + 1'b1;     // TxPointer is word-aligned
847 38 mohor
end
848
 
849 96 mohor
 
850 159 mohor
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
851
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
852
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
853
// set by this two bits.
854 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
855
begin
856
  if(Reset)
857 159 mohor
    TxPointerLSB[1:0] <=#Tp 0;
858 96 mohor
  else
859
  if(TxEn & TxEn_q & TxPointerRead)
860 159 mohor
    TxPointerLSB[1:0] <=#Tp ram_do[1:0];
861 96 mohor
end
862
 
863
 
864 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
865
// After the read access, TxLength needs to be decremented for the number of the valid
866
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
867
// valid so this two bits are reset to zero. 
868 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
869
begin
870
  if(Reset)
871 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
872 150 mohor
  else
873
  if(TxEn & TxEn_q & TxPointerRead)
874 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
875 150 mohor
  else
876
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
877 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
878 150 mohor
end
879 96 mohor
 
880 150 mohor
 
881 159 mohor
reg  [3:0] RxByteSel;
882 39 mohor
wire MasterAccessFinished;
883 38 mohor
 
884 39 mohor
 
885 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
886 38 mohor
begin
887 40 mohor
  if(Reset)
888 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
889 38 mohor
  else
890 39 mohor
  if(MasterAccessFinished)
891
    BlockingIncrementTxPointer <=#Tp 0;
892 38 mohor
  else
893 150 mohor
  if(IncrTxPointer)
894 39 mohor
    BlockingIncrementTxPointer <=#Tp 1'b1;
895 38 mohor
end
896
 
897
 
898 39 mohor
wire TxBufferAlmostFull;
899
wire TxBufferFull;
900
wire TxBufferEmpty;
901
wire TxBufferAlmostEmpty;
902 40 mohor
wire SetReadTxDataFromMemory;
903 39 mohor
 
904 40 mohor
reg BlockReadTxDataFromMemory;
905 39 mohor
 
906 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
907 39 mohor
 
908 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
909 38 mohor
begin
910 40 mohor
  if(Reset)
911
    ReadTxDataFromMemory <=#Tp 1'b0;
912 38 mohor
  else
913 219 mohor
  if(TxLengthEq0 | TxAbortPacket | TxRetryPacket)
914 40 mohor
    ReadTxDataFromMemory <=#Tp 1'b0;
915 39 mohor
  else
916 40 mohor
  if(SetReadTxDataFromMemory)
917
    ReadTxDataFromMemory <=#Tp 1'b1;
918 38 mohor
end
919
 
920 226 tadejm
reg tx_burst_en;
921
reg rx_burst_en;
922 221 mohor
reg BlockingLastReadOn_Abort_Retry;
923
 
924
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory & ~BlockingLastReadOn_Abort_Retry;
925 226 tadejm
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
926 221 mohor
 
927 39 mohor
wire [31:0] TxData_wb;
928
wire ReadTxDataFromFifo_wb;
929 38 mohor
 
930 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
931 38 mohor
begin
932 40 mohor
  if(Reset)
933
    BlockReadTxDataFromMemory <=#Tp 1'b0;
934 38 mohor
  else
935 221 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (!(TxAbortPacket | TxRetryPacket)))
936 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
937 219 mohor
  else
938 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
939 219 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b0;
940 39 mohor
end
941
 
942
 
943 221 mohor
always @ (posedge WB_CLK_I or posedge Reset)
944
begin
945
  if(Reset)
946
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
947
  else
948
  if(TxAbortPacket | TxRetryPacket)
949
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
950
  else
951
  if(((TxAbort_wb & !TxAbortPacket_NotCleared) | (TxRetry_wb & !TxRetryPacket_NotCleared)) & !TxBDReady)
952
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b1;
953
end
954 39 mohor
 
955 221 mohor
 
956
 
957
 
958 39 mohor
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
959 219 mohor
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
960
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
961 226 tadejm
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
962
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
963 159 mohor
 
964 226 tadejm
wire rx_burst;
965
wire enough_data_in_rxfifo_for_burst;
966
wire enough_data_in_rxfifo_for_burst_plus1;
967 229 mohor
 
968 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
969 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
970 39 mohor
begin
971 40 mohor
  if(Reset)
972 38 mohor
    begin
973 39 mohor
      MasterWbTX <=#Tp 1'b0;
974
      MasterWbRX <=#Tp 1'b0;
975
      m_wb_adr_o <=#Tp 32'h0;
976
      m_wb_cyc_o <=#Tp 1'b0;
977
      m_wb_stb_o <=#Tp 1'b0;
978
      m_wb_we_o  <=#Tp 1'b0;
979 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
980 110 mohor
      cyc_cleared<=#Tp 1'b0;
981 226 tadejm
      tx_burst_cnt<=#Tp 0;
982
      rx_burst_cnt<=#Tp 0;
983 150 mohor
      IncrTxPointer<=#Tp 1'b0;
984 226 tadejm
      tx_burst_en<=#Tp 1'b1;
985
      rx_burst_en<=#Tp 1'b0;
986
      `ifdef ETH_WISHBONE_B3
987
        m_wb_cti_o <=#Tp 3'b0;
988
      `endif
989 38 mohor
    end
990 39 mohor
  else
991
    begin
992
      // Switching between two stages depends on enable signals
993 229 mohor
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst})  // synopsys parallel_case
994 226 tadejm
        8'b00_10_00_10,             // Idle and MRB needed
995 229 mohor
        8'b10_1x_10_1x,             // MRB continues
996 226 tadejm
        8'b10_10_01_10,             // Clear (previously MR) and MRB needed
997 229 mohor
        8'b01_1x_01_1x :            // Clear (previously MW) and MRB needed
998 39 mohor
          begin
999 226 tadejm
            MasterWbTX <=#Tp 1'b1;  // tx burst
1000
            MasterWbRX <=#Tp 1'b0;
1001
            m_wb_cyc_o <=#Tp 1'b1;
1002
            m_wb_stb_o <=#Tp 1'b1;
1003
            m_wb_we_o  <=#Tp 1'b0;
1004
            m_wb_sel_o <=#Tp 4'hf;
1005
            cyc_cleared<=#Tp 1'b0;
1006
            IncrTxPointer<=#Tp 1'b1;
1007
            tx_burst_cnt <=#Tp tx_burst_cnt+1;
1008
            if(tx_burst_cnt==0)
1009
              m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1010
            else
1011
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1012
 
1013
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1014
              begin
1015
                tx_burst_en<=#Tp 1'b0;
1016
              `ifdef ETH_WISHBONE_B3
1017
                m_wb_cti_o <=#Tp 3'b111;
1018
              `endif
1019
              end
1020
            else
1021
              begin
1022
              `ifdef ETH_WISHBONE_B3
1023
                m_wb_cti_o <=#Tp 3'b010;
1024
              `endif
1025
              end
1026
          end
1027 229 mohor
        8'b00_x1_00_x1,             // Idle and MWB needed
1028
        8'b01_x1_10_x1,             // MWB continues
1029 226 tadejm
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1030 229 mohor
        8'b10_x1_01_x1 :            // Clear (previously MR) and MWB needed
1031 226 tadejm
          begin
1032
            MasterWbTX <=#Tp 1'b0;  // rx burst
1033 39 mohor
            MasterWbRX <=#Tp 1'b1;
1034 226 tadejm
            m_wb_cyc_o <=#Tp 1'b1;
1035
            m_wb_stb_o <=#Tp 1'b1;
1036
            m_wb_we_o  <=#Tp 1'b1;
1037
            m_wb_sel_o <=#Tp RxByteSel;
1038
            IncrTxPointer<=#Tp 1'b0;
1039
            cyc_cleared<=#Tp 1'b0;
1040
            rx_burst_cnt <=#Tp rx_burst_cnt+1;
1041
 
1042
            if(rx_burst_cnt==0)
1043
              m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1044
            else
1045
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1046
 
1047
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1048
              begin
1049
                rx_burst_en<=#Tp 1'b0;
1050
              `ifdef ETH_WISHBONE_B3
1051
                m_wb_cti_o <=#Tp 3'b111;
1052
              `endif
1053
              end
1054
            else
1055
              begin
1056
              `ifdef ETH_WISHBONE_B3
1057
                m_wb_cti_o <=#Tp 3'b010;
1058
              `endif
1059
              end
1060
          end
1061 229 mohor
        8'b00_x1_00_x0 :            // idle and MW is needed (data write to rx buffer)
1062 226 tadejm
          begin
1063
            MasterWbTX <=#Tp 1'b0;
1064
            MasterWbRX <=#Tp 1'b1;
1065 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1066 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1067
            m_wb_stb_o <=#Tp 1'b1;
1068
            m_wb_we_o  <=#Tp 1'b1;
1069 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1070 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1071 39 mohor
          end
1072 226 tadejm
        8'b00_10_00_00 :            // idle and MR is needed (data read from tx buffer)
1073 39 mohor
          begin
1074 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1075 39 mohor
            MasterWbRX <=#Tp 1'b0;
1076 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1077 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1078
            m_wb_stb_o <=#Tp 1'b1;
1079
            m_wb_we_o  <=#Tp 1'b0;
1080 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1081
            IncrTxPointer<=#Tp 1'b1;
1082 39 mohor
          end
1083 226 tadejm
        8'b10_10_01_00,             // MR and MR is needed (data read from tx buffer)
1084 229 mohor
        8'b01_1x_01_0x  :           // MW and MR is needed (data read from tx buffer)
1085 39 mohor
          begin
1086 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1087 39 mohor
            MasterWbRX <=#Tp 1'b0;
1088 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1089 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1090
            m_wb_stb_o <=#Tp 1'b1;
1091
            m_wb_we_o  <=#Tp 1'b0;
1092 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1093 110 mohor
            cyc_cleared<=#Tp 1'b0;
1094 150 mohor
            IncrTxPointer<=#Tp 1'b1;
1095 39 mohor
          end
1096 226 tadejm
        8'b01_01_01_00,             // MW and MW needed (data write to rx buffer)
1097 229 mohor
        8'b10_x1_01_x0  :           // MR and MW is needed (data write to rx buffer)
1098 39 mohor
          begin
1099 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1100 39 mohor
            MasterWbRX <=#Tp 1'b1;
1101 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1102 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1103
            m_wb_stb_o <=#Tp 1'b1;
1104 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
1105 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1106 110 mohor
            cyc_cleared<=#Tp 1'b0;
1107 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1108 39 mohor
          end
1109 226 tadejm
        8'b01_01_10_00,             // MW and MW needed (cycle is cleared between previous and next access)
1110 229 mohor
        8'b01_1x_10_x0,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1111 226 tadejm
        8'b10_10_10_00,             // MR and MR needed (cycle is cleared between previous and next access)
1112 229 mohor
        8'b10_x1_10_0x :            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1113 39 mohor
          begin
1114 110 mohor
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
1115
            m_wb_stb_o <=#Tp 1'b0;
1116
            cyc_cleared<=#Tp 1'b1;
1117 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1118 226 tadejm
            tx_burst_cnt<=#Tp 0;
1119
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1120
            rx_burst_cnt<=#Tp 0;
1121
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1122
            `ifdef ETH_WISHBONE_B3
1123
              m_wb_cti_o <=#Tp 3'b0;
1124
            `endif
1125 110 mohor
          end
1126 229 mohor
        8'bxx_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1127
        8'bxx_00_01_00 :            // Between cyc_cleared request was cleared
1128 110 mohor
          begin
1129 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1130 39 mohor
            MasterWbRX <=#Tp 1'b0;
1131
            m_wb_cyc_o <=#Tp 1'b0;
1132
            m_wb_stb_o <=#Tp 1'b0;
1133 226 tadejm
            cyc_cleared<=#Tp 1'b0;
1134 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1135 226 tadejm
            rx_burst_cnt<=#Tp 0;
1136
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1137
            `ifdef ETH_WISHBONE_B3
1138
              m_wb_cti_o <=#Tp 3'b0;
1139
            `endif
1140 39 mohor
          end
1141 226 tadejm
        8'b00_00_00_00:             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1142 127 mohor
          begin
1143 226 tadejm
            tx_burst_cnt<=#Tp 0;
1144
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1145 127 mohor
          end
1146 226 tadejm
        default:                    // Don't touch
1147 82 mohor
          begin
1148
            MasterWbTX <=#Tp MasterWbTX;
1149
            MasterWbRX <=#Tp MasterWbRX;
1150
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
1151
            m_wb_stb_o <=#Tp m_wb_stb_o;
1152 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
1153 150 mohor
            IncrTxPointer<=#Tp IncrTxPointer;
1154 82 mohor
          end
1155 39 mohor
      endcase
1156
    end
1157 38 mohor
end
1158
 
1159 110 mohor
 
1160 39 mohor
wire TxFifoClear;
1161 96 mohor
 
1162 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1163 38 mohor
 
1164 219 mohor
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
1165 150 mohor
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
1166 96 mohor
          .clk(WB_CLK_I),                                   .reset(Reset),
1167 226 tadejm
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1168 96 mohor
          .clear(TxFifoClear),                              .full(TxBufferFull),
1169
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
1170 150 mohor
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
1171 96 mohor
        );
1172 39 mohor
 
1173
 
1174
reg StartOccured;
1175
reg TxStartFrm_sync1;
1176
reg TxStartFrm_sync2;
1177
reg TxStartFrm_syncb1;
1178
reg TxStartFrm_syncb2;
1179
 
1180
 
1181
 
1182
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1183 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1184 38 mohor
begin
1185 40 mohor
  if(Reset)
1186 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
1187 38 mohor
  else
1188 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1189
    TxStartFrm_wb <=#Tp 1'b1;
1190 38 mohor
  else
1191 39 mohor
  if(TxStartFrm_syncb2)
1192
    TxStartFrm_wb <=#Tp 1'b0;
1193 38 mohor
end
1194
 
1195 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1196 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1197 38 mohor
begin
1198 40 mohor
  if(Reset)
1199 39 mohor
    StartOccured <=#Tp 1'b0;
1200 38 mohor
  else
1201 39 mohor
  if(TxStartFrm_wb)
1202
    StartOccured <=#Tp 1'b1;
1203 38 mohor
  else
1204 39 mohor
  if(ResetTxBDReady)
1205
    StartOccured <=#Tp 1'b0;
1206 38 mohor
end
1207
 
1208 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1209 40 mohor
always @ (posedge MTxClk or posedge Reset)
1210 39 mohor
begin
1211 40 mohor
  if(Reset)
1212 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1213
  else
1214
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1215
end
1216 38 mohor
 
1217 40 mohor
always @ (posedge MTxClk or posedge Reset)
1218 39 mohor
begin
1219 40 mohor
  if(Reset)
1220 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1221
  else
1222
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1223
end
1224
 
1225 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1226 38 mohor
begin
1227 40 mohor
  if(Reset)
1228 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1229 38 mohor
  else
1230 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1231 38 mohor
end
1232
 
1233 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1234 38 mohor
begin
1235 40 mohor
  if(Reset)
1236 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1237 38 mohor
  else
1238 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1239
end
1240
 
1241 40 mohor
always @ (posedge MTxClk or posedge Reset)
1242 39 mohor
begin
1243 40 mohor
  if(Reset)
1244 39 mohor
    TxStartFrm <=#Tp 1'b0;
1245 38 mohor
  else
1246 39 mohor
  if(TxStartFrm_sync2)
1247 61 mohor
    TxStartFrm <=#Tp 1'b1;
1248 39 mohor
  else
1249 61 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry | TxAbort))
1250 39 mohor
    TxStartFrm <=#Tp 1'b0;
1251 38 mohor
end
1252 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1253 38 mohor
 
1254
 
1255 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1256 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1257 38 mohor
begin
1258 40 mohor
  if(Reset)
1259 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1260 38 mohor
  else
1261 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1262 39 mohor
    TxEndFrm_wb <=#Tp 1'b1;
1263 38 mohor
  else
1264 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1265
    TxEndFrm_wb <=#Tp 1'b0;
1266 38 mohor
end
1267
 
1268
 
1269
// Marks which bytes are valid within the word.
1270 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1271 38 mohor
 
1272 39 mohor
reg LatchValidBytes;
1273
reg LatchValidBytes_q;
1274 38 mohor
 
1275 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1276 38 mohor
begin
1277 40 mohor
  if(Reset)
1278 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1279 38 mohor
  else
1280 39 mohor
  if(TxLengthLt4 & TxBDReady)
1281
    LatchValidBytes <=#Tp 1'b1;
1282 38 mohor
  else
1283 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1284 38 mohor
end
1285
 
1286 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1287 38 mohor
begin
1288 40 mohor
  if(Reset)
1289 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1290 38 mohor
  else
1291 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1292 38 mohor
end
1293
 
1294
 
1295 39 mohor
// Latching valid bytes
1296 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1297 38 mohor
begin
1298 40 mohor
  if(Reset)
1299 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1300 38 mohor
  else
1301 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1302
    TxValidBytesLatched <=#Tp TxValidBytes;
1303
  else
1304
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1305
    TxValidBytesLatched <=#Tp 2'h0;
1306 38 mohor
end
1307
 
1308
 
1309
assign TxIRQEn          = TxStatus[14];
1310 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1311
assign PerPacketPad     = TxStatus[12];
1312
assign PerPacketCrcEn   = TxStatus[11];
1313 38 mohor
 
1314
 
1315 77 mohor
assign RxIRQEn         = RxStatus[14];
1316 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1317 38 mohor
 
1318
 
1319
// Temporary Tx and Rx buffer descriptor address 
1320 39 mohor
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
1321 134 mohor
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1)     | // Using first Rx BD
1322 39 mohor
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
1323 38 mohor
 
1324
 
1325
// Latching Tx buffer descriptor address
1326 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1327 38 mohor
begin
1328 40 mohor
  if(Reset)
1329 38 mohor
    TxBDAddress <=#Tp 8'h0;
1330
  else
1331
  if(TxStatusWrite)
1332
    TxBDAddress <=#Tp TempTxBDAddress;
1333
end
1334
 
1335
 
1336
// Latching Rx buffer descriptor address
1337 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1338 38 mohor
begin
1339 40 mohor
  if(Reset)
1340 134 mohor
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1;
1341 38 mohor
  else
1342 77 mohor
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
1343 134 mohor
    RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
1344 38 mohor
  else
1345
  if(RxStatusWrite)
1346
    RxBDAddress <=#Tp TempRxBDAddress;
1347
end
1348
 
1349 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1350 38 mohor
 
1351 250 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 5'h0, RxStatusInLatched};
1352 60 mohor
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1353 38 mohor
 
1354 60 mohor
 
1355 38 mohor
// Signals used for various purposes
1356 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1357 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1358
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1359
 
1360
 
1361
 
1362 39 mohor
// Generating delayed signals
1363 40 mohor
always @ (posedge MTxClk or posedge Reset)
1364 38 mohor
begin
1365 40 mohor
  if(Reset)
1366 39 mohor
    begin
1367
      TxAbort_q      <=#Tp 1'b0;
1368
      TxRetry_q      <=#Tp 1'b0;
1369
      TxUsedData_q   <=#Tp 1'b0;
1370
    end
1371 38 mohor
  else
1372 39 mohor
    begin
1373
      TxAbort_q      <=#Tp TxAbort;
1374
      TxRetry_q      <=#Tp TxRetry;
1375
      TxUsedData_q   <=#Tp TxUsedData;
1376
    end
1377 38 mohor
end
1378
 
1379
// Generating delayed signals
1380 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1381 38 mohor
begin
1382 40 mohor
  if(Reset)
1383 38 mohor
    begin
1384 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1385
      TxAbort_wb_q  <=#Tp 1'b0;
1386 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1387 38 mohor
    end
1388
  else
1389
    begin
1390 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1391
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1392 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1393 38 mohor
    end
1394
end
1395
 
1396
 
1397 219 mohor
reg TxAbortPacketBlocked;
1398
always @ (posedge WB_CLK_I or posedge Reset)
1399
begin
1400
  if(Reset)
1401
    TxAbortPacket <=#Tp 1'b0;
1402
  else
1403 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxAbortPacketBlocked |
1404
     TxAbort_wb & !MasterWbTX & !TxAbortPacketBlocked)
1405 219 mohor
    TxAbortPacket <=#Tp 1'b1;
1406
  else
1407
    TxAbortPacket <=#Tp 1'b0;
1408
end
1409
 
1410
 
1411
always @ (posedge WB_CLK_I or posedge Reset)
1412
begin
1413
  if(Reset)
1414 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1415
  else
1416 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1417
     TxAbort_wb & !MasterWbTX)
1418 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b1;
1419
  else
1420
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1421
end
1422
 
1423
 
1424
always @ (posedge WB_CLK_I or posedge Reset)
1425
begin
1426
  if(Reset)
1427 219 mohor
    TxAbortPacketBlocked <=#Tp 1'b0;
1428
  else
1429
  if(TxAbortPacket)
1430
    TxAbortPacketBlocked <=#Tp 1'b1;
1431
  else
1432
  if(!TxAbort_wb & TxAbort_wb_q)
1433
    TxAbortPacketBlocked <=#Tp 1'b0;
1434
end
1435
 
1436
 
1437
reg TxRetryPacketBlocked;
1438
always @ (posedge WB_CLK_I or posedge Reset)
1439
begin
1440
  if(Reset)
1441
    TxRetryPacket <=#Tp 1'b0;
1442
  else
1443 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1444
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1445 219 mohor
    TxRetryPacket <=#Tp 1'b1;
1446
  else
1447
    TxRetryPacket <=#Tp 1'b0;
1448
end
1449
 
1450
 
1451
always @ (posedge WB_CLK_I or posedge Reset)
1452
begin
1453
  if(Reset)
1454 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1455
  else
1456 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1457
     TxRetry_wb & !MasterWbTX)
1458 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b1;
1459
  else
1460
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1461
end
1462
 
1463
 
1464
always @ (posedge WB_CLK_I or posedge Reset)
1465
begin
1466
  if(Reset)
1467 219 mohor
    TxRetryPacketBlocked <=#Tp 1'b0;
1468
  else
1469
  if(TxRetryPacket)
1470
    TxRetryPacketBlocked <=#Tp 1'b1;
1471
  else
1472
  if(!TxRetry_wb & TxRetry_wb_q)
1473
    TxRetryPacketBlocked <=#Tp 1'b0;
1474
end
1475
 
1476
 
1477 221 mohor
reg TxDonePacketBlocked;
1478
always @ (posedge WB_CLK_I or posedge Reset)
1479
begin
1480
  if(Reset)
1481
    TxDonePacket <=#Tp 1'b0;
1482
  else
1483 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
1484
     TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1485 221 mohor
    TxDonePacket <=#Tp 1'b1;
1486
  else
1487
    TxDonePacket <=#Tp 1'b0;
1488
end
1489
 
1490
 
1491
always @ (posedge WB_CLK_I or posedge Reset)
1492
begin
1493
  if(Reset)
1494
    TxDonePacket_NotCleared <=#Tp 1'b0;
1495
  else
1496 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1497
     TxDone_wb & !MasterWbTX)
1498 221 mohor
    TxDonePacket_NotCleared <=#Tp 1'b1;
1499
  else
1500
    TxDonePacket_NotCleared <=#Tp 1'b0;
1501
end
1502
 
1503
 
1504
always @ (posedge WB_CLK_I or posedge Reset)
1505
begin
1506
  if(Reset)
1507
    TxDonePacketBlocked <=#Tp 1'b0;
1508
  else
1509
  if(TxDonePacket)
1510
    TxDonePacketBlocked <=#Tp 1'b1;
1511
  else
1512
  if(!TxDone_wb & TxDone_wb_q)
1513
    TxDonePacketBlocked <=#Tp 1'b0;
1514
end
1515
 
1516
 
1517 38 mohor
// Sinchronizing and evaluating tx data
1518 39 mohor
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
1519 219 mohor
assign SetGotData = (TxStartFrm_wb);
1520 38 mohor
 
1521
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
1522 40 mohor
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1523
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1524 38 mohor
 
1525
 
1526
// Indication of the last word
1527 40 mohor
always @ (posedge MTxClk or posedge Reset)
1528 38 mohor
begin
1529 40 mohor
  if(Reset)
1530 38 mohor
    LastWord <=#Tp 1'b0;
1531
  else
1532
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1533
    LastWord <=#Tp 1'b0;
1534
  else
1535
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1536 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1537 38 mohor
end
1538
 
1539
 
1540
// Tx end frame generation
1541 40 mohor
always @ (posedge MTxClk or posedge Reset)
1542 38 mohor
begin
1543 40 mohor
  if(Reset)
1544 38 mohor
    TxEndFrm <=#Tp 1'b0;
1545
  else
1546 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1547 38 mohor
    TxEndFrm <=#Tp 1'b0;
1548
  else
1549
  if(Flop & LastWord)
1550
    begin
1551 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1552 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1553
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1554
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1555
 
1556
        default : TxEndFrm <=#Tp 1'b0;
1557
      endcase
1558
    end
1559
end
1560
 
1561
 
1562
// Tx data selection (latching)
1563 40 mohor
always @ (posedge MTxClk or posedge Reset)
1564 38 mohor
begin
1565 40 mohor
  if(Reset)
1566 96 mohor
    TxData <=#Tp 0;
1567 38 mohor
  else
1568 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1569 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1570 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1571
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1572
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1573
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1574
    endcase
1575 38 mohor
  else
1576 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1577 96 mohor
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1578
  else
1579 38 mohor
  if(TxUsedData & Flop)
1580
    begin
1581 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1582 226 tadejm
 
1583 82 mohor
        1 : TxData <=#Tp TxDataLatched[23:16];
1584
        2 : TxData <=#Tp TxDataLatched[15:8];
1585
        3 : TxData <=#Tp TxDataLatched[7:0];
1586 38 mohor
      endcase
1587
    end
1588
end
1589
 
1590
 
1591
// Latching tx data
1592 40 mohor
always @ (posedge MTxClk or posedge Reset)
1593 38 mohor
begin
1594 40 mohor
  if(Reset)
1595 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1596
  else
1597 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1598 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1599 38 mohor
end
1600
 
1601
 
1602
// Tx under run
1603 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1604 38 mohor
begin
1605 40 mohor
  if(Reset)
1606 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1607 38 mohor
  else
1608 39 mohor
  if(TxAbortPulse)
1609 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1610
  else
1611
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1612
    TxUnderRun_wb <=#Tp 1'b1;
1613
end
1614
 
1615
 
1616 159 mohor
reg TxUnderRun_sync1;
1617
 
1618 60 mohor
// Tx under run
1619
always @ (posedge MTxClk or posedge Reset)
1620
begin
1621
  if(Reset)
1622 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b0;
1623 43 mohor
  else
1624 60 mohor
  if(TxUnderRun_wb)
1625 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b1;
1626 60 mohor
  else
1627 159 mohor
  if(BlockingTxStatusWrite_sync2)
1628
    TxUnderRun_sync1 <=#Tp 1'b0;
1629
end
1630
 
1631
// Tx under run
1632
always @ (posedge MTxClk or posedge Reset)
1633
begin
1634
  if(Reset)
1635 60 mohor
    TxUnderRun <=#Tp 1'b0;
1636 159 mohor
  else
1637
  if(BlockingTxStatusWrite_sync2)
1638
    TxUnderRun <=#Tp 1'b0;
1639
  else
1640
  if(TxUnderRun_sync1)
1641
    TxUnderRun <=#Tp 1'b1;
1642 38 mohor
end
1643
 
1644
 
1645
// Tx Byte counter
1646 40 mohor
always @ (posedge MTxClk or posedge Reset)
1647 38 mohor
begin
1648 40 mohor
  if(Reset)
1649 38 mohor
    TxByteCnt <=#Tp 2'h0;
1650
  else
1651
  if(TxAbort_q | TxRetry_q)
1652
    TxByteCnt <=#Tp 2'h0;
1653
  else
1654
  if(TxStartFrm & ~TxUsedData)
1655 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1656 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1657
      2'h1 : TxByteCnt <=#Tp 2'h2;
1658
      2'h2 : TxByteCnt <=#Tp 2'h3;
1659
      2'h3 : TxByteCnt <=#Tp 2'h0;
1660
    endcase
1661 38 mohor
  else
1662
  if(TxUsedData & Flop)
1663 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1664 38 mohor
end
1665
 
1666 39 mohor
 
1667 150 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1668
reg ReadTxDataFromFifo_sync1;
1669
reg ReadTxDataFromFifo_sync2;
1670
reg ReadTxDataFromFifo_sync3;
1671
reg ReadTxDataFromFifo_syncb1;
1672
reg ReadTxDataFromFifo_syncb2;
1673
reg ReadTxDataFromFifo_syncb3;
1674
 
1675
 
1676
always @ (posedge MTxClk or posedge Reset)
1677
begin
1678
  if(Reset)
1679
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1680
  else
1681 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1682 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1683 150 mohor
  else
1684
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1685
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1686 38 mohor
end
1687
 
1688 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1689 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1690 38 mohor
begin
1691 40 mohor
  if(Reset)
1692 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1693 38 mohor
  else
1694 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1695
end
1696 38 mohor
 
1697 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1698 38 mohor
begin
1699 40 mohor
  if(Reset)
1700 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1701 38 mohor
  else
1702 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1703 38 mohor
end
1704
 
1705 40 mohor
always @ (posedge MTxClk or posedge Reset)
1706 38 mohor
begin
1707 40 mohor
  if(Reset)
1708 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1709 38 mohor
  else
1710 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1711 38 mohor
end
1712
 
1713 40 mohor
always @ (posedge MTxClk or posedge Reset)
1714 38 mohor
begin
1715 40 mohor
  if(Reset)
1716 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1717 38 mohor
  else
1718 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1719 38 mohor
end
1720
 
1721 150 mohor
always @ (posedge MTxClk or posedge Reset)
1722
begin
1723
  if(Reset)
1724
    ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
1725
  else
1726
    ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
1727
end
1728
 
1729 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1730 38 mohor
begin
1731 40 mohor
  if(Reset)
1732 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1733 38 mohor
  else
1734 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1735 38 mohor
end
1736
 
1737 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1738
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1739 38 mohor
 
1740
 
1741 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1742 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1743 38 mohor
begin
1744 40 mohor
  if(Reset)
1745 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1746 38 mohor
  else
1747 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1748 38 mohor
end
1749
 
1750 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1751 38 mohor
begin
1752 40 mohor
  if(Reset)
1753 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1754 38 mohor
  else
1755 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1756 38 mohor
end
1757
 
1758
 
1759 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1760 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1761 38 mohor
begin
1762 40 mohor
  if(Reset)
1763 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1764 38 mohor
  else
1765 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1766 38 mohor
end
1767
 
1768 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1769 38 mohor
begin
1770 40 mohor
  if(Reset)
1771 39 mohor
    TxDone_wb <=#Tp 1'b0;
1772 38 mohor
  else
1773 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1774 38 mohor
end
1775
 
1776 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1777 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1778 38 mohor
begin
1779 40 mohor
  if(Reset)
1780 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1781 38 mohor
  else
1782 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1783 38 mohor
end
1784
 
1785 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1786 38 mohor
begin
1787 40 mohor
  if(Reset)
1788 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1789
  else
1790 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1791 38 mohor
end
1792
 
1793
 
1794 150 mohor
reg RxAbortSync1;
1795
reg RxAbortSync2;
1796
reg RxAbortSync3;
1797
reg RxAbortSync4;
1798
reg RxAbortSyncb1;
1799
reg RxAbortSyncb2;
1800 39 mohor
 
1801 150 mohor
//assign StartRxBDRead = RxStatusWrite | RxAbortLatched;
1802
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
1803
 
1804 40 mohor
// Reading the Rx buffer descriptor
1805
always @ (posedge WB_CLK_I or posedge Reset)
1806
begin
1807
  if(Reset)
1808
    RxBDRead <=#Tp 1'b1;
1809
  else
1810 166 mohor
  if(StartRxBDRead & ~RxReady)
1811 40 mohor
    RxBDRead <=#Tp 1'b1;
1812
  else
1813
  if(RxBDReady)
1814
    RxBDRead <=#Tp 1'b0;
1815
end
1816 39 mohor
 
1817
 
1818 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1819
// written to the previous one.
1820
 
1821
// Latching READY status of the Rx buffer descriptor
1822 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1823 38 mohor
begin
1824 40 mohor
  if(Reset)
1825 38 mohor
    RxBDReady <=#Tp 1'b0;
1826
  else
1827 166 mohor
  if(RxPointerRead)
1828 150 mohor
    RxBDReady <=#Tp 1'b0;
1829
  else
1830 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1831
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1832 38 mohor
end
1833
 
1834 40 mohor
// Latching Rx buffer descriptor status
1835
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1836
always @ (posedge WB_CLK_I or posedge Reset)
1837 38 mohor
begin
1838 40 mohor
  if(Reset)
1839 60 mohor
    RxStatus <=#Tp 2'h0;
1840 38 mohor
  else
1841 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1842 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1843 38 mohor
end
1844
 
1845
 
1846 166 mohor
// RxReady generation
1847
always @ (posedge WB_CLK_I or posedge Reset)
1848
begin
1849
  if(Reset)
1850
    RxReady <=#Tp 1'b0;
1851
  else
1852
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
1853
    RxReady <=#Tp 1'b0;
1854
  else
1855
  if(RxEn & RxEn_q & RxPointerRead)
1856
    RxReady <=#Tp 1'b1;
1857
end
1858 38 mohor
 
1859
 
1860 40 mohor
// Reading Rx BD pointer
1861
 
1862
 
1863
assign StartRxPointerRead = RxBDRead & RxBDReady;
1864
 
1865
// Reading Tx BD Pointer
1866
always @ (posedge WB_CLK_I or posedge Reset)
1867 38 mohor
begin
1868 40 mohor
  if(Reset)
1869
    RxPointerRead <=#Tp 1'b0;
1870 38 mohor
  else
1871 40 mohor
  if(StartRxPointerRead)
1872
    RxPointerRead <=#Tp 1'b1;
1873 38 mohor
  else
1874 166 mohor
  if(RxEn & RxEn_q)
1875 40 mohor
    RxPointerRead <=#Tp 1'b0;
1876 38 mohor
end
1877
 
1878 113 mohor
 
1879 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1880
always @ (posedge WB_CLK_I or posedge Reset)
1881
begin
1882
  if(Reset)
1883 159 mohor
    RxPointerMSB <=#Tp 30'h0;
1884 40 mohor
  else
1885
  if(RxEn & RxEn_q & RxPointerRead)
1886 159 mohor
    RxPointerMSB <=#Tp ram_do[31:2];
1887 40 mohor
  else
1888 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1889 159 mohor
      RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1890 40 mohor
end
1891 38 mohor
 
1892
 
1893 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1894 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1895
begin
1896
  if(Reset)
1897 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp 0;
1898 96 mohor
  else
1899 159 mohor
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
1900
    RxPointerLSB_rst[1:0] <=#Tp 0;
1901 96 mohor
  else
1902
  if(RxEn & RxEn_q & RxPointerRead)
1903 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
1904 96 mohor
end
1905
 
1906
 
1907 159 mohor
always @ (RxPointerLSB_rst)
1908 96 mohor
begin
1909 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1910
    2'h0 : RxByteSel[3:0] = 4'hf;
1911
    2'h1 : RxByteSel[3:0] = 4'h7;
1912
    2'h2 : RxByteSel[3:0] = 4'h3;
1913
    2'h3 : RxByteSel[3:0] = 4'h1;
1914 96 mohor
  endcase
1915
end
1916
 
1917
 
1918
always @ (posedge WB_CLK_I or posedge Reset)
1919
begin
1920
  if(Reset)
1921 40 mohor
    RxEn_needed <=#Tp 1'b0;
1922 38 mohor
  else
1923 166 mohor
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1924 40 mohor
    RxEn_needed <=#Tp 1'b1;
1925 38 mohor
  else
1926 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1927
    RxEn_needed <=#Tp 1'b0;
1928 38 mohor
end
1929
 
1930
 
1931 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1932
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1933 38 mohor
 
1934 42 mohor
reg RxStatusWriteLatched;
1935
reg RxStatusWrite_rck;
1936
 
1937
always @ (posedge WB_CLK_I or posedge Reset)
1938
begin
1939
  if(Reset)
1940
    RxStatusWriteLatched <=#Tp 1'b0;
1941
  else
1942 87 mohor
  if(RxStatusWrite & ~RxStatusWrite_rck)
1943 42 mohor
    RxStatusWriteLatched <=#Tp 1'b1;
1944
  else
1945
  if(RxStatusWrite_rck)
1946
    RxStatusWriteLatched <=#Tp 1'b0;
1947
end
1948
 
1949
 
1950
always @ (posedge MRxClk or posedge Reset)
1951
begin
1952
  if(Reset)
1953
    RxStatusWrite_rck <=#Tp 1'b0;
1954
  else
1955 87 mohor
  if(RxStatusWriteLatched)
1956
    RxStatusWrite_rck <=#Tp 1'b1;
1957
  else
1958
    RxStatusWrite_rck <=#Tp 1'b0;
1959 42 mohor
end
1960
 
1961
 
1962 40 mohor
reg RxEnableWindow;
1963 38 mohor
 
1964
// Indicating that last byte is being reveived
1965 40 mohor
always @ (posedge MRxClk or posedge Reset)
1966 38 mohor
begin
1967 40 mohor
  if(Reset)
1968 38 mohor
    LastByteIn <=#Tp 1'b0;
1969
  else
1970 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1971 38 mohor
    LastByteIn <=#Tp 1'b0;
1972
  else
1973 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1974 38 mohor
    LastByteIn <=#Tp 1'b1;
1975
end
1976
 
1977 159 mohor
reg ShiftEnded_rck;
1978 40 mohor
reg ShiftEndedSync1;
1979
reg ShiftEndedSync2;
1980 118 mohor
reg ShiftEndedSync3;
1981
reg ShiftEndedSync_c1;
1982
reg ShiftEndedSync_c2;
1983
 
1984 40 mohor
wire StartShiftWillEnd;
1985 96 mohor
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1986 38 mohor
 
1987
// Indicating that data reception will end
1988 40 mohor
always @ (posedge MRxClk or posedge Reset)
1989 38 mohor
begin
1990 40 mohor
  if(Reset)
1991 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1992
  else
1993 159 mohor
  if(ShiftEnded_rck | RxAbort)
1994 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1995
  else
1996 40 mohor
  if(StartShiftWillEnd)
1997 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
1998
end
1999
 
2000
 
2001 40 mohor
 
2002 38 mohor
// Receive byte counter
2003 40 mohor
always @ (posedge MRxClk or posedge Reset)
2004 38 mohor
begin
2005 40 mohor
  if(Reset)
2006 38 mohor
    RxByteCnt <=#Tp 2'h0;
2007
  else
2008 159 mohor
  if(ShiftEnded_rck | RxAbort)
2009 38 mohor
    RxByteCnt <=#Tp 2'h0;
2010 97 lampret
  else
2011 166 mohor
  if(RxValid & RxStartFrm & RxReady)
2012 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2013 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
2014
      2'h1 : RxByteCnt <=#Tp 2'h2;
2015
      2'h2 : RxByteCnt <=#Tp 2'h3;
2016
      2'h3 : RxByteCnt <=#Tp 2'h0;
2017
    endcase
2018 38 mohor
  else
2019 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
2020 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
2021 38 mohor
end
2022
 
2023
 
2024
// Indicates how many bytes are valid within the last word
2025 40 mohor
always @ (posedge MRxClk or posedge Reset)
2026 38 mohor
begin
2027 40 mohor
  if(Reset)
2028 38 mohor
    RxValidBytes <=#Tp 2'h1;
2029
  else
2030 96 mohor
  if(RxValid & RxStartFrm)
2031 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2032 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
2033
      2'h1 : RxValidBytes <=#Tp 2'h2;
2034
      2'h2 : RxValidBytes <=#Tp 2'h3;
2035
      2'h3 : RxValidBytes <=#Tp 2'h0;
2036
    endcase
2037 38 mohor
  else
2038 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2039 38 mohor
    RxValidBytes <=#Tp RxValidBytes + 1;
2040
end
2041
 
2042
 
2043 40 mohor
always @ (posedge MRxClk or posedge Reset)
2044 38 mohor
begin
2045 40 mohor
  if(Reset)
2046
    RxDataLatched1       <=#Tp 24'h0;
2047 38 mohor
  else
2048 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2049 96 mohor
    if(RxStartFrm)
2050 40 mohor
    begin
2051 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2052 96 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2053
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2054
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2055
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2056
      endcase
2057
    end
2058
    else if (RxEnableWindow)
2059
    begin
2060 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2061 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2062
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2063
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2064 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2065
      endcase
2066
    end
2067 38 mohor
end
2068
 
2069 40 mohor
wire SetWriteRxDataToFifo;
2070 38 mohor
 
2071 40 mohor
// Assembling data that will be written to the rx_fifo
2072
always @ (posedge MRxClk or posedge Reset)
2073 38 mohor
begin
2074 40 mohor
  if(Reset)
2075
    RxDataLatched2 <=#Tp 32'h0;
2076 38 mohor
  else
2077 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2078 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
2079 38 mohor
  else
2080 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2081 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2082 82 mohor
 
2083
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2084
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
2085
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
2086 40 mohor
    endcase
2087 38 mohor
end
2088
 
2089
 
2090 40 mohor
reg WriteRxDataToFifoSync1;
2091
reg WriteRxDataToFifoSync2;
2092 150 mohor
reg WriteRxDataToFifoSync3;
2093 38 mohor
 
2094
 
2095 40 mohor
// Indicating start of the reception process
2096 166 mohor
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
2097
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
2098
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
2099 38 mohor
 
2100 150 mohor
always @ (posedge MRxClk or posedge Reset)
2101
begin
2102
  if(Reset)
2103
    WriteRxDataToFifo <=#Tp 1'b0;
2104
  else
2105
  if(SetWriteRxDataToFifo & ~RxAbort)
2106
    WriteRxDataToFifo <=#Tp 1'b1;
2107
  else
2108
  if(WriteRxDataToFifoSync2 | RxAbort)
2109
    WriteRxDataToFifo <=#Tp 1'b0;
2110
end
2111 40 mohor
 
2112 150 mohor
 
2113
 
2114
always @ (posedge WB_CLK_I or posedge Reset)
2115
begin
2116
  if(Reset)
2117
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2118
  else
2119
  if(WriteRxDataToFifo)
2120
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
2121
  else
2122
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2123
end
2124
 
2125
always @ (posedge WB_CLK_I or posedge Reset)
2126
begin
2127
  if(Reset)
2128
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
2129
  else
2130
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
2131
end
2132
 
2133
always @ (posedge WB_CLK_I or posedge Reset)
2134
begin
2135
  if(Reset)
2136
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
2137
  else
2138
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
2139
end
2140
 
2141
wire WriteRxDataToFifo_wb;
2142
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
2143
 
2144
 
2145 90 mohor
reg LatchedRxStartFrm;
2146
reg SyncRxStartFrm;
2147
reg SyncRxStartFrm_q;
2148 150 mohor
reg SyncRxStartFrm_q2;
2149 90 mohor
wire RxFifoReset;
2150 40 mohor
 
2151 90 mohor
always @ (posedge MRxClk or posedge Reset)
2152
begin
2153
  if(Reset)
2154
    LatchedRxStartFrm <=#Tp 0;
2155
  else
2156 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2157 90 mohor
    LatchedRxStartFrm <=#Tp 1;
2158
  else
2159 150 mohor
  if(SyncRxStartFrm_q)
2160 90 mohor
    LatchedRxStartFrm <=#Tp 0;
2161
end
2162
 
2163
 
2164
always @ (posedge WB_CLK_I or posedge Reset)
2165
begin
2166
  if(Reset)
2167
    SyncRxStartFrm <=#Tp 0;
2168
  else
2169
  if(LatchedRxStartFrm)
2170
    SyncRxStartFrm <=#Tp 1;
2171
  else
2172
    SyncRxStartFrm <=#Tp 0;
2173
end
2174
 
2175
 
2176
always @ (posedge WB_CLK_I or posedge Reset)
2177
begin
2178
  if(Reset)
2179
    SyncRxStartFrm_q <=#Tp 0;
2180
  else
2181
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
2182
end
2183
 
2184 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2185
begin
2186
  if(Reset)
2187
    SyncRxStartFrm_q2 <=#Tp 0;
2188
  else
2189
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
2190
end
2191 90 mohor
 
2192
 
2193 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2194 90 mohor
 
2195 150 mohor
 
2196 219 mohor
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
2197 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
2198
         .clk(WB_CLK_I),                                .reset(Reset),
2199 219 mohor
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
2200 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
2201 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
2202 150 mohor
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
2203 88 mohor
        );
2204 40 mohor
 
2205 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2206
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2207 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2208 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2209 40 mohor
 
2210
 
2211
// Generation of the end-of-frame signal
2212
always @ (posedge MRxClk or posedge Reset)
2213 38 mohor
begin
2214 40 mohor
  if(Reset)
2215 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2216 38 mohor
  else
2217 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2218 159 mohor
    ShiftEnded_rck <=#Tp 1'b1;
2219 38 mohor
  else
2220 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2221 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2222 38 mohor
end
2223
 
2224 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2225
begin
2226
  if(Reset)
2227
    ShiftEndedSync1 <=#Tp 1'b0;
2228
  else
2229 159 mohor
    ShiftEndedSync1 <=#Tp ShiftEnded_rck;
2230 40 mohor
end
2231 38 mohor
 
2232 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2233 38 mohor
begin
2234 40 mohor
  if(Reset)
2235
    ShiftEndedSync2 <=#Tp 1'b0;
2236 38 mohor
  else
2237 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
2238 40 mohor
end
2239 38 mohor
 
2240 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2241
begin
2242
  if(Reset)
2243
    ShiftEndedSync3 <=#Tp 1'b0;
2244
  else
2245
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2246
    ShiftEndedSync3 <=#Tp 1'b1;
2247
  else
2248
  if(ShiftEnded)
2249
    ShiftEndedSync3 <=#Tp 1'b0;
2250
end
2251 38 mohor
 
2252 40 mohor
// Generation of the end-of-frame signal
2253
always @ (posedge WB_CLK_I or posedge Reset)
2254 38 mohor
begin
2255 40 mohor
  if(Reset)
2256
    ShiftEnded <=#Tp 1'b0;
2257 38 mohor
  else
2258 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2259 40 mohor
    ShiftEnded <=#Tp 1'b1;
2260 38 mohor
  else
2261 40 mohor
  if(RxStatusWrite)
2262
    ShiftEnded <=#Tp 1'b0;
2263 38 mohor
end
2264
 
2265 118 mohor
always @ (posedge MRxClk or posedge Reset)
2266
begin
2267
  if(Reset)
2268
    ShiftEndedSync_c1 <=#Tp 1'b0;
2269
  else
2270
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
2271
end
2272 38 mohor
 
2273 118 mohor
always @ (posedge MRxClk or posedge Reset)
2274
begin
2275
  if(Reset)
2276
    ShiftEndedSync_c2 <=#Tp 1'b0;
2277
  else
2278
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
2279
end
2280
 
2281 40 mohor
// Generation of the end-of-frame signal
2282
always @ (posedge MRxClk or posedge Reset)
2283 38 mohor
begin
2284 40 mohor
  if(Reset)
2285
    RxEnableWindow <=#Tp 1'b0;
2286 38 mohor
  else
2287 40 mohor
  if(RxStartFrm)
2288
    RxEnableWindow <=#Tp 1'b1;
2289 38 mohor
  else
2290 40 mohor
  if(RxEndFrm | RxAbort)
2291
    RxEnableWindow <=#Tp 1'b0;
2292 38 mohor
end
2293
 
2294
 
2295 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2296 38 mohor
begin
2297 40 mohor
  if(Reset)
2298
    RxAbortSync1 <=#Tp 1'b0;
2299 38 mohor
  else
2300 150 mohor
    RxAbortSync1 <=#Tp RxAbortLatched;
2301 40 mohor
end
2302
 
2303
always @ (posedge WB_CLK_I or posedge Reset)
2304
begin
2305
  if(Reset)
2306
    RxAbortSync2 <=#Tp 1'b0;
2307 38 mohor
  else
2308 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
2309 38 mohor
end
2310
 
2311 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2312
begin
2313
  if(Reset)
2314
    RxAbortSync3 <=#Tp 1'b0;
2315
  else
2316
    RxAbortSync3 <=#Tp RxAbortSync2;
2317
end
2318
 
2319
always @ (posedge WB_CLK_I or posedge Reset)
2320
begin
2321
  if(Reset)
2322
    RxAbortSync4 <=#Tp 1'b0;
2323
  else
2324
    RxAbortSync4 <=#Tp RxAbortSync3;
2325
end
2326
 
2327 40 mohor
always @ (posedge MRxClk or posedge Reset)
2328
begin
2329
  if(Reset)
2330
    RxAbortSyncb1 <=#Tp 1'b0;
2331
  else
2332
    RxAbortSyncb1 <=#Tp RxAbortSync2;
2333
end
2334 38 mohor
 
2335 40 mohor
always @ (posedge MRxClk or posedge Reset)
2336 38 mohor
begin
2337 40 mohor
  if(Reset)
2338
    RxAbortSyncb2 <=#Tp 1'b0;
2339 38 mohor
  else
2340 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
2341 38 mohor
end
2342
 
2343
 
2344 64 mohor
always @ (posedge MRxClk or posedge Reset)
2345
begin
2346
  if(Reset)
2347
    RxAbortLatched <=#Tp 1'b0;
2348
  else
2349 150 mohor
  if(RxAbortSyncb2)
2350
    RxAbortLatched <=#Tp 1'b0;
2351
  else
2352 64 mohor
  if(RxAbort)
2353
    RxAbortLatched <=#Tp 1'b1;
2354
end
2355 40 mohor
 
2356 64 mohor
 
2357 42 mohor
always @ (posedge MRxClk or posedge Reset)
2358
begin
2359
  if(Reset)
2360
    LatchedRxLength[15:0] <=#Tp 16'h0;
2361
  else
2362 150 mohor
  if(LoadRxStatus)
2363 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
2364
end
2365
 
2366
 
2367 250 mohor
assign RxStatusIn = {AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2368 42 mohor
 
2369
always @ (posedge MRxClk or posedge Reset)
2370
begin
2371
  if(Reset)
2372
    RxStatusInLatched <=#Tp 'h0;
2373
  else
2374 150 mohor
  if(LoadRxStatus)
2375 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
2376
end
2377
 
2378
 
2379 60 mohor
// Rx overrun
2380
always @ (posedge WB_CLK_I or posedge Reset)
2381
begin
2382
  if(Reset)
2383
    RxOverrun <=#Tp 1'b0;
2384
  else
2385
  if(RxStatusWrite)
2386
    RxOverrun <=#Tp 1'b0;
2387
  else
2388
  if(RxBufferFull & WriteRxDataToFifo_wb)
2389
    RxOverrun <=#Tp 1'b1;
2390
end
2391 48 mohor
 
2392 77 mohor
 
2393
 
2394
wire TxError;
2395
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2396
 
2397
wire RxError;
2398
 
2399 239 tadejm
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
2400 250 mohor
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
2401
// AddressMiss is identifying that a frame was received because of the promiscous
2402
// mode and is not an error
2403 239 tadejm
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
2404
 
2405 77 mohor
// Tx Done Interrupt
2406
always @ (posedge WB_CLK_I or posedge Reset)
2407
begin
2408
  if(Reset)
2409
    TxB_IRQ <=#Tp 1'b0;
2410
  else
2411
  if(TxStatusWrite & TxIRQEn)
2412
    TxB_IRQ <=#Tp ~TxError;
2413
  else
2414
    TxB_IRQ <=#Tp 1'b0;
2415
end
2416
 
2417
 
2418
// Tx Error Interrupt
2419
always @ (posedge WB_CLK_I or posedge Reset)
2420
begin
2421
  if(Reset)
2422
    TxE_IRQ <=#Tp 1'b0;
2423
  else
2424
  if(TxStatusWrite & TxIRQEn)
2425
    TxE_IRQ <=#Tp TxError;
2426
  else
2427
    TxE_IRQ <=#Tp 1'b0;
2428
end
2429
 
2430
 
2431
// Rx Done Interrupt
2432
always @ (posedge WB_CLK_I or posedge Reset)
2433
begin
2434
  if(Reset)
2435
    RxB_IRQ <=#Tp 1'b0;
2436
  else
2437
  if(RxStatusWrite & RxIRQEn)
2438 167 mohor
    RxB_IRQ <=#Tp ReceivedPacketGood & ~RxError;
2439 77 mohor
  else
2440
    RxB_IRQ <=#Tp 1'b0;
2441
end
2442
 
2443
 
2444
// Rx Error Interrupt
2445
always @ (posedge WB_CLK_I or posedge Reset)
2446
begin
2447
  if(Reset)
2448
    RxE_IRQ <=#Tp 1'b0;
2449
  else
2450
  if(RxStatusWrite & RxIRQEn)
2451
    RxE_IRQ <=#Tp RxError;
2452
  else
2453
    RxE_IRQ <=#Tp 1'b0;
2454
end
2455
 
2456
 
2457 166 mohor
// Busy Interrupt
2458 77 mohor
 
2459 166 mohor
reg Busy_IRQ_rck;
2460
reg Busy_IRQ_sync1;
2461
reg Busy_IRQ_sync2;
2462
reg Busy_IRQ_sync3;
2463
reg Busy_IRQ_syncb1;
2464
reg Busy_IRQ_syncb2;
2465 77 mohor
 
2466
 
2467 166 mohor
always @ (posedge MRxClk or posedge Reset)
2468
begin
2469
  if(Reset)
2470
    Busy_IRQ_rck <=#Tp 1'b0;
2471
  else
2472
  if(RxValid & RxStartFrm & ~RxReady)
2473
    Busy_IRQ_rck <=#Tp 1'b1;
2474
  else
2475
  if(Busy_IRQ_syncb2)
2476
    Busy_IRQ_rck <=#Tp 1'b0;
2477
end
2478 77 mohor
 
2479 166 mohor
always @ (posedge WB_CLK_I)
2480
begin
2481
    Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
2482
    Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
2483
    Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
2484
end
2485
 
2486
always @ (posedge MRxClk)
2487
begin
2488
    Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
2489
    Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
2490
end
2491
 
2492
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
2493
 
2494
 
2495 60 mohor
 
2496
// TX
2497 61 mohor
// bit 15 ready
2498
// bit 14 interrupt
2499
// bit 13 wrap
2500
// bit 12 pad
2501
// bit 11 crc
2502
// bit 10 last
2503
// bit 9  pause request (control frame)
2504
// bit 8  TxUnderRun          
2505
// bit 7-4 RetryCntLatched    
2506
// bit 3  retransmittion limit
2507
// bit 2  LateCollLatched        
2508
// bit 1  DeferLatched        
2509
// bit 0  CarrierSenseLost    
2510 60 mohor
 
2511
 
2512
// RX
2513
// bit 15 od rx je empty
2514 61 mohor
// bit 14 od rx je interrupt
2515 60 mohor
// bit 13 od rx je wrap
2516
// bit 12 od rx je reserved
2517
// bit 11 od rx je reserved
2518
// bit 10 od rx je reserved
2519
// bit 9  od rx je reserved
2520
// bit 8  od rx je reserved
2521 110 mohor
// bit 7  od rx je Miss
2522 60 mohor
// bit 6  od rx je RxOverrun
2523
// bit 5  od rx je InvalidSymbol
2524
// bit 4  od rx je DribbleNibble
2525
// bit 3  od rx je ReceivedPacketTooBig
2526
// bit 2  od rx je ShortFrame
2527
// bit 1  od rx je LatchedCrcError
2528
// bit 0  od rx je RxLateCollision
2529
 
2530 110 mohor
 
2531 38 mohor
endmodule
2532
 

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