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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 264

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 264 mohor
// Revision 1.46  2002/11/22 01:57:06  mohor
45
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
46
// synchronized.
47
//
48 261 mohor
// Revision 1.45  2002/11/19 17:33:34  mohor
49
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
50
// that a frame was received because of the promiscous mode.
51
//
52 250 mohor
// Revision 1.44  2002/11/13 22:21:40  tadejm
53
// RxError is not generated when small frame reception is enabled and small
54
// frames are received.
55
//
56 239 tadejm
// Revision 1.43  2002/10/18 20:53:34  mohor
57
// case changed to casex.
58
//
59 229 mohor
// Revision 1.42  2002/10/18 17:04:20  tadejm
60
// Changed BIST scan signals.
61
//
62 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
63
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
64
//
65 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
66
// TxStatus is written after last access to the TX fifo is finished (in case of abort
67
// or retry). TxDone is fixed.
68
//
69 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
70
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
71
// TxDone and TxRetry are generated after the current WISHBONE access is
72
// finished.
73
//
74 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
75
// BIST added.
76
//
77 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
78
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
79
//
80 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
81
// Reception is possible after RxPointer is read and not after BD is read. For
82
// that reason RxBDReady is changed to RxReady.
83
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
84
// comes, interrupt is generated.
85
//
86 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
87
// Ethernet debug registers removed.
88
//
89 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
90
// Async reset for WB_ACK_O removed (when core was in reset, it was
91
// impossible to access BDs).
92
// RxPointers and TxPointers names changed to be more descriptive.
93
// TxUnderRun synchronized.
94
//
95 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
96
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
97
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
98
// was not used OK.
99
//
100 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
101
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
102
// need to multiply or devide any more.
103
//
104 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
105
// WriteRxDataToMemory signal changed so end of frame (when last word is
106
// written to fifo) is changed.
107
//
108 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
109
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
110
//
111 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
112
// ShiftEnded synchronization changed.
113
//
114 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
115
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
116
//
117 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
118
// RxPointer bug fixed.
119
//
120 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
121
// Previous bug wasn't succesfully removed. Now fixed.
122
//
123 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
124
// Master state machine had a bug when switching from master write to
125
// master read.
126
//
127 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
128
// m_wb_cyc_o signal released after every single transfer.
129
//
130 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
131
// Outputs registered. Reset changed for eth_wishbone module.
132
//
133 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
134
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
135
// bug fixed.
136
//
137 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
138
// Small typo fixed.
139
//
140 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
141
// Any address can be used for Tx and Rx BD pointers. Address does not need
142
// to be aligned.
143
//
144 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
145
// Comments in Slovene language removed.
146
//
147 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
148
// casex changed with case, fifo reset changed.
149
//
150 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
151
// rx_fifo was not always cleared ok. Fixed.
152
//
153 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
154
// Status was not latched correctly sometimes. Fixed.
155
//
156 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
157
// Big Endian problem when sending frames fixed.
158
//
159 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
160
// Byte ordering changed (Big Endian used). casex changed with case because
161
// Xilinx Foundation had problems. Tested in HW. It WORKS.
162
//
163 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
164
// Small fixes for external/internal DMA missmatches.
165
//
166 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
167
// Interrupts changed
168
//
169 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
170
// Status was not written correctly when frames were discarted because of
171
// address mismatch.
172
//
173 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
174
// RxStartFrm cleared when abort or retry comes.
175
//
176 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
177
// Changes that were lost when updating from 1.5 to 1.8 fixed.
178
//
179 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
180
// Addition  of new module eth_addrcheck.v
181
//
182
// Revision 1.7  2002/02/12 17:03:47  mohor
183
// RxOverRun added to statuses.
184
//
185
// Revision 1.6  2002/02/11 09:18:22  mohor
186
// Tx status is written back to the BD.
187
//
188 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
189
// Rx status is written back to the BD.
190
//
191 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
192
// non-DMA host interface added. Select the right configutation in eth_defines.
193
//
194 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
195
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
196
// MHz. Statuses, overrun, control frame transmission and reception still  need
197
// to be fixed.
198
//
199 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
200
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
201
// added.
202
//
203 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
204
// Initial version. Equals to eth_wishbonedma.v at this moment.
205 38 mohor
//
206
//
207
//
208
 
209
`include "eth_defines.v"
210
`include "timescale.v"
211
 
212
 
213
module eth_wishbone
214
   (
215
 
216
    // WISHBONE common
217 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
218 38 mohor
 
219
    // WISHBONE slave
220 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
221 40 mohor
    BDCs,
222 38 mohor
 
223 40 mohor
    Reset,
224
 
225 39 mohor
    // WISHBONE master
226
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
227
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
228
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
229
 
230 219 mohor
`ifdef ETH_WISHBONE_B3
231
    m_wb_cti_o, m_wb_bte_o,
232
`endif
233
 
234 38 mohor
    //TX
235 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
236 150 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
237 38 mohor
    PerPacketPad,
238
 
239
    //RX
240 40 mohor
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
241 38 mohor
 
242
    // Register
243 261 mohor
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow,
244 38 mohor
 
245
    // Interrupts
246 150 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
247 42 mohor
 
248 60 mohor
    // Rx Status
249 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
250 250 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
251 261 mohor
    ReceivedPauseFrm,
252 60 mohor
 
253
    // Tx Status
254 164 mohor
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
255
 
256 210 mohor
    // Bist
257
`ifdef ETH_BIST
258 227 tadejm
    ,
259
    // debug chain signals
260
    scanb_rst,      // bist scan reset
261
    scanb_clk,      // bist scan clock
262
    scanb_si,       // bist scan serial in
263
    scanb_so,       // bist scan serial out
264
    scanb_en        // bist scan shift enable
265 210 mohor
`endif
266
 
267
 
268
 
269 38 mohor
                );
270
 
271
 
272
parameter Tp = 1;
273
 
274 150 mohor
 
275 38 mohor
// WISHBONE common
276
input           WB_CLK_I;       // WISHBONE clock
277
input  [31:0]   WB_DAT_I;       // WISHBONE data input
278
output [31:0]   WB_DAT_O;       // WISHBONE data output
279
 
280
// WISHBONE slave
281
input   [9:2]   WB_ADR_I;       // WISHBONE address input
282
input           WB_WE_I;        // WISHBONE write enable input
283
input           BDCs;           // Buffer descriptors are selected
284
output          WB_ACK_O;       // WISHBONE acknowledge output
285
 
286 39 mohor
// WISHBONE master
287
output  [31:0]  m_wb_adr_o;     // 
288
output   [3:0]  m_wb_sel_o;     // 
289
output          m_wb_we_o;      // 
290
output  [31:0]  m_wb_dat_o;     // 
291
output          m_wb_cyc_o;     // 
292
output          m_wb_stb_o;     // 
293
input   [31:0]  m_wb_dat_i;     // 
294
input           m_wb_ack_i;     // 
295
input           m_wb_err_i;     // 
296
 
297 219 mohor
`ifdef ETH_WISHBONE_B3
298
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
299
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
300
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
301
`endif
302
 
303 40 mohor
input           Reset;       // Reset signal
304 39 mohor
 
305 60 mohor
// Rx Status signals
306 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
307
input           LatchedCrcError;  // CRC error
308
input           RxLateCollision;  // Late collision occured while receiving frame
309
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
310
input           DribbleNibble;    // Extra nibble received
311
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
312
input    [15:0] RxLength;         // Length of the incoming frame
313
input           LoadRxStatus;     // Rx status was loaded
314 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
315 250 mohor
input           AddressMiss;      // When a packet is received AddressMiss status is written to the Rx BD
316 261 mohor
input           r_RxFlow;
317
input           ReceivedPauseFrm;
318 39 mohor
 
319 60 mohor
// Tx Status signals
320
input     [3:0] RetryCntLatched;  // Latched Retry Counter
321
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
322
input           LateCollLatched;  // Late collision occured
323
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
324
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
325
 
326 38 mohor
// Tx
327
input           MTxClk;         // Transmit clock (from PHY)
328
input           TxUsedData;     // Transmit packet used data
329
input           TxRetry;        // Transmit packet retry
330
input           TxAbort;        // Transmit packet abort
331
input           TxDone;         // Transmission ended
332
output          TxStartFrm;     // Transmit packet start frame
333
output          TxEndFrm;       // Transmit packet end frame
334
output  [7:0]   TxData;         // Transmit packet data byte
335
output          TxUnderRun;     // Transmit packet under-run
336
output          PerPacketCrcEn; // Per packet crc enable
337
output          PerPacketPad;   // Per packet pading
338
 
339
// Rx
340
input           MRxClk;         // Receive clock (from PHY)
341
input   [7:0]   RxData;         // Received data byte (from PHY)
342
input           RxValid;        // 
343
input           RxStartFrm;     // 
344
input           RxEndFrm;       // 
345 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
346 38 mohor
 
347
//Register
348
input           r_TxEn;         // Transmit enable
349
input           r_RxEn;         // Receive enable
350
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
351
input           TX_BD_NUM_Wr;   // RxBDNumber written
352
 
353
// Interrupts
354
output TxB_IRQ;
355
output TxE_IRQ;
356
output RxB_IRQ;
357 77 mohor
output RxE_IRQ;
358 38 mohor
output Busy_IRQ;
359
 
360 77 mohor
 
361 210 mohor
// Bist
362
`ifdef ETH_BIST
363 227 tadejm
input   scanb_rst;      // bist scan reset
364
input   scanb_clk;      // bist scan clock
365
input   scanb_si;       // bist scan serial in
366
output  scanb_so;       // bist scan serial out
367
input   scanb_en;       // bist scan shift enable
368 210 mohor
`endif
369
 
370 77 mohor
reg TxB_IRQ;
371
reg TxE_IRQ;
372
reg RxB_IRQ;
373
reg RxE_IRQ;
374
 
375 38 mohor
reg             TxStartFrm;
376
reg             TxEndFrm;
377
reg     [7:0]   TxData;
378
 
379
reg             TxUnderRun;
380 60 mohor
reg             TxUnderRun_wb;
381 38 mohor
 
382
reg             TxBDRead;
383 39 mohor
wire            TxStatusWrite;
384 38 mohor
 
385
reg     [1:0]   TxValidBytesLatched;
386
 
387
reg    [15:0]   TxLength;
388 60 mohor
reg    [15:0]   LatchedTxLength;
389
reg   [14:11]   TxStatus;
390 38 mohor
 
391 60 mohor
reg   [14:13]   RxStatus;
392 38 mohor
 
393
reg             TxStartFrm_wb;
394
reg             TxRetry_wb;
395 39 mohor
reg             TxAbort_wb;
396 38 mohor
reg             TxDone_wb;
397
 
398
reg             TxDone_wb_q;
399
reg             TxAbort_wb_q;
400 39 mohor
reg             TxRetry_wb_q;
401 219 mohor
reg             TxRetryPacket;
402 221 mohor
reg             TxRetryPacket_NotCleared;
403
reg             TxDonePacket;
404
reg             TxDonePacket_NotCleared;
405 219 mohor
reg             TxAbortPacket;
406 221 mohor
reg             TxAbortPacket_NotCleared;
407 38 mohor
reg             RxBDReady;
408 166 mohor
reg             RxReady;
409 38 mohor
reg             TxBDReady;
410
 
411
reg             RxBDRead;
412 40 mohor
wire            RxStatusWrite;
413 38 mohor
 
414
reg    [31:0]   TxDataLatched;
415
reg     [1:0]   TxByteCnt;
416
reg             LastWord;
417 39 mohor
reg             ReadTxDataFromFifo_tck;
418 38 mohor
 
419
reg             BlockingTxStatusWrite;
420
reg             BlockingTxBDRead;
421
 
422 40 mohor
reg             Flop;
423 38 mohor
 
424
reg     [7:0]   TxBDAddress;
425
reg     [7:0]   RxBDAddress;
426
 
427
reg             TxRetrySync1;
428
reg             TxAbortSync1;
429 39 mohor
reg             TxDoneSync1;
430 38 mohor
 
431
reg             TxAbort_q;
432
reg             TxRetry_q;
433
reg             TxUsedData_q;
434
 
435
reg    [31:0]   RxDataLatched2;
436 82 mohor
 
437
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
438
 
439 38 mohor
reg     [1:0]   RxValidBytes;
440
reg     [1:0]   RxByteCnt;
441
reg             LastByteIn;
442
reg             ShiftWillEnd;
443
 
444 40 mohor
reg             WriteRxDataToFifo;
445 42 mohor
reg    [15:0]   LatchedRxLength;
446 64 mohor
reg             RxAbortLatched;
447 38 mohor
 
448 40 mohor
reg             ShiftEnded;
449 60 mohor
reg             RxOverrun;
450 38 mohor
 
451 40 mohor
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
452
reg             BDRead;                     // BD Read access from WISHBONE side
453 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
454
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
455 38 mohor
 
456 39 mohor
reg             TxEndFrm_wb;
457 38 mohor
 
458 39 mohor
wire            TxRetryPulse;
459 38 mohor
wire            TxDonePulse;
460
wire            TxAbortPulse;
461
 
462
wire            StartRxBDRead;
463
 
464
wire            StartTxBDRead;
465
 
466
wire            TxIRQEn;
467
wire            WrapTxStatusBit;
468
 
469 77 mohor
wire            RxIRQEn;
470 38 mohor
wire            WrapRxStatusBit;
471
 
472
wire    [1:0]   TxValidBytes;
473
 
474
wire    [7:0]   TempTxBDAddress;
475
wire    [7:0]   TempRxBDAddress;
476
 
477
wire            SetGotData;
478
wire            GotDataEvaluate;
479
 
480 106 mohor
reg             WB_ACK_O;
481 38 mohor
 
482 261 mohor
wire    [8:0]   RxStatusIn;
483
reg     [8:0]   RxStatusInLatched;
484 42 mohor
 
485 39 mohor
reg WbEn, WbEn_q;
486
reg RxEn, RxEn_q;
487
reg TxEn, TxEn_q;
488 38 mohor
 
489 39 mohor
wire ram_ce;
490
wire ram_we;
491
wire ram_oe;
492
reg [7:0]   ram_addr;
493
reg [31:0]  ram_di;
494
wire [31:0] ram_do;
495 38 mohor
 
496 39 mohor
wire StartTxPointerRead;
497
reg  TxPointerRead;
498
reg TxEn_needed;
499 40 mohor
reg RxEn_needed;
500 38 mohor
 
501 40 mohor
wire StartRxPointerRead;
502
reg RxPointerRead;
503 38 mohor
 
504 219 mohor
`ifdef ETH_WISHBONE_B3
505
assign m_wb_bte_o = 2'b00;    // Linear burst
506
`endif
507 39 mohor
 
508 219 mohor
 
509 159 mohor
always @ (posedge WB_CLK_I)
510 40 mohor
begin
511 159 mohor
  WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
512 40 mohor
end
513 39 mohor
 
514 106 mohor
assign WB_DAT_O = ram_do;
515 39 mohor
 
516 41 mohor
// Generic synchronous single-port RAM interface
517 119 mohor
eth_spram_256x32 bd_ram (
518 226 tadejm
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
519 210 mohor
`ifdef ETH_BIST
520 227 tadejm
  ,
521
  .scanb_rst      (scanb_rst),
522
  .scanb_clk      (scanb_clk),
523
  .scanb_si       (scanb_si),
524
  .scanb_so       (scanb_so),
525
  .scanb_en       (scanb_en)
526 210 mohor
`endif
527 39 mohor
);
528 41 mohor
 
529 39 mohor
assign ram_ce = 1'b1;
530 40 mohor
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
531 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
532 39 mohor
 
533
 
534 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
535 38 mohor
begin
536 40 mohor
  if(Reset)
537 39 mohor
    TxEn_needed <=#Tp 1'b0;
538 38 mohor
  else
539 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
540 39 mohor
    TxEn_needed <=#Tp 1'b1;
541
  else
542
  if(TxPointerRead & TxEn & TxEn_q)
543
    TxEn_needed <=#Tp 1'b0;
544 38 mohor
end
545
 
546 39 mohor
// Enabling access to the RAM for three devices.
547 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
548 39 mohor
begin
549 40 mohor
  if(Reset)
550 39 mohor
    begin
551
      WbEn <=#Tp 1'b1;
552
      RxEn <=#Tp 1'b0;
553
      TxEn <=#Tp 1'b0;
554
      ram_addr <=#Tp 8'h0;
555
      ram_di <=#Tp 32'h0;
556 77 mohor
      BDRead <=#Tp 1'b0;
557
      BDWrite <=#Tp 1'b0;
558 39 mohor
    end
559
  else
560
    begin
561
      // Switching between three stages depends on enable signals
562 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
563
        5'b100_10, 5'b100_11 :
564 39 mohor
          begin
565
            WbEn <=#Tp 1'b0;
566
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
567
            TxEn <=#Tp 1'b0;
568 40 mohor
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
569 39 mohor
            ram_di <=#Tp RxBDDataIn;
570
          end
571
        5'b100_01 :
572
          begin
573
            WbEn <=#Tp 1'b0;
574
            RxEn <=#Tp 1'b0;
575
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
576
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
577
            ram_di <=#Tp TxBDDataIn;
578
          end
579 90 mohor
        5'b010_00, 5'b010_10 :
580 39 mohor
          begin
581
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
582
            RxEn <=#Tp 1'b0;
583
            TxEn <=#Tp 1'b0;
584
            ram_addr <=#Tp WB_ADR_I[9:2];
585
            ram_di <=#Tp WB_DAT_I;
586 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
587
            BDRead <=#Tp BDCs & ~WB_WE_I;
588 39 mohor
          end
589 90 mohor
        5'b010_01, 5'b010_11 :
590 39 mohor
          begin
591
            WbEn <=#Tp 1'b0;
592
            RxEn <=#Tp 1'b0;
593
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
594
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
595
            ram_di <=#Tp TxBDDataIn;
596
          end
597 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
598 39 mohor
          begin
599
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
600
            RxEn <=#Tp 1'b0;
601
            TxEn <=#Tp 1'b0;
602
            ram_addr <=#Tp WB_ADR_I[9:2];
603
            ram_di <=#Tp WB_DAT_I;
604 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
605
            BDRead <=#Tp BDCs & ~WB_WE_I;
606 39 mohor
          end
607
        5'b100_00 :
608
          begin
609
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
610
          end
611
        5'b000_00 :
612
          begin
613
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
614
            RxEn <=#Tp 1'b0;
615
            TxEn <=#Tp 1'b0;
616
            ram_addr <=#Tp WB_ADR_I[9:2];
617
            ram_di <=#Tp WB_DAT_I;
618 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
619
            BDRead <=#Tp BDCs & ~WB_WE_I;
620 39 mohor
          end
621
      endcase
622
    end
623
end
624
 
625
 
626
// Delayed stage signals
627 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
628 39 mohor
begin
629 40 mohor
  if(Reset)
630 39 mohor
    begin
631
      WbEn_q <=#Tp 1'b0;
632
      RxEn_q <=#Tp 1'b0;
633
      TxEn_q <=#Tp 1'b0;
634
    end
635
  else
636
    begin
637
      WbEn_q <=#Tp WbEn;
638
      RxEn_q <=#Tp RxEn;
639
      TxEn_q <=#Tp TxEn;
640
    end
641
end
642
 
643 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
644 40 mohor
always @ (posedge MTxClk or posedge Reset)
645 38 mohor
begin
646 40 mohor
  if(Reset)
647 38 mohor
    Flop <=#Tp 1'b0;
648
  else
649
  if(TxDone | TxAbort | TxRetry_q)
650
    Flop <=#Tp 1'b0;
651
  else
652
  if(TxUsedData)
653
    Flop <=#Tp ~Flop;
654
end
655
 
656 39 mohor
wire ResetTxBDReady;
657
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
658 38 mohor
 
659
// Latching READY status of the Tx buffer descriptor
660 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
661 38 mohor
begin
662 40 mohor
  if(Reset)
663 38 mohor
    TxBDReady <=#Tp 1'b0;
664
  else
665 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
666
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
667
  else                                                // Only packets larger then 4 bytes are transmitted.
668 39 mohor
  if(ResetTxBDReady)
669 38 mohor
    TxBDReady <=#Tp 1'b0;
670
end
671
 
672
 
673 39 mohor
// Reading the Tx buffer descriptor
674 221 mohor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
675 39 mohor
 
676 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
677 38 mohor
begin
678 40 mohor
  if(Reset)
679 39 mohor
    TxBDRead <=#Tp 1'b1;
680 38 mohor
  else
681 110 mohor
  if(StartTxBDRead)
682 39 mohor
    TxBDRead <=#Tp 1'b1;
683 38 mohor
  else
684 39 mohor
  if(TxBDReady)
685
    TxBDRead <=#Tp 1'b0;
686 38 mohor
end
687
 
688
 
689 39 mohor
// Reading Tx BD pointer
690
assign StartTxPointerRead = TxBDRead & TxBDReady;
691 38 mohor
 
692 39 mohor
// Reading Tx BD Pointer
693 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
694 38 mohor
begin
695 40 mohor
  if(Reset)
696 39 mohor
    TxPointerRead <=#Tp 1'b0;
697 38 mohor
  else
698 39 mohor
  if(StartTxPointerRead)
699
    TxPointerRead <=#Tp 1'b1;
700 38 mohor
  else
701 39 mohor
  if(TxEn_q)
702
    TxPointerRead <=#Tp 1'b0;
703 38 mohor
end
704
 
705
 
706 39 mohor
// Writing status back to the Tx buffer descriptor
707 221 mohor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
708 38 mohor
 
709
 
710
 
711 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
712 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
713 38 mohor
begin
714 40 mohor
  if(Reset)
715 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
716 38 mohor
  else
717 39 mohor
  if(TxStatusWrite)
718
    BlockingTxStatusWrite <=#Tp 1'b1;
719 38 mohor
  else
720 39 mohor
  if(~TxDone_wb & ~TxAbort_wb)
721
    BlockingTxStatusWrite <=#Tp 1'b0;
722 38 mohor
end
723
 
724
 
725 159 mohor
reg BlockingTxStatusWrite_sync1;
726
reg BlockingTxStatusWrite_sync2;
727
 
728
// Synchronizing BlockingTxStatusWrite to MTxClk
729
always @ (posedge MTxClk or posedge Reset)
730
begin
731
  if(Reset)
732
    BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
733
  else
734
    BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
735
end
736
 
737
// Synchronizing BlockingTxStatusWrite to MTxClk
738
always @ (posedge MTxClk or posedge Reset)
739
begin
740
  if(Reset)
741
    BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
742
  else
743
    BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
744
end
745
 
746
 
747 39 mohor
// TxBDRead state is activated only once. 
748 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
749 39 mohor
begin
750 40 mohor
  if(Reset)
751 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
752
  else
753 110 mohor
  if(StartTxBDRead)
754 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
755
  else
756 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
757 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
758
end
759 38 mohor
 
760
 
761 39 mohor
// Latching status from the tx buffer descriptor
762
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
763 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
764 38 mohor
begin
765 40 mohor
  if(Reset)
766 60 mohor
    TxStatus <=#Tp 4'h0;
767 38 mohor
  else
768 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
769 60 mohor
    TxStatus <=#Tp ram_do[14:11];
770 38 mohor
end
771
 
772 40 mohor
reg ReadTxDataFromMemory;
773
wire WriteRxDataToMemory;
774 38 mohor
 
775 39 mohor
reg MasterWbTX;
776
reg MasterWbRX;
777
 
778
reg [31:0] m_wb_adr_o;
779
reg        m_wb_cyc_o;
780
reg        m_wb_stb_o;
781 96 mohor
reg  [3:0] m_wb_sel_o;
782 39 mohor
reg        m_wb_we_o;
783 40 mohor
 
784 39 mohor
wire TxLengthEq0;
785
wire TxLengthLt4;
786
 
787 150 mohor
reg BlockingIncrementTxPointer;
788 159 mohor
reg [31:2] TxPointerMSB;
789
reg [1:0]  TxPointerLSB;
790
reg [1:0]  TxPointerLSB_rst;
791
reg [31:2] RxPointerMSB;
792
reg [1:0]  RxPointerLSB_rst;
793 39 mohor
 
794 150 mohor
wire RxBurstAcc;
795
wire RxWordAcc;
796
wire RxHalfAcc;
797
wire RxByteAcc;
798
 
799 39 mohor
//Latching length from the buffer descriptor;
800 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
801 38 mohor
begin
802 40 mohor
  if(Reset)
803 39 mohor
    TxLength <=#Tp 16'h0;
804 38 mohor
  else
805 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
806
    TxLength <=#Tp ram_do[31:16];
807 38 mohor
  else
808 39 mohor
  if(MasterWbTX & m_wb_ack_i)
809
    begin
810
      if(TxLengthLt4)
811
        TxLength <=#Tp 16'h0;
812 150 mohor
      else
813 159 mohor
      if(TxPointerLSB_rst==2'h0)
814 96 mohor
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
815 39 mohor
      else
816 159 mohor
      if(TxPointerLSB_rst==2'h1)
817 150 mohor
        TxLength <=#Tp TxLength - 3'h3;    // Length is subtracted at the data request
818
      else
819 159 mohor
      if(TxPointerLSB_rst==2'h2)
820 150 mohor
        TxLength <=#Tp TxLength - 3'h2;    // Length is subtracted at the data request
821
      else
822 159 mohor
      if(TxPointerLSB_rst==2'h3)
823 150 mohor
        TxLength <=#Tp TxLength - 3'h1;    // Length is subtracted at the data request
824 39 mohor
    end
825 38 mohor
end
826
 
827 96 mohor
 
828
 
829 60 mohor
//Latching length from the buffer descriptor;
830
always @ (posedge WB_CLK_I or posedge Reset)
831
begin
832
  if(Reset)
833
    LatchedTxLength <=#Tp 16'h0;
834
  else
835
  if(TxEn & TxEn_q & TxBDRead)
836
    LatchedTxLength <=#Tp ram_do[31:16];
837
end
838
 
839 39 mohor
assign TxLengthEq0 = TxLength == 0;
840
assign TxLengthLt4 = TxLength < 4;
841 38 mohor
 
842 150 mohor
reg cyc_cleared;
843
reg IncrTxPointer;
844 39 mohor
 
845
 
846 159 mohor
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
847
// because TxPointerMSB is only used for word-aligned accesses.
848 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
849 38 mohor
begin
850 40 mohor
  if(Reset)
851 159 mohor
    TxPointerMSB <=#Tp 30'h0;
852 38 mohor
  else
853 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
854 159 mohor
    TxPointerMSB <=#Tp ram_do[31:2];
855 38 mohor
  else
856 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
857 159 mohor
    TxPointerMSB <=#Tp TxPointerMSB + 1'b1;     // TxPointer is word-aligned
858 38 mohor
end
859
 
860 96 mohor
 
861 159 mohor
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
862
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
863
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
864
// set by this two bits.
865 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
866
begin
867
  if(Reset)
868 159 mohor
    TxPointerLSB[1:0] <=#Tp 0;
869 96 mohor
  else
870
  if(TxEn & TxEn_q & TxPointerRead)
871 159 mohor
    TxPointerLSB[1:0] <=#Tp ram_do[1:0];
872 96 mohor
end
873
 
874
 
875 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
876
// After the read access, TxLength needs to be decremented for the number of the valid
877
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
878
// valid so this two bits are reset to zero. 
879 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
880
begin
881
  if(Reset)
882 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
883 150 mohor
  else
884
  if(TxEn & TxEn_q & TxPointerRead)
885 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
886 150 mohor
  else
887
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
888 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
889 150 mohor
end
890 96 mohor
 
891 150 mohor
 
892 159 mohor
reg  [3:0] RxByteSel;
893 39 mohor
wire MasterAccessFinished;
894 38 mohor
 
895 39 mohor
 
896 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
897 38 mohor
begin
898 40 mohor
  if(Reset)
899 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
900 38 mohor
  else
901 39 mohor
  if(MasterAccessFinished)
902
    BlockingIncrementTxPointer <=#Tp 0;
903 38 mohor
  else
904 150 mohor
  if(IncrTxPointer)
905 39 mohor
    BlockingIncrementTxPointer <=#Tp 1'b1;
906 38 mohor
end
907
 
908
 
909 39 mohor
wire TxBufferAlmostFull;
910
wire TxBufferFull;
911
wire TxBufferEmpty;
912
wire TxBufferAlmostEmpty;
913 40 mohor
wire SetReadTxDataFromMemory;
914 39 mohor
 
915 40 mohor
reg BlockReadTxDataFromMemory;
916 39 mohor
 
917 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
918 39 mohor
 
919 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
920 38 mohor
begin
921 40 mohor
  if(Reset)
922
    ReadTxDataFromMemory <=#Tp 1'b0;
923 38 mohor
  else
924 219 mohor
  if(TxLengthEq0 | TxAbortPacket | TxRetryPacket)
925 40 mohor
    ReadTxDataFromMemory <=#Tp 1'b0;
926 39 mohor
  else
927 40 mohor
  if(SetReadTxDataFromMemory)
928
    ReadTxDataFromMemory <=#Tp 1'b1;
929 38 mohor
end
930
 
931 226 tadejm
reg tx_burst_en;
932
reg rx_burst_en;
933 221 mohor
reg BlockingLastReadOn_Abort_Retry;
934
 
935
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory & ~BlockingLastReadOn_Abort_Retry;
936 226 tadejm
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
937 221 mohor
 
938 39 mohor
wire [31:0] TxData_wb;
939
wire ReadTxDataFromFifo_wb;
940 38 mohor
 
941 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
942 38 mohor
begin
943 40 mohor
  if(Reset)
944
    BlockReadTxDataFromMemory <=#Tp 1'b0;
945 38 mohor
  else
946 221 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (!(TxAbortPacket | TxRetryPacket)))
947 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
948 219 mohor
  else
949 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
950 219 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b0;
951 39 mohor
end
952
 
953
 
954 221 mohor
always @ (posedge WB_CLK_I or posedge Reset)
955
begin
956
  if(Reset)
957
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
958
  else
959
  if(TxAbortPacket | TxRetryPacket)
960
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
961
  else
962
  if(((TxAbort_wb & !TxAbortPacket_NotCleared) | (TxRetry_wb & !TxRetryPacket_NotCleared)) & !TxBDReady)
963
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b1;
964
end
965 39 mohor
 
966 221 mohor
 
967
 
968
 
969 39 mohor
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
970 219 mohor
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
971
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
972 226 tadejm
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
973
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
974 159 mohor
 
975 226 tadejm
wire rx_burst;
976
wire enough_data_in_rxfifo_for_burst;
977
wire enough_data_in_rxfifo_for_burst_plus1;
978 229 mohor
 
979 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
980 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
981 39 mohor
begin
982 40 mohor
  if(Reset)
983 38 mohor
    begin
984 39 mohor
      MasterWbTX <=#Tp 1'b0;
985
      MasterWbRX <=#Tp 1'b0;
986
      m_wb_adr_o <=#Tp 32'h0;
987
      m_wb_cyc_o <=#Tp 1'b0;
988
      m_wb_stb_o <=#Tp 1'b0;
989
      m_wb_we_o  <=#Tp 1'b0;
990 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
991 110 mohor
      cyc_cleared<=#Tp 1'b0;
992 226 tadejm
      tx_burst_cnt<=#Tp 0;
993
      rx_burst_cnt<=#Tp 0;
994 150 mohor
      IncrTxPointer<=#Tp 1'b0;
995 226 tadejm
      tx_burst_en<=#Tp 1'b1;
996
      rx_burst_en<=#Tp 1'b0;
997
      `ifdef ETH_WISHBONE_B3
998
        m_wb_cti_o <=#Tp 3'b0;
999
      `endif
1000 38 mohor
    end
1001 39 mohor
  else
1002
    begin
1003
      // Switching between two stages depends on enable signals
1004 229 mohor
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst})  // synopsys parallel_case
1005 226 tadejm
        8'b00_10_00_10,             // Idle and MRB needed
1006 229 mohor
        8'b10_1x_10_1x,             // MRB continues
1007 226 tadejm
        8'b10_10_01_10,             // Clear (previously MR) and MRB needed
1008 229 mohor
        8'b01_1x_01_1x :            // Clear (previously MW) and MRB needed
1009 39 mohor
          begin
1010 226 tadejm
            MasterWbTX <=#Tp 1'b1;  // tx burst
1011
            MasterWbRX <=#Tp 1'b0;
1012
            m_wb_cyc_o <=#Tp 1'b1;
1013
            m_wb_stb_o <=#Tp 1'b1;
1014
            m_wb_we_o  <=#Tp 1'b0;
1015
            m_wb_sel_o <=#Tp 4'hf;
1016
            cyc_cleared<=#Tp 1'b0;
1017
            IncrTxPointer<=#Tp 1'b1;
1018
            tx_burst_cnt <=#Tp tx_burst_cnt+1;
1019
            if(tx_burst_cnt==0)
1020
              m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1021
            else
1022
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1023
 
1024
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1025
              begin
1026
                tx_burst_en<=#Tp 1'b0;
1027
              `ifdef ETH_WISHBONE_B3
1028
                m_wb_cti_o <=#Tp 3'b111;
1029
              `endif
1030
              end
1031
            else
1032
              begin
1033
              `ifdef ETH_WISHBONE_B3
1034
                m_wb_cti_o <=#Tp 3'b010;
1035
              `endif
1036
              end
1037
          end
1038 229 mohor
        8'b00_x1_00_x1,             // Idle and MWB needed
1039
        8'b01_x1_10_x1,             // MWB continues
1040 226 tadejm
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1041 229 mohor
        8'b10_x1_01_x1 :            // Clear (previously MR) and MWB needed
1042 226 tadejm
          begin
1043
            MasterWbTX <=#Tp 1'b0;  // rx burst
1044 39 mohor
            MasterWbRX <=#Tp 1'b1;
1045 226 tadejm
            m_wb_cyc_o <=#Tp 1'b1;
1046
            m_wb_stb_o <=#Tp 1'b1;
1047
            m_wb_we_o  <=#Tp 1'b1;
1048
            m_wb_sel_o <=#Tp RxByteSel;
1049
            IncrTxPointer<=#Tp 1'b0;
1050
            cyc_cleared<=#Tp 1'b0;
1051
            rx_burst_cnt <=#Tp rx_burst_cnt+1;
1052
 
1053
            if(rx_burst_cnt==0)
1054
              m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1055
            else
1056
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1057
 
1058
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1059
              begin
1060
                rx_burst_en<=#Tp 1'b0;
1061
              `ifdef ETH_WISHBONE_B3
1062
                m_wb_cti_o <=#Tp 3'b111;
1063
              `endif
1064
              end
1065
            else
1066
              begin
1067
              `ifdef ETH_WISHBONE_B3
1068
                m_wb_cti_o <=#Tp 3'b010;
1069
              `endif
1070
              end
1071
          end
1072 229 mohor
        8'b00_x1_00_x0 :            // idle and MW is needed (data write to rx buffer)
1073 226 tadejm
          begin
1074
            MasterWbTX <=#Tp 1'b0;
1075
            MasterWbRX <=#Tp 1'b1;
1076 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1077 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1078
            m_wb_stb_o <=#Tp 1'b1;
1079
            m_wb_we_o  <=#Tp 1'b1;
1080 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1081 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1082 39 mohor
          end
1083 226 tadejm
        8'b00_10_00_00 :            // idle and MR is needed (data read from tx buffer)
1084 39 mohor
          begin
1085 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1086 39 mohor
            MasterWbRX <=#Tp 1'b0;
1087 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1088 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1089
            m_wb_stb_o <=#Tp 1'b1;
1090
            m_wb_we_o  <=#Tp 1'b0;
1091 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1092
            IncrTxPointer<=#Tp 1'b1;
1093 39 mohor
          end
1094 226 tadejm
        8'b10_10_01_00,             // MR and MR is needed (data read from tx buffer)
1095 229 mohor
        8'b01_1x_01_0x  :           // MW and MR is needed (data read from tx buffer)
1096 39 mohor
          begin
1097 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1098 39 mohor
            MasterWbRX <=#Tp 1'b0;
1099 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1100 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1101
            m_wb_stb_o <=#Tp 1'b1;
1102
            m_wb_we_o  <=#Tp 1'b0;
1103 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1104 110 mohor
            cyc_cleared<=#Tp 1'b0;
1105 150 mohor
            IncrTxPointer<=#Tp 1'b1;
1106 39 mohor
          end
1107 226 tadejm
        8'b01_01_01_00,             // MW and MW needed (data write to rx buffer)
1108 229 mohor
        8'b10_x1_01_x0  :           // MR and MW is needed (data write to rx buffer)
1109 39 mohor
          begin
1110 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1111 39 mohor
            MasterWbRX <=#Tp 1'b1;
1112 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1113 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1114
            m_wb_stb_o <=#Tp 1'b1;
1115 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
1116 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1117 110 mohor
            cyc_cleared<=#Tp 1'b0;
1118 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1119 39 mohor
          end
1120 226 tadejm
        8'b01_01_10_00,             // MW and MW needed (cycle is cleared between previous and next access)
1121 229 mohor
        8'b01_1x_10_x0,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1122 226 tadejm
        8'b10_10_10_00,             // MR and MR needed (cycle is cleared between previous and next access)
1123 229 mohor
        8'b10_x1_10_0x :            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1124 39 mohor
          begin
1125 110 mohor
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
1126
            m_wb_stb_o <=#Tp 1'b0;
1127
            cyc_cleared<=#Tp 1'b1;
1128 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1129 226 tadejm
            tx_burst_cnt<=#Tp 0;
1130
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1131
            rx_burst_cnt<=#Tp 0;
1132
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1133
            `ifdef ETH_WISHBONE_B3
1134
              m_wb_cti_o <=#Tp 3'b0;
1135
            `endif
1136 110 mohor
          end
1137 229 mohor
        8'bxx_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1138
        8'bxx_00_01_00 :            // Between cyc_cleared request was cleared
1139 110 mohor
          begin
1140 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1141 39 mohor
            MasterWbRX <=#Tp 1'b0;
1142
            m_wb_cyc_o <=#Tp 1'b0;
1143
            m_wb_stb_o <=#Tp 1'b0;
1144 226 tadejm
            cyc_cleared<=#Tp 1'b0;
1145 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1146 226 tadejm
            rx_burst_cnt<=#Tp 0;
1147
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1148
            `ifdef ETH_WISHBONE_B3
1149
              m_wb_cti_o <=#Tp 3'b0;
1150
            `endif
1151 39 mohor
          end
1152 226 tadejm
        8'b00_00_00_00:             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1153 127 mohor
          begin
1154 226 tadejm
            tx_burst_cnt<=#Tp 0;
1155
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1156 127 mohor
          end
1157 226 tadejm
        default:                    // Don't touch
1158 82 mohor
          begin
1159
            MasterWbTX <=#Tp MasterWbTX;
1160
            MasterWbRX <=#Tp MasterWbRX;
1161
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
1162
            m_wb_stb_o <=#Tp m_wb_stb_o;
1163 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
1164 150 mohor
            IncrTxPointer<=#Tp IncrTxPointer;
1165 82 mohor
          end
1166 39 mohor
      endcase
1167
    end
1168 38 mohor
end
1169
 
1170 110 mohor
 
1171 39 mohor
wire TxFifoClear;
1172 96 mohor
 
1173 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1174 38 mohor
 
1175 219 mohor
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
1176 150 mohor
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
1177 96 mohor
          .clk(WB_CLK_I),                                   .reset(Reset),
1178 226 tadejm
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1179 96 mohor
          .clear(TxFifoClear),                              .full(TxBufferFull),
1180
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
1181 150 mohor
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
1182 96 mohor
        );
1183 39 mohor
 
1184
 
1185
reg StartOccured;
1186
reg TxStartFrm_sync1;
1187
reg TxStartFrm_sync2;
1188
reg TxStartFrm_syncb1;
1189
reg TxStartFrm_syncb2;
1190
 
1191
 
1192
 
1193
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1194 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1195 38 mohor
begin
1196 40 mohor
  if(Reset)
1197 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
1198 38 mohor
  else
1199 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1200
    TxStartFrm_wb <=#Tp 1'b1;
1201 38 mohor
  else
1202 39 mohor
  if(TxStartFrm_syncb2)
1203
    TxStartFrm_wb <=#Tp 1'b0;
1204 38 mohor
end
1205
 
1206 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1207 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1208 38 mohor
begin
1209 40 mohor
  if(Reset)
1210 39 mohor
    StartOccured <=#Tp 1'b0;
1211 38 mohor
  else
1212 39 mohor
  if(TxStartFrm_wb)
1213
    StartOccured <=#Tp 1'b1;
1214 38 mohor
  else
1215 39 mohor
  if(ResetTxBDReady)
1216
    StartOccured <=#Tp 1'b0;
1217 38 mohor
end
1218
 
1219 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1220 40 mohor
always @ (posedge MTxClk or posedge Reset)
1221 39 mohor
begin
1222 40 mohor
  if(Reset)
1223 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1224
  else
1225
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1226
end
1227 38 mohor
 
1228 40 mohor
always @ (posedge MTxClk or posedge Reset)
1229 39 mohor
begin
1230 40 mohor
  if(Reset)
1231 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1232
  else
1233
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1234
end
1235
 
1236 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1237 38 mohor
begin
1238 40 mohor
  if(Reset)
1239 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1240 38 mohor
  else
1241 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1242 38 mohor
end
1243
 
1244 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1245 38 mohor
begin
1246 40 mohor
  if(Reset)
1247 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1248 38 mohor
  else
1249 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1250
end
1251
 
1252 40 mohor
always @ (posedge MTxClk or posedge Reset)
1253 39 mohor
begin
1254 40 mohor
  if(Reset)
1255 39 mohor
    TxStartFrm <=#Tp 1'b0;
1256 38 mohor
  else
1257 39 mohor
  if(TxStartFrm_sync2)
1258 61 mohor
    TxStartFrm <=#Tp 1'b1;
1259 39 mohor
  else
1260 61 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry | TxAbort))
1261 39 mohor
    TxStartFrm <=#Tp 1'b0;
1262 38 mohor
end
1263 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1264 38 mohor
 
1265
 
1266 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1267 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1268 38 mohor
begin
1269 40 mohor
  if(Reset)
1270 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1271 38 mohor
  else
1272 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1273 39 mohor
    TxEndFrm_wb <=#Tp 1'b1;
1274 38 mohor
  else
1275 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1276
    TxEndFrm_wb <=#Tp 1'b0;
1277 38 mohor
end
1278
 
1279
 
1280
// Marks which bytes are valid within the word.
1281 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1282 38 mohor
 
1283 39 mohor
reg LatchValidBytes;
1284
reg LatchValidBytes_q;
1285 38 mohor
 
1286 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1287 38 mohor
begin
1288 40 mohor
  if(Reset)
1289 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1290 38 mohor
  else
1291 39 mohor
  if(TxLengthLt4 & TxBDReady)
1292
    LatchValidBytes <=#Tp 1'b1;
1293 38 mohor
  else
1294 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1295 38 mohor
end
1296
 
1297 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1298 38 mohor
begin
1299 40 mohor
  if(Reset)
1300 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1301 38 mohor
  else
1302 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1303 38 mohor
end
1304
 
1305
 
1306 39 mohor
// Latching valid bytes
1307 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1308 38 mohor
begin
1309 40 mohor
  if(Reset)
1310 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1311 38 mohor
  else
1312 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1313
    TxValidBytesLatched <=#Tp TxValidBytes;
1314
  else
1315
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1316
    TxValidBytesLatched <=#Tp 2'h0;
1317 38 mohor
end
1318
 
1319
 
1320
assign TxIRQEn          = TxStatus[14];
1321 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1322
assign PerPacketPad     = TxStatus[12];
1323
assign PerPacketCrcEn   = TxStatus[11];
1324 38 mohor
 
1325
 
1326 77 mohor
assign RxIRQEn         = RxStatus[14];
1327 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1328 38 mohor
 
1329
 
1330
// Temporary Tx and Rx buffer descriptor address 
1331 39 mohor
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
1332 134 mohor
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1)     | // Using first Rx BD
1333 39 mohor
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
1334 38 mohor
 
1335
 
1336
// Latching Tx buffer descriptor address
1337 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1338 38 mohor
begin
1339 40 mohor
  if(Reset)
1340 38 mohor
    TxBDAddress <=#Tp 8'h0;
1341
  else
1342
  if(TxStatusWrite)
1343
    TxBDAddress <=#Tp TempTxBDAddress;
1344
end
1345
 
1346
 
1347
// Latching Rx buffer descriptor address
1348 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1349 38 mohor
begin
1350 40 mohor
  if(Reset)
1351 134 mohor
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1;
1352 38 mohor
  else
1353 77 mohor
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
1354 134 mohor
    RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
1355 38 mohor
  else
1356
  if(RxStatusWrite)
1357
    RxBDAddress <=#Tp TempRxBDAddress;
1358
end
1359
 
1360 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1361 38 mohor
 
1362 261 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
1363 60 mohor
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1364 38 mohor
 
1365 60 mohor
 
1366 38 mohor
// Signals used for various purposes
1367 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1368 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1369
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1370
 
1371
 
1372
 
1373 39 mohor
// Generating delayed signals
1374 40 mohor
always @ (posedge MTxClk or posedge Reset)
1375 38 mohor
begin
1376 40 mohor
  if(Reset)
1377 39 mohor
    begin
1378
      TxAbort_q      <=#Tp 1'b0;
1379
      TxRetry_q      <=#Tp 1'b0;
1380
      TxUsedData_q   <=#Tp 1'b0;
1381
    end
1382 38 mohor
  else
1383 39 mohor
    begin
1384
      TxAbort_q      <=#Tp TxAbort;
1385
      TxRetry_q      <=#Tp TxRetry;
1386
      TxUsedData_q   <=#Tp TxUsedData;
1387
    end
1388 38 mohor
end
1389
 
1390
// Generating delayed signals
1391 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1392 38 mohor
begin
1393 40 mohor
  if(Reset)
1394 38 mohor
    begin
1395 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1396
      TxAbort_wb_q  <=#Tp 1'b0;
1397 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1398 38 mohor
    end
1399
  else
1400
    begin
1401 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1402
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1403 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1404 38 mohor
    end
1405
end
1406
 
1407
 
1408 219 mohor
reg TxAbortPacketBlocked;
1409
always @ (posedge WB_CLK_I or posedge Reset)
1410
begin
1411
  if(Reset)
1412
    TxAbortPacket <=#Tp 1'b0;
1413
  else
1414 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxAbortPacketBlocked |
1415
     TxAbort_wb & !MasterWbTX & !TxAbortPacketBlocked)
1416 219 mohor
    TxAbortPacket <=#Tp 1'b1;
1417
  else
1418
    TxAbortPacket <=#Tp 1'b0;
1419
end
1420
 
1421
 
1422
always @ (posedge WB_CLK_I or posedge Reset)
1423
begin
1424
  if(Reset)
1425 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1426
  else
1427 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1428
     TxAbort_wb & !MasterWbTX)
1429 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b1;
1430
  else
1431
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1432
end
1433
 
1434
 
1435
always @ (posedge WB_CLK_I or posedge Reset)
1436
begin
1437
  if(Reset)
1438 219 mohor
    TxAbortPacketBlocked <=#Tp 1'b0;
1439
  else
1440
  if(TxAbortPacket)
1441
    TxAbortPacketBlocked <=#Tp 1'b1;
1442
  else
1443
  if(!TxAbort_wb & TxAbort_wb_q)
1444
    TxAbortPacketBlocked <=#Tp 1'b0;
1445
end
1446
 
1447
 
1448
reg TxRetryPacketBlocked;
1449
always @ (posedge WB_CLK_I or posedge Reset)
1450
begin
1451
  if(Reset)
1452
    TxRetryPacket <=#Tp 1'b0;
1453
  else
1454 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1455
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1456 219 mohor
    TxRetryPacket <=#Tp 1'b1;
1457
  else
1458
    TxRetryPacket <=#Tp 1'b0;
1459
end
1460
 
1461
 
1462
always @ (posedge WB_CLK_I or posedge Reset)
1463
begin
1464
  if(Reset)
1465 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1466
  else
1467 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1468
     TxRetry_wb & !MasterWbTX)
1469 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b1;
1470
  else
1471
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1472
end
1473
 
1474
 
1475
always @ (posedge WB_CLK_I or posedge Reset)
1476
begin
1477
  if(Reset)
1478 219 mohor
    TxRetryPacketBlocked <=#Tp 1'b0;
1479
  else
1480
  if(TxRetryPacket)
1481
    TxRetryPacketBlocked <=#Tp 1'b1;
1482
  else
1483
  if(!TxRetry_wb & TxRetry_wb_q)
1484
    TxRetryPacketBlocked <=#Tp 1'b0;
1485
end
1486
 
1487
 
1488 221 mohor
reg TxDonePacketBlocked;
1489
always @ (posedge WB_CLK_I or posedge Reset)
1490
begin
1491
  if(Reset)
1492
    TxDonePacket <=#Tp 1'b0;
1493
  else
1494 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
1495
     TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1496 221 mohor
    TxDonePacket <=#Tp 1'b1;
1497
  else
1498
    TxDonePacket <=#Tp 1'b0;
1499
end
1500
 
1501
 
1502
always @ (posedge WB_CLK_I or posedge Reset)
1503
begin
1504
  if(Reset)
1505
    TxDonePacket_NotCleared <=#Tp 1'b0;
1506
  else
1507 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1508
     TxDone_wb & !MasterWbTX)
1509 221 mohor
    TxDonePacket_NotCleared <=#Tp 1'b1;
1510
  else
1511
    TxDonePacket_NotCleared <=#Tp 1'b0;
1512
end
1513
 
1514
 
1515
always @ (posedge WB_CLK_I or posedge Reset)
1516
begin
1517
  if(Reset)
1518
    TxDonePacketBlocked <=#Tp 1'b0;
1519
  else
1520
  if(TxDonePacket)
1521
    TxDonePacketBlocked <=#Tp 1'b1;
1522
  else
1523
  if(!TxDone_wb & TxDone_wb_q)
1524
    TxDonePacketBlocked <=#Tp 1'b0;
1525
end
1526
 
1527
 
1528 38 mohor
// Sinchronizing and evaluating tx data
1529 39 mohor
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
1530 219 mohor
assign SetGotData = (TxStartFrm_wb);
1531 38 mohor
 
1532
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
1533 40 mohor
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1534
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1535 38 mohor
 
1536
 
1537
// Indication of the last word
1538 40 mohor
always @ (posedge MTxClk or posedge Reset)
1539 38 mohor
begin
1540 40 mohor
  if(Reset)
1541 38 mohor
    LastWord <=#Tp 1'b0;
1542
  else
1543
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1544
    LastWord <=#Tp 1'b0;
1545
  else
1546
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1547 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1548 38 mohor
end
1549
 
1550
 
1551
// Tx end frame generation
1552 40 mohor
always @ (posedge MTxClk or posedge Reset)
1553 38 mohor
begin
1554 40 mohor
  if(Reset)
1555 38 mohor
    TxEndFrm <=#Tp 1'b0;
1556
  else
1557 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1558 38 mohor
    TxEndFrm <=#Tp 1'b0;
1559
  else
1560
  if(Flop & LastWord)
1561
    begin
1562 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1563 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1564
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1565
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1566
 
1567
        default : TxEndFrm <=#Tp 1'b0;
1568
      endcase
1569
    end
1570
end
1571
 
1572
 
1573
// Tx data selection (latching)
1574 40 mohor
always @ (posedge MTxClk or posedge Reset)
1575 38 mohor
begin
1576 40 mohor
  if(Reset)
1577 96 mohor
    TxData <=#Tp 0;
1578 38 mohor
  else
1579 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1580 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1581 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1582
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1583
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1584
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1585
    endcase
1586 38 mohor
  else
1587 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1588 96 mohor
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1589
  else
1590 38 mohor
  if(TxUsedData & Flop)
1591
    begin
1592 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1593 226 tadejm
 
1594 82 mohor
        1 : TxData <=#Tp TxDataLatched[23:16];
1595
        2 : TxData <=#Tp TxDataLatched[15:8];
1596
        3 : TxData <=#Tp TxDataLatched[7:0];
1597 38 mohor
      endcase
1598
    end
1599
end
1600
 
1601
 
1602
// Latching tx data
1603 40 mohor
always @ (posedge MTxClk or posedge Reset)
1604 38 mohor
begin
1605 40 mohor
  if(Reset)
1606 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1607
  else
1608 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1609 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1610 38 mohor
end
1611
 
1612
 
1613
// Tx under run
1614 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1615 38 mohor
begin
1616 40 mohor
  if(Reset)
1617 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1618 38 mohor
  else
1619 39 mohor
  if(TxAbortPulse)
1620 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1621
  else
1622
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1623
    TxUnderRun_wb <=#Tp 1'b1;
1624
end
1625
 
1626
 
1627 159 mohor
reg TxUnderRun_sync1;
1628
 
1629 60 mohor
// Tx under run
1630
always @ (posedge MTxClk or posedge Reset)
1631
begin
1632
  if(Reset)
1633 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b0;
1634 43 mohor
  else
1635 60 mohor
  if(TxUnderRun_wb)
1636 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b1;
1637 60 mohor
  else
1638 159 mohor
  if(BlockingTxStatusWrite_sync2)
1639
    TxUnderRun_sync1 <=#Tp 1'b0;
1640
end
1641
 
1642
// Tx under run
1643
always @ (posedge MTxClk or posedge Reset)
1644
begin
1645
  if(Reset)
1646 60 mohor
    TxUnderRun <=#Tp 1'b0;
1647 159 mohor
  else
1648
  if(BlockingTxStatusWrite_sync2)
1649
    TxUnderRun <=#Tp 1'b0;
1650
  else
1651
  if(TxUnderRun_sync1)
1652
    TxUnderRun <=#Tp 1'b1;
1653 38 mohor
end
1654
 
1655
 
1656
// Tx Byte counter
1657 40 mohor
always @ (posedge MTxClk or posedge Reset)
1658 38 mohor
begin
1659 40 mohor
  if(Reset)
1660 38 mohor
    TxByteCnt <=#Tp 2'h0;
1661
  else
1662
  if(TxAbort_q | TxRetry_q)
1663
    TxByteCnt <=#Tp 2'h0;
1664
  else
1665
  if(TxStartFrm & ~TxUsedData)
1666 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1667 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1668
      2'h1 : TxByteCnt <=#Tp 2'h2;
1669
      2'h2 : TxByteCnt <=#Tp 2'h3;
1670
      2'h3 : TxByteCnt <=#Tp 2'h0;
1671
    endcase
1672 38 mohor
  else
1673
  if(TxUsedData & Flop)
1674 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1675 38 mohor
end
1676
 
1677 39 mohor
 
1678 150 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1679
reg ReadTxDataFromFifo_sync1;
1680
reg ReadTxDataFromFifo_sync2;
1681
reg ReadTxDataFromFifo_sync3;
1682
reg ReadTxDataFromFifo_syncb1;
1683
reg ReadTxDataFromFifo_syncb2;
1684
reg ReadTxDataFromFifo_syncb3;
1685
 
1686
 
1687
always @ (posedge MTxClk or posedge Reset)
1688
begin
1689
  if(Reset)
1690
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1691
  else
1692 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1693 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1694 150 mohor
  else
1695
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1696
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1697 38 mohor
end
1698
 
1699 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1700 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1701 38 mohor
begin
1702 40 mohor
  if(Reset)
1703 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1704 38 mohor
  else
1705 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1706
end
1707 38 mohor
 
1708 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1709 38 mohor
begin
1710 40 mohor
  if(Reset)
1711 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1712 38 mohor
  else
1713 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1714 38 mohor
end
1715
 
1716 40 mohor
always @ (posedge MTxClk or posedge Reset)
1717 38 mohor
begin
1718 40 mohor
  if(Reset)
1719 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1720 38 mohor
  else
1721 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1722 38 mohor
end
1723
 
1724 40 mohor
always @ (posedge MTxClk or posedge Reset)
1725 38 mohor
begin
1726 40 mohor
  if(Reset)
1727 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1728 38 mohor
  else
1729 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1730 38 mohor
end
1731
 
1732 150 mohor
always @ (posedge MTxClk or posedge Reset)
1733
begin
1734
  if(Reset)
1735
    ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
1736
  else
1737
    ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
1738
end
1739
 
1740 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1741 38 mohor
begin
1742 40 mohor
  if(Reset)
1743 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1744 38 mohor
  else
1745 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1746 38 mohor
end
1747
 
1748 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1749
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1750 38 mohor
 
1751
 
1752 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1753 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1754 38 mohor
begin
1755 40 mohor
  if(Reset)
1756 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1757 38 mohor
  else
1758 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1759 38 mohor
end
1760
 
1761 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1762 38 mohor
begin
1763 40 mohor
  if(Reset)
1764 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1765 38 mohor
  else
1766 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1767 38 mohor
end
1768
 
1769
 
1770 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1771 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1772 38 mohor
begin
1773 40 mohor
  if(Reset)
1774 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1775 38 mohor
  else
1776 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1777 38 mohor
end
1778
 
1779 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1780 38 mohor
begin
1781 40 mohor
  if(Reset)
1782 39 mohor
    TxDone_wb <=#Tp 1'b0;
1783 38 mohor
  else
1784 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1785 38 mohor
end
1786
 
1787 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1788 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1789 38 mohor
begin
1790 40 mohor
  if(Reset)
1791 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1792 38 mohor
  else
1793 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1794 38 mohor
end
1795
 
1796 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1797 38 mohor
begin
1798 40 mohor
  if(Reset)
1799 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1800
  else
1801 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1802 38 mohor
end
1803
 
1804
 
1805 150 mohor
reg RxAbortSync1;
1806
reg RxAbortSync2;
1807
reg RxAbortSync3;
1808
reg RxAbortSync4;
1809
reg RxAbortSyncb1;
1810
reg RxAbortSyncb2;
1811 39 mohor
 
1812 150 mohor
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
1813
 
1814 40 mohor
// Reading the Rx buffer descriptor
1815
always @ (posedge WB_CLK_I or posedge Reset)
1816
begin
1817
  if(Reset)
1818
    RxBDRead <=#Tp 1'b1;
1819
  else
1820 166 mohor
  if(StartRxBDRead & ~RxReady)
1821 40 mohor
    RxBDRead <=#Tp 1'b1;
1822
  else
1823
  if(RxBDReady)
1824
    RxBDRead <=#Tp 1'b0;
1825
end
1826 39 mohor
 
1827
 
1828 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1829
// written to the previous one.
1830
 
1831
// Latching READY status of the Rx buffer descriptor
1832 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1833 38 mohor
begin
1834 40 mohor
  if(Reset)
1835 38 mohor
    RxBDReady <=#Tp 1'b0;
1836
  else
1837 166 mohor
  if(RxPointerRead)
1838 150 mohor
    RxBDReady <=#Tp 1'b0;
1839
  else
1840 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1841
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1842 38 mohor
end
1843
 
1844 40 mohor
// Latching Rx buffer descriptor status
1845
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1846
always @ (posedge WB_CLK_I or posedge Reset)
1847 38 mohor
begin
1848 40 mohor
  if(Reset)
1849 60 mohor
    RxStatus <=#Tp 2'h0;
1850 38 mohor
  else
1851 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1852 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1853 38 mohor
end
1854
 
1855
 
1856 166 mohor
// RxReady generation
1857
always @ (posedge WB_CLK_I or posedge Reset)
1858
begin
1859
  if(Reset)
1860
    RxReady <=#Tp 1'b0;
1861
  else
1862
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
1863
    RxReady <=#Tp 1'b0;
1864
  else
1865
  if(RxEn & RxEn_q & RxPointerRead)
1866
    RxReady <=#Tp 1'b1;
1867
end
1868 38 mohor
 
1869
 
1870 40 mohor
// Reading Rx BD pointer
1871
 
1872
 
1873
assign StartRxPointerRead = RxBDRead & RxBDReady;
1874
 
1875
// Reading Tx BD Pointer
1876
always @ (posedge WB_CLK_I or posedge Reset)
1877 38 mohor
begin
1878 40 mohor
  if(Reset)
1879
    RxPointerRead <=#Tp 1'b0;
1880 38 mohor
  else
1881 40 mohor
  if(StartRxPointerRead)
1882
    RxPointerRead <=#Tp 1'b1;
1883 38 mohor
  else
1884 166 mohor
  if(RxEn & RxEn_q)
1885 40 mohor
    RxPointerRead <=#Tp 1'b0;
1886 38 mohor
end
1887
 
1888 113 mohor
 
1889 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1890
always @ (posedge WB_CLK_I or posedge Reset)
1891
begin
1892
  if(Reset)
1893 159 mohor
    RxPointerMSB <=#Tp 30'h0;
1894 40 mohor
  else
1895
  if(RxEn & RxEn_q & RxPointerRead)
1896 159 mohor
    RxPointerMSB <=#Tp ram_do[31:2];
1897 40 mohor
  else
1898 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1899 159 mohor
      RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1900 40 mohor
end
1901 38 mohor
 
1902
 
1903 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1904 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1905
begin
1906
  if(Reset)
1907 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp 0;
1908 96 mohor
  else
1909 159 mohor
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
1910
    RxPointerLSB_rst[1:0] <=#Tp 0;
1911 96 mohor
  else
1912
  if(RxEn & RxEn_q & RxPointerRead)
1913 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
1914 96 mohor
end
1915
 
1916
 
1917 159 mohor
always @ (RxPointerLSB_rst)
1918 96 mohor
begin
1919 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1920
    2'h0 : RxByteSel[3:0] = 4'hf;
1921
    2'h1 : RxByteSel[3:0] = 4'h7;
1922
    2'h2 : RxByteSel[3:0] = 4'h3;
1923
    2'h3 : RxByteSel[3:0] = 4'h1;
1924 96 mohor
  endcase
1925
end
1926
 
1927
 
1928
always @ (posedge WB_CLK_I or posedge Reset)
1929
begin
1930
  if(Reset)
1931 40 mohor
    RxEn_needed <=#Tp 1'b0;
1932 38 mohor
  else
1933 166 mohor
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1934 40 mohor
    RxEn_needed <=#Tp 1'b1;
1935 38 mohor
  else
1936 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1937
    RxEn_needed <=#Tp 1'b0;
1938 38 mohor
end
1939
 
1940
 
1941 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1942
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1943 38 mohor
 
1944 40 mohor
reg RxEnableWindow;
1945 38 mohor
 
1946
// Indicating that last byte is being reveived
1947 40 mohor
always @ (posedge MRxClk or posedge Reset)
1948 38 mohor
begin
1949 40 mohor
  if(Reset)
1950 38 mohor
    LastByteIn <=#Tp 1'b0;
1951
  else
1952 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1953 38 mohor
    LastByteIn <=#Tp 1'b0;
1954
  else
1955 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1956 38 mohor
    LastByteIn <=#Tp 1'b1;
1957
end
1958
 
1959 159 mohor
reg ShiftEnded_rck;
1960 40 mohor
reg ShiftEndedSync1;
1961
reg ShiftEndedSync2;
1962 118 mohor
reg ShiftEndedSync3;
1963
reg ShiftEndedSync_c1;
1964
reg ShiftEndedSync_c2;
1965
 
1966 40 mohor
wire StartShiftWillEnd;
1967 96 mohor
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1968 38 mohor
 
1969
// Indicating that data reception will end
1970 40 mohor
always @ (posedge MRxClk or posedge Reset)
1971 38 mohor
begin
1972 40 mohor
  if(Reset)
1973 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1974
  else
1975 159 mohor
  if(ShiftEnded_rck | RxAbort)
1976 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1977
  else
1978 40 mohor
  if(StartShiftWillEnd)
1979 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
1980
end
1981
 
1982
 
1983 40 mohor
 
1984 38 mohor
// Receive byte counter
1985 40 mohor
always @ (posedge MRxClk or posedge Reset)
1986 38 mohor
begin
1987 40 mohor
  if(Reset)
1988 38 mohor
    RxByteCnt <=#Tp 2'h0;
1989
  else
1990 159 mohor
  if(ShiftEnded_rck | RxAbort)
1991 38 mohor
    RxByteCnt <=#Tp 2'h0;
1992 97 lampret
  else
1993 166 mohor
  if(RxValid & RxStartFrm & RxReady)
1994 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
1995 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
1996
      2'h1 : RxByteCnt <=#Tp 2'h2;
1997
      2'h2 : RxByteCnt <=#Tp 2'h3;
1998
      2'h3 : RxByteCnt <=#Tp 2'h0;
1999
    endcase
2000 38 mohor
  else
2001 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
2002 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
2003 38 mohor
end
2004
 
2005
 
2006
// Indicates how many bytes are valid within the last word
2007 40 mohor
always @ (posedge MRxClk or posedge Reset)
2008 38 mohor
begin
2009 40 mohor
  if(Reset)
2010 38 mohor
    RxValidBytes <=#Tp 2'h1;
2011
  else
2012 96 mohor
  if(RxValid & RxStartFrm)
2013 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2014 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
2015
      2'h1 : RxValidBytes <=#Tp 2'h2;
2016
      2'h2 : RxValidBytes <=#Tp 2'h3;
2017
      2'h3 : RxValidBytes <=#Tp 2'h0;
2018
    endcase
2019 38 mohor
  else
2020 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2021 38 mohor
    RxValidBytes <=#Tp RxValidBytes + 1;
2022
end
2023
 
2024
 
2025 40 mohor
always @ (posedge MRxClk or posedge Reset)
2026 38 mohor
begin
2027 40 mohor
  if(Reset)
2028
    RxDataLatched1       <=#Tp 24'h0;
2029 38 mohor
  else
2030 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2031 96 mohor
    if(RxStartFrm)
2032 40 mohor
    begin
2033 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2034 96 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2035
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2036
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2037
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2038
      endcase
2039
    end
2040
    else if (RxEnableWindow)
2041
    begin
2042 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2043 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2044
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2045
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2046 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2047
      endcase
2048
    end
2049 38 mohor
end
2050
 
2051 40 mohor
wire SetWriteRxDataToFifo;
2052 38 mohor
 
2053 40 mohor
// Assembling data that will be written to the rx_fifo
2054
always @ (posedge MRxClk or posedge Reset)
2055 38 mohor
begin
2056 40 mohor
  if(Reset)
2057
    RxDataLatched2 <=#Tp 32'h0;
2058 38 mohor
  else
2059 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2060 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
2061 38 mohor
  else
2062 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2063 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2064 82 mohor
 
2065
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2066
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
2067
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
2068 40 mohor
    endcase
2069 38 mohor
end
2070
 
2071
 
2072 40 mohor
reg WriteRxDataToFifoSync1;
2073
reg WriteRxDataToFifoSync2;
2074 150 mohor
reg WriteRxDataToFifoSync3;
2075 38 mohor
 
2076
 
2077 40 mohor
// Indicating start of the reception process
2078 166 mohor
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
2079
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
2080
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
2081 38 mohor
 
2082 150 mohor
always @ (posedge MRxClk or posedge Reset)
2083
begin
2084
  if(Reset)
2085
    WriteRxDataToFifo <=#Tp 1'b0;
2086
  else
2087
  if(SetWriteRxDataToFifo & ~RxAbort)
2088
    WriteRxDataToFifo <=#Tp 1'b1;
2089
  else
2090
  if(WriteRxDataToFifoSync2 | RxAbort)
2091
    WriteRxDataToFifo <=#Tp 1'b0;
2092
end
2093 40 mohor
 
2094 150 mohor
 
2095
 
2096
always @ (posedge WB_CLK_I or posedge Reset)
2097
begin
2098
  if(Reset)
2099
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2100
  else
2101
  if(WriteRxDataToFifo)
2102
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
2103
  else
2104
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2105
end
2106
 
2107
always @ (posedge WB_CLK_I or posedge Reset)
2108
begin
2109
  if(Reset)
2110
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
2111
  else
2112
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
2113
end
2114
 
2115
always @ (posedge WB_CLK_I or posedge Reset)
2116
begin
2117
  if(Reset)
2118
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
2119
  else
2120
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
2121
end
2122
 
2123
wire WriteRxDataToFifo_wb;
2124
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
2125
 
2126
 
2127 90 mohor
reg LatchedRxStartFrm;
2128
reg SyncRxStartFrm;
2129
reg SyncRxStartFrm_q;
2130 150 mohor
reg SyncRxStartFrm_q2;
2131 90 mohor
wire RxFifoReset;
2132 40 mohor
 
2133 90 mohor
always @ (posedge MRxClk or posedge Reset)
2134
begin
2135
  if(Reset)
2136
    LatchedRxStartFrm <=#Tp 0;
2137
  else
2138 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2139 90 mohor
    LatchedRxStartFrm <=#Tp 1;
2140
  else
2141 150 mohor
  if(SyncRxStartFrm_q)
2142 90 mohor
    LatchedRxStartFrm <=#Tp 0;
2143
end
2144
 
2145
 
2146
always @ (posedge WB_CLK_I or posedge Reset)
2147
begin
2148
  if(Reset)
2149
    SyncRxStartFrm <=#Tp 0;
2150
  else
2151
  if(LatchedRxStartFrm)
2152
    SyncRxStartFrm <=#Tp 1;
2153
  else
2154
    SyncRxStartFrm <=#Tp 0;
2155
end
2156
 
2157
 
2158
always @ (posedge WB_CLK_I or posedge Reset)
2159
begin
2160
  if(Reset)
2161
    SyncRxStartFrm_q <=#Tp 0;
2162
  else
2163
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
2164
end
2165
 
2166 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2167
begin
2168
  if(Reset)
2169
    SyncRxStartFrm_q2 <=#Tp 0;
2170
  else
2171
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
2172
end
2173 90 mohor
 
2174
 
2175 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2176 90 mohor
 
2177 150 mohor
 
2178 219 mohor
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
2179 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
2180
         .clk(WB_CLK_I),                                .reset(Reset),
2181 219 mohor
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
2182 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
2183 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
2184 150 mohor
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
2185 88 mohor
        );
2186 40 mohor
 
2187 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2188
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2189 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2190 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2191 40 mohor
 
2192
 
2193
// Generation of the end-of-frame signal
2194
always @ (posedge MRxClk or posedge Reset)
2195 38 mohor
begin
2196 40 mohor
  if(Reset)
2197 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2198 38 mohor
  else
2199 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2200 159 mohor
    ShiftEnded_rck <=#Tp 1'b1;
2201 38 mohor
  else
2202 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2203 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2204 38 mohor
end
2205
 
2206 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2207
begin
2208
  if(Reset)
2209
    ShiftEndedSync1 <=#Tp 1'b0;
2210
  else
2211 159 mohor
    ShiftEndedSync1 <=#Tp ShiftEnded_rck;
2212 40 mohor
end
2213 38 mohor
 
2214 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2215 38 mohor
begin
2216 40 mohor
  if(Reset)
2217
    ShiftEndedSync2 <=#Tp 1'b0;
2218 38 mohor
  else
2219 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
2220 40 mohor
end
2221 38 mohor
 
2222 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2223
begin
2224
  if(Reset)
2225
    ShiftEndedSync3 <=#Tp 1'b0;
2226
  else
2227
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2228
    ShiftEndedSync3 <=#Tp 1'b1;
2229
  else
2230
  if(ShiftEnded)
2231
    ShiftEndedSync3 <=#Tp 1'b0;
2232
end
2233 38 mohor
 
2234 40 mohor
// Generation of the end-of-frame signal
2235
always @ (posedge WB_CLK_I or posedge Reset)
2236 38 mohor
begin
2237 40 mohor
  if(Reset)
2238
    ShiftEnded <=#Tp 1'b0;
2239 38 mohor
  else
2240 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2241 40 mohor
    ShiftEnded <=#Tp 1'b1;
2242 38 mohor
  else
2243 40 mohor
  if(RxStatusWrite)
2244
    ShiftEnded <=#Tp 1'b0;
2245 38 mohor
end
2246
 
2247 118 mohor
always @ (posedge MRxClk or posedge Reset)
2248
begin
2249
  if(Reset)
2250
    ShiftEndedSync_c1 <=#Tp 1'b0;
2251
  else
2252
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
2253
end
2254 38 mohor
 
2255 118 mohor
always @ (posedge MRxClk or posedge Reset)
2256
begin
2257
  if(Reset)
2258
    ShiftEndedSync_c2 <=#Tp 1'b0;
2259
  else
2260
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
2261
end
2262
 
2263 40 mohor
// Generation of the end-of-frame signal
2264
always @ (posedge MRxClk or posedge Reset)
2265 38 mohor
begin
2266 40 mohor
  if(Reset)
2267
    RxEnableWindow <=#Tp 1'b0;
2268 38 mohor
  else
2269 40 mohor
  if(RxStartFrm)
2270
    RxEnableWindow <=#Tp 1'b1;
2271 38 mohor
  else
2272 40 mohor
  if(RxEndFrm | RxAbort)
2273
    RxEnableWindow <=#Tp 1'b0;
2274 38 mohor
end
2275
 
2276
 
2277 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2278 38 mohor
begin
2279 40 mohor
  if(Reset)
2280
    RxAbortSync1 <=#Tp 1'b0;
2281 38 mohor
  else
2282 150 mohor
    RxAbortSync1 <=#Tp RxAbortLatched;
2283 40 mohor
end
2284
 
2285
always @ (posedge WB_CLK_I or posedge Reset)
2286
begin
2287
  if(Reset)
2288
    RxAbortSync2 <=#Tp 1'b0;
2289 38 mohor
  else
2290 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
2291 38 mohor
end
2292
 
2293 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2294
begin
2295
  if(Reset)
2296
    RxAbortSync3 <=#Tp 1'b0;
2297
  else
2298
    RxAbortSync3 <=#Tp RxAbortSync2;
2299
end
2300
 
2301
always @ (posedge WB_CLK_I or posedge Reset)
2302
begin
2303
  if(Reset)
2304
    RxAbortSync4 <=#Tp 1'b0;
2305
  else
2306
    RxAbortSync4 <=#Tp RxAbortSync3;
2307
end
2308
 
2309 40 mohor
always @ (posedge MRxClk or posedge Reset)
2310
begin
2311
  if(Reset)
2312
    RxAbortSyncb1 <=#Tp 1'b0;
2313
  else
2314
    RxAbortSyncb1 <=#Tp RxAbortSync2;
2315
end
2316 38 mohor
 
2317 40 mohor
always @ (posedge MRxClk or posedge Reset)
2318 38 mohor
begin
2319 40 mohor
  if(Reset)
2320
    RxAbortSyncb2 <=#Tp 1'b0;
2321 38 mohor
  else
2322 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
2323 38 mohor
end
2324
 
2325
 
2326 64 mohor
always @ (posedge MRxClk or posedge Reset)
2327
begin
2328
  if(Reset)
2329
    RxAbortLatched <=#Tp 1'b0;
2330
  else
2331 150 mohor
  if(RxAbortSyncb2)
2332
    RxAbortLatched <=#Tp 1'b0;
2333
  else
2334 64 mohor
  if(RxAbort)
2335
    RxAbortLatched <=#Tp 1'b1;
2336
end
2337 40 mohor
 
2338 64 mohor
 
2339 42 mohor
always @ (posedge MRxClk or posedge Reset)
2340
begin
2341
  if(Reset)
2342
    LatchedRxLength[15:0] <=#Tp 16'h0;
2343
  else
2344 150 mohor
  if(LoadRxStatus)
2345 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
2346
end
2347
 
2348
 
2349 261 mohor
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2350 42 mohor
 
2351
always @ (posedge MRxClk or posedge Reset)
2352
begin
2353
  if(Reset)
2354
    RxStatusInLatched <=#Tp 'h0;
2355
  else
2356 150 mohor
  if(LoadRxStatus)
2357 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
2358
end
2359
 
2360
 
2361 60 mohor
// Rx overrun
2362
always @ (posedge WB_CLK_I or posedge Reset)
2363
begin
2364
  if(Reset)
2365
    RxOverrun <=#Tp 1'b0;
2366
  else
2367
  if(RxStatusWrite)
2368
    RxOverrun <=#Tp 1'b0;
2369
  else
2370
  if(RxBufferFull & WriteRxDataToFifo_wb)
2371
    RxOverrun <=#Tp 1'b1;
2372
end
2373 48 mohor
 
2374 77 mohor
 
2375
 
2376
wire TxError;
2377
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2378
 
2379
wire RxError;
2380
 
2381 239 tadejm
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
2382 250 mohor
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
2383
// AddressMiss is identifying that a frame was received because of the promiscous
2384
// mode and is not an error
2385 239 tadejm
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
2386
 
2387 77 mohor
// Tx Done Interrupt
2388
always @ (posedge WB_CLK_I or posedge Reset)
2389
begin
2390
  if(Reset)
2391
    TxB_IRQ <=#Tp 1'b0;
2392
  else
2393
  if(TxStatusWrite & TxIRQEn)
2394
    TxB_IRQ <=#Tp ~TxError;
2395
  else
2396
    TxB_IRQ <=#Tp 1'b0;
2397
end
2398
 
2399
 
2400
// Tx Error Interrupt
2401
always @ (posedge WB_CLK_I or posedge Reset)
2402
begin
2403
  if(Reset)
2404
    TxE_IRQ <=#Tp 1'b0;
2405
  else
2406
  if(TxStatusWrite & TxIRQEn)
2407
    TxE_IRQ <=#Tp TxError;
2408
  else
2409
    TxE_IRQ <=#Tp 1'b0;
2410
end
2411
 
2412
 
2413
// Rx Done Interrupt
2414
always @ (posedge WB_CLK_I or posedge Reset)
2415
begin
2416
  if(Reset)
2417
    RxB_IRQ <=#Tp 1'b0;
2418
  else
2419
  if(RxStatusWrite & RxIRQEn)
2420 261 mohor
    RxB_IRQ <=#Tp ReceivedPacketGood & (~RxError) & (~r_RxFlow); // When r_RxFlow is set, RXC irq is set.
2421 77 mohor
  else
2422
    RxB_IRQ <=#Tp 1'b0;
2423
end
2424
 
2425
 
2426
// Rx Error Interrupt
2427
always @ (posedge WB_CLK_I or posedge Reset)
2428
begin
2429
  if(Reset)
2430
    RxE_IRQ <=#Tp 1'b0;
2431
  else
2432
  if(RxStatusWrite & RxIRQEn)
2433
    RxE_IRQ <=#Tp RxError;
2434
  else
2435
    RxE_IRQ <=#Tp 1'b0;
2436
end
2437
 
2438
 
2439 166 mohor
// Busy Interrupt
2440 77 mohor
 
2441 166 mohor
reg Busy_IRQ_rck;
2442
reg Busy_IRQ_sync1;
2443
reg Busy_IRQ_sync2;
2444
reg Busy_IRQ_sync3;
2445
reg Busy_IRQ_syncb1;
2446
reg Busy_IRQ_syncb2;
2447 77 mohor
 
2448
 
2449 166 mohor
always @ (posedge MRxClk or posedge Reset)
2450
begin
2451
  if(Reset)
2452
    Busy_IRQ_rck <=#Tp 1'b0;
2453
  else
2454
  if(RxValid & RxStartFrm & ~RxReady)
2455
    Busy_IRQ_rck <=#Tp 1'b1;
2456
  else
2457
  if(Busy_IRQ_syncb2)
2458
    Busy_IRQ_rck <=#Tp 1'b0;
2459
end
2460 77 mohor
 
2461 166 mohor
always @ (posedge WB_CLK_I)
2462
begin
2463
    Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
2464
    Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
2465
    Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
2466
end
2467
 
2468
always @ (posedge MRxClk)
2469
begin
2470
    Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
2471
    Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
2472
end
2473
 
2474
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
2475
 
2476
 
2477 60 mohor
 
2478
// TX
2479 61 mohor
// bit 15 ready
2480
// bit 14 interrupt
2481
// bit 13 wrap
2482
// bit 12 pad
2483
// bit 11 crc
2484
// bit 10 last
2485
// bit 9  pause request (control frame)
2486
// bit 8  TxUnderRun          
2487
// bit 7-4 RetryCntLatched    
2488
// bit 3  retransmittion limit
2489
// bit 2  LateCollLatched        
2490
// bit 1  DeferLatched        
2491
// bit 0  CarrierSenseLost    
2492 60 mohor
 
2493
 
2494
// RX
2495
// bit 15 od rx je empty
2496 61 mohor
// bit 14 od rx je interrupt
2497 60 mohor
// bit 13 od rx je wrap
2498
// bit 12 od rx je reserved
2499
// bit 11 od rx je reserved
2500
// bit 10 od rx je reserved
2501
// bit 9  od rx je reserved
2502
// bit 8  od rx je reserved
2503 110 mohor
// bit 7  od rx je Miss
2504 60 mohor
// bit 6  od rx je RxOverrun
2505
// bit 5  od rx je InvalidSymbol
2506
// bit 4  od rx je DribbleNibble
2507
// bit 3  od rx je ReceivedPacketTooBig
2508
// bit 2  od rx je ShortFrame
2509
// bit 1  od rx je LatchedCrcError
2510
// bit 0  od rx je RxLateCollision
2511
 
2512 110 mohor
 
2513 38 mohor
endmodule
2514
 

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