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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 272

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 272 tadejm
// Revision 1.49  2003/01/21 12:09:40  mohor
45
// When receiving normal data frame and RxFlow control was switched on, RXB
46
// interrupt was not set.
47
//
48 270 mohor
// Revision 1.48  2003/01/20 12:05:26  mohor
49
// When in full duplex, transmit was sometimes blocked. Fixed.
50
//
51 269 mohor
// Revision 1.47  2002/11/22 13:26:21  mohor
52
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
53
// anywhere. Removed.
54
//
55 264 mohor
// Revision 1.46  2002/11/22 01:57:06  mohor
56
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
57
// synchronized.
58
//
59 261 mohor
// Revision 1.45  2002/11/19 17:33:34  mohor
60
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
61
// that a frame was received because of the promiscous mode.
62
//
63 250 mohor
// Revision 1.44  2002/11/13 22:21:40  tadejm
64
// RxError is not generated when small frame reception is enabled and small
65
// frames are received.
66
//
67 239 tadejm
// Revision 1.43  2002/10/18 20:53:34  mohor
68
// case changed to casex.
69
//
70 229 mohor
// Revision 1.42  2002/10/18 17:04:20  tadejm
71
// Changed BIST scan signals.
72
//
73 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
74
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
75
//
76 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
77
// TxStatus is written after last access to the TX fifo is finished (in case of abort
78
// or retry). TxDone is fixed.
79
//
80 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
81
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
82
// TxDone and TxRetry are generated after the current WISHBONE access is
83
// finished.
84
//
85 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
86
// BIST added.
87
//
88 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
89
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
90
//
91 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
92
// Reception is possible after RxPointer is read and not after BD is read. For
93
// that reason RxBDReady is changed to RxReady.
94
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
95
// comes, interrupt is generated.
96
//
97 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
98
// Ethernet debug registers removed.
99
//
100 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
101
// Async reset for WB_ACK_O removed (when core was in reset, it was
102
// impossible to access BDs).
103
// RxPointers and TxPointers names changed to be more descriptive.
104
// TxUnderRun synchronized.
105
//
106 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
107
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
108
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
109
// was not used OK.
110
//
111 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
112
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
113
// need to multiply or devide any more.
114
//
115 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
116
// WriteRxDataToMemory signal changed so end of frame (when last word is
117
// written to fifo) is changed.
118
//
119 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
120
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
121
//
122 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
123
// ShiftEnded synchronization changed.
124
//
125 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
126
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
127
//
128 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
129
// RxPointer bug fixed.
130
//
131 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
132
// Previous bug wasn't succesfully removed. Now fixed.
133
//
134 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
135
// Master state machine had a bug when switching from master write to
136
// master read.
137
//
138 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
139
// m_wb_cyc_o signal released after every single transfer.
140
//
141 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
142
// Outputs registered. Reset changed for eth_wishbone module.
143
//
144 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
145
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
146
// bug fixed.
147
//
148 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
149
// Small typo fixed.
150
//
151 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
152
// Any address can be used for Tx and Rx BD pointers. Address does not need
153
// to be aligned.
154
//
155 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
156
// Comments in Slovene language removed.
157
//
158 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
159
// casex changed with case, fifo reset changed.
160
//
161 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
162
// rx_fifo was not always cleared ok. Fixed.
163
//
164 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
165
// Status was not latched correctly sometimes. Fixed.
166
//
167 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
168
// Big Endian problem when sending frames fixed.
169
//
170 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
171
// Byte ordering changed (Big Endian used). casex changed with case because
172
// Xilinx Foundation had problems. Tested in HW. It WORKS.
173
//
174 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
175
// Small fixes for external/internal DMA missmatches.
176
//
177 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
178
// Interrupts changed
179
//
180 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
181
// Status was not written correctly when frames were discarted because of
182
// address mismatch.
183
//
184 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
185
// RxStartFrm cleared when abort or retry comes.
186
//
187 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
188
// Changes that were lost when updating from 1.5 to 1.8 fixed.
189
//
190 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
191
// Addition  of new module eth_addrcheck.v
192
//
193
// Revision 1.7  2002/02/12 17:03:47  mohor
194
// RxOverRun added to statuses.
195
//
196
// Revision 1.6  2002/02/11 09:18:22  mohor
197
// Tx status is written back to the BD.
198
//
199 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
200
// Rx status is written back to the BD.
201
//
202 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
203
// non-DMA host interface added. Select the right configutation in eth_defines.
204
//
205 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
206
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
207
// MHz. Statuses, overrun, control frame transmission and reception still  need
208
// to be fixed.
209
//
210 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
211
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
212
// added.
213
//
214 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
215
// Initial version. Equals to eth_wishbonedma.v at this moment.
216 38 mohor
//
217
//
218
//
219
 
220
`include "eth_defines.v"
221
`include "timescale.v"
222
 
223
 
224
module eth_wishbone
225
   (
226
 
227
    // WISHBONE common
228 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
229 38 mohor
 
230
    // WISHBONE slave
231 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
232 40 mohor
    BDCs,
233 38 mohor
 
234 40 mohor
    Reset,
235
 
236 39 mohor
    // WISHBONE master
237
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
238
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
239
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
240
 
241 219 mohor
`ifdef ETH_WISHBONE_B3
242
    m_wb_cti_o, m_wb_bte_o,
243
`endif
244
 
245 38 mohor
    //TX
246 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
247 150 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
248 38 mohor
    PerPacketPad,
249
 
250
    //RX
251 272 tadejm
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
252 38 mohor
 
253
    // Register
254 270 mohor
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow, r_PassAll,
255 38 mohor
 
256
    // Interrupts
257 150 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
258 42 mohor
 
259 60 mohor
    // Rx Status
260 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
261 250 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
262 261 mohor
    ReceivedPauseFrm,
263 60 mohor
 
264
    // Tx Status
265 164 mohor
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
266
 
267 210 mohor
    // Bist
268
`ifdef ETH_BIST
269 227 tadejm
    ,
270
    // debug chain signals
271
    scanb_rst,      // bist scan reset
272
    scanb_clk,      // bist scan clock
273
    scanb_si,       // bist scan serial in
274
    scanb_so,       // bist scan serial out
275
    scanb_en        // bist scan shift enable
276 210 mohor
`endif
277
 
278
 
279
 
280 38 mohor
                );
281
 
282
 
283
parameter Tp = 1;
284
 
285 150 mohor
 
286 38 mohor
// WISHBONE common
287
input           WB_CLK_I;       // WISHBONE clock
288
input  [31:0]   WB_DAT_I;       // WISHBONE data input
289
output [31:0]   WB_DAT_O;       // WISHBONE data output
290
 
291
// WISHBONE slave
292
input   [9:2]   WB_ADR_I;       // WISHBONE address input
293
input           WB_WE_I;        // WISHBONE write enable input
294
input           BDCs;           // Buffer descriptors are selected
295
output          WB_ACK_O;       // WISHBONE acknowledge output
296
 
297 39 mohor
// WISHBONE master
298
output  [31:0]  m_wb_adr_o;     // 
299
output   [3:0]  m_wb_sel_o;     // 
300
output          m_wb_we_o;      // 
301
output  [31:0]  m_wb_dat_o;     // 
302
output          m_wb_cyc_o;     // 
303
output          m_wb_stb_o;     // 
304
input   [31:0]  m_wb_dat_i;     // 
305
input           m_wb_ack_i;     // 
306
input           m_wb_err_i;     // 
307
 
308 219 mohor
`ifdef ETH_WISHBONE_B3
309
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
310
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
311
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
312
`endif
313
 
314 40 mohor
input           Reset;       // Reset signal
315 39 mohor
 
316 60 mohor
// Rx Status signals
317 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
318
input           LatchedCrcError;  // CRC error
319
input           RxLateCollision;  // Late collision occured while receiving frame
320
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
321
input           DribbleNibble;    // Extra nibble received
322
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
323
input    [15:0] RxLength;         // Length of the incoming frame
324
input           LoadRxStatus;     // Rx status was loaded
325 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
326 250 mohor
input           AddressMiss;      // When a packet is received AddressMiss status is written to the Rx BD
327 261 mohor
input           r_RxFlow;
328 270 mohor
input           r_PassAll;
329 261 mohor
input           ReceivedPauseFrm;
330 39 mohor
 
331 60 mohor
// Tx Status signals
332
input     [3:0] RetryCntLatched;  // Latched Retry Counter
333
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
334
input           LateCollLatched;  // Late collision occured
335
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
336
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
337
 
338 38 mohor
// Tx
339
input           MTxClk;         // Transmit clock (from PHY)
340
input           TxUsedData;     // Transmit packet used data
341
input           TxRetry;        // Transmit packet retry
342
input           TxAbort;        // Transmit packet abort
343
input           TxDone;         // Transmission ended
344
output          TxStartFrm;     // Transmit packet start frame
345
output          TxEndFrm;       // Transmit packet end frame
346
output  [7:0]   TxData;         // Transmit packet data byte
347
output          TxUnderRun;     // Transmit packet under-run
348
output          PerPacketCrcEn; // Per packet crc enable
349
output          PerPacketPad;   // Per packet pading
350
 
351
// Rx
352
input           MRxClk;         // Receive clock (from PHY)
353
input   [7:0]   RxData;         // Received data byte (from PHY)
354
input           RxValid;        // 
355
input           RxStartFrm;     // 
356
input           RxEndFrm;       // 
357 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
358 272 tadejm
output          RxStatusWriteLatched_sync2;
359 38 mohor
 
360
//Register
361
input           r_TxEn;         // Transmit enable
362
input           r_RxEn;         // Receive enable
363
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
364
input           TX_BD_NUM_Wr;   // RxBDNumber written
365
 
366
// Interrupts
367
output TxB_IRQ;
368
output TxE_IRQ;
369
output RxB_IRQ;
370 77 mohor
output RxE_IRQ;
371 38 mohor
output Busy_IRQ;
372
 
373 77 mohor
 
374 210 mohor
// Bist
375
`ifdef ETH_BIST
376 227 tadejm
input   scanb_rst;      // bist scan reset
377
input   scanb_clk;      // bist scan clock
378
input   scanb_si;       // bist scan serial in
379
output  scanb_so;       // bist scan serial out
380
input   scanb_en;       // bist scan shift enable
381 210 mohor
`endif
382
 
383 77 mohor
reg TxB_IRQ;
384
reg TxE_IRQ;
385
reg RxB_IRQ;
386
reg RxE_IRQ;
387
 
388 38 mohor
reg             TxStartFrm;
389
reg             TxEndFrm;
390
reg     [7:0]   TxData;
391
 
392
reg             TxUnderRun;
393 60 mohor
reg             TxUnderRun_wb;
394 38 mohor
 
395
reg             TxBDRead;
396 39 mohor
wire            TxStatusWrite;
397 38 mohor
 
398
reg     [1:0]   TxValidBytesLatched;
399
 
400
reg    [15:0]   TxLength;
401 60 mohor
reg    [15:0]   LatchedTxLength;
402
reg   [14:11]   TxStatus;
403 38 mohor
 
404 60 mohor
reg   [14:13]   RxStatus;
405 38 mohor
 
406
reg             TxStartFrm_wb;
407
reg             TxRetry_wb;
408 39 mohor
reg             TxAbort_wb;
409 38 mohor
reg             TxDone_wb;
410
 
411
reg             TxDone_wb_q;
412
reg             TxAbort_wb_q;
413 39 mohor
reg             TxRetry_wb_q;
414 219 mohor
reg             TxRetryPacket;
415 221 mohor
reg             TxRetryPacket_NotCleared;
416
reg             TxDonePacket;
417
reg             TxDonePacket_NotCleared;
418 219 mohor
reg             TxAbortPacket;
419 221 mohor
reg             TxAbortPacket_NotCleared;
420 38 mohor
reg             RxBDReady;
421 166 mohor
reg             RxReady;
422 38 mohor
reg             TxBDReady;
423
 
424
reg             RxBDRead;
425
 
426
reg    [31:0]   TxDataLatched;
427
reg     [1:0]   TxByteCnt;
428
reg             LastWord;
429 39 mohor
reg             ReadTxDataFromFifo_tck;
430 38 mohor
 
431
reg             BlockingTxStatusWrite;
432
reg             BlockingTxBDRead;
433
 
434 40 mohor
reg             Flop;
435 38 mohor
 
436
reg     [7:0]   TxBDAddress;
437
reg     [7:0]   RxBDAddress;
438
 
439
reg             TxRetrySync1;
440
reg             TxAbortSync1;
441 39 mohor
reg             TxDoneSync1;
442 38 mohor
 
443
reg             TxAbort_q;
444
reg             TxRetry_q;
445
reg             TxUsedData_q;
446
 
447
reg    [31:0]   RxDataLatched2;
448 82 mohor
 
449
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
450
 
451 38 mohor
reg     [1:0]   RxValidBytes;
452
reg     [1:0]   RxByteCnt;
453
reg             LastByteIn;
454
reg             ShiftWillEnd;
455
 
456 40 mohor
reg             WriteRxDataToFifo;
457 42 mohor
reg    [15:0]   LatchedRxLength;
458 64 mohor
reg             RxAbortLatched;
459 38 mohor
 
460 40 mohor
reg             ShiftEnded;
461 60 mohor
reg             RxOverrun;
462 38 mohor
 
463 40 mohor
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
464
reg             BDRead;                     // BD Read access from WISHBONE side
465 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
466
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
467 38 mohor
 
468 39 mohor
reg             TxEndFrm_wb;
469 38 mohor
 
470 39 mohor
wire            TxRetryPulse;
471 38 mohor
wire            TxDonePulse;
472
wire            TxAbortPulse;
473
 
474
wire            StartRxBDRead;
475
 
476
wire            StartTxBDRead;
477
 
478
wire            TxIRQEn;
479
wire            WrapTxStatusBit;
480
 
481 77 mohor
wire            RxIRQEn;
482 38 mohor
wire            WrapRxStatusBit;
483
 
484
wire    [1:0]   TxValidBytes;
485
 
486
wire    [7:0]   TempTxBDAddress;
487
wire    [7:0]   TempRxBDAddress;
488
 
489
wire            SetGotData;
490
wire            GotDataEvaluate;
491
 
492 272 tadejm
wire            RxStatusWrite;
493
 
494 106 mohor
reg             WB_ACK_O;
495 38 mohor
 
496 261 mohor
wire    [8:0]   RxStatusIn;
497
reg     [8:0]   RxStatusInLatched;
498 42 mohor
 
499 39 mohor
reg WbEn, WbEn_q;
500
reg RxEn, RxEn_q;
501
reg TxEn, TxEn_q;
502 38 mohor
 
503 39 mohor
wire ram_ce;
504
wire ram_we;
505
wire ram_oe;
506
reg [7:0]   ram_addr;
507
reg [31:0]  ram_di;
508
wire [31:0] ram_do;
509 38 mohor
 
510 39 mohor
wire StartTxPointerRead;
511
reg  TxPointerRead;
512
reg TxEn_needed;
513 40 mohor
reg RxEn_needed;
514 38 mohor
 
515 40 mohor
wire StartRxPointerRead;
516
reg RxPointerRead;
517 38 mohor
 
518 219 mohor
`ifdef ETH_WISHBONE_B3
519
assign m_wb_bte_o = 2'b00;    // Linear burst
520
`endif
521 39 mohor
 
522 219 mohor
 
523 159 mohor
always @ (posedge WB_CLK_I)
524 40 mohor
begin
525 159 mohor
  WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
526 40 mohor
end
527 39 mohor
 
528 106 mohor
assign WB_DAT_O = ram_do;
529 39 mohor
 
530 41 mohor
// Generic synchronous single-port RAM interface
531 119 mohor
eth_spram_256x32 bd_ram (
532 226 tadejm
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
533 210 mohor
`ifdef ETH_BIST
534 227 tadejm
  ,
535
  .scanb_rst      (scanb_rst),
536
  .scanb_clk      (scanb_clk),
537
  .scanb_si       (scanb_si),
538
  .scanb_so       (scanb_so),
539
  .scanb_en       (scanb_en)
540 210 mohor
`endif
541 39 mohor
);
542 41 mohor
 
543 39 mohor
assign ram_ce = 1'b1;
544 40 mohor
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
545 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
546 39 mohor
 
547
 
548 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
549 38 mohor
begin
550 40 mohor
  if(Reset)
551 39 mohor
    TxEn_needed <=#Tp 1'b0;
552 38 mohor
  else
553 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
554 39 mohor
    TxEn_needed <=#Tp 1'b1;
555
  else
556
  if(TxPointerRead & TxEn & TxEn_q)
557
    TxEn_needed <=#Tp 1'b0;
558 38 mohor
end
559
 
560 39 mohor
// Enabling access to the RAM for three devices.
561 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
562 39 mohor
begin
563 40 mohor
  if(Reset)
564 39 mohor
    begin
565
      WbEn <=#Tp 1'b1;
566
      RxEn <=#Tp 1'b0;
567
      TxEn <=#Tp 1'b0;
568
      ram_addr <=#Tp 8'h0;
569
      ram_di <=#Tp 32'h0;
570 77 mohor
      BDRead <=#Tp 1'b0;
571
      BDWrite <=#Tp 1'b0;
572 39 mohor
    end
573
  else
574
    begin
575
      // Switching between three stages depends on enable signals
576 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
577
        5'b100_10, 5'b100_11 :
578 39 mohor
          begin
579
            WbEn <=#Tp 1'b0;
580
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
581
            TxEn <=#Tp 1'b0;
582 40 mohor
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
583 39 mohor
            ram_di <=#Tp RxBDDataIn;
584
          end
585
        5'b100_01 :
586
          begin
587
            WbEn <=#Tp 1'b0;
588
            RxEn <=#Tp 1'b0;
589
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
590
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
591
            ram_di <=#Tp TxBDDataIn;
592
          end
593 90 mohor
        5'b010_00, 5'b010_10 :
594 39 mohor
          begin
595
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
596
            RxEn <=#Tp 1'b0;
597
            TxEn <=#Tp 1'b0;
598
            ram_addr <=#Tp WB_ADR_I[9:2];
599
            ram_di <=#Tp WB_DAT_I;
600 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
601
            BDRead <=#Tp BDCs & ~WB_WE_I;
602 39 mohor
          end
603 90 mohor
        5'b010_01, 5'b010_11 :
604 39 mohor
          begin
605
            WbEn <=#Tp 1'b0;
606
            RxEn <=#Tp 1'b0;
607
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
608
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
609
            ram_di <=#Tp TxBDDataIn;
610
          end
611 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
612 39 mohor
          begin
613
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
614
            RxEn <=#Tp 1'b0;
615
            TxEn <=#Tp 1'b0;
616
            ram_addr <=#Tp WB_ADR_I[9:2];
617
            ram_di <=#Tp WB_DAT_I;
618 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
619
            BDRead <=#Tp BDCs & ~WB_WE_I;
620 39 mohor
          end
621
        5'b100_00 :
622
          begin
623
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
624
          end
625
        5'b000_00 :
626
          begin
627
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
628
            RxEn <=#Tp 1'b0;
629
            TxEn <=#Tp 1'b0;
630
            ram_addr <=#Tp WB_ADR_I[9:2];
631
            ram_di <=#Tp WB_DAT_I;
632 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
633
            BDRead <=#Tp BDCs & ~WB_WE_I;
634 39 mohor
          end
635
      endcase
636
    end
637
end
638
 
639
 
640
// Delayed stage signals
641 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
642 39 mohor
begin
643 40 mohor
  if(Reset)
644 39 mohor
    begin
645
      WbEn_q <=#Tp 1'b0;
646
      RxEn_q <=#Tp 1'b0;
647
      TxEn_q <=#Tp 1'b0;
648
    end
649
  else
650
    begin
651
      WbEn_q <=#Tp WbEn;
652
      RxEn_q <=#Tp RxEn;
653
      TxEn_q <=#Tp TxEn;
654
    end
655
end
656
 
657 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
658 40 mohor
always @ (posedge MTxClk or posedge Reset)
659 38 mohor
begin
660 40 mohor
  if(Reset)
661 38 mohor
    Flop <=#Tp 1'b0;
662
  else
663
  if(TxDone | TxAbort | TxRetry_q)
664
    Flop <=#Tp 1'b0;
665
  else
666
  if(TxUsedData)
667
    Flop <=#Tp ~Flop;
668
end
669
 
670 39 mohor
wire ResetTxBDReady;
671
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
672 38 mohor
 
673
// Latching READY status of the Tx buffer descriptor
674 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
675 38 mohor
begin
676 40 mohor
  if(Reset)
677 38 mohor
    TxBDReady <=#Tp 1'b0;
678
  else
679 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
680
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
681
  else                                                // Only packets larger then 4 bytes are transmitted.
682 39 mohor
  if(ResetTxBDReady)
683 38 mohor
    TxBDReady <=#Tp 1'b0;
684
end
685
 
686
 
687 39 mohor
// Reading the Tx buffer descriptor
688 221 mohor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
689 39 mohor
 
690 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
691 38 mohor
begin
692 40 mohor
  if(Reset)
693 39 mohor
    TxBDRead <=#Tp 1'b1;
694 38 mohor
  else
695 110 mohor
  if(StartTxBDRead)
696 39 mohor
    TxBDRead <=#Tp 1'b1;
697 38 mohor
  else
698 39 mohor
  if(TxBDReady)
699
    TxBDRead <=#Tp 1'b0;
700 38 mohor
end
701
 
702
 
703 39 mohor
// Reading Tx BD pointer
704
assign StartTxPointerRead = TxBDRead & TxBDReady;
705 38 mohor
 
706 39 mohor
// Reading Tx BD Pointer
707 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
708 38 mohor
begin
709 40 mohor
  if(Reset)
710 39 mohor
    TxPointerRead <=#Tp 1'b0;
711 38 mohor
  else
712 39 mohor
  if(StartTxPointerRead)
713
    TxPointerRead <=#Tp 1'b1;
714 38 mohor
  else
715 39 mohor
  if(TxEn_q)
716
    TxPointerRead <=#Tp 1'b0;
717 38 mohor
end
718
 
719
 
720 39 mohor
// Writing status back to the Tx buffer descriptor
721 221 mohor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
722 38 mohor
 
723
 
724
 
725 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
726 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
727 38 mohor
begin
728 40 mohor
  if(Reset)
729 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
730 38 mohor
  else
731 272 tadejm
  if(~TxDone_wb & ~TxAbort_wb)
732
    BlockingTxStatusWrite <=#Tp 1'b0;
733
  else
734 39 mohor
  if(TxStatusWrite)
735
    BlockingTxStatusWrite <=#Tp 1'b1;
736 38 mohor
end
737
 
738
 
739 159 mohor
reg BlockingTxStatusWrite_sync1;
740
reg BlockingTxStatusWrite_sync2;
741
 
742
// Synchronizing BlockingTxStatusWrite to MTxClk
743
always @ (posedge MTxClk or posedge Reset)
744
begin
745
  if(Reset)
746
    BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
747
  else
748
    BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
749
end
750
 
751
// Synchronizing BlockingTxStatusWrite to MTxClk
752
always @ (posedge MTxClk or posedge Reset)
753
begin
754
  if(Reset)
755
    BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
756
  else
757
    BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
758
end
759
 
760
 
761 39 mohor
// TxBDRead state is activated only once. 
762 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
763 39 mohor
begin
764 40 mohor
  if(Reset)
765 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
766
  else
767 110 mohor
  if(StartTxBDRead)
768 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
769
  else
770 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
771 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
772
end
773 38 mohor
 
774
 
775 39 mohor
// Latching status from the tx buffer descriptor
776
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
777 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
778 38 mohor
begin
779 40 mohor
  if(Reset)
780 60 mohor
    TxStatus <=#Tp 4'h0;
781 38 mohor
  else
782 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
783 60 mohor
    TxStatus <=#Tp ram_do[14:11];
784 38 mohor
end
785
 
786 40 mohor
reg ReadTxDataFromMemory;
787
wire WriteRxDataToMemory;
788 38 mohor
 
789 39 mohor
reg MasterWbTX;
790
reg MasterWbRX;
791
 
792
reg [31:0] m_wb_adr_o;
793
reg        m_wb_cyc_o;
794
reg        m_wb_stb_o;
795 96 mohor
reg  [3:0] m_wb_sel_o;
796 39 mohor
reg        m_wb_we_o;
797 40 mohor
 
798 39 mohor
wire TxLengthEq0;
799
wire TxLengthLt4;
800
 
801 150 mohor
reg BlockingIncrementTxPointer;
802 159 mohor
reg [31:2] TxPointerMSB;
803
reg [1:0]  TxPointerLSB;
804
reg [1:0]  TxPointerLSB_rst;
805
reg [31:2] RxPointerMSB;
806
reg [1:0]  RxPointerLSB_rst;
807 39 mohor
 
808 150 mohor
wire RxBurstAcc;
809
wire RxWordAcc;
810
wire RxHalfAcc;
811
wire RxByteAcc;
812
 
813 39 mohor
//Latching length from the buffer descriptor;
814 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
815 38 mohor
begin
816 40 mohor
  if(Reset)
817 39 mohor
    TxLength <=#Tp 16'h0;
818 38 mohor
  else
819 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
820
    TxLength <=#Tp ram_do[31:16];
821 38 mohor
  else
822 39 mohor
  if(MasterWbTX & m_wb_ack_i)
823
    begin
824
      if(TxLengthLt4)
825
        TxLength <=#Tp 16'h0;
826 150 mohor
      else
827 159 mohor
      if(TxPointerLSB_rst==2'h0)
828 96 mohor
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
829 39 mohor
      else
830 159 mohor
      if(TxPointerLSB_rst==2'h1)
831 150 mohor
        TxLength <=#Tp TxLength - 3'h3;    // Length is subtracted at the data request
832
      else
833 159 mohor
      if(TxPointerLSB_rst==2'h2)
834 150 mohor
        TxLength <=#Tp TxLength - 3'h2;    // Length is subtracted at the data request
835
      else
836 159 mohor
      if(TxPointerLSB_rst==2'h3)
837 150 mohor
        TxLength <=#Tp TxLength - 3'h1;    // Length is subtracted at the data request
838 39 mohor
    end
839 38 mohor
end
840
 
841 96 mohor
 
842
 
843 60 mohor
//Latching length from the buffer descriptor;
844
always @ (posedge WB_CLK_I or posedge Reset)
845
begin
846
  if(Reset)
847
    LatchedTxLength <=#Tp 16'h0;
848
  else
849
  if(TxEn & TxEn_q & TxBDRead)
850
    LatchedTxLength <=#Tp ram_do[31:16];
851
end
852
 
853 39 mohor
assign TxLengthEq0 = TxLength == 0;
854
assign TxLengthLt4 = TxLength < 4;
855 38 mohor
 
856 150 mohor
reg cyc_cleared;
857
reg IncrTxPointer;
858 39 mohor
 
859
 
860 159 mohor
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
861
// because TxPointerMSB is only used for word-aligned accesses.
862 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
863 38 mohor
begin
864 40 mohor
  if(Reset)
865 159 mohor
    TxPointerMSB <=#Tp 30'h0;
866 38 mohor
  else
867 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
868 159 mohor
    TxPointerMSB <=#Tp ram_do[31:2];
869 38 mohor
  else
870 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
871 159 mohor
    TxPointerMSB <=#Tp TxPointerMSB + 1'b1;     // TxPointer is word-aligned
872 38 mohor
end
873
 
874 96 mohor
 
875 159 mohor
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
876
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
877
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
878
// set by this two bits.
879 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
880
begin
881
  if(Reset)
882 159 mohor
    TxPointerLSB[1:0] <=#Tp 0;
883 96 mohor
  else
884
  if(TxEn & TxEn_q & TxPointerRead)
885 159 mohor
    TxPointerLSB[1:0] <=#Tp ram_do[1:0];
886 96 mohor
end
887
 
888
 
889 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
890
// After the read access, TxLength needs to be decremented for the number of the valid
891
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
892
// valid so this two bits are reset to zero. 
893 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
894
begin
895
  if(Reset)
896 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
897 150 mohor
  else
898
  if(TxEn & TxEn_q & TxPointerRead)
899 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
900 150 mohor
  else
901
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
902 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
903 150 mohor
end
904 96 mohor
 
905 150 mohor
 
906 159 mohor
reg  [3:0] RxByteSel;
907 39 mohor
wire MasterAccessFinished;
908 38 mohor
 
909 39 mohor
 
910 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
911 38 mohor
begin
912 40 mohor
  if(Reset)
913 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
914 38 mohor
  else
915 39 mohor
  if(MasterAccessFinished)
916
    BlockingIncrementTxPointer <=#Tp 0;
917 38 mohor
  else
918 150 mohor
  if(IncrTxPointer)
919 39 mohor
    BlockingIncrementTxPointer <=#Tp 1'b1;
920 38 mohor
end
921
 
922
 
923 39 mohor
wire TxBufferAlmostFull;
924
wire TxBufferFull;
925
wire TxBufferEmpty;
926
wire TxBufferAlmostEmpty;
927 40 mohor
wire SetReadTxDataFromMemory;
928 39 mohor
 
929 40 mohor
reg BlockReadTxDataFromMemory;
930 39 mohor
 
931 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
932 39 mohor
 
933 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
934 38 mohor
begin
935 40 mohor
  if(Reset)
936
    ReadTxDataFromMemory <=#Tp 1'b0;
937 38 mohor
  else
938 219 mohor
  if(TxLengthEq0 | TxAbortPacket | TxRetryPacket)
939 40 mohor
    ReadTxDataFromMemory <=#Tp 1'b0;
940 39 mohor
  else
941 40 mohor
  if(SetReadTxDataFromMemory)
942
    ReadTxDataFromMemory <=#Tp 1'b1;
943 38 mohor
end
944
 
945 226 tadejm
reg tx_burst_en;
946
reg rx_burst_en;
947 221 mohor
reg BlockingLastReadOn_Abort_Retry;
948
 
949
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory & ~BlockingLastReadOn_Abort_Retry;
950 226 tadejm
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
951 221 mohor
 
952 39 mohor
wire [31:0] TxData_wb;
953
wire ReadTxDataFromFifo_wb;
954 38 mohor
 
955 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
956 38 mohor
begin
957 40 mohor
  if(Reset)
958
    BlockReadTxDataFromMemory <=#Tp 1'b0;
959 38 mohor
  else
960 269 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket | TxRetryPacket)))
961 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
962 219 mohor
  else
963 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
964 219 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b0;
965 39 mohor
end
966
 
967
 
968 221 mohor
always @ (posedge WB_CLK_I or posedge Reset)
969
begin
970
  if(Reset)
971
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
972
  else
973
  if(TxAbortPacket | TxRetryPacket)
974
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
975
  else
976
  if(((TxAbort_wb & !TxAbortPacket_NotCleared) | (TxRetry_wb & !TxRetryPacket_NotCleared)) & !TxBDReady)
977
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b1;
978
end
979 39 mohor
 
980 221 mohor
 
981
 
982
 
983 39 mohor
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
984 219 mohor
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
985
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
986 226 tadejm
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
987
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
988 159 mohor
 
989 226 tadejm
wire rx_burst;
990
wire enough_data_in_rxfifo_for_burst;
991
wire enough_data_in_rxfifo_for_burst_plus1;
992 229 mohor
 
993 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
994 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
995 39 mohor
begin
996 40 mohor
  if(Reset)
997 38 mohor
    begin
998 39 mohor
      MasterWbTX <=#Tp 1'b0;
999
      MasterWbRX <=#Tp 1'b0;
1000
      m_wb_adr_o <=#Tp 32'h0;
1001
      m_wb_cyc_o <=#Tp 1'b0;
1002
      m_wb_stb_o <=#Tp 1'b0;
1003
      m_wb_we_o  <=#Tp 1'b0;
1004 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
1005 110 mohor
      cyc_cleared<=#Tp 1'b0;
1006 226 tadejm
      tx_burst_cnt<=#Tp 0;
1007
      rx_burst_cnt<=#Tp 0;
1008 150 mohor
      IncrTxPointer<=#Tp 1'b0;
1009 226 tadejm
      tx_burst_en<=#Tp 1'b1;
1010
      rx_burst_en<=#Tp 1'b0;
1011
      `ifdef ETH_WISHBONE_B3
1012
        m_wb_cti_o <=#Tp 3'b0;
1013
      `endif
1014 38 mohor
    end
1015 39 mohor
  else
1016
    begin
1017
      // Switching between two stages depends on enable signals
1018 229 mohor
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst})  // synopsys parallel_case
1019 226 tadejm
        8'b00_10_00_10,             // Idle and MRB needed
1020 229 mohor
        8'b10_1x_10_1x,             // MRB continues
1021 226 tadejm
        8'b10_10_01_10,             // Clear (previously MR) and MRB needed
1022 229 mohor
        8'b01_1x_01_1x :            // Clear (previously MW) and MRB needed
1023 39 mohor
          begin
1024 226 tadejm
            MasterWbTX <=#Tp 1'b1;  // tx burst
1025
            MasterWbRX <=#Tp 1'b0;
1026
            m_wb_cyc_o <=#Tp 1'b1;
1027
            m_wb_stb_o <=#Tp 1'b1;
1028
            m_wb_we_o  <=#Tp 1'b0;
1029
            m_wb_sel_o <=#Tp 4'hf;
1030
            cyc_cleared<=#Tp 1'b0;
1031
            IncrTxPointer<=#Tp 1'b1;
1032
            tx_burst_cnt <=#Tp tx_burst_cnt+1;
1033
            if(tx_burst_cnt==0)
1034
              m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1035
            else
1036
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1037
 
1038
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1039
              begin
1040
                tx_burst_en<=#Tp 1'b0;
1041
              `ifdef ETH_WISHBONE_B3
1042
                m_wb_cti_o <=#Tp 3'b111;
1043
              `endif
1044
              end
1045
            else
1046
              begin
1047
              `ifdef ETH_WISHBONE_B3
1048
                m_wb_cti_o <=#Tp 3'b010;
1049
              `endif
1050
              end
1051
          end
1052 229 mohor
        8'b00_x1_00_x1,             // Idle and MWB needed
1053
        8'b01_x1_10_x1,             // MWB continues
1054 226 tadejm
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1055 229 mohor
        8'b10_x1_01_x1 :            // Clear (previously MR) and MWB needed
1056 226 tadejm
          begin
1057
            MasterWbTX <=#Tp 1'b0;  // rx burst
1058 39 mohor
            MasterWbRX <=#Tp 1'b1;
1059 226 tadejm
            m_wb_cyc_o <=#Tp 1'b1;
1060
            m_wb_stb_o <=#Tp 1'b1;
1061
            m_wb_we_o  <=#Tp 1'b1;
1062
            m_wb_sel_o <=#Tp RxByteSel;
1063
            IncrTxPointer<=#Tp 1'b0;
1064
            cyc_cleared<=#Tp 1'b0;
1065
            rx_burst_cnt <=#Tp rx_burst_cnt+1;
1066
 
1067
            if(rx_burst_cnt==0)
1068
              m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1069
            else
1070
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1071
 
1072
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1073
              begin
1074
                rx_burst_en<=#Tp 1'b0;
1075
              `ifdef ETH_WISHBONE_B3
1076
                m_wb_cti_o <=#Tp 3'b111;
1077
              `endif
1078
              end
1079
            else
1080
              begin
1081
              `ifdef ETH_WISHBONE_B3
1082
                m_wb_cti_o <=#Tp 3'b010;
1083
              `endif
1084
              end
1085
          end
1086 229 mohor
        8'b00_x1_00_x0 :            // idle and MW is needed (data write to rx buffer)
1087 226 tadejm
          begin
1088
            MasterWbTX <=#Tp 1'b0;
1089
            MasterWbRX <=#Tp 1'b1;
1090 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1091 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1092
            m_wb_stb_o <=#Tp 1'b1;
1093
            m_wb_we_o  <=#Tp 1'b1;
1094 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1095 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1096 39 mohor
          end
1097 226 tadejm
        8'b00_10_00_00 :            // idle and MR is needed (data read from tx buffer)
1098 39 mohor
          begin
1099 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1100 39 mohor
            MasterWbRX <=#Tp 1'b0;
1101 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1102 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1103
            m_wb_stb_o <=#Tp 1'b1;
1104
            m_wb_we_o  <=#Tp 1'b0;
1105 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1106
            IncrTxPointer<=#Tp 1'b1;
1107 39 mohor
          end
1108 226 tadejm
        8'b10_10_01_00,             // MR and MR is needed (data read from tx buffer)
1109 229 mohor
        8'b01_1x_01_0x  :           // MW and MR is needed (data read from tx buffer)
1110 39 mohor
          begin
1111 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1112 39 mohor
            MasterWbRX <=#Tp 1'b0;
1113 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1114 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1115
            m_wb_stb_o <=#Tp 1'b1;
1116
            m_wb_we_o  <=#Tp 1'b0;
1117 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1118 110 mohor
            cyc_cleared<=#Tp 1'b0;
1119 150 mohor
            IncrTxPointer<=#Tp 1'b1;
1120 39 mohor
          end
1121 226 tadejm
        8'b01_01_01_00,             // MW and MW needed (data write to rx buffer)
1122 229 mohor
        8'b10_x1_01_x0  :           // MR and MW is needed (data write to rx buffer)
1123 39 mohor
          begin
1124 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1125 39 mohor
            MasterWbRX <=#Tp 1'b1;
1126 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1127 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1128
            m_wb_stb_o <=#Tp 1'b1;
1129 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
1130 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1131 110 mohor
            cyc_cleared<=#Tp 1'b0;
1132 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1133 39 mohor
          end
1134 226 tadejm
        8'b01_01_10_00,             // MW and MW needed (cycle is cleared between previous and next access)
1135 229 mohor
        8'b01_1x_10_x0,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1136 226 tadejm
        8'b10_10_10_00,             // MR and MR needed (cycle is cleared between previous and next access)
1137 229 mohor
        8'b10_x1_10_0x :            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1138 39 mohor
          begin
1139 110 mohor
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
1140
            m_wb_stb_o <=#Tp 1'b0;
1141
            cyc_cleared<=#Tp 1'b1;
1142 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1143 226 tadejm
            tx_burst_cnt<=#Tp 0;
1144
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1145
            rx_burst_cnt<=#Tp 0;
1146
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1147
            `ifdef ETH_WISHBONE_B3
1148
              m_wb_cti_o <=#Tp 3'b0;
1149
            `endif
1150 110 mohor
          end
1151 229 mohor
        8'bxx_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1152
        8'bxx_00_01_00 :            // Between cyc_cleared request was cleared
1153 110 mohor
          begin
1154 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1155 39 mohor
            MasterWbRX <=#Tp 1'b0;
1156
            m_wb_cyc_o <=#Tp 1'b0;
1157
            m_wb_stb_o <=#Tp 1'b0;
1158 226 tadejm
            cyc_cleared<=#Tp 1'b0;
1159 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1160 226 tadejm
            rx_burst_cnt<=#Tp 0;
1161
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1162
            `ifdef ETH_WISHBONE_B3
1163
              m_wb_cti_o <=#Tp 3'b0;
1164
            `endif
1165 39 mohor
          end
1166 226 tadejm
        8'b00_00_00_00:             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1167 127 mohor
          begin
1168 226 tadejm
            tx_burst_cnt<=#Tp 0;
1169
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1170 127 mohor
          end
1171 226 tadejm
        default:                    // Don't touch
1172 82 mohor
          begin
1173
            MasterWbTX <=#Tp MasterWbTX;
1174
            MasterWbRX <=#Tp MasterWbRX;
1175
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
1176
            m_wb_stb_o <=#Tp m_wb_stb_o;
1177 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
1178 150 mohor
            IncrTxPointer<=#Tp IncrTxPointer;
1179 82 mohor
          end
1180 39 mohor
      endcase
1181
    end
1182 38 mohor
end
1183
 
1184 110 mohor
 
1185 39 mohor
wire TxFifoClear;
1186 96 mohor
 
1187 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1188 38 mohor
 
1189 219 mohor
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
1190 150 mohor
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
1191 96 mohor
          .clk(WB_CLK_I),                                   .reset(Reset),
1192 226 tadejm
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1193 96 mohor
          .clear(TxFifoClear),                              .full(TxBufferFull),
1194
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
1195 150 mohor
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
1196 96 mohor
        );
1197 39 mohor
 
1198
 
1199
reg StartOccured;
1200
reg TxStartFrm_sync1;
1201
reg TxStartFrm_sync2;
1202
reg TxStartFrm_syncb1;
1203
reg TxStartFrm_syncb2;
1204
 
1205
 
1206
 
1207
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1208 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1209 38 mohor
begin
1210 40 mohor
  if(Reset)
1211 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
1212 38 mohor
  else
1213 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1214
    TxStartFrm_wb <=#Tp 1'b1;
1215 38 mohor
  else
1216 39 mohor
  if(TxStartFrm_syncb2)
1217
    TxStartFrm_wb <=#Tp 1'b0;
1218 38 mohor
end
1219
 
1220 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1221 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1222 38 mohor
begin
1223 40 mohor
  if(Reset)
1224 39 mohor
    StartOccured <=#Tp 1'b0;
1225 38 mohor
  else
1226 39 mohor
  if(TxStartFrm_wb)
1227
    StartOccured <=#Tp 1'b1;
1228 38 mohor
  else
1229 39 mohor
  if(ResetTxBDReady)
1230
    StartOccured <=#Tp 1'b0;
1231 38 mohor
end
1232
 
1233 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1234 40 mohor
always @ (posedge MTxClk or posedge Reset)
1235 39 mohor
begin
1236 40 mohor
  if(Reset)
1237 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1238
  else
1239
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1240
end
1241 38 mohor
 
1242 40 mohor
always @ (posedge MTxClk or posedge Reset)
1243 39 mohor
begin
1244 40 mohor
  if(Reset)
1245 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1246
  else
1247
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1248
end
1249
 
1250 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1251 38 mohor
begin
1252 40 mohor
  if(Reset)
1253 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1254 38 mohor
  else
1255 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1256 38 mohor
end
1257
 
1258 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1259 38 mohor
begin
1260 40 mohor
  if(Reset)
1261 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1262 38 mohor
  else
1263 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1264
end
1265
 
1266 40 mohor
always @ (posedge MTxClk or posedge Reset)
1267 39 mohor
begin
1268 40 mohor
  if(Reset)
1269 39 mohor
    TxStartFrm <=#Tp 1'b0;
1270 38 mohor
  else
1271 39 mohor
  if(TxStartFrm_sync2)
1272 61 mohor
    TxStartFrm <=#Tp 1'b1;
1273 39 mohor
  else
1274 61 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry | TxAbort))
1275 39 mohor
    TxStartFrm <=#Tp 1'b0;
1276 38 mohor
end
1277 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1278 38 mohor
 
1279
 
1280 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1281 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1282 38 mohor
begin
1283 40 mohor
  if(Reset)
1284 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1285 38 mohor
  else
1286 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1287 39 mohor
    TxEndFrm_wb <=#Tp 1'b1;
1288 38 mohor
  else
1289 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1290
    TxEndFrm_wb <=#Tp 1'b0;
1291 38 mohor
end
1292
 
1293
 
1294
// Marks which bytes are valid within the word.
1295 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1296 38 mohor
 
1297 39 mohor
reg LatchValidBytes;
1298
reg LatchValidBytes_q;
1299 38 mohor
 
1300 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1301 38 mohor
begin
1302 40 mohor
  if(Reset)
1303 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1304 38 mohor
  else
1305 39 mohor
  if(TxLengthLt4 & TxBDReady)
1306
    LatchValidBytes <=#Tp 1'b1;
1307 38 mohor
  else
1308 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1309 38 mohor
end
1310
 
1311 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1312 38 mohor
begin
1313 40 mohor
  if(Reset)
1314 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1315 38 mohor
  else
1316 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1317 38 mohor
end
1318
 
1319
 
1320 39 mohor
// Latching valid bytes
1321 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1322 38 mohor
begin
1323 40 mohor
  if(Reset)
1324 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1325 38 mohor
  else
1326 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1327
    TxValidBytesLatched <=#Tp TxValidBytes;
1328
  else
1329
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1330
    TxValidBytesLatched <=#Tp 2'h0;
1331 38 mohor
end
1332
 
1333
 
1334
assign TxIRQEn          = TxStatus[14];
1335 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1336
assign PerPacketPad     = TxStatus[12];
1337
assign PerPacketCrcEn   = TxStatus[11];
1338 38 mohor
 
1339
 
1340 77 mohor
assign RxIRQEn         = RxStatus[14];
1341 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1342 38 mohor
 
1343
 
1344
// Temporary Tx and Rx buffer descriptor address 
1345 39 mohor
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
1346 134 mohor
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1)     | // Using first Rx BD
1347 39 mohor
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
1348 38 mohor
 
1349
 
1350
// Latching Tx buffer descriptor address
1351 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1352 38 mohor
begin
1353 40 mohor
  if(Reset)
1354 38 mohor
    TxBDAddress <=#Tp 8'h0;
1355
  else
1356
  if(TxStatusWrite)
1357
    TxBDAddress <=#Tp TempTxBDAddress;
1358
end
1359
 
1360
 
1361
// Latching Rx buffer descriptor address
1362 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1363 38 mohor
begin
1364 40 mohor
  if(Reset)
1365 134 mohor
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1;
1366 38 mohor
  else
1367 77 mohor
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
1368 134 mohor
    RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
1369 38 mohor
  else
1370
  if(RxStatusWrite)
1371
    RxBDAddress <=#Tp TempRxBDAddress;
1372
end
1373
 
1374 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1375 38 mohor
 
1376 261 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
1377 60 mohor
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1378 38 mohor
 
1379 60 mohor
 
1380 38 mohor
// Signals used for various purposes
1381 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1382 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1383
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1384
 
1385
 
1386
 
1387 39 mohor
// Generating delayed signals
1388 40 mohor
always @ (posedge MTxClk or posedge Reset)
1389 38 mohor
begin
1390 40 mohor
  if(Reset)
1391 39 mohor
    begin
1392
      TxAbort_q      <=#Tp 1'b0;
1393
      TxRetry_q      <=#Tp 1'b0;
1394
      TxUsedData_q   <=#Tp 1'b0;
1395
    end
1396 38 mohor
  else
1397 39 mohor
    begin
1398
      TxAbort_q      <=#Tp TxAbort;
1399
      TxRetry_q      <=#Tp TxRetry;
1400
      TxUsedData_q   <=#Tp TxUsedData;
1401
    end
1402 38 mohor
end
1403
 
1404
// Generating delayed signals
1405 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1406 38 mohor
begin
1407 40 mohor
  if(Reset)
1408 38 mohor
    begin
1409 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1410
      TxAbort_wb_q  <=#Tp 1'b0;
1411 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1412 38 mohor
    end
1413
  else
1414
    begin
1415 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1416
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1417 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1418 38 mohor
    end
1419
end
1420
 
1421
 
1422 219 mohor
reg TxAbortPacketBlocked;
1423
always @ (posedge WB_CLK_I or posedge Reset)
1424
begin
1425
  if(Reset)
1426
    TxAbortPacket <=#Tp 1'b0;
1427
  else
1428 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxAbortPacketBlocked |
1429
     TxAbort_wb & !MasterWbTX & !TxAbortPacketBlocked)
1430 219 mohor
    TxAbortPacket <=#Tp 1'b1;
1431
  else
1432
    TxAbortPacket <=#Tp 1'b0;
1433
end
1434
 
1435
 
1436
always @ (posedge WB_CLK_I or posedge Reset)
1437
begin
1438
  if(Reset)
1439 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1440
  else
1441 272 tadejm
  if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
1442
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1443
  else
1444 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1445
     TxAbort_wb & !MasterWbTX)
1446 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b1;
1447
end
1448
 
1449
 
1450
always @ (posedge WB_CLK_I or posedge Reset)
1451
begin
1452
  if(Reset)
1453 219 mohor
    TxAbortPacketBlocked <=#Tp 1'b0;
1454
  else
1455
  if(TxAbortPacket)
1456
    TxAbortPacketBlocked <=#Tp 1'b1;
1457
  else
1458
  if(!TxAbort_wb & TxAbort_wb_q)
1459
    TxAbortPacketBlocked <=#Tp 1'b0;
1460
end
1461
 
1462
 
1463
reg TxRetryPacketBlocked;
1464
always @ (posedge WB_CLK_I or posedge Reset)
1465
begin
1466
  if(Reset)
1467
    TxRetryPacket <=#Tp 1'b0;
1468
  else
1469 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1470
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1471 219 mohor
    TxRetryPacket <=#Tp 1'b1;
1472
  else
1473
    TxRetryPacket <=#Tp 1'b0;
1474
end
1475
 
1476
 
1477
always @ (posedge WB_CLK_I or posedge Reset)
1478
begin
1479
  if(Reset)
1480 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1481
  else
1482 272 tadejm
  if(StartTxBDRead)
1483
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1484
  else
1485 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1486
     TxRetry_wb & !MasterWbTX)
1487 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b1;
1488
end
1489
 
1490
 
1491
always @ (posedge WB_CLK_I or posedge Reset)
1492
begin
1493
  if(Reset)
1494 219 mohor
    TxRetryPacketBlocked <=#Tp 1'b0;
1495
  else
1496
  if(TxRetryPacket)
1497
    TxRetryPacketBlocked <=#Tp 1'b1;
1498
  else
1499
  if(!TxRetry_wb & TxRetry_wb_q)
1500
    TxRetryPacketBlocked <=#Tp 1'b0;
1501
end
1502
 
1503
 
1504 221 mohor
reg TxDonePacketBlocked;
1505
always @ (posedge WB_CLK_I or posedge Reset)
1506
begin
1507
  if(Reset)
1508
    TxDonePacket <=#Tp 1'b0;
1509
  else
1510 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
1511
     TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1512 221 mohor
    TxDonePacket <=#Tp 1'b1;
1513
  else
1514
    TxDonePacket <=#Tp 1'b0;
1515
end
1516
 
1517
 
1518
always @ (posedge WB_CLK_I or posedge Reset)
1519
begin
1520
  if(Reset)
1521
    TxDonePacket_NotCleared <=#Tp 1'b0;
1522
  else
1523 272 tadejm
  if(TxEn & TxEn_q & TxDonePacket_NotCleared)
1524
    TxDonePacket_NotCleared <=#Tp 1'b0;
1525
  else
1526 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1527
     TxDone_wb & !MasterWbTX)
1528 221 mohor
    TxDonePacket_NotCleared <=#Tp 1'b1;
1529
end
1530
 
1531
 
1532
always @ (posedge WB_CLK_I or posedge Reset)
1533
begin
1534
  if(Reset)
1535
    TxDonePacketBlocked <=#Tp 1'b0;
1536
  else
1537
  if(TxDonePacket)
1538
    TxDonePacketBlocked <=#Tp 1'b1;
1539
  else
1540
  if(!TxDone_wb & TxDone_wb_q)
1541
    TxDonePacketBlocked <=#Tp 1'b0;
1542
end
1543
 
1544
 
1545 38 mohor
// Sinchronizing and evaluating tx data
1546 39 mohor
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
1547 219 mohor
assign SetGotData = (TxStartFrm_wb);
1548 38 mohor
 
1549
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
1550 40 mohor
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1551
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1552 38 mohor
 
1553
 
1554
// Indication of the last word
1555 40 mohor
always @ (posedge MTxClk or posedge Reset)
1556 38 mohor
begin
1557 40 mohor
  if(Reset)
1558 38 mohor
    LastWord <=#Tp 1'b0;
1559
  else
1560
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1561
    LastWord <=#Tp 1'b0;
1562
  else
1563
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1564 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1565 38 mohor
end
1566
 
1567
 
1568
// Tx end frame generation
1569 40 mohor
always @ (posedge MTxClk or posedge Reset)
1570 38 mohor
begin
1571 40 mohor
  if(Reset)
1572 38 mohor
    TxEndFrm <=#Tp 1'b0;
1573
  else
1574 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1575 38 mohor
    TxEndFrm <=#Tp 1'b0;
1576
  else
1577
  if(Flop & LastWord)
1578
    begin
1579 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1580 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1581
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1582
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1583
 
1584
        default : TxEndFrm <=#Tp 1'b0;
1585
      endcase
1586
    end
1587
end
1588
 
1589
 
1590
// Tx data selection (latching)
1591 40 mohor
always @ (posedge MTxClk or posedge Reset)
1592 38 mohor
begin
1593 40 mohor
  if(Reset)
1594 96 mohor
    TxData <=#Tp 0;
1595 38 mohor
  else
1596 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1597 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1598 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1599
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1600
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1601
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1602
    endcase
1603 38 mohor
  else
1604 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1605 96 mohor
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1606
  else
1607 38 mohor
  if(TxUsedData & Flop)
1608
    begin
1609 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1610 226 tadejm
 
1611 82 mohor
        1 : TxData <=#Tp TxDataLatched[23:16];
1612
        2 : TxData <=#Tp TxDataLatched[15:8];
1613
        3 : TxData <=#Tp TxDataLatched[7:0];
1614 38 mohor
      endcase
1615
    end
1616
end
1617
 
1618
 
1619
// Latching tx data
1620 40 mohor
always @ (posedge MTxClk or posedge Reset)
1621 38 mohor
begin
1622 40 mohor
  if(Reset)
1623 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1624
  else
1625 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1626 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1627 38 mohor
end
1628
 
1629
 
1630
// Tx under run
1631 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1632 38 mohor
begin
1633 40 mohor
  if(Reset)
1634 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1635 38 mohor
  else
1636 39 mohor
  if(TxAbortPulse)
1637 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1638
  else
1639
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1640
    TxUnderRun_wb <=#Tp 1'b1;
1641
end
1642
 
1643
 
1644 159 mohor
reg TxUnderRun_sync1;
1645
 
1646 60 mohor
// Tx under run
1647
always @ (posedge MTxClk or posedge Reset)
1648
begin
1649
  if(Reset)
1650 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b0;
1651 43 mohor
  else
1652 60 mohor
  if(TxUnderRun_wb)
1653 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b1;
1654 60 mohor
  else
1655 159 mohor
  if(BlockingTxStatusWrite_sync2)
1656
    TxUnderRun_sync1 <=#Tp 1'b0;
1657
end
1658
 
1659
// Tx under run
1660
always @ (posedge MTxClk or posedge Reset)
1661
begin
1662
  if(Reset)
1663 60 mohor
    TxUnderRun <=#Tp 1'b0;
1664 159 mohor
  else
1665
  if(BlockingTxStatusWrite_sync2)
1666
    TxUnderRun <=#Tp 1'b0;
1667
  else
1668
  if(TxUnderRun_sync1)
1669
    TxUnderRun <=#Tp 1'b1;
1670 38 mohor
end
1671
 
1672
 
1673
// Tx Byte counter
1674 40 mohor
always @ (posedge MTxClk or posedge Reset)
1675 38 mohor
begin
1676 40 mohor
  if(Reset)
1677 38 mohor
    TxByteCnt <=#Tp 2'h0;
1678
  else
1679
  if(TxAbort_q | TxRetry_q)
1680
    TxByteCnt <=#Tp 2'h0;
1681
  else
1682
  if(TxStartFrm & ~TxUsedData)
1683 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1684 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1685
      2'h1 : TxByteCnt <=#Tp 2'h2;
1686
      2'h2 : TxByteCnt <=#Tp 2'h3;
1687
      2'h3 : TxByteCnt <=#Tp 2'h0;
1688
    endcase
1689 38 mohor
  else
1690
  if(TxUsedData & Flop)
1691 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1692 38 mohor
end
1693
 
1694 39 mohor
 
1695 150 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1696
reg ReadTxDataFromFifo_sync1;
1697
reg ReadTxDataFromFifo_sync2;
1698
reg ReadTxDataFromFifo_sync3;
1699
reg ReadTxDataFromFifo_syncb1;
1700
reg ReadTxDataFromFifo_syncb2;
1701
reg ReadTxDataFromFifo_syncb3;
1702
 
1703
 
1704
always @ (posedge MTxClk or posedge Reset)
1705
begin
1706
  if(Reset)
1707
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1708
  else
1709 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1710 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1711 150 mohor
  else
1712
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1713
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1714 38 mohor
end
1715
 
1716 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1717 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1718 38 mohor
begin
1719 40 mohor
  if(Reset)
1720 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1721 38 mohor
  else
1722 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1723
end
1724 38 mohor
 
1725 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1726 38 mohor
begin
1727 40 mohor
  if(Reset)
1728 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1729 38 mohor
  else
1730 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1731 38 mohor
end
1732
 
1733 40 mohor
always @ (posedge MTxClk or posedge Reset)
1734 38 mohor
begin
1735 40 mohor
  if(Reset)
1736 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1737 38 mohor
  else
1738 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1739 38 mohor
end
1740
 
1741 40 mohor
always @ (posedge MTxClk or posedge Reset)
1742 38 mohor
begin
1743 40 mohor
  if(Reset)
1744 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1745 38 mohor
  else
1746 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1747 38 mohor
end
1748
 
1749 150 mohor
always @ (posedge MTxClk or posedge Reset)
1750
begin
1751
  if(Reset)
1752
    ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
1753
  else
1754
    ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
1755
end
1756
 
1757 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1758 38 mohor
begin
1759 40 mohor
  if(Reset)
1760 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1761 38 mohor
  else
1762 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1763 38 mohor
end
1764
 
1765 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1766
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1767 38 mohor
 
1768
 
1769 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1770 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1771 38 mohor
begin
1772 40 mohor
  if(Reset)
1773 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1774 38 mohor
  else
1775 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1776 38 mohor
end
1777
 
1778 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1779 38 mohor
begin
1780 40 mohor
  if(Reset)
1781 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1782 38 mohor
  else
1783 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1784 38 mohor
end
1785
 
1786
 
1787 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1788 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1789 38 mohor
begin
1790 40 mohor
  if(Reset)
1791 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1792 38 mohor
  else
1793 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1794 38 mohor
end
1795
 
1796 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1797 38 mohor
begin
1798 40 mohor
  if(Reset)
1799 39 mohor
    TxDone_wb <=#Tp 1'b0;
1800 38 mohor
  else
1801 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1802 38 mohor
end
1803
 
1804 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1805 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1806 38 mohor
begin
1807 40 mohor
  if(Reset)
1808 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1809 38 mohor
  else
1810 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1811 38 mohor
end
1812
 
1813 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1814 38 mohor
begin
1815 40 mohor
  if(Reset)
1816 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1817
  else
1818 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1819 38 mohor
end
1820
 
1821
 
1822 150 mohor
reg RxAbortSync1;
1823
reg RxAbortSync2;
1824
reg RxAbortSync3;
1825
reg RxAbortSync4;
1826
reg RxAbortSyncb1;
1827
reg RxAbortSyncb2;
1828 39 mohor
 
1829 150 mohor
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
1830
 
1831 40 mohor
// Reading the Rx buffer descriptor
1832
always @ (posedge WB_CLK_I or posedge Reset)
1833
begin
1834
  if(Reset)
1835
    RxBDRead <=#Tp 1'b1;
1836
  else
1837 166 mohor
  if(StartRxBDRead & ~RxReady)
1838 40 mohor
    RxBDRead <=#Tp 1'b1;
1839
  else
1840
  if(RxBDReady)
1841
    RxBDRead <=#Tp 1'b0;
1842
end
1843 39 mohor
 
1844
 
1845 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1846
// written to the previous one.
1847
 
1848
// Latching READY status of the Rx buffer descriptor
1849 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1850 38 mohor
begin
1851 40 mohor
  if(Reset)
1852 38 mohor
    RxBDReady <=#Tp 1'b0;
1853
  else
1854 166 mohor
  if(RxPointerRead)
1855 150 mohor
    RxBDReady <=#Tp 1'b0;
1856
  else
1857 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1858
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1859 38 mohor
end
1860
 
1861 40 mohor
// Latching Rx buffer descriptor status
1862
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1863
always @ (posedge WB_CLK_I or posedge Reset)
1864 38 mohor
begin
1865 40 mohor
  if(Reset)
1866 60 mohor
    RxStatus <=#Tp 2'h0;
1867 38 mohor
  else
1868 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1869 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1870 38 mohor
end
1871
 
1872
 
1873 166 mohor
// RxReady generation
1874
always @ (posedge WB_CLK_I or posedge Reset)
1875
begin
1876
  if(Reset)
1877
    RxReady <=#Tp 1'b0;
1878
  else
1879
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
1880
    RxReady <=#Tp 1'b0;
1881
  else
1882
  if(RxEn & RxEn_q & RxPointerRead)
1883
    RxReady <=#Tp 1'b1;
1884
end
1885 38 mohor
 
1886
 
1887 40 mohor
// Reading Rx BD pointer
1888
 
1889
 
1890
assign StartRxPointerRead = RxBDRead & RxBDReady;
1891
 
1892
// Reading Tx BD Pointer
1893
always @ (posedge WB_CLK_I or posedge Reset)
1894 38 mohor
begin
1895 40 mohor
  if(Reset)
1896
    RxPointerRead <=#Tp 1'b0;
1897 38 mohor
  else
1898 40 mohor
  if(StartRxPointerRead)
1899
    RxPointerRead <=#Tp 1'b1;
1900 38 mohor
  else
1901 166 mohor
  if(RxEn & RxEn_q)
1902 40 mohor
    RxPointerRead <=#Tp 1'b0;
1903 38 mohor
end
1904
 
1905 113 mohor
 
1906 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1907
always @ (posedge WB_CLK_I or posedge Reset)
1908
begin
1909
  if(Reset)
1910 159 mohor
    RxPointerMSB <=#Tp 30'h0;
1911 40 mohor
  else
1912
  if(RxEn & RxEn_q & RxPointerRead)
1913 159 mohor
    RxPointerMSB <=#Tp ram_do[31:2];
1914 40 mohor
  else
1915 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1916 159 mohor
      RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1917 40 mohor
end
1918 38 mohor
 
1919
 
1920 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1921 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1922
begin
1923
  if(Reset)
1924 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp 0;
1925 96 mohor
  else
1926 159 mohor
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
1927
    RxPointerLSB_rst[1:0] <=#Tp 0;
1928 96 mohor
  else
1929
  if(RxEn & RxEn_q & RxPointerRead)
1930 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
1931 96 mohor
end
1932
 
1933
 
1934 159 mohor
always @ (RxPointerLSB_rst)
1935 96 mohor
begin
1936 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1937
    2'h0 : RxByteSel[3:0] = 4'hf;
1938
    2'h1 : RxByteSel[3:0] = 4'h7;
1939
    2'h2 : RxByteSel[3:0] = 4'h3;
1940
    2'h3 : RxByteSel[3:0] = 4'h1;
1941 96 mohor
  endcase
1942
end
1943
 
1944
 
1945
always @ (posedge WB_CLK_I or posedge Reset)
1946
begin
1947
  if(Reset)
1948 40 mohor
    RxEn_needed <=#Tp 1'b0;
1949 38 mohor
  else
1950 166 mohor
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1951 40 mohor
    RxEn_needed <=#Tp 1'b1;
1952 38 mohor
  else
1953 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1954
    RxEn_needed <=#Tp 1'b0;
1955 38 mohor
end
1956
 
1957
 
1958 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1959
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1960 38 mohor
 
1961 40 mohor
reg RxEnableWindow;
1962 38 mohor
 
1963
// Indicating that last byte is being reveived
1964 40 mohor
always @ (posedge MRxClk or posedge Reset)
1965 38 mohor
begin
1966 40 mohor
  if(Reset)
1967 38 mohor
    LastByteIn <=#Tp 1'b0;
1968
  else
1969 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1970 38 mohor
    LastByteIn <=#Tp 1'b0;
1971
  else
1972 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1973 38 mohor
    LastByteIn <=#Tp 1'b1;
1974
end
1975
 
1976 159 mohor
reg ShiftEnded_rck;
1977 40 mohor
reg ShiftEndedSync1;
1978
reg ShiftEndedSync2;
1979 118 mohor
reg ShiftEndedSync3;
1980
reg ShiftEndedSync_c1;
1981
reg ShiftEndedSync_c2;
1982
 
1983 40 mohor
wire StartShiftWillEnd;
1984 96 mohor
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1985 38 mohor
 
1986
// Indicating that data reception will end
1987 40 mohor
always @ (posedge MRxClk or posedge Reset)
1988 38 mohor
begin
1989 40 mohor
  if(Reset)
1990 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1991
  else
1992 159 mohor
  if(ShiftEnded_rck | RxAbort)
1993 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1994
  else
1995 40 mohor
  if(StartShiftWillEnd)
1996 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
1997
end
1998
 
1999
 
2000 40 mohor
 
2001 38 mohor
// Receive byte counter
2002 40 mohor
always @ (posedge MRxClk or posedge Reset)
2003 38 mohor
begin
2004 40 mohor
  if(Reset)
2005 38 mohor
    RxByteCnt <=#Tp 2'h0;
2006
  else
2007 159 mohor
  if(ShiftEnded_rck | RxAbort)
2008 38 mohor
    RxByteCnt <=#Tp 2'h0;
2009 97 lampret
  else
2010 166 mohor
  if(RxValid & RxStartFrm & RxReady)
2011 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2012 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
2013
      2'h1 : RxByteCnt <=#Tp 2'h2;
2014
      2'h2 : RxByteCnt <=#Tp 2'h3;
2015
      2'h3 : RxByteCnt <=#Tp 2'h0;
2016
    endcase
2017 38 mohor
  else
2018 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
2019 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
2020 38 mohor
end
2021
 
2022
 
2023
// Indicates how many bytes are valid within the last word
2024 40 mohor
always @ (posedge MRxClk or posedge Reset)
2025 38 mohor
begin
2026 40 mohor
  if(Reset)
2027 38 mohor
    RxValidBytes <=#Tp 2'h1;
2028
  else
2029 96 mohor
  if(RxValid & RxStartFrm)
2030 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2031 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
2032
      2'h1 : RxValidBytes <=#Tp 2'h2;
2033
      2'h2 : RxValidBytes <=#Tp 2'h3;
2034
      2'h3 : RxValidBytes <=#Tp 2'h0;
2035
    endcase
2036 38 mohor
  else
2037 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2038 38 mohor
    RxValidBytes <=#Tp RxValidBytes + 1;
2039
end
2040
 
2041
 
2042 40 mohor
always @ (posedge MRxClk or posedge Reset)
2043 38 mohor
begin
2044 40 mohor
  if(Reset)
2045
    RxDataLatched1       <=#Tp 24'h0;
2046 38 mohor
  else
2047 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2048 96 mohor
    if(RxStartFrm)
2049 40 mohor
    begin
2050 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2051 96 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2052
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2053
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2054
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2055
      endcase
2056
    end
2057
    else if (RxEnableWindow)
2058
    begin
2059 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2060 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2061
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2062
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2063 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2064
      endcase
2065
    end
2066 38 mohor
end
2067
 
2068 40 mohor
wire SetWriteRxDataToFifo;
2069 38 mohor
 
2070 40 mohor
// Assembling data that will be written to the rx_fifo
2071
always @ (posedge MRxClk or posedge Reset)
2072 38 mohor
begin
2073 40 mohor
  if(Reset)
2074
    RxDataLatched2 <=#Tp 32'h0;
2075 38 mohor
  else
2076 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2077 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
2078 38 mohor
  else
2079 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2080 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2081 82 mohor
 
2082
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2083
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
2084
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
2085 40 mohor
    endcase
2086 38 mohor
end
2087
 
2088
 
2089 40 mohor
reg WriteRxDataToFifoSync1;
2090
reg WriteRxDataToFifoSync2;
2091 150 mohor
reg WriteRxDataToFifoSync3;
2092 38 mohor
 
2093
 
2094 40 mohor
// Indicating start of the reception process
2095 166 mohor
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
2096
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
2097
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
2098 38 mohor
 
2099 150 mohor
always @ (posedge MRxClk or posedge Reset)
2100
begin
2101
  if(Reset)
2102
    WriteRxDataToFifo <=#Tp 1'b0;
2103
  else
2104
  if(SetWriteRxDataToFifo & ~RxAbort)
2105
    WriteRxDataToFifo <=#Tp 1'b1;
2106
  else
2107
  if(WriteRxDataToFifoSync2 | RxAbort)
2108
    WriteRxDataToFifo <=#Tp 1'b0;
2109
end
2110 40 mohor
 
2111 150 mohor
 
2112
 
2113
always @ (posedge WB_CLK_I or posedge Reset)
2114
begin
2115
  if(Reset)
2116
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2117
  else
2118
  if(WriteRxDataToFifo)
2119
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
2120
  else
2121
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2122
end
2123
 
2124
always @ (posedge WB_CLK_I or posedge Reset)
2125
begin
2126
  if(Reset)
2127
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
2128
  else
2129
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
2130
end
2131
 
2132
always @ (posedge WB_CLK_I or posedge Reset)
2133
begin
2134
  if(Reset)
2135
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
2136
  else
2137
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
2138
end
2139
 
2140
wire WriteRxDataToFifo_wb;
2141
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
2142
 
2143
 
2144 90 mohor
reg LatchedRxStartFrm;
2145
reg SyncRxStartFrm;
2146
reg SyncRxStartFrm_q;
2147 150 mohor
reg SyncRxStartFrm_q2;
2148 90 mohor
wire RxFifoReset;
2149 40 mohor
 
2150 90 mohor
always @ (posedge MRxClk or posedge Reset)
2151
begin
2152
  if(Reset)
2153
    LatchedRxStartFrm <=#Tp 0;
2154
  else
2155 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2156 90 mohor
    LatchedRxStartFrm <=#Tp 1;
2157
  else
2158 150 mohor
  if(SyncRxStartFrm_q)
2159 90 mohor
    LatchedRxStartFrm <=#Tp 0;
2160
end
2161
 
2162
 
2163
always @ (posedge WB_CLK_I or posedge Reset)
2164
begin
2165
  if(Reset)
2166
    SyncRxStartFrm <=#Tp 0;
2167
  else
2168
  if(LatchedRxStartFrm)
2169
    SyncRxStartFrm <=#Tp 1;
2170
  else
2171
    SyncRxStartFrm <=#Tp 0;
2172
end
2173
 
2174
 
2175
always @ (posedge WB_CLK_I or posedge Reset)
2176
begin
2177
  if(Reset)
2178
    SyncRxStartFrm_q <=#Tp 0;
2179
  else
2180
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
2181
end
2182
 
2183 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2184
begin
2185
  if(Reset)
2186
    SyncRxStartFrm_q2 <=#Tp 0;
2187
  else
2188
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
2189
end
2190 90 mohor
 
2191
 
2192 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2193 90 mohor
 
2194 150 mohor
 
2195 219 mohor
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
2196 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
2197
         .clk(WB_CLK_I),                                .reset(Reset),
2198 219 mohor
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
2199 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
2200 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
2201 150 mohor
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
2202 88 mohor
        );
2203 40 mohor
 
2204 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2205
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2206 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2207 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2208 40 mohor
 
2209
 
2210
// Generation of the end-of-frame signal
2211
always @ (posedge MRxClk or posedge Reset)
2212 38 mohor
begin
2213 40 mohor
  if(Reset)
2214 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2215 38 mohor
  else
2216 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2217 159 mohor
    ShiftEnded_rck <=#Tp 1'b1;
2218 38 mohor
  else
2219 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2220 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2221 38 mohor
end
2222
 
2223 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2224
begin
2225
  if(Reset)
2226
    ShiftEndedSync1 <=#Tp 1'b0;
2227
  else
2228 159 mohor
    ShiftEndedSync1 <=#Tp ShiftEnded_rck;
2229 40 mohor
end
2230 38 mohor
 
2231 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2232 38 mohor
begin
2233 40 mohor
  if(Reset)
2234
    ShiftEndedSync2 <=#Tp 1'b0;
2235 38 mohor
  else
2236 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
2237 40 mohor
end
2238 38 mohor
 
2239 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2240
begin
2241
  if(Reset)
2242
    ShiftEndedSync3 <=#Tp 1'b0;
2243
  else
2244
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2245
    ShiftEndedSync3 <=#Tp 1'b1;
2246
  else
2247
  if(ShiftEnded)
2248
    ShiftEndedSync3 <=#Tp 1'b0;
2249
end
2250 38 mohor
 
2251 40 mohor
// Generation of the end-of-frame signal
2252
always @ (posedge WB_CLK_I or posedge Reset)
2253 38 mohor
begin
2254 40 mohor
  if(Reset)
2255
    ShiftEnded <=#Tp 1'b0;
2256 38 mohor
  else
2257 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2258 40 mohor
    ShiftEnded <=#Tp 1'b1;
2259 38 mohor
  else
2260 40 mohor
  if(RxStatusWrite)
2261
    ShiftEnded <=#Tp 1'b0;
2262 38 mohor
end
2263
 
2264 118 mohor
always @ (posedge MRxClk or posedge Reset)
2265
begin
2266
  if(Reset)
2267
    ShiftEndedSync_c1 <=#Tp 1'b0;
2268
  else
2269
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
2270
end
2271 38 mohor
 
2272 118 mohor
always @ (posedge MRxClk or posedge Reset)
2273
begin
2274
  if(Reset)
2275
    ShiftEndedSync_c2 <=#Tp 1'b0;
2276
  else
2277
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
2278
end
2279
 
2280 40 mohor
// Generation of the end-of-frame signal
2281
always @ (posedge MRxClk or posedge Reset)
2282 38 mohor
begin
2283 40 mohor
  if(Reset)
2284
    RxEnableWindow <=#Tp 1'b0;
2285 38 mohor
  else
2286 40 mohor
  if(RxStartFrm)
2287
    RxEnableWindow <=#Tp 1'b1;
2288 38 mohor
  else
2289 40 mohor
  if(RxEndFrm | RxAbort)
2290
    RxEnableWindow <=#Tp 1'b0;
2291 38 mohor
end
2292
 
2293
 
2294 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2295 38 mohor
begin
2296 40 mohor
  if(Reset)
2297
    RxAbortSync1 <=#Tp 1'b0;
2298 38 mohor
  else
2299 150 mohor
    RxAbortSync1 <=#Tp RxAbortLatched;
2300 40 mohor
end
2301
 
2302
always @ (posedge WB_CLK_I or posedge Reset)
2303
begin
2304
  if(Reset)
2305
    RxAbortSync2 <=#Tp 1'b0;
2306 38 mohor
  else
2307 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
2308 38 mohor
end
2309
 
2310 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2311
begin
2312
  if(Reset)
2313
    RxAbortSync3 <=#Tp 1'b0;
2314
  else
2315
    RxAbortSync3 <=#Tp RxAbortSync2;
2316
end
2317
 
2318
always @ (posedge WB_CLK_I or posedge Reset)
2319
begin
2320
  if(Reset)
2321
    RxAbortSync4 <=#Tp 1'b0;
2322
  else
2323
    RxAbortSync4 <=#Tp RxAbortSync3;
2324
end
2325
 
2326 40 mohor
always @ (posedge MRxClk or posedge Reset)
2327
begin
2328
  if(Reset)
2329
    RxAbortSyncb1 <=#Tp 1'b0;
2330
  else
2331
    RxAbortSyncb1 <=#Tp RxAbortSync2;
2332
end
2333 38 mohor
 
2334 40 mohor
always @ (posedge MRxClk or posedge Reset)
2335 38 mohor
begin
2336 40 mohor
  if(Reset)
2337
    RxAbortSyncb2 <=#Tp 1'b0;
2338 38 mohor
  else
2339 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
2340 38 mohor
end
2341
 
2342
 
2343 64 mohor
always @ (posedge MRxClk or posedge Reset)
2344
begin
2345
  if(Reset)
2346
    RxAbortLatched <=#Tp 1'b0;
2347
  else
2348 150 mohor
  if(RxAbortSyncb2)
2349
    RxAbortLatched <=#Tp 1'b0;
2350
  else
2351 64 mohor
  if(RxAbort)
2352
    RxAbortLatched <=#Tp 1'b1;
2353
end
2354 40 mohor
 
2355 64 mohor
 
2356 42 mohor
always @ (posedge MRxClk or posedge Reset)
2357
begin
2358
  if(Reset)
2359
    LatchedRxLength[15:0] <=#Tp 16'h0;
2360
  else
2361 150 mohor
  if(LoadRxStatus)
2362 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
2363
end
2364
 
2365
 
2366 261 mohor
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2367 42 mohor
 
2368
always @ (posedge MRxClk or posedge Reset)
2369
begin
2370
  if(Reset)
2371
    RxStatusInLatched <=#Tp 'h0;
2372
  else
2373 150 mohor
  if(LoadRxStatus)
2374 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
2375
end
2376
 
2377
 
2378 60 mohor
// Rx overrun
2379
always @ (posedge WB_CLK_I or posedge Reset)
2380
begin
2381
  if(Reset)
2382
    RxOverrun <=#Tp 1'b0;
2383
  else
2384
  if(RxStatusWrite)
2385
    RxOverrun <=#Tp 1'b0;
2386
  else
2387
  if(RxBufferFull & WriteRxDataToFifo_wb)
2388
    RxOverrun <=#Tp 1'b1;
2389
end
2390 48 mohor
 
2391 77 mohor
 
2392
 
2393
wire TxError;
2394
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2395
 
2396
wire RxError;
2397
 
2398 239 tadejm
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
2399 250 mohor
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
2400
// AddressMiss is identifying that a frame was received because of the promiscous
2401
// mode and is not an error
2402 239 tadejm
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
2403
 
2404 272 tadejm
 
2405
 
2406
reg RxStatusWriteLatched;
2407
reg RxStatusWriteLatched_sync1;
2408
reg RxStatusWriteLatched_sync2;
2409
reg RxStatusWriteLatched_syncb1;
2410
reg RxStatusWriteLatched_syncb2;
2411
 
2412
 
2413
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
2414
always @ (posedge WB_CLK_I or posedge Reset)
2415
begin
2416
  if(Reset)
2417
    RxStatusWriteLatched <=#Tp 1'b0;
2418
  else
2419
  if(RxStatusWriteLatched_syncb2)
2420
    RxStatusWriteLatched <=#Tp 1'b0;
2421
  else
2422
  if(RxStatusWrite)
2423
    RxStatusWriteLatched <=#Tp 1'b1;
2424
end
2425
 
2426
 
2427
always @ (posedge MRxClk or posedge Reset)
2428
begin
2429
  if(Reset)
2430
    begin
2431
      RxStatusWriteLatched_sync1 <=#Tp 1'b0;
2432
      RxStatusWriteLatched_sync2 <=#Tp 1'b0;
2433
    end
2434
  else
2435
    begin
2436
      RxStatusWriteLatched_sync1 <=#Tp RxStatusWriteLatched;
2437
      RxStatusWriteLatched_sync2 <=#Tp RxStatusWriteLatched_sync1;
2438
    end
2439
end
2440
 
2441
 
2442
always @ (posedge WB_CLK_I or posedge Reset)
2443
begin
2444
  if(Reset)
2445
    begin
2446
      RxStatusWriteLatched_syncb1 <=#Tp 1'b0;
2447
      RxStatusWriteLatched_syncb2 <=#Tp 1'b0;
2448
    end
2449
  else
2450
    begin
2451
      RxStatusWriteLatched_syncb1 <=#Tp RxStatusWriteLatched_sync2;
2452
      RxStatusWriteLatched_syncb2 <=#Tp RxStatusWriteLatched_syncb1;
2453
    end
2454
end
2455
 
2456
 
2457
 
2458 77 mohor
// Tx Done Interrupt
2459
always @ (posedge WB_CLK_I or posedge Reset)
2460
begin
2461
  if(Reset)
2462
    TxB_IRQ <=#Tp 1'b0;
2463
  else
2464
  if(TxStatusWrite & TxIRQEn)
2465
    TxB_IRQ <=#Tp ~TxError;
2466
  else
2467
    TxB_IRQ <=#Tp 1'b0;
2468
end
2469
 
2470
 
2471
// Tx Error Interrupt
2472
always @ (posedge WB_CLK_I or posedge Reset)
2473
begin
2474
  if(Reset)
2475
    TxE_IRQ <=#Tp 1'b0;
2476
  else
2477
  if(TxStatusWrite & TxIRQEn)
2478
    TxE_IRQ <=#Tp TxError;
2479
  else
2480
    TxE_IRQ <=#Tp 1'b0;
2481
end
2482
 
2483
 
2484
// Rx Done Interrupt
2485
always @ (posedge WB_CLK_I or posedge Reset)
2486
begin
2487
  if(Reset)
2488
    RxB_IRQ <=#Tp 1'b0;
2489
  else
2490 270 mohor
  if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
2491
    RxB_IRQ <=#Tp (~RxError);
2492 77 mohor
  else
2493
    RxB_IRQ <=#Tp 1'b0;
2494
end
2495
 
2496
 
2497
// Rx Error Interrupt
2498
always @ (posedge WB_CLK_I or posedge Reset)
2499
begin
2500
  if(Reset)
2501
    RxE_IRQ <=#Tp 1'b0;
2502
  else
2503 270 mohor
  if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
2504 77 mohor
    RxE_IRQ <=#Tp RxError;
2505
  else
2506
    RxE_IRQ <=#Tp 1'b0;
2507
end
2508
 
2509
 
2510 166 mohor
// Busy Interrupt
2511 77 mohor
 
2512 166 mohor
reg Busy_IRQ_rck;
2513
reg Busy_IRQ_sync1;
2514
reg Busy_IRQ_sync2;
2515
reg Busy_IRQ_sync3;
2516
reg Busy_IRQ_syncb1;
2517
reg Busy_IRQ_syncb2;
2518 77 mohor
 
2519
 
2520 166 mohor
always @ (posedge MRxClk or posedge Reset)
2521
begin
2522
  if(Reset)
2523
    Busy_IRQ_rck <=#Tp 1'b0;
2524
  else
2525
  if(RxValid & RxStartFrm & ~RxReady)
2526
    Busy_IRQ_rck <=#Tp 1'b1;
2527
  else
2528
  if(Busy_IRQ_syncb2)
2529
    Busy_IRQ_rck <=#Tp 1'b0;
2530
end
2531 77 mohor
 
2532 166 mohor
always @ (posedge WB_CLK_I)
2533
begin
2534
    Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
2535
    Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
2536
    Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
2537
end
2538
 
2539
always @ (posedge MRxClk)
2540
begin
2541
    Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
2542
    Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
2543
end
2544
 
2545
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
2546
 
2547
 
2548 60 mohor
 
2549
 
2550
 
2551 38 mohor
endmodule

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