OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 321

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 321 igorm
// Revision 1.54  2003/11/12 18:24:59  tadejm
45
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
46
//
47 304 tadejm
// Revision 1.53  2003/10/17 07:46:17  markom
48
// mbist signals updated according to newest convention
49
//
50 302 markom
// Revision 1.52  2003/01/30 14:51:31  mohor
51
// Reset has priority in some flipflops.
52
//
53 280 mohor
// Revision 1.51  2003/01/30 13:36:22  mohor
54
// A new bug (entered with previous update) fixed. When abort occured sometimes
55
// data transmission was blocked.
56
//
57 278 mohor
// Revision 1.50  2003/01/22 13:49:26  tadejm
58
// When control packets were received, they were ignored in some cases.
59
//
60 272 tadejm
// Revision 1.49  2003/01/21 12:09:40  mohor
61
// When receiving normal data frame and RxFlow control was switched on, RXB
62
// interrupt was not set.
63
//
64 270 mohor
// Revision 1.48  2003/01/20 12:05:26  mohor
65
// When in full duplex, transmit was sometimes blocked. Fixed.
66
//
67 269 mohor
// Revision 1.47  2002/11/22 13:26:21  mohor
68
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
69
// anywhere. Removed.
70
//
71 264 mohor
// Revision 1.46  2002/11/22 01:57:06  mohor
72
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
73
// synchronized.
74
//
75 261 mohor
// Revision 1.45  2002/11/19 17:33:34  mohor
76
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
77
// that a frame was received because of the promiscous mode.
78
//
79 250 mohor
// Revision 1.44  2002/11/13 22:21:40  tadejm
80
// RxError is not generated when small frame reception is enabled and small
81
// frames are received.
82
//
83 239 tadejm
// Revision 1.43  2002/10/18 20:53:34  mohor
84
// case changed to casex.
85
//
86 229 mohor
// Revision 1.42  2002/10/18 17:04:20  tadejm
87
// Changed BIST scan signals.
88
//
89 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
90
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
91
//
92 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
93
// TxStatus is written after last access to the TX fifo is finished (in case of abort
94
// or retry). TxDone is fixed.
95
//
96 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
97
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
98
// TxDone and TxRetry are generated after the current WISHBONE access is
99
// finished.
100
//
101 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
102
// BIST added.
103
//
104 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
105
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
106
//
107 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
108
// Reception is possible after RxPointer is read and not after BD is read. For
109
// that reason RxBDReady is changed to RxReady.
110
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
111
// comes, interrupt is generated.
112
//
113 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
114
// Ethernet debug registers removed.
115
//
116 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
117
// Async reset for WB_ACK_O removed (when core was in reset, it was
118
// impossible to access BDs).
119
// RxPointers and TxPointers names changed to be more descriptive.
120
// TxUnderRun synchronized.
121
//
122 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
123
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
124
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
125
// was not used OK.
126
//
127 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
128
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
129
// need to multiply or devide any more.
130
//
131 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
132
// WriteRxDataToMemory signal changed so end of frame (when last word is
133
// written to fifo) is changed.
134
//
135 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
136
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
137
//
138 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
139
// ShiftEnded synchronization changed.
140
//
141 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
142
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
143
//
144 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
145
// RxPointer bug fixed.
146
//
147 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
148
// Previous bug wasn't succesfully removed. Now fixed.
149
//
150 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
151
// Master state machine had a bug when switching from master write to
152
// master read.
153
//
154 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
155
// m_wb_cyc_o signal released after every single transfer.
156
//
157 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
158
// Outputs registered. Reset changed for eth_wishbone module.
159
//
160 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
161
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
162
// bug fixed.
163
//
164 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
165
// Small typo fixed.
166
//
167 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
168
// Any address can be used for Tx and Rx BD pointers. Address does not need
169
// to be aligned.
170
//
171 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
172
// Comments in Slovene language removed.
173
//
174 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
175
// casex changed with case, fifo reset changed.
176
//
177 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
178
// rx_fifo was not always cleared ok. Fixed.
179
//
180 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
181
// Status was not latched correctly sometimes. Fixed.
182
//
183 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
184
// Big Endian problem when sending frames fixed.
185
//
186 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
187
// Byte ordering changed (Big Endian used). casex changed with case because
188
// Xilinx Foundation had problems. Tested in HW. It WORKS.
189
//
190 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
191
// Small fixes for external/internal DMA missmatches.
192
//
193 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
194
// Interrupts changed
195
//
196 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
197
// Status was not written correctly when frames were discarted because of
198
// address mismatch.
199
//
200 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
201
// RxStartFrm cleared when abort or retry comes.
202
//
203 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
204
// Changes that were lost when updating from 1.5 to 1.8 fixed.
205
//
206 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
207
// Addition  of new module eth_addrcheck.v
208
//
209
// Revision 1.7  2002/02/12 17:03:47  mohor
210
// RxOverRun added to statuses.
211
//
212
// Revision 1.6  2002/02/11 09:18:22  mohor
213
// Tx status is written back to the BD.
214
//
215 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
216
// Rx status is written back to the BD.
217
//
218 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
219
// non-DMA host interface added. Select the right configutation in eth_defines.
220
//
221 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
222
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
223
// MHz. Statuses, overrun, control frame transmission and reception still  need
224
// to be fixed.
225
//
226 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
227
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
228
// added.
229
//
230 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
231
// Initial version. Equals to eth_wishbonedma.v at this moment.
232 38 mohor
//
233
//
234
//
235
 
236
`include "eth_defines.v"
237
`include "timescale.v"
238
 
239
 
240
module eth_wishbone
241
   (
242
 
243
    // WISHBONE common
244 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
245 38 mohor
 
246
    // WISHBONE slave
247 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
248 40 mohor
    BDCs,
249 38 mohor
 
250 40 mohor
    Reset,
251
 
252 39 mohor
    // WISHBONE master
253
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
254
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
255
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
256
 
257 219 mohor
`ifdef ETH_WISHBONE_B3
258
    m_wb_cti_o, m_wb_bte_o,
259
`endif
260
 
261 38 mohor
    //TX
262 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
263 150 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
264 38 mohor
    PerPacketPad,
265
 
266
    //RX
267 272 tadejm
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
268 38 mohor
 
269
    // Register
270 321 igorm
    r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
271 38 mohor
 
272
    // Interrupts
273 150 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
274 42 mohor
 
275 60 mohor
    // Rx Status
276 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
277 250 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
278 261 mohor
    ReceivedPauseFrm,
279 60 mohor
 
280
    // Tx Status
281 164 mohor
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
282
 
283 210 mohor
    // Bist
284
`ifdef ETH_BIST
285 227 tadejm
    ,
286
    // debug chain signals
287 302 markom
    mbist_si_i,       // bist scan serial in
288
    mbist_so_o,       // bist scan serial out
289
    mbist_ctrl_i        // bist chain shift control
290 210 mohor
`endif
291
 
292
 
293
 
294 38 mohor
                );
295
 
296
 
297
parameter Tp = 1;
298
 
299 150 mohor
 
300 38 mohor
// WISHBONE common
301
input           WB_CLK_I;       // WISHBONE clock
302
input  [31:0]   WB_DAT_I;       // WISHBONE data input
303
output [31:0]   WB_DAT_O;       // WISHBONE data output
304
 
305
// WISHBONE slave
306
input   [9:2]   WB_ADR_I;       // WISHBONE address input
307
input           WB_WE_I;        // WISHBONE write enable input
308 304 tadejm
input   [3:0]   BDCs;           // Buffer descriptors are selected
309 38 mohor
output          WB_ACK_O;       // WISHBONE acknowledge output
310
 
311 39 mohor
// WISHBONE master
312
output  [31:0]  m_wb_adr_o;     // 
313
output   [3:0]  m_wb_sel_o;     // 
314
output          m_wb_we_o;      // 
315
output  [31:0]  m_wb_dat_o;     // 
316
output          m_wb_cyc_o;     // 
317
output          m_wb_stb_o;     // 
318
input   [31:0]  m_wb_dat_i;     // 
319
input           m_wb_ack_i;     // 
320
input           m_wb_err_i;     // 
321
 
322 219 mohor
`ifdef ETH_WISHBONE_B3
323
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
324
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
325
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
326
`endif
327
 
328 40 mohor
input           Reset;       // Reset signal
329 39 mohor
 
330 60 mohor
// Rx Status signals
331 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
332
input           LatchedCrcError;  // CRC error
333
input           RxLateCollision;  // Late collision occured while receiving frame
334
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
335
input           DribbleNibble;    // Extra nibble received
336
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
337
input    [15:0] RxLength;         // Length of the incoming frame
338
input           LoadRxStatus;     // Rx status was loaded
339 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
340 250 mohor
input           AddressMiss;      // When a packet is received AddressMiss status is written to the Rx BD
341 261 mohor
input           r_RxFlow;
342 270 mohor
input           r_PassAll;
343 261 mohor
input           ReceivedPauseFrm;
344 39 mohor
 
345 60 mohor
// Tx Status signals
346
input     [3:0] RetryCntLatched;  // Latched Retry Counter
347
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
348
input           LateCollLatched;  // Late collision occured
349
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
350
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
351
 
352 38 mohor
// Tx
353
input           MTxClk;         // Transmit clock (from PHY)
354
input           TxUsedData;     // Transmit packet used data
355
input           TxRetry;        // Transmit packet retry
356
input           TxAbort;        // Transmit packet abort
357
input           TxDone;         // Transmission ended
358
output          TxStartFrm;     // Transmit packet start frame
359
output          TxEndFrm;       // Transmit packet end frame
360
output  [7:0]   TxData;         // Transmit packet data byte
361
output          TxUnderRun;     // Transmit packet under-run
362
output          PerPacketCrcEn; // Per packet crc enable
363
output          PerPacketPad;   // Per packet pading
364
 
365
// Rx
366
input           MRxClk;         // Receive clock (from PHY)
367
input   [7:0]   RxData;         // Received data byte (from PHY)
368
input           RxValid;        // 
369
input           RxStartFrm;     // 
370
input           RxEndFrm;       // 
371 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
372 272 tadejm
output          RxStatusWriteLatched_sync2;
373 38 mohor
 
374
//Register
375
input           r_TxEn;         // Transmit enable
376
input           r_RxEn;         // Receive enable
377
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
378
 
379
// Interrupts
380
output TxB_IRQ;
381
output TxE_IRQ;
382
output RxB_IRQ;
383 77 mohor
output RxE_IRQ;
384 38 mohor
output Busy_IRQ;
385
 
386 77 mohor
 
387 210 mohor
// Bist
388
`ifdef ETH_BIST
389 302 markom
input   mbist_si_i;       // bist scan serial in
390
output  mbist_so_o;       // bist scan serial out
391
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
392 210 mohor
`endif
393
 
394 77 mohor
reg TxB_IRQ;
395
reg TxE_IRQ;
396
reg RxB_IRQ;
397
reg RxE_IRQ;
398
 
399 38 mohor
reg             TxStartFrm;
400
reg             TxEndFrm;
401
reg     [7:0]   TxData;
402
 
403
reg             TxUnderRun;
404 60 mohor
reg             TxUnderRun_wb;
405 38 mohor
 
406
reg             TxBDRead;
407 39 mohor
wire            TxStatusWrite;
408 38 mohor
 
409
reg     [1:0]   TxValidBytesLatched;
410
 
411
reg    [15:0]   TxLength;
412 60 mohor
reg    [15:0]   LatchedTxLength;
413
reg   [14:11]   TxStatus;
414 38 mohor
 
415 60 mohor
reg   [14:13]   RxStatus;
416 38 mohor
 
417
reg             TxStartFrm_wb;
418
reg             TxRetry_wb;
419 39 mohor
reg             TxAbort_wb;
420 38 mohor
reg             TxDone_wb;
421
 
422
reg             TxDone_wb_q;
423
reg             TxAbort_wb_q;
424 39 mohor
reg             TxRetry_wb_q;
425 219 mohor
reg             TxRetryPacket;
426 221 mohor
reg             TxRetryPacket_NotCleared;
427
reg             TxDonePacket;
428
reg             TxDonePacket_NotCleared;
429 219 mohor
reg             TxAbortPacket;
430 221 mohor
reg             TxAbortPacket_NotCleared;
431 38 mohor
reg             RxBDReady;
432 166 mohor
reg             RxReady;
433 38 mohor
reg             TxBDReady;
434
 
435
reg             RxBDRead;
436
 
437
reg    [31:0]   TxDataLatched;
438
reg     [1:0]   TxByteCnt;
439
reg             LastWord;
440 39 mohor
reg             ReadTxDataFromFifo_tck;
441 38 mohor
 
442
reg             BlockingTxStatusWrite;
443
reg             BlockingTxBDRead;
444
 
445 40 mohor
reg             Flop;
446 38 mohor
 
447
reg     [7:0]   TxBDAddress;
448
reg     [7:0]   RxBDAddress;
449
 
450
reg             TxRetrySync1;
451
reg             TxAbortSync1;
452 39 mohor
reg             TxDoneSync1;
453 38 mohor
 
454
reg             TxAbort_q;
455
reg             TxRetry_q;
456
reg             TxUsedData_q;
457
 
458
reg    [31:0]   RxDataLatched2;
459 82 mohor
 
460
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
461
 
462 38 mohor
reg     [1:0]   RxValidBytes;
463
reg     [1:0]   RxByteCnt;
464
reg             LastByteIn;
465
reg             ShiftWillEnd;
466
 
467 40 mohor
reg             WriteRxDataToFifo;
468 42 mohor
reg    [15:0]   LatchedRxLength;
469 64 mohor
reg             RxAbortLatched;
470 38 mohor
 
471 40 mohor
reg             ShiftEnded;
472 60 mohor
reg             RxOverrun;
473 38 mohor
 
474 304 tadejm
reg     [3:0]   BDWrite;                    // BD Write Enable for access from WISHBONE side
475 40 mohor
reg             BDRead;                     // BD Read access from WISHBONE side
476 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
477
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
478 38 mohor
 
479 39 mohor
reg             TxEndFrm_wb;
480 38 mohor
 
481 39 mohor
wire            TxRetryPulse;
482 38 mohor
wire            TxDonePulse;
483
wire            TxAbortPulse;
484
 
485
wire            StartRxBDRead;
486
 
487
wire            StartTxBDRead;
488
 
489
wire            TxIRQEn;
490
wire            WrapTxStatusBit;
491
 
492 77 mohor
wire            RxIRQEn;
493 38 mohor
wire            WrapRxStatusBit;
494
 
495
wire    [1:0]   TxValidBytes;
496
 
497
wire    [7:0]   TempTxBDAddress;
498
wire    [7:0]   TempRxBDAddress;
499
 
500 272 tadejm
wire            RxStatusWrite;
501
 
502 106 mohor
reg             WB_ACK_O;
503 38 mohor
 
504 261 mohor
wire    [8:0]   RxStatusIn;
505
reg     [8:0]   RxStatusInLatched;
506 42 mohor
 
507 39 mohor
reg WbEn, WbEn_q;
508
reg RxEn, RxEn_q;
509
reg TxEn, TxEn_q;
510 321 igorm
reg r_TxEn_q;
511
reg r_RxEn_q;
512 38 mohor
 
513 39 mohor
wire ram_ce;
514 304 tadejm
wire [3:0]  ram_we;
515 39 mohor
wire ram_oe;
516
reg [7:0]   ram_addr;
517
reg [31:0]  ram_di;
518
wire [31:0] ram_do;
519 38 mohor
 
520 39 mohor
wire StartTxPointerRead;
521
reg  TxPointerRead;
522
reg TxEn_needed;
523 40 mohor
reg RxEn_needed;
524 38 mohor
 
525 40 mohor
wire StartRxPointerRead;
526
reg RxPointerRead;
527 38 mohor
 
528 219 mohor
`ifdef ETH_WISHBONE_B3
529
assign m_wb_bte_o = 2'b00;    // Linear burst
530
`endif
531 39 mohor
 
532 219 mohor
 
533 159 mohor
always @ (posedge WB_CLK_I)
534 40 mohor
begin
535 304 tadejm
  WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
536 40 mohor
end
537 39 mohor
 
538 106 mohor
assign WB_DAT_O = ram_do;
539 39 mohor
 
540 41 mohor
// Generic synchronous single-port RAM interface
541 119 mohor
eth_spram_256x32 bd_ram (
542 226 tadejm
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
543 210 mohor
`ifdef ETH_BIST
544 227 tadejm
  ,
545 302 markom
  .mbist_si_i       (mbist_si_i),
546
  .mbist_so_o       (mbist_so_o),
547
  .mbist_ctrl_i       (mbist_ctrl_i)
548 210 mohor
`endif
549 39 mohor
);
550 41 mohor
 
551 39 mohor
assign ram_ce = 1'b1;
552 304 tadejm
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | {4{(TxStatusWrite | RxStatusWrite)}};
553 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
554 39 mohor
 
555
 
556 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
557 38 mohor
begin
558 40 mohor
  if(Reset)
559 39 mohor
    TxEn_needed <=#Tp 1'b0;
560 38 mohor
  else
561 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
562 39 mohor
    TxEn_needed <=#Tp 1'b1;
563
  else
564
  if(TxPointerRead & TxEn & TxEn_q)
565
    TxEn_needed <=#Tp 1'b0;
566 38 mohor
end
567
 
568 39 mohor
// Enabling access to the RAM for three devices.
569 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
570 39 mohor
begin
571 40 mohor
  if(Reset)
572 39 mohor
    begin
573
      WbEn <=#Tp 1'b1;
574
      RxEn <=#Tp 1'b0;
575
      TxEn <=#Tp 1'b0;
576
      ram_addr <=#Tp 8'h0;
577
      ram_di <=#Tp 32'h0;
578 77 mohor
      BDRead <=#Tp 1'b0;
579
      BDWrite <=#Tp 1'b0;
580 39 mohor
    end
581
  else
582
    begin
583
      // Switching between three stages depends on enable signals
584 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
585
        5'b100_10, 5'b100_11 :
586 39 mohor
          begin
587
            WbEn <=#Tp 1'b0;
588
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
589
            TxEn <=#Tp 1'b0;
590 40 mohor
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
591 39 mohor
            ram_di <=#Tp RxBDDataIn;
592
          end
593
        5'b100_01 :
594
          begin
595
            WbEn <=#Tp 1'b0;
596
            RxEn <=#Tp 1'b0;
597
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
598
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
599
            ram_di <=#Tp TxBDDataIn;
600
          end
601 90 mohor
        5'b010_00, 5'b010_10 :
602 39 mohor
          begin
603
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
604
            RxEn <=#Tp 1'b0;
605
            TxEn <=#Tp 1'b0;
606
            ram_addr <=#Tp WB_ADR_I[9:2];
607
            ram_di <=#Tp WB_DAT_I;
608 304 tadejm
            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
609
            BDRead <=#Tp (|BDCs) & ~WB_WE_I;
610 39 mohor
          end
611 90 mohor
        5'b010_01, 5'b010_11 :
612 39 mohor
          begin
613
            WbEn <=#Tp 1'b0;
614
            RxEn <=#Tp 1'b0;
615
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
616
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
617
            ram_di <=#Tp TxBDDataIn;
618
          end
619 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
620 39 mohor
          begin
621
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
622
            RxEn <=#Tp 1'b0;
623
            TxEn <=#Tp 1'b0;
624
            ram_addr <=#Tp WB_ADR_I[9:2];
625
            ram_di <=#Tp WB_DAT_I;
626 304 tadejm
            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
627
            BDRead <=#Tp (|BDCs) & ~WB_WE_I;
628 39 mohor
          end
629
        5'b100_00 :
630
          begin
631
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
632
          end
633
        5'b000_00 :
634
          begin
635
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
636
            RxEn <=#Tp 1'b0;
637
            TxEn <=#Tp 1'b0;
638
            ram_addr <=#Tp WB_ADR_I[9:2];
639
            ram_di <=#Tp WB_DAT_I;
640 304 tadejm
            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
641
            BDRead <=#Tp (|BDCs) & ~WB_WE_I;
642 39 mohor
          end
643
      endcase
644
    end
645
end
646
 
647
 
648
// Delayed stage signals
649 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
650 39 mohor
begin
651 40 mohor
  if(Reset)
652 39 mohor
    begin
653
      WbEn_q <=#Tp 1'b0;
654
      RxEn_q <=#Tp 1'b0;
655
      TxEn_q <=#Tp 1'b0;
656 321 igorm
      r_TxEn_q <=#Tp 1'b0;
657
      r_RxEn_q <=#Tp 1'b0;
658 39 mohor
    end
659
  else
660
    begin
661
      WbEn_q <=#Tp WbEn;
662
      RxEn_q <=#Tp RxEn;
663
      TxEn_q <=#Tp TxEn;
664 321 igorm
      r_RxEn_q <=#Tp r_RxEn;
665 39 mohor
    end
666
end
667
 
668 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
669 40 mohor
always @ (posedge MTxClk or posedge Reset)
670 38 mohor
begin
671 40 mohor
  if(Reset)
672 38 mohor
    Flop <=#Tp 1'b0;
673
  else
674
  if(TxDone | TxAbort | TxRetry_q)
675
    Flop <=#Tp 1'b0;
676
  else
677
  if(TxUsedData)
678
    Flop <=#Tp ~Flop;
679
end
680
 
681 39 mohor
wire ResetTxBDReady;
682
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
683 38 mohor
 
684
// Latching READY status of the Tx buffer descriptor
685 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
686 38 mohor
begin
687 40 mohor
  if(Reset)
688 38 mohor
    TxBDReady <=#Tp 1'b0;
689
  else
690 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
691
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
692
  else                                                // Only packets larger then 4 bytes are transmitted.
693 39 mohor
  if(ResetTxBDReady)
694 38 mohor
    TxBDReady <=#Tp 1'b0;
695
end
696
 
697
 
698 39 mohor
// Reading the Tx buffer descriptor
699 221 mohor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
700 39 mohor
 
701 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
702 38 mohor
begin
703 40 mohor
  if(Reset)
704 39 mohor
    TxBDRead <=#Tp 1'b1;
705 38 mohor
  else
706 110 mohor
  if(StartTxBDRead)
707 39 mohor
    TxBDRead <=#Tp 1'b1;
708 38 mohor
  else
709 39 mohor
  if(TxBDReady)
710
    TxBDRead <=#Tp 1'b0;
711 38 mohor
end
712
 
713
 
714 39 mohor
// Reading Tx BD pointer
715
assign StartTxPointerRead = TxBDRead & TxBDReady;
716 38 mohor
 
717 39 mohor
// Reading Tx BD Pointer
718 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
719 38 mohor
begin
720 40 mohor
  if(Reset)
721 39 mohor
    TxPointerRead <=#Tp 1'b0;
722 38 mohor
  else
723 39 mohor
  if(StartTxPointerRead)
724
    TxPointerRead <=#Tp 1'b1;
725 38 mohor
  else
726 39 mohor
  if(TxEn_q)
727
    TxPointerRead <=#Tp 1'b0;
728 38 mohor
end
729
 
730
 
731 39 mohor
// Writing status back to the Tx buffer descriptor
732 221 mohor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
733 38 mohor
 
734
 
735
 
736 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
737 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
738 38 mohor
begin
739 40 mohor
  if(Reset)
740 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
741 38 mohor
  else
742 272 tadejm
  if(~TxDone_wb & ~TxAbort_wb)
743
    BlockingTxStatusWrite <=#Tp 1'b0;
744
  else
745 39 mohor
  if(TxStatusWrite)
746
    BlockingTxStatusWrite <=#Tp 1'b1;
747 38 mohor
end
748
 
749
 
750 159 mohor
reg BlockingTxStatusWrite_sync1;
751
reg BlockingTxStatusWrite_sync2;
752
 
753
// Synchronizing BlockingTxStatusWrite to MTxClk
754
always @ (posedge MTxClk or posedge Reset)
755
begin
756
  if(Reset)
757
    BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
758
  else
759
    BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
760
end
761
 
762
// Synchronizing BlockingTxStatusWrite to MTxClk
763
always @ (posedge MTxClk or posedge Reset)
764
begin
765
  if(Reset)
766
    BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
767
  else
768
    BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
769
end
770
 
771
 
772 39 mohor
// TxBDRead state is activated only once. 
773 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
774 39 mohor
begin
775 40 mohor
  if(Reset)
776 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
777
  else
778 110 mohor
  if(StartTxBDRead)
779 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
780
  else
781 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
782 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
783
end
784 38 mohor
 
785
 
786 39 mohor
// Latching status from the tx buffer descriptor
787
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
788 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
789 38 mohor
begin
790 40 mohor
  if(Reset)
791 60 mohor
    TxStatus <=#Tp 4'h0;
792 38 mohor
  else
793 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
794 60 mohor
    TxStatus <=#Tp ram_do[14:11];
795 38 mohor
end
796
 
797 40 mohor
reg ReadTxDataFromMemory;
798
wire WriteRxDataToMemory;
799 38 mohor
 
800 39 mohor
reg MasterWbTX;
801
reg MasterWbRX;
802
 
803
reg [31:0] m_wb_adr_o;
804
reg        m_wb_cyc_o;
805
reg        m_wb_stb_o;
806 96 mohor
reg  [3:0] m_wb_sel_o;
807 39 mohor
reg        m_wb_we_o;
808 40 mohor
 
809 39 mohor
wire TxLengthEq0;
810
wire TxLengthLt4;
811
 
812 150 mohor
reg BlockingIncrementTxPointer;
813 159 mohor
reg [31:2] TxPointerMSB;
814
reg [1:0]  TxPointerLSB;
815
reg [1:0]  TxPointerLSB_rst;
816
reg [31:2] RxPointerMSB;
817
reg [1:0]  RxPointerLSB_rst;
818 39 mohor
 
819 150 mohor
wire RxBurstAcc;
820
wire RxWordAcc;
821
wire RxHalfAcc;
822
wire RxByteAcc;
823
 
824 39 mohor
//Latching length from the buffer descriptor;
825 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
826 38 mohor
begin
827 40 mohor
  if(Reset)
828 39 mohor
    TxLength <=#Tp 16'h0;
829 38 mohor
  else
830 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
831
    TxLength <=#Tp ram_do[31:16];
832 38 mohor
  else
833 39 mohor
  if(MasterWbTX & m_wb_ack_i)
834
    begin
835
      if(TxLengthLt4)
836
        TxLength <=#Tp 16'h0;
837 150 mohor
      else
838 159 mohor
      if(TxPointerLSB_rst==2'h0)
839 96 mohor
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
840 39 mohor
      else
841 159 mohor
      if(TxPointerLSB_rst==2'h1)
842 150 mohor
        TxLength <=#Tp TxLength - 3'h3;    // Length is subtracted at the data request
843
      else
844 159 mohor
      if(TxPointerLSB_rst==2'h2)
845 150 mohor
        TxLength <=#Tp TxLength - 3'h2;    // Length is subtracted at the data request
846
      else
847 159 mohor
      if(TxPointerLSB_rst==2'h3)
848 150 mohor
        TxLength <=#Tp TxLength - 3'h1;    // Length is subtracted at the data request
849 39 mohor
    end
850 38 mohor
end
851
 
852 96 mohor
 
853
 
854 60 mohor
//Latching length from the buffer descriptor;
855
always @ (posedge WB_CLK_I or posedge Reset)
856
begin
857
  if(Reset)
858
    LatchedTxLength <=#Tp 16'h0;
859
  else
860
  if(TxEn & TxEn_q & TxBDRead)
861
    LatchedTxLength <=#Tp ram_do[31:16];
862
end
863
 
864 39 mohor
assign TxLengthEq0 = TxLength == 0;
865
assign TxLengthLt4 = TxLength < 4;
866 38 mohor
 
867 150 mohor
reg cyc_cleared;
868
reg IncrTxPointer;
869 39 mohor
 
870
 
871 159 mohor
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
872
// because TxPointerMSB is only used for word-aligned accesses.
873 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
874 38 mohor
begin
875 40 mohor
  if(Reset)
876 159 mohor
    TxPointerMSB <=#Tp 30'h0;
877 38 mohor
  else
878 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
879 159 mohor
    TxPointerMSB <=#Tp ram_do[31:2];
880 38 mohor
  else
881 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
882 159 mohor
    TxPointerMSB <=#Tp TxPointerMSB + 1'b1;     // TxPointer is word-aligned
883 38 mohor
end
884
 
885 96 mohor
 
886 159 mohor
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
887
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
888
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
889
// set by this two bits.
890 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
891
begin
892
  if(Reset)
893 159 mohor
    TxPointerLSB[1:0] <=#Tp 0;
894 96 mohor
  else
895
  if(TxEn & TxEn_q & TxPointerRead)
896 159 mohor
    TxPointerLSB[1:0] <=#Tp ram_do[1:0];
897 96 mohor
end
898
 
899
 
900 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
901
// After the read access, TxLength needs to be decremented for the number of the valid
902
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
903
// valid so this two bits are reset to zero. 
904 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
905
begin
906
  if(Reset)
907 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
908 150 mohor
  else
909
  if(TxEn & TxEn_q & TxPointerRead)
910 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
911 150 mohor
  else
912
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
913 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
914 150 mohor
end
915 96 mohor
 
916 150 mohor
 
917 159 mohor
reg  [3:0] RxByteSel;
918 39 mohor
wire MasterAccessFinished;
919 38 mohor
 
920 39 mohor
 
921 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
922 38 mohor
begin
923 40 mohor
  if(Reset)
924 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
925 38 mohor
  else
926 39 mohor
  if(MasterAccessFinished)
927
    BlockingIncrementTxPointer <=#Tp 0;
928 38 mohor
  else
929 150 mohor
  if(IncrTxPointer)
930 39 mohor
    BlockingIncrementTxPointer <=#Tp 1'b1;
931 38 mohor
end
932
 
933
 
934 39 mohor
wire TxBufferAlmostFull;
935
wire TxBufferFull;
936
wire TxBufferEmpty;
937
wire TxBufferAlmostEmpty;
938 40 mohor
wire SetReadTxDataFromMemory;
939 39 mohor
 
940 40 mohor
reg BlockReadTxDataFromMemory;
941 39 mohor
 
942 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
943 39 mohor
 
944 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
945 38 mohor
begin
946 40 mohor
  if(Reset)
947
    ReadTxDataFromMemory <=#Tp 1'b0;
948 38 mohor
  else
949 278 mohor
  if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
950 40 mohor
    ReadTxDataFromMemory <=#Tp 1'b0;
951 39 mohor
  else
952 40 mohor
  if(SetReadTxDataFromMemory)
953
    ReadTxDataFromMemory <=#Tp 1'b1;
954 38 mohor
end
955
 
956 226 tadejm
reg tx_burst_en;
957
reg rx_burst_en;
958 221 mohor
 
959 278 mohor
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
960 226 tadejm
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
961 221 mohor
 
962 39 mohor
wire [31:0] TxData_wb;
963
wire ReadTxDataFromFifo_wb;
964 38 mohor
 
965 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
966 38 mohor
begin
967 40 mohor
  if(Reset)
968
    BlockReadTxDataFromMemory <=#Tp 1'b0;
969 38 mohor
  else
970 278 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
971 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
972 219 mohor
  else
973 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
974 219 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b0;
975 39 mohor
end
976
 
977
 
978
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
979 219 mohor
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
980
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
981 226 tadejm
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
982
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
983 159 mohor
 
984 226 tadejm
wire rx_burst;
985
wire enough_data_in_rxfifo_for_burst;
986
wire enough_data_in_rxfifo_for_burst_plus1;
987 229 mohor
 
988 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
989 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
990 39 mohor
begin
991 40 mohor
  if(Reset)
992 38 mohor
    begin
993 39 mohor
      MasterWbTX <=#Tp 1'b0;
994
      MasterWbRX <=#Tp 1'b0;
995
      m_wb_adr_o <=#Tp 32'h0;
996
      m_wb_cyc_o <=#Tp 1'b0;
997
      m_wb_stb_o <=#Tp 1'b0;
998
      m_wb_we_o  <=#Tp 1'b0;
999 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
1000 110 mohor
      cyc_cleared<=#Tp 1'b0;
1001 226 tadejm
      tx_burst_cnt<=#Tp 0;
1002
      rx_burst_cnt<=#Tp 0;
1003 150 mohor
      IncrTxPointer<=#Tp 1'b0;
1004 226 tadejm
      tx_burst_en<=#Tp 1'b1;
1005
      rx_burst_en<=#Tp 1'b0;
1006
      `ifdef ETH_WISHBONE_B3
1007
        m_wb_cti_o <=#Tp 3'b0;
1008
      `endif
1009 38 mohor
    end
1010 39 mohor
  else
1011
    begin
1012
      // Switching between two stages depends on enable signals
1013 229 mohor
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst})  // synopsys parallel_case
1014 226 tadejm
        8'b00_10_00_10,             // Idle and MRB needed
1015 229 mohor
        8'b10_1x_10_1x,             // MRB continues
1016 226 tadejm
        8'b10_10_01_10,             // Clear (previously MR) and MRB needed
1017 229 mohor
        8'b01_1x_01_1x :            // Clear (previously MW) and MRB needed
1018 39 mohor
          begin
1019 226 tadejm
            MasterWbTX <=#Tp 1'b1;  // tx burst
1020
            MasterWbRX <=#Tp 1'b0;
1021
            m_wb_cyc_o <=#Tp 1'b1;
1022
            m_wb_stb_o <=#Tp 1'b1;
1023
            m_wb_we_o  <=#Tp 1'b0;
1024
            m_wb_sel_o <=#Tp 4'hf;
1025
            cyc_cleared<=#Tp 1'b0;
1026
            IncrTxPointer<=#Tp 1'b1;
1027
            tx_burst_cnt <=#Tp tx_burst_cnt+1;
1028
            if(tx_burst_cnt==0)
1029
              m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1030
            else
1031
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1032
 
1033
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1034
              begin
1035
                tx_burst_en<=#Tp 1'b0;
1036
              `ifdef ETH_WISHBONE_B3
1037
                m_wb_cti_o <=#Tp 3'b111;
1038
              `endif
1039
              end
1040
            else
1041
              begin
1042
              `ifdef ETH_WISHBONE_B3
1043
                m_wb_cti_o <=#Tp 3'b010;
1044
              `endif
1045
              end
1046
          end
1047 229 mohor
        8'b00_x1_00_x1,             // Idle and MWB needed
1048
        8'b01_x1_10_x1,             // MWB continues
1049 226 tadejm
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1050 229 mohor
        8'b10_x1_01_x1 :            // Clear (previously MR) and MWB needed
1051 226 tadejm
          begin
1052
            MasterWbTX <=#Tp 1'b0;  // rx burst
1053 39 mohor
            MasterWbRX <=#Tp 1'b1;
1054 226 tadejm
            m_wb_cyc_o <=#Tp 1'b1;
1055
            m_wb_stb_o <=#Tp 1'b1;
1056
            m_wb_we_o  <=#Tp 1'b1;
1057
            m_wb_sel_o <=#Tp RxByteSel;
1058
            IncrTxPointer<=#Tp 1'b0;
1059
            cyc_cleared<=#Tp 1'b0;
1060
            rx_burst_cnt <=#Tp rx_burst_cnt+1;
1061
 
1062
            if(rx_burst_cnt==0)
1063
              m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1064
            else
1065
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1066
 
1067
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1068
              begin
1069
                rx_burst_en<=#Tp 1'b0;
1070
              `ifdef ETH_WISHBONE_B3
1071
                m_wb_cti_o <=#Tp 3'b111;
1072
              `endif
1073
              end
1074
            else
1075
              begin
1076
              `ifdef ETH_WISHBONE_B3
1077
                m_wb_cti_o <=#Tp 3'b010;
1078
              `endif
1079
              end
1080
          end
1081 229 mohor
        8'b00_x1_00_x0 :            // idle and MW is needed (data write to rx buffer)
1082 226 tadejm
          begin
1083
            MasterWbTX <=#Tp 1'b0;
1084
            MasterWbRX <=#Tp 1'b1;
1085 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1086 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1087
            m_wb_stb_o <=#Tp 1'b1;
1088
            m_wb_we_o  <=#Tp 1'b1;
1089 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1090 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1091 39 mohor
          end
1092 226 tadejm
        8'b00_10_00_00 :            // idle and MR is needed (data read from tx buffer)
1093 39 mohor
          begin
1094 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1095 39 mohor
            MasterWbRX <=#Tp 1'b0;
1096 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1097 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1098
            m_wb_stb_o <=#Tp 1'b1;
1099
            m_wb_we_o  <=#Tp 1'b0;
1100 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1101
            IncrTxPointer<=#Tp 1'b1;
1102 39 mohor
          end
1103 226 tadejm
        8'b10_10_01_00,             // MR and MR is needed (data read from tx buffer)
1104 229 mohor
        8'b01_1x_01_0x  :           // MW and MR is needed (data read from tx buffer)
1105 39 mohor
          begin
1106 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1107 39 mohor
            MasterWbRX <=#Tp 1'b0;
1108 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1109 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1110
            m_wb_stb_o <=#Tp 1'b1;
1111
            m_wb_we_o  <=#Tp 1'b0;
1112 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1113 110 mohor
            cyc_cleared<=#Tp 1'b0;
1114 150 mohor
            IncrTxPointer<=#Tp 1'b1;
1115 39 mohor
          end
1116 226 tadejm
        8'b01_01_01_00,             // MW and MW needed (data write to rx buffer)
1117 229 mohor
        8'b10_x1_01_x0  :           // MR and MW is needed (data write to rx buffer)
1118 39 mohor
          begin
1119 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1120 39 mohor
            MasterWbRX <=#Tp 1'b1;
1121 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1122 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1123
            m_wb_stb_o <=#Tp 1'b1;
1124 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
1125 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1126 110 mohor
            cyc_cleared<=#Tp 1'b0;
1127 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1128 39 mohor
          end
1129 226 tadejm
        8'b01_01_10_00,             // MW and MW needed (cycle is cleared between previous and next access)
1130 229 mohor
        8'b01_1x_10_x0,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1131 226 tadejm
        8'b10_10_10_00,             // MR and MR needed (cycle is cleared between previous and next access)
1132 229 mohor
        8'b10_x1_10_0x :            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1133 39 mohor
          begin
1134 110 mohor
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
1135
            m_wb_stb_o <=#Tp 1'b0;
1136
            cyc_cleared<=#Tp 1'b1;
1137 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1138 226 tadejm
            tx_burst_cnt<=#Tp 0;
1139
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1140
            rx_burst_cnt<=#Tp 0;
1141
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1142
            `ifdef ETH_WISHBONE_B3
1143
              m_wb_cti_o <=#Tp 3'b0;
1144
            `endif
1145 110 mohor
          end
1146 229 mohor
        8'bxx_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1147
        8'bxx_00_01_00 :            // Between cyc_cleared request was cleared
1148 110 mohor
          begin
1149 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1150 39 mohor
            MasterWbRX <=#Tp 1'b0;
1151
            m_wb_cyc_o <=#Tp 1'b0;
1152
            m_wb_stb_o <=#Tp 1'b0;
1153 226 tadejm
            cyc_cleared<=#Tp 1'b0;
1154 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1155 226 tadejm
            rx_burst_cnt<=#Tp 0;
1156
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1157
            `ifdef ETH_WISHBONE_B3
1158
              m_wb_cti_o <=#Tp 3'b0;
1159
            `endif
1160 39 mohor
          end
1161 226 tadejm
        8'b00_00_00_00:             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1162 127 mohor
          begin
1163 226 tadejm
            tx_burst_cnt<=#Tp 0;
1164
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1165 127 mohor
          end
1166 226 tadejm
        default:                    // Don't touch
1167 82 mohor
          begin
1168
            MasterWbTX <=#Tp MasterWbTX;
1169
            MasterWbRX <=#Tp MasterWbRX;
1170
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
1171
            m_wb_stb_o <=#Tp m_wb_stb_o;
1172 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
1173 150 mohor
            IncrTxPointer<=#Tp IncrTxPointer;
1174 82 mohor
          end
1175 39 mohor
      endcase
1176
    end
1177 38 mohor
end
1178
 
1179 110 mohor
 
1180 39 mohor
wire TxFifoClear;
1181 96 mohor
 
1182 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1183 38 mohor
 
1184 219 mohor
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
1185 150 mohor
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
1186 96 mohor
          .clk(WB_CLK_I),                                   .reset(Reset),
1187 226 tadejm
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1188 96 mohor
          .clear(TxFifoClear),                              .full(TxBufferFull),
1189
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
1190 150 mohor
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
1191 96 mohor
        );
1192 39 mohor
 
1193
 
1194
reg StartOccured;
1195
reg TxStartFrm_sync1;
1196
reg TxStartFrm_sync2;
1197
reg TxStartFrm_syncb1;
1198
reg TxStartFrm_syncb2;
1199
 
1200
 
1201
 
1202
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1203 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1204 38 mohor
begin
1205 40 mohor
  if(Reset)
1206 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
1207 38 mohor
  else
1208 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1209
    TxStartFrm_wb <=#Tp 1'b1;
1210 38 mohor
  else
1211 39 mohor
  if(TxStartFrm_syncb2)
1212
    TxStartFrm_wb <=#Tp 1'b0;
1213 38 mohor
end
1214
 
1215 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1216 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1217 38 mohor
begin
1218 40 mohor
  if(Reset)
1219 39 mohor
    StartOccured <=#Tp 1'b0;
1220 38 mohor
  else
1221 39 mohor
  if(TxStartFrm_wb)
1222
    StartOccured <=#Tp 1'b1;
1223 38 mohor
  else
1224 39 mohor
  if(ResetTxBDReady)
1225
    StartOccured <=#Tp 1'b0;
1226 38 mohor
end
1227
 
1228 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1229 40 mohor
always @ (posedge MTxClk or posedge Reset)
1230 39 mohor
begin
1231 40 mohor
  if(Reset)
1232 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1233
  else
1234
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1235
end
1236 38 mohor
 
1237 40 mohor
always @ (posedge MTxClk or posedge Reset)
1238 39 mohor
begin
1239 40 mohor
  if(Reset)
1240 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1241
  else
1242
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1243
end
1244
 
1245 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1246 38 mohor
begin
1247 40 mohor
  if(Reset)
1248 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1249 38 mohor
  else
1250 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1251 38 mohor
end
1252
 
1253 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1254 38 mohor
begin
1255 40 mohor
  if(Reset)
1256 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1257 38 mohor
  else
1258 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1259
end
1260
 
1261 40 mohor
always @ (posedge MTxClk or posedge Reset)
1262 39 mohor
begin
1263 40 mohor
  if(Reset)
1264 39 mohor
    TxStartFrm <=#Tp 1'b0;
1265 38 mohor
  else
1266 39 mohor
  if(TxStartFrm_sync2)
1267 61 mohor
    TxStartFrm <=#Tp 1'b1;
1268 39 mohor
  else
1269 278 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
1270 39 mohor
    TxStartFrm <=#Tp 1'b0;
1271 38 mohor
end
1272 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1273 38 mohor
 
1274
 
1275 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1276 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1277 38 mohor
begin
1278 40 mohor
  if(Reset)
1279 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1280 38 mohor
  else
1281 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1282 39 mohor
    TxEndFrm_wb <=#Tp 1'b1;
1283 38 mohor
  else
1284 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1285
    TxEndFrm_wb <=#Tp 1'b0;
1286 38 mohor
end
1287
 
1288
 
1289
// Marks which bytes are valid within the word.
1290 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1291 38 mohor
 
1292 39 mohor
reg LatchValidBytes;
1293
reg LatchValidBytes_q;
1294 38 mohor
 
1295 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1296 38 mohor
begin
1297 40 mohor
  if(Reset)
1298 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1299 38 mohor
  else
1300 39 mohor
  if(TxLengthLt4 & TxBDReady)
1301
    LatchValidBytes <=#Tp 1'b1;
1302 38 mohor
  else
1303 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1304 38 mohor
end
1305
 
1306 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1307 38 mohor
begin
1308 40 mohor
  if(Reset)
1309 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1310 38 mohor
  else
1311 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1312 38 mohor
end
1313
 
1314
 
1315 39 mohor
// Latching valid bytes
1316 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1317 38 mohor
begin
1318 40 mohor
  if(Reset)
1319 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1320 38 mohor
  else
1321 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1322
    TxValidBytesLatched <=#Tp TxValidBytes;
1323
  else
1324
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1325
    TxValidBytesLatched <=#Tp 2'h0;
1326 38 mohor
end
1327
 
1328
 
1329
assign TxIRQEn          = TxStatus[14];
1330 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1331
assign PerPacketPad     = TxStatus[12];
1332
assign PerPacketCrcEn   = TxStatus[11];
1333 38 mohor
 
1334
 
1335 77 mohor
assign RxIRQEn         = RxStatus[14];
1336 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1337 38 mohor
 
1338
 
1339
// Temporary Tx and Rx buffer descriptor address 
1340 39 mohor
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
1341 134 mohor
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1)     | // Using first Rx BD
1342 39 mohor
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
1343 38 mohor
 
1344
 
1345
// Latching Tx buffer descriptor address
1346 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1347 38 mohor
begin
1348 40 mohor
  if(Reset)
1349 38 mohor
    TxBDAddress <=#Tp 8'h0;
1350 321 igorm
  else if (r_TxEn & (~r_TxEn_q))
1351
    TxBDAddress <=#Tp 8'h0;
1352
  else if (TxStatusWrite)
1353 38 mohor
    TxBDAddress <=#Tp TempTxBDAddress;
1354
end
1355
 
1356
 
1357
// Latching Rx buffer descriptor address
1358 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1359 38 mohor
begin
1360 40 mohor
  if(Reset)
1361 321 igorm
    RxBDAddress <=#Tp 8'h0;
1362
  else if(r_RxEn & (~r_RxEn_q))
1363
    RxBDAddress <=#Tp r_TxBDNum << 1;
1364
  else if(RxStatusWrite)
1365 38 mohor
    RxBDAddress <=#Tp TempRxBDAddress;
1366
end
1367
 
1368 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1369 38 mohor
 
1370 261 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
1371 60 mohor
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1372 38 mohor
 
1373 60 mohor
 
1374 38 mohor
// Signals used for various purposes
1375 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1376 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1377
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1378
 
1379
 
1380
 
1381 39 mohor
// Generating delayed signals
1382 40 mohor
always @ (posedge MTxClk or posedge Reset)
1383 38 mohor
begin
1384 40 mohor
  if(Reset)
1385 39 mohor
    begin
1386
      TxAbort_q      <=#Tp 1'b0;
1387
      TxRetry_q      <=#Tp 1'b0;
1388
      TxUsedData_q   <=#Tp 1'b0;
1389
    end
1390 38 mohor
  else
1391 39 mohor
    begin
1392
      TxAbort_q      <=#Tp TxAbort;
1393
      TxRetry_q      <=#Tp TxRetry;
1394
      TxUsedData_q   <=#Tp TxUsedData;
1395
    end
1396 38 mohor
end
1397
 
1398
// Generating delayed signals
1399 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1400 38 mohor
begin
1401 40 mohor
  if(Reset)
1402 38 mohor
    begin
1403 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1404
      TxAbort_wb_q  <=#Tp 1'b0;
1405 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1406 38 mohor
    end
1407
  else
1408
    begin
1409 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1410
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1411 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1412 38 mohor
    end
1413
end
1414
 
1415
 
1416 219 mohor
reg TxAbortPacketBlocked;
1417
always @ (posedge WB_CLK_I or posedge Reset)
1418
begin
1419
  if(Reset)
1420
    TxAbortPacket <=#Tp 1'b0;
1421
  else
1422 278 mohor
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
1423
     TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
1424 219 mohor
    TxAbortPacket <=#Tp 1'b1;
1425
  else
1426
    TxAbortPacket <=#Tp 1'b0;
1427
end
1428
 
1429
 
1430
always @ (posedge WB_CLK_I or posedge Reset)
1431
begin
1432
  if(Reset)
1433 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1434
  else
1435 272 tadejm
  if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
1436
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1437
  else
1438 278 mohor
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
1439
     TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
1440 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b1;
1441
end
1442
 
1443
 
1444
always @ (posedge WB_CLK_I or posedge Reset)
1445
begin
1446
  if(Reset)
1447 219 mohor
    TxAbortPacketBlocked <=#Tp 1'b0;
1448
  else
1449 280 mohor
  if(!TxAbort_wb & TxAbort_wb_q)
1450
    TxAbortPacketBlocked <=#Tp 1'b0;
1451
  else
1452 219 mohor
  if(TxAbortPacket)
1453
    TxAbortPacketBlocked <=#Tp 1'b1;
1454
end
1455
 
1456
 
1457
reg TxRetryPacketBlocked;
1458
always @ (posedge WB_CLK_I or posedge Reset)
1459
begin
1460
  if(Reset)
1461
    TxRetryPacket <=#Tp 1'b0;
1462
  else
1463 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1464
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1465 219 mohor
    TxRetryPacket <=#Tp 1'b1;
1466
  else
1467
    TxRetryPacket <=#Tp 1'b0;
1468
end
1469
 
1470
 
1471
always @ (posedge WB_CLK_I or posedge Reset)
1472
begin
1473
  if(Reset)
1474 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1475
  else
1476 272 tadejm
  if(StartTxBDRead)
1477
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1478
  else
1479 278 mohor
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1480
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1481 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b1;
1482
end
1483
 
1484
 
1485
always @ (posedge WB_CLK_I or posedge Reset)
1486
begin
1487
  if(Reset)
1488 219 mohor
    TxRetryPacketBlocked <=#Tp 1'b0;
1489
  else
1490 280 mohor
  if(!TxRetry_wb & TxRetry_wb_q)
1491
    TxRetryPacketBlocked <=#Tp 1'b0;
1492
  else
1493 219 mohor
  if(TxRetryPacket)
1494
    TxRetryPacketBlocked <=#Tp 1'b1;
1495
end
1496
 
1497
 
1498 221 mohor
reg TxDonePacketBlocked;
1499
always @ (posedge WB_CLK_I or posedge Reset)
1500
begin
1501
  if(Reset)
1502
    TxDonePacket <=#Tp 1'b0;
1503
  else
1504 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
1505
     TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1506 221 mohor
    TxDonePacket <=#Tp 1'b1;
1507
  else
1508
    TxDonePacket <=#Tp 1'b0;
1509
end
1510
 
1511
 
1512
always @ (posedge WB_CLK_I or posedge Reset)
1513
begin
1514
  if(Reset)
1515
    TxDonePacket_NotCleared <=#Tp 1'b0;
1516
  else
1517 272 tadejm
  if(TxEn & TxEn_q & TxDonePacket_NotCleared)
1518
    TxDonePacket_NotCleared <=#Tp 1'b0;
1519
  else
1520 278 mohor
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) |
1521
     TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
1522 221 mohor
    TxDonePacket_NotCleared <=#Tp 1'b1;
1523
end
1524
 
1525
 
1526
always @ (posedge WB_CLK_I or posedge Reset)
1527
begin
1528
  if(Reset)
1529
    TxDonePacketBlocked <=#Tp 1'b0;
1530
  else
1531 280 mohor
  if(!TxDone_wb & TxDone_wb_q)
1532
    TxDonePacketBlocked <=#Tp 1'b0;
1533
  else
1534 221 mohor
  if(TxDonePacket)
1535
    TxDonePacketBlocked <=#Tp 1'b1;
1536
end
1537
 
1538
 
1539 38 mohor
// Indication of the last word
1540 40 mohor
always @ (posedge MTxClk or posedge Reset)
1541 38 mohor
begin
1542 40 mohor
  if(Reset)
1543 38 mohor
    LastWord <=#Tp 1'b0;
1544
  else
1545
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1546
    LastWord <=#Tp 1'b0;
1547
  else
1548
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1549 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1550 38 mohor
end
1551
 
1552
 
1553
// Tx end frame generation
1554 40 mohor
always @ (posedge MTxClk or posedge Reset)
1555 38 mohor
begin
1556 40 mohor
  if(Reset)
1557 38 mohor
    TxEndFrm <=#Tp 1'b0;
1558
  else
1559 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1560 38 mohor
    TxEndFrm <=#Tp 1'b0;
1561
  else
1562
  if(Flop & LastWord)
1563
    begin
1564 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1565 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1566
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1567
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1568
 
1569
        default : TxEndFrm <=#Tp 1'b0;
1570
      endcase
1571
    end
1572
end
1573
 
1574
 
1575
// Tx data selection (latching)
1576 40 mohor
always @ (posedge MTxClk or posedge Reset)
1577 38 mohor
begin
1578 40 mohor
  if(Reset)
1579 96 mohor
    TxData <=#Tp 0;
1580 38 mohor
  else
1581 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1582 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1583 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1584
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1585
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1586
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1587
    endcase
1588 38 mohor
  else
1589 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1590 96 mohor
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1591
  else
1592 38 mohor
  if(TxUsedData & Flop)
1593
    begin
1594 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1595 226 tadejm
 
1596 82 mohor
        1 : TxData <=#Tp TxDataLatched[23:16];
1597
        2 : TxData <=#Tp TxDataLatched[15:8];
1598
        3 : TxData <=#Tp TxDataLatched[7:0];
1599 38 mohor
      endcase
1600
    end
1601
end
1602
 
1603
 
1604
// Latching tx data
1605 40 mohor
always @ (posedge MTxClk or posedge Reset)
1606 38 mohor
begin
1607 40 mohor
  if(Reset)
1608 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1609
  else
1610 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1611 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1612 38 mohor
end
1613
 
1614
 
1615
// Tx under run
1616 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1617 38 mohor
begin
1618 40 mohor
  if(Reset)
1619 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1620 38 mohor
  else
1621 39 mohor
  if(TxAbortPulse)
1622 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1623
  else
1624
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1625
    TxUnderRun_wb <=#Tp 1'b1;
1626
end
1627
 
1628
 
1629 159 mohor
reg TxUnderRun_sync1;
1630
 
1631 60 mohor
// Tx under run
1632
always @ (posedge MTxClk or posedge Reset)
1633
begin
1634
  if(Reset)
1635 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b0;
1636 43 mohor
  else
1637 60 mohor
  if(TxUnderRun_wb)
1638 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b1;
1639 60 mohor
  else
1640 159 mohor
  if(BlockingTxStatusWrite_sync2)
1641
    TxUnderRun_sync1 <=#Tp 1'b0;
1642
end
1643
 
1644
// Tx under run
1645
always @ (posedge MTxClk or posedge Reset)
1646
begin
1647
  if(Reset)
1648 60 mohor
    TxUnderRun <=#Tp 1'b0;
1649 159 mohor
  else
1650
  if(BlockingTxStatusWrite_sync2)
1651
    TxUnderRun <=#Tp 1'b0;
1652
  else
1653
  if(TxUnderRun_sync1)
1654
    TxUnderRun <=#Tp 1'b1;
1655 38 mohor
end
1656
 
1657
 
1658
// Tx Byte counter
1659 40 mohor
always @ (posedge MTxClk or posedge Reset)
1660 38 mohor
begin
1661 40 mohor
  if(Reset)
1662 38 mohor
    TxByteCnt <=#Tp 2'h0;
1663
  else
1664
  if(TxAbort_q | TxRetry_q)
1665
    TxByteCnt <=#Tp 2'h0;
1666
  else
1667
  if(TxStartFrm & ~TxUsedData)
1668 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1669 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1670
      2'h1 : TxByteCnt <=#Tp 2'h2;
1671
      2'h2 : TxByteCnt <=#Tp 2'h3;
1672
      2'h3 : TxByteCnt <=#Tp 2'h0;
1673
    endcase
1674 38 mohor
  else
1675
  if(TxUsedData & Flop)
1676 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1677 38 mohor
end
1678
 
1679 39 mohor
 
1680 150 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1681
reg ReadTxDataFromFifo_sync1;
1682
reg ReadTxDataFromFifo_sync2;
1683
reg ReadTxDataFromFifo_sync3;
1684
reg ReadTxDataFromFifo_syncb1;
1685
reg ReadTxDataFromFifo_syncb2;
1686
reg ReadTxDataFromFifo_syncb3;
1687
 
1688
 
1689
always @ (posedge MTxClk or posedge Reset)
1690
begin
1691
  if(Reset)
1692
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1693
  else
1694 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1695 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1696 150 mohor
  else
1697
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1698
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1699 38 mohor
end
1700
 
1701 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1702 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1703 38 mohor
begin
1704 40 mohor
  if(Reset)
1705 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1706 38 mohor
  else
1707 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1708
end
1709 38 mohor
 
1710 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1711 38 mohor
begin
1712 40 mohor
  if(Reset)
1713 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1714 38 mohor
  else
1715 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1716 38 mohor
end
1717
 
1718 40 mohor
always @ (posedge MTxClk or posedge Reset)
1719 38 mohor
begin
1720 40 mohor
  if(Reset)
1721 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1722 38 mohor
  else
1723 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1724 38 mohor
end
1725
 
1726 40 mohor
always @ (posedge MTxClk or posedge Reset)
1727 38 mohor
begin
1728 40 mohor
  if(Reset)
1729 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1730 38 mohor
  else
1731 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1732 38 mohor
end
1733
 
1734 150 mohor
always @ (posedge MTxClk or posedge Reset)
1735
begin
1736
  if(Reset)
1737
    ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
1738
  else
1739
    ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
1740
end
1741
 
1742 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1743 38 mohor
begin
1744 40 mohor
  if(Reset)
1745 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1746 38 mohor
  else
1747 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1748 38 mohor
end
1749
 
1750 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1751
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1752 38 mohor
 
1753
 
1754 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1755 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1756 38 mohor
begin
1757 40 mohor
  if(Reset)
1758 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1759 38 mohor
  else
1760 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1761 38 mohor
end
1762
 
1763 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1764 38 mohor
begin
1765 40 mohor
  if(Reset)
1766 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1767 38 mohor
  else
1768 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1769 38 mohor
end
1770
 
1771
 
1772 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1773 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1774 38 mohor
begin
1775 40 mohor
  if(Reset)
1776 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1777 38 mohor
  else
1778 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1779 38 mohor
end
1780
 
1781 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1782 38 mohor
begin
1783 40 mohor
  if(Reset)
1784 39 mohor
    TxDone_wb <=#Tp 1'b0;
1785 38 mohor
  else
1786 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1787 38 mohor
end
1788
 
1789 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1790 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1791 38 mohor
begin
1792 40 mohor
  if(Reset)
1793 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1794 38 mohor
  else
1795 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1796 38 mohor
end
1797
 
1798 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1799 38 mohor
begin
1800 40 mohor
  if(Reset)
1801 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1802
  else
1803 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1804 38 mohor
end
1805
 
1806
 
1807 150 mohor
reg RxAbortSync1;
1808
reg RxAbortSync2;
1809
reg RxAbortSync3;
1810
reg RxAbortSync4;
1811
reg RxAbortSyncb1;
1812
reg RxAbortSyncb2;
1813 39 mohor
 
1814 150 mohor
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
1815
 
1816 40 mohor
// Reading the Rx buffer descriptor
1817
always @ (posedge WB_CLK_I or posedge Reset)
1818
begin
1819
  if(Reset)
1820
    RxBDRead <=#Tp 1'b1;
1821
  else
1822 166 mohor
  if(StartRxBDRead & ~RxReady)
1823 40 mohor
    RxBDRead <=#Tp 1'b1;
1824
  else
1825
  if(RxBDReady)
1826
    RxBDRead <=#Tp 1'b0;
1827
end
1828 39 mohor
 
1829
 
1830 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1831
// written to the previous one.
1832
 
1833
// Latching READY status of the Rx buffer descriptor
1834 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1835 38 mohor
begin
1836 40 mohor
  if(Reset)
1837 38 mohor
    RxBDReady <=#Tp 1'b0;
1838
  else
1839 166 mohor
  if(RxPointerRead)
1840 150 mohor
    RxBDReady <=#Tp 1'b0;
1841
  else
1842 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1843
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1844 38 mohor
end
1845
 
1846 40 mohor
// Latching Rx buffer descriptor status
1847
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1848
always @ (posedge WB_CLK_I or posedge Reset)
1849 38 mohor
begin
1850 40 mohor
  if(Reset)
1851 60 mohor
    RxStatus <=#Tp 2'h0;
1852 38 mohor
  else
1853 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1854 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1855 38 mohor
end
1856
 
1857
 
1858 166 mohor
// RxReady generation
1859
always @ (posedge WB_CLK_I or posedge Reset)
1860
begin
1861
  if(Reset)
1862
    RxReady <=#Tp 1'b0;
1863
  else
1864
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
1865
    RxReady <=#Tp 1'b0;
1866
  else
1867
  if(RxEn & RxEn_q & RxPointerRead)
1868
    RxReady <=#Tp 1'b1;
1869
end
1870 38 mohor
 
1871
 
1872 40 mohor
// Reading Rx BD pointer
1873
 
1874
 
1875
assign StartRxPointerRead = RxBDRead & RxBDReady;
1876
 
1877
// Reading Tx BD Pointer
1878
always @ (posedge WB_CLK_I or posedge Reset)
1879 38 mohor
begin
1880 40 mohor
  if(Reset)
1881
    RxPointerRead <=#Tp 1'b0;
1882 38 mohor
  else
1883 40 mohor
  if(StartRxPointerRead)
1884
    RxPointerRead <=#Tp 1'b1;
1885 38 mohor
  else
1886 166 mohor
  if(RxEn & RxEn_q)
1887 40 mohor
    RxPointerRead <=#Tp 1'b0;
1888 38 mohor
end
1889
 
1890 113 mohor
 
1891 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1892
always @ (posedge WB_CLK_I or posedge Reset)
1893
begin
1894
  if(Reset)
1895 159 mohor
    RxPointerMSB <=#Tp 30'h0;
1896 40 mohor
  else
1897
  if(RxEn & RxEn_q & RxPointerRead)
1898 159 mohor
    RxPointerMSB <=#Tp ram_do[31:2];
1899 40 mohor
  else
1900 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1901 159 mohor
      RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1902 40 mohor
end
1903 38 mohor
 
1904
 
1905 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1906 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1907
begin
1908
  if(Reset)
1909 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp 0;
1910 96 mohor
  else
1911 159 mohor
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
1912
    RxPointerLSB_rst[1:0] <=#Tp 0;
1913 96 mohor
  else
1914
  if(RxEn & RxEn_q & RxPointerRead)
1915 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
1916 96 mohor
end
1917
 
1918
 
1919 159 mohor
always @ (RxPointerLSB_rst)
1920 96 mohor
begin
1921 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1922
    2'h0 : RxByteSel[3:0] = 4'hf;
1923
    2'h1 : RxByteSel[3:0] = 4'h7;
1924
    2'h2 : RxByteSel[3:0] = 4'h3;
1925
    2'h3 : RxByteSel[3:0] = 4'h1;
1926 96 mohor
  endcase
1927
end
1928
 
1929
 
1930
always @ (posedge WB_CLK_I or posedge Reset)
1931
begin
1932
  if(Reset)
1933 40 mohor
    RxEn_needed <=#Tp 1'b0;
1934 38 mohor
  else
1935 166 mohor
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1936 40 mohor
    RxEn_needed <=#Tp 1'b1;
1937 38 mohor
  else
1938 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1939
    RxEn_needed <=#Tp 1'b0;
1940 38 mohor
end
1941
 
1942
 
1943 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1944
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1945 38 mohor
 
1946 40 mohor
reg RxEnableWindow;
1947 38 mohor
 
1948
// Indicating that last byte is being reveived
1949 40 mohor
always @ (posedge MRxClk or posedge Reset)
1950 38 mohor
begin
1951 40 mohor
  if(Reset)
1952 38 mohor
    LastByteIn <=#Tp 1'b0;
1953
  else
1954 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1955 38 mohor
    LastByteIn <=#Tp 1'b0;
1956
  else
1957 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1958 38 mohor
    LastByteIn <=#Tp 1'b1;
1959
end
1960
 
1961 159 mohor
reg ShiftEnded_rck;
1962 40 mohor
reg ShiftEndedSync1;
1963
reg ShiftEndedSync2;
1964 118 mohor
reg ShiftEndedSync3;
1965
reg ShiftEndedSync_c1;
1966
reg ShiftEndedSync_c2;
1967
 
1968 40 mohor
wire StartShiftWillEnd;
1969 96 mohor
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1970 38 mohor
 
1971
// Indicating that data reception will end
1972 40 mohor
always @ (posedge MRxClk or posedge Reset)
1973 38 mohor
begin
1974 40 mohor
  if(Reset)
1975 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1976
  else
1977 159 mohor
  if(ShiftEnded_rck | RxAbort)
1978 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1979
  else
1980 40 mohor
  if(StartShiftWillEnd)
1981 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
1982
end
1983
 
1984
 
1985 40 mohor
 
1986 38 mohor
// Receive byte counter
1987 40 mohor
always @ (posedge MRxClk or posedge Reset)
1988 38 mohor
begin
1989 40 mohor
  if(Reset)
1990 38 mohor
    RxByteCnt <=#Tp 2'h0;
1991
  else
1992 159 mohor
  if(ShiftEnded_rck | RxAbort)
1993 38 mohor
    RxByteCnt <=#Tp 2'h0;
1994 97 lampret
  else
1995 166 mohor
  if(RxValid & RxStartFrm & RxReady)
1996 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
1997 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
1998
      2'h1 : RxByteCnt <=#Tp 2'h2;
1999
      2'h2 : RxByteCnt <=#Tp 2'h3;
2000
      2'h3 : RxByteCnt <=#Tp 2'h0;
2001
    endcase
2002 38 mohor
  else
2003 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
2004 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
2005 38 mohor
end
2006
 
2007
 
2008
// Indicates how many bytes are valid within the last word
2009 40 mohor
always @ (posedge MRxClk or posedge Reset)
2010 38 mohor
begin
2011 40 mohor
  if(Reset)
2012 38 mohor
    RxValidBytes <=#Tp 2'h1;
2013
  else
2014 96 mohor
  if(RxValid & RxStartFrm)
2015 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2016 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
2017
      2'h1 : RxValidBytes <=#Tp 2'h2;
2018
      2'h2 : RxValidBytes <=#Tp 2'h3;
2019
      2'h3 : RxValidBytes <=#Tp 2'h0;
2020
    endcase
2021 38 mohor
  else
2022 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2023 38 mohor
    RxValidBytes <=#Tp RxValidBytes + 1;
2024
end
2025
 
2026
 
2027 40 mohor
always @ (posedge MRxClk or posedge Reset)
2028 38 mohor
begin
2029 40 mohor
  if(Reset)
2030
    RxDataLatched1       <=#Tp 24'h0;
2031 38 mohor
  else
2032 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2033 96 mohor
    if(RxStartFrm)
2034 40 mohor
    begin
2035 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2036 96 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2037
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2038
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2039
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2040
      endcase
2041
    end
2042
    else if (RxEnableWindow)
2043
    begin
2044 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2045 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2046
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2047
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2048 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2049
      endcase
2050
    end
2051 38 mohor
end
2052
 
2053 40 mohor
wire SetWriteRxDataToFifo;
2054 38 mohor
 
2055 40 mohor
// Assembling data that will be written to the rx_fifo
2056
always @ (posedge MRxClk or posedge Reset)
2057 38 mohor
begin
2058 40 mohor
  if(Reset)
2059
    RxDataLatched2 <=#Tp 32'h0;
2060 38 mohor
  else
2061 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2062 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
2063 38 mohor
  else
2064 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2065 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2066 82 mohor
 
2067
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2068
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
2069
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
2070 40 mohor
    endcase
2071 38 mohor
end
2072
 
2073
 
2074 40 mohor
reg WriteRxDataToFifoSync1;
2075
reg WriteRxDataToFifoSync2;
2076 150 mohor
reg WriteRxDataToFifoSync3;
2077 38 mohor
 
2078
 
2079 40 mohor
// Indicating start of the reception process
2080 166 mohor
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
2081
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
2082
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
2083 38 mohor
 
2084 150 mohor
always @ (posedge MRxClk or posedge Reset)
2085
begin
2086
  if(Reset)
2087
    WriteRxDataToFifo <=#Tp 1'b0;
2088
  else
2089
  if(SetWriteRxDataToFifo & ~RxAbort)
2090
    WriteRxDataToFifo <=#Tp 1'b1;
2091
  else
2092
  if(WriteRxDataToFifoSync2 | RxAbort)
2093
    WriteRxDataToFifo <=#Tp 1'b0;
2094
end
2095 40 mohor
 
2096 150 mohor
 
2097
 
2098
always @ (posedge WB_CLK_I or posedge Reset)
2099
begin
2100
  if(Reset)
2101
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2102
  else
2103
  if(WriteRxDataToFifo)
2104
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
2105
  else
2106
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2107
end
2108
 
2109
always @ (posedge WB_CLK_I or posedge Reset)
2110
begin
2111
  if(Reset)
2112
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
2113
  else
2114
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
2115
end
2116
 
2117
always @ (posedge WB_CLK_I or posedge Reset)
2118
begin
2119
  if(Reset)
2120
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
2121
  else
2122
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
2123
end
2124
 
2125
wire WriteRxDataToFifo_wb;
2126
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
2127
 
2128
 
2129 90 mohor
reg LatchedRxStartFrm;
2130
reg SyncRxStartFrm;
2131
reg SyncRxStartFrm_q;
2132 150 mohor
reg SyncRxStartFrm_q2;
2133 90 mohor
wire RxFifoReset;
2134 40 mohor
 
2135 90 mohor
always @ (posedge MRxClk or posedge Reset)
2136
begin
2137
  if(Reset)
2138
    LatchedRxStartFrm <=#Tp 0;
2139
  else
2140 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2141 90 mohor
    LatchedRxStartFrm <=#Tp 1;
2142
  else
2143 150 mohor
  if(SyncRxStartFrm_q)
2144 90 mohor
    LatchedRxStartFrm <=#Tp 0;
2145
end
2146
 
2147
 
2148
always @ (posedge WB_CLK_I or posedge Reset)
2149
begin
2150
  if(Reset)
2151
    SyncRxStartFrm <=#Tp 0;
2152
  else
2153
  if(LatchedRxStartFrm)
2154
    SyncRxStartFrm <=#Tp 1;
2155
  else
2156
    SyncRxStartFrm <=#Tp 0;
2157
end
2158
 
2159
 
2160
always @ (posedge WB_CLK_I or posedge Reset)
2161
begin
2162
  if(Reset)
2163
    SyncRxStartFrm_q <=#Tp 0;
2164
  else
2165
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
2166
end
2167
 
2168 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2169
begin
2170
  if(Reset)
2171
    SyncRxStartFrm_q2 <=#Tp 0;
2172
  else
2173
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
2174
end
2175 90 mohor
 
2176
 
2177 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2178 90 mohor
 
2179 150 mohor
 
2180 219 mohor
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
2181 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
2182
         .clk(WB_CLK_I),                                .reset(Reset),
2183 219 mohor
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
2184 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
2185 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
2186 150 mohor
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
2187 88 mohor
        );
2188 40 mohor
 
2189 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2190
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2191 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2192 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2193 40 mohor
 
2194
 
2195
// Generation of the end-of-frame signal
2196
always @ (posedge MRxClk or posedge Reset)
2197 38 mohor
begin
2198 40 mohor
  if(Reset)
2199 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2200 38 mohor
  else
2201 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2202 159 mohor
    ShiftEnded_rck <=#Tp 1'b1;
2203 38 mohor
  else
2204 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2205 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2206 38 mohor
end
2207
 
2208 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2209
begin
2210
  if(Reset)
2211
    ShiftEndedSync1 <=#Tp 1'b0;
2212
  else
2213 159 mohor
    ShiftEndedSync1 <=#Tp ShiftEnded_rck;
2214 40 mohor
end
2215 38 mohor
 
2216 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2217 38 mohor
begin
2218 40 mohor
  if(Reset)
2219
    ShiftEndedSync2 <=#Tp 1'b0;
2220 38 mohor
  else
2221 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
2222 40 mohor
end
2223 38 mohor
 
2224 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2225
begin
2226
  if(Reset)
2227
    ShiftEndedSync3 <=#Tp 1'b0;
2228
  else
2229
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2230
    ShiftEndedSync3 <=#Tp 1'b1;
2231
  else
2232
  if(ShiftEnded)
2233
    ShiftEndedSync3 <=#Tp 1'b0;
2234
end
2235 38 mohor
 
2236 40 mohor
// Generation of the end-of-frame signal
2237
always @ (posedge WB_CLK_I or posedge Reset)
2238 38 mohor
begin
2239 40 mohor
  if(Reset)
2240
    ShiftEnded <=#Tp 1'b0;
2241 38 mohor
  else
2242 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2243 40 mohor
    ShiftEnded <=#Tp 1'b1;
2244 38 mohor
  else
2245 40 mohor
  if(RxStatusWrite)
2246
    ShiftEnded <=#Tp 1'b0;
2247 38 mohor
end
2248
 
2249 118 mohor
always @ (posedge MRxClk or posedge Reset)
2250
begin
2251
  if(Reset)
2252
    ShiftEndedSync_c1 <=#Tp 1'b0;
2253
  else
2254
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
2255
end
2256 38 mohor
 
2257 118 mohor
always @ (posedge MRxClk or posedge Reset)
2258
begin
2259
  if(Reset)
2260
    ShiftEndedSync_c2 <=#Tp 1'b0;
2261
  else
2262
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
2263
end
2264
 
2265 40 mohor
// Generation of the end-of-frame signal
2266
always @ (posedge MRxClk or posedge Reset)
2267 38 mohor
begin
2268 40 mohor
  if(Reset)
2269
    RxEnableWindow <=#Tp 1'b0;
2270 38 mohor
  else
2271 40 mohor
  if(RxStartFrm)
2272
    RxEnableWindow <=#Tp 1'b1;
2273 38 mohor
  else
2274 40 mohor
  if(RxEndFrm | RxAbort)
2275
    RxEnableWindow <=#Tp 1'b0;
2276 38 mohor
end
2277
 
2278
 
2279 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2280 38 mohor
begin
2281 40 mohor
  if(Reset)
2282
    RxAbortSync1 <=#Tp 1'b0;
2283 38 mohor
  else
2284 150 mohor
    RxAbortSync1 <=#Tp RxAbortLatched;
2285 40 mohor
end
2286
 
2287
always @ (posedge WB_CLK_I or posedge Reset)
2288
begin
2289
  if(Reset)
2290
    RxAbortSync2 <=#Tp 1'b0;
2291 38 mohor
  else
2292 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
2293 38 mohor
end
2294
 
2295 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2296
begin
2297
  if(Reset)
2298
    RxAbortSync3 <=#Tp 1'b0;
2299
  else
2300
    RxAbortSync3 <=#Tp RxAbortSync2;
2301
end
2302
 
2303
always @ (posedge WB_CLK_I or posedge Reset)
2304
begin
2305
  if(Reset)
2306
    RxAbortSync4 <=#Tp 1'b0;
2307
  else
2308
    RxAbortSync4 <=#Tp RxAbortSync3;
2309
end
2310
 
2311 40 mohor
always @ (posedge MRxClk or posedge Reset)
2312
begin
2313
  if(Reset)
2314
    RxAbortSyncb1 <=#Tp 1'b0;
2315
  else
2316
    RxAbortSyncb1 <=#Tp RxAbortSync2;
2317
end
2318 38 mohor
 
2319 40 mohor
always @ (posedge MRxClk or posedge Reset)
2320 38 mohor
begin
2321 40 mohor
  if(Reset)
2322
    RxAbortSyncb2 <=#Tp 1'b0;
2323 38 mohor
  else
2324 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
2325 38 mohor
end
2326
 
2327
 
2328 64 mohor
always @ (posedge MRxClk or posedge Reset)
2329
begin
2330
  if(Reset)
2331
    RxAbortLatched <=#Tp 1'b0;
2332
  else
2333 150 mohor
  if(RxAbortSyncb2)
2334
    RxAbortLatched <=#Tp 1'b0;
2335
  else
2336 64 mohor
  if(RxAbort)
2337
    RxAbortLatched <=#Tp 1'b1;
2338
end
2339 40 mohor
 
2340 64 mohor
 
2341 42 mohor
always @ (posedge MRxClk or posedge Reset)
2342
begin
2343
  if(Reset)
2344
    LatchedRxLength[15:0] <=#Tp 16'h0;
2345
  else
2346 150 mohor
  if(LoadRxStatus)
2347 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
2348
end
2349
 
2350
 
2351 261 mohor
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2352 42 mohor
 
2353
always @ (posedge MRxClk or posedge Reset)
2354
begin
2355
  if(Reset)
2356
    RxStatusInLatched <=#Tp 'h0;
2357
  else
2358 150 mohor
  if(LoadRxStatus)
2359 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
2360
end
2361
 
2362
 
2363 60 mohor
// Rx overrun
2364
always @ (posedge WB_CLK_I or posedge Reset)
2365
begin
2366
  if(Reset)
2367
    RxOverrun <=#Tp 1'b0;
2368
  else
2369
  if(RxStatusWrite)
2370
    RxOverrun <=#Tp 1'b0;
2371
  else
2372
  if(RxBufferFull & WriteRxDataToFifo_wb)
2373
    RxOverrun <=#Tp 1'b1;
2374
end
2375 48 mohor
 
2376 77 mohor
 
2377
 
2378
wire TxError;
2379
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2380
 
2381
wire RxError;
2382
 
2383 239 tadejm
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
2384 250 mohor
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
2385
// AddressMiss is identifying that a frame was received because of the promiscous
2386
// mode and is not an error
2387 239 tadejm
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
2388
 
2389 272 tadejm
 
2390
 
2391
reg RxStatusWriteLatched;
2392
reg RxStatusWriteLatched_sync1;
2393
reg RxStatusWriteLatched_sync2;
2394
reg RxStatusWriteLatched_syncb1;
2395
reg RxStatusWriteLatched_syncb2;
2396
 
2397
 
2398
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
2399
always @ (posedge WB_CLK_I or posedge Reset)
2400
begin
2401
  if(Reset)
2402
    RxStatusWriteLatched <=#Tp 1'b0;
2403
  else
2404
  if(RxStatusWriteLatched_syncb2)
2405
    RxStatusWriteLatched <=#Tp 1'b0;
2406
  else
2407
  if(RxStatusWrite)
2408
    RxStatusWriteLatched <=#Tp 1'b1;
2409
end
2410
 
2411
 
2412
always @ (posedge MRxClk or posedge Reset)
2413
begin
2414
  if(Reset)
2415
    begin
2416
      RxStatusWriteLatched_sync1 <=#Tp 1'b0;
2417
      RxStatusWriteLatched_sync2 <=#Tp 1'b0;
2418
    end
2419
  else
2420
    begin
2421
      RxStatusWriteLatched_sync1 <=#Tp RxStatusWriteLatched;
2422
      RxStatusWriteLatched_sync2 <=#Tp RxStatusWriteLatched_sync1;
2423
    end
2424
end
2425
 
2426
 
2427
always @ (posedge WB_CLK_I or posedge Reset)
2428
begin
2429
  if(Reset)
2430
    begin
2431
      RxStatusWriteLatched_syncb1 <=#Tp 1'b0;
2432
      RxStatusWriteLatched_syncb2 <=#Tp 1'b0;
2433
    end
2434
  else
2435
    begin
2436
      RxStatusWriteLatched_syncb1 <=#Tp RxStatusWriteLatched_sync2;
2437
      RxStatusWriteLatched_syncb2 <=#Tp RxStatusWriteLatched_syncb1;
2438
    end
2439
end
2440
 
2441
 
2442
 
2443 77 mohor
// Tx Done Interrupt
2444
always @ (posedge WB_CLK_I or posedge Reset)
2445
begin
2446
  if(Reset)
2447
    TxB_IRQ <=#Tp 1'b0;
2448
  else
2449
  if(TxStatusWrite & TxIRQEn)
2450
    TxB_IRQ <=#Tp ~TxError;
2451
  else
2452
    TxB_IRQ <=#Tp 1'b0;
2453
end
2454
 
2455
 
2456
// Tx Error Interrupt
2457
always @ (posedge WB_CLK_I or posedge Reset)
2458
begin
2459
  if(Reset)
2460
    TxE_IRQ <=#Tp 1'b0;
2461
  else
2462
  if(TxStatusWrite & TxIRQEn)
2463
    TxE_IRQ <=#Tp TxError;
2464
  else
2465
    TxE_IRQ <=#Tp 1'b0;
2466
end
2467
 
2468
 
2469
// Rx Done Interrupt
2470
always @ (posedge WB_CLK_I or posedge Reset)
2471
begin
2472
  if(Reset)
2473
    RxB_IRQ <=#Tp 1'b0;
2474
  else
2475 270 mohor
  if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
2476
    RxB_IRQ <=#Tp (~RxError);
2477 77 mohor
  else
2478
    RxB_IRQ <=#Tp 1'b0;
2479
end
2480
 
2481
 
2482
// Rx Error Interrupt
2483
always @ (posedge WB_CLK_I or posedge Reset)
2484
begin
2485
  if(Reset)
2486
    RxE_IRQ <=#Tp 1'b0;
2487
  else
2488 270 mohor
  if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
2489 77 mohor
    RxE_IRQ <=#Tp RxError;
2490
  else
2491
    RxE_IRQ <=#Tp 1'b0;
2492
end
2493
 
2494
 
2495 166 mohor
// Busy Interrupt
2496 77 mohor
 
2497 166 mohor
reg Busy_IRQ_rck;
2498
reg Busy_IRQ_sync1;
2499
reg Busy_IRQ_sync2;
2500
reg Busy_IRQ_sync3;
2501
reg Busy_IRQ_syncb1;
2502
reg Busy_IRQ_syncb2;
2503 77 mohor
 
2504
 
2505 166 mohor
always @ (posedge MRxClk or posedge Reset)
2506
begin
2507
  if(Reset)
2508
    Busy_IRQ_rck <=#Tp 1'b0;
2509
  else
2510
  if(RxValid & RxStartFrm & ~RxReady)
2511
    Busy_IRQ_rck <=#Tp 1'b1;
2512
  else
2513
  if(Busy_IRQ_syncb2)
2514
    Busy_IRQ_rck <=#Tp 1'b0;
2515
end
2516 77 mohor
 
2517 166 mohor
always @ (posedge WB_CLK_I)
2518
begin
2519
    Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
2520
    Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
2521
    Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
2522
end
2523
 
2524
always @ (posedge MRxClk)
2525
begin
2526
    Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
2527
    Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
2528
end
2529
 
2530
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
2531
 
2532
 
2533 60 mohor
 
2534
 
2535
 
2536 38 mohor
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.