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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 346

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 38 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 333 igorm
// Revision 1.57  2005/02/21 11:35:33  igorm
45
// Defer indication fixed.
46
//
47 329 igorm
// Revision 1.56  2004/04/30 10:30:00  igorm
48
// Accidently deleted line put back.
49
//
50 323 igorm
// Revision 1.55  2004/04/26 15:26:23  igorm
51
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
52
//   previous update of the core.
53
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
54
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
55
//   register. (thanks to Mathias and Torbjorn)
56
// - Multicast reception was fixed. Thanks to Ulrich Gries
57
//
58 321 igorm
// Revision 1.54  2003/11/12 18:24:59  tadejm
59
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
60
//
61 304 tadejm
// Revision 1.53  2003/10/17 07:46:17  markom
62
// mbist signals updated according to newest convention
63
//
64 302 markom
// Revision 1.52  2003/01/30 14:51:31  mohor
65
// Reset has priority in some flipflops.
66
//
67 280 mohor
// Revision 1.51  2003/01/30 13:36:22  mohor
68
// A new bug (entered with previous update) fixed. When abort occured sometimes
69
// data transmission was blocked.
70
//
71 278 mohor
// Revision 1.50  2003/01/22 13:49:26  tadejm
72
// When control packets were received, they were ignored in some cases.
73
//
74 272 tadejm
// Revision 1.49  2003/01/21 12:09:40  mohor
75
// When receiving normal data frame and RxFlow control was switched on, RXB
76
// interrupt was not set.
77
//
78 270 mohor
// Revision 1.48  2003/01/20 12:05:26  mohor
79
// When in full duplex, transmit was sometimes blocked. Fixed.
80
//
81 269 mohor
// Revision 1.47  2002/11/22 13:26:21  mohor
82
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
83
// anywhere. Removed.
84
//
85 264 mohor
// Revision 1.46  2002/11/22 01:57:06  mohor
86
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
87
// synchronized.
88
//
89 261 mohor
// Revision 1.45  2002/11/19 17:33:34  mohor
90
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
91
// that a frame was received because of the promiscous mode.
92
//
93 250 mohor
// Revision 1.44  2002/11/13 22:21:40  tadejm
94
// RxError is not generated when small frame reception is enabled and small
95
// frames are received.
96
//
97 239 tadejm
// Revision 1.43  2002/10/18 20:53:34  mohor
98
// case changed to casex.
99
//
100 229 mohor
// Revision 1.42  2002/10/18 17:04:20  tadejm
101
// Changed BIST scan signals.
102
//
103 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
104
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
105
//
106 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
107
// TxStatus is written after last access to the TX fifo is finished (in case of abort
108
// or retry). TxDone is fixed.
109
//
110 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
111
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
112
// TxDone and TxRetry are generated after the current WISHBONE access is
113
// finished.
114
//
115 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
116
// BIST added.
117
//
118 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
119
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
120
//
121 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
122
// Reception is possible after RxPointer is read and not after BD is read. For
123
// that reason RxBDReady is changed to RxReady.
124
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
125
// comes, interrupt is generated.
126
//
127 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
128
// Ethernet debug registers removed.
129
//
130 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
131
// Async reset for WB_ACK_O removed (when core was in reset, it was
132
// impossible to access BDs).
133
// RxPointers and TxPointers names changed to be more descriptive.
134
// TxUnderRun synchronized.
135
//
136 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
137
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
138
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
139
// was not used OK.
140
//
141 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
142
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
143
// need to multiply or devide any more.
144
//
145 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
146
// WriteRxDataToMemory signal changed so end of frame (when last word is
147
// written to fifo) is changed.
148
//
149 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
150
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
151
//
152 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
153
// ShiftEnded synchronization changed.
154
//
155 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
156
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
157
//
158 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
159
// RxPointer bug fixed.
160
//
161 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
162
// Previous bug wasn't succesfully removed. Now fixed.
163
//
164 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
165
// Master state machine had a bug when switching from master write to
166
// master read.
167
//
168 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
169
// m_wb_cyc_o signal released after every single transfer.
170
//
171 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
172
// Outputs registered. Reset changed for eth_wishbone module.
173
//
174 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
175
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
176
// bug fixed.
177
//
178 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
179
// Small typo fixed.
180
//
181 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
182
// Any address can be used for Tx and Rx BD pointers. Address does not need
183
// to be aligned.
184
//
185 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
186
// Comments in Slovene language removed.
187
//
188 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
189
// casex changed with case, fifo reset changed.
190
//
191 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
192
// rx_fifo was not always cleared ok. Fixed.
193
//
194 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
195
// Status was not latched correctly sometimes. Fixed.
196
//
197 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
198
// Big Endian problem when sending frames fixed.
199
//
200 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
201
// Byte ordering changed (Big Endian used). casex changed with case because
202
// Xilinx Foundation had problems. Tested in HW. It WORKS.
203
//
204 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
205
// Small fixes for external/internal DMA missmatches.
206
//
207 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
208
// Interrupts changed
209
//
210 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
211
// Status was not written correctly when frames were discarted because of
212
// address mismatch.
213
//
214 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
215
// RxStartFrm cleared when abort or retry comes.
216
//
217 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
218
// Changes that were lost when updating from 1.5 to 1.8 fixed.
219
//
220 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
221
// Addition  of new module eth_addrcheck.v
222
//
223
// Revision 1.7  2002/02/12 17:03:47  mohor
224
// RxOverRun added to statuses.
225
//
226
// Revision 1.6  2002/02/11 09:18:22  mohor
227
// Tx status is written back to the BD.
228
//
229 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
230
// Rx status is written back to the BD.
231
//
232 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
233
// non-DMA host interface added. Select the right configutation in eth_defines.
234
//
235 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
236
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
237
// MHz. Statuses, overrun, control frame transmission and reception still  need
238
// to be fixed.
239
//
240 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
241
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
242
// added.
243
//
244 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
245
// Initial version. Equals to eth_wishbonedma.v at this moment.
246 38 mohor
//
247
//
248
//
249
 
250
`include "eth_defines.v"
251
`include "timescale.v"
252
 
253
 
254
module eth_wishbone
255
   (
256
 
257
    // WISHBONE common
258 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
259 38 mohor
 
260
    // WISHBONE slave
261 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
262 40 mohor
    BDCs,
263 38 mohor
 
264 40 mohor
    Reset,
265
 
266 39 mohor
    // WISHBONE master
267
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
268
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
269
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
270
 
271 219 mohor
`ifdef ETH_WISHBONE_B3
272
    m_wb_cti_o, m_wb_bte_o,
273
`endif
274
 
275 38 mohor
    //TX
276 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
277 150 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
278 38 mohor
    PerPacketPad,
279
 
280
    //RX
281 272 tadejm
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
282 38 mohor
 
283
    // Register
284 321 igorm
    r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
285 38 mohor
 
286
    // Interrupts
287 150 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
288 42 mohor
 
289 60 mohor
    // Rx Status
290 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
291 250 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
292 261 mohor
    ReceivedPauseFrm,
293 60 mohor
 
294
    // Tx Status
295 329 igorm
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost
296 164 mohor
 
297 210 mohor
    // Bist
298
`ifdef ETH_BIST
299 227 tadejm
    ,
300
    // debug chain signals
301 302 markom
    mbist_si_i,       // bist scan serial in
302
    mbist_so_o,       // bist scan serial out
303
    mbist_ctrl_i        // bist chain shift control
304 210 mohor
`endif
305
 
306
 
307
 
308 38 mohor
                );
309
 
310
 
311
parameter Tp = 1;
312
 
313 150 mohor
 
314 38 mohor
// WISHBONE common
315
input           WB_CLK_I;       // WISHBONE clock
316
input  [31:0]   WB_DAT_I;       // WISHBONE data input
317
output [31:0]   WB_DAT_O;       // WISHBONE data output
318
 
319
// WISHBONE slave
320
input   [9:2]   WB_ADR_I;       // WISHBONE address input
321
input           WB_WE_I;        // WISHBONE write enable input
322 304 tadejm
input   [3:0]   BDCs;           // Buffer descriptors are selected
323 38 mohor
output          WB_ACK_O;       // WISHBONE acknowledge output
324
 
325 39 mohor
// WISHBONE master
326 329 igorm
output  [29:0]  m_wb_adr_o;     // 
327 39 mohor
output   [3:0]  m_wb_sel_o;     // 
328
output          m_wb_we_o;      // 
329
output  [31:0]  m_wb_dat_o;     // 
330
output          m_wb_cyc_o;     // 
331
output          m_wb_stb_o;     // 
332
input   [31:0]  m_wb_dat_i;     // 
333
input           m_wb_ack_i;     // 
334
input           m_wb_err_i;     // 
335
 
336 219 mohor
`ifdef ETH_WISHBONE_B3
337
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
338
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
339
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
340
`endif
341
 
342 40 mohor
input           Reset;       // Reset signal
343 39 mohor
 
344 60 mohor
// Rx Status signals
345 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
346
input           LatchedCrcError;  // CRC error
347
input           RxLateCollision;  // Late collision occured while receiving frame
348
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
349
input           DribbleNibble;    // Extra nibble received
350
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
351
input    [15:0] RxLength;         // Length of the incoming frame
352
input           LoadRxStatus;     // Rx status was loaded
353 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
354 250 mohor
input           AddressMiss;      // When a packet is received AddressMiss status is written to the Rx BD
355 261 mohor
input           r_RxFlow;
356 270 mohor
input           r_PassAll;
357 261 mohor
input           ReceivedPauseFrm;
358 39 mohor
 
359 60 mohor
// Tx Status signals
360
input     [3:0] RetryCntLatched;  // Latched Retry Counter
361
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
362
input           LateCollLatched;  // Late collision occured
363
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
364 329 igorm
output          RstDeferLatched;
365 60 mohor
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
366
 
367 38 mohor
// Tx
368
input           MTxClk;         // Transmit clock (from PHY)
369
input           TxUsedData;     // Transmit packet used data
370
input           TxRetry;        // Transmit packet retry
371
input           TxAbort;        // Transmit packet abort
372
input           TxDone;         // Transmission ended
373
output          TxStartFrm;     // Transmit packet start frame
374
output          TxEndFrm;       // Transmit packet end frame
375
output  [7:0]   TxData;         // Transmit packet data byte
376
output          TxUnderRun;     // Transmit packet under-run
377
output          PerPacketCrcEn; // Per packet crc enable
378
output          PerPacketPad;   // Per packet pading
379
 
380
// Rx
381
input           MRxClk;         // Receive clock (from PHY)
382
input   [7:0]   RxData;         // Received data byte (from PHY)
383
input           RxValid;        // 
384
input           RxStartFrm;     // 
385
input           RxEndFrm;       // 
386 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
387 272 tadejm
output          RxStatusWriteLatched_sync2;
388 38 mohor
 
389
//Register
390
input           r_TxEn;         // Transmit enable
391
input           r_RxEn;         // Receive enable
392
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
393
 
394
// Interrupts
395
output TxB_IRQ;
396
output TxE_IRQ;
397
output RxB_IRQ;
398 77 mohor
output RxE_IRQ;
399 38 mohor
output Busy_IRQ;
400
 
401 77 mohor
 
402 210 mohor
// Bist
403
`ifdef ETH_BIST
404 302 markom
input   mbist_si_i;       // bist scan serial in
405
output  mbist_so_o;       // bist scan serial out
406
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
407 210 mohor
`endif
408
 
409 77 mohor
reg TxB_IRQ;
410
reg TxE_IRQ;
411
reg RxB_IRQ;
412
reg RxE_IRQ;
413
 
414 38 mohor
reg             TxStartFrm;
415
reg             TxEndFrm;
416
reg     [7:0]   TxData;
417
 
418
reg             TxUnderRun;
419 60 mohor
reg             TxUnderRun_wb;
420 38 mohor
 
421
reg             TxBDRead;
422 39 mohor
wire            TxStatusWrite;
423 38 mohor
 
424
reg     [1:0]   TxValidBytesLatched;
425
 
426
reg    [15:0]   TxLength;
427 60 mohor
reg    [15:0]   LatchedTxLength;
428
reg   [14:11]   TxStatus;
429 38 mohor
 
430 60 mohor
reg   [14:13]   RxStatus;
431 38 mohor
 
432
reg             TxStartFrm_wb;
433
reg             TxRetry_wb;
434 39 mohor
reg             TxAbort_wb;
435 38 mohor
reg             TxDone_wb;
436
 
437
reg             TxDone_wb_q;
438
reg             TxAbort_wb_q;
439 39 mohor
reg             TxRetry_wb_q;
440 219 mohor
reg             TxRetryPacket;
441 221 mohor
reg             TxRetryPacket_NotCleared;
442
reg             TxDonePacket;
443
reg             TxDonePacket_NotCleared;
444 219 mohor
reg             TxAbortPacket;
445 221 mohor
reg             TxAbortPacket_NotCleared;
446 38 mohor
reg             RxBDReady;
447 166 mohor
reg             RxReady;
448 38 mohor
reg             TxBDReady;
449
 
450
reg             RxBDRead;
451
 
452
reg    [31:0]   TxDataLatched;
453
reg     [1:0]   TxByteCnt;
454
reg             LastWord;
455 39 mohor
reg             ReadTxDataFromFifo_tck;
456 38 mohor
 
457
reg             BlockingTxStatusWrite;
458
reg             BlockingTxBDRead;
459
 
460 40 mohor
reg             Flop;
461 38 mohor
 
462 329 igorm
reg     [7:1]   TxBDAddress;
463
reg     [7:1]   RxBDAddress;
464 38 mohor
 
465
reg             TxRetrySync1;
466
reg             TxAbortSync1;
467 39 mohor
reg             TxDoneSync1;
468 38 mohor
 
469
reg             TxAbort_q;
470
reg             TxRetry_q;
471
reg             TxUsedData_q;
472
 
473
reg    [31:0]   RxDataLatched2;
474 82 mohor
 
475
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
476
 
477 38 mohor
reg     [1:0]   RxValidBytes;
478
reg     [1:0]   RxByteCnt;
479
reg             LastByteIn;
480
reg             ShiftWillEnd;
481
 
482 40 mohor
reg             WriteRxDataToFifo;
483 42 mohor
reg    [15:0]   LatchedRxLength;
484 64 mohor
reg             RxAbortLatched;
485 38 mohor
 
486 40 mohor
reg             ShiftEnded;
487 60 mohor
reg             RxOverrun;
488 38 mohor
 
489 304 tadejm
reg     [3:0]   BDWrite;                    // BD Write Enable for access from WISHBONE side
490 40 mohor
reg             BDRead;                     // BD Read access from WISHBONE side
491 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
492
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
493 38 mohor
 
494 39 mohor
reg             TxEndFrm_wb;
495 38 mohor
 
496 39 mohor
wire            TxRetryPulse;
497 38 mohor
wire            TxDonePulse;
498
wire            TxAbortPulse;
499
 
500
wire            StartRxBDRead;
501
 
502
wire            StartTxBDRead;
503
 
504
wire            TxIRQEn;
505
wire            WrapTxStatusBit;
506
 
507 77 mohor
wire            RxIRQEn;
508 38 mohor
wire            WrapRxStatusBit;
509
 
510
wire    [1:0]   TxValidBytes;
511
 
512 329 igorm
wire    [7:1]   TempTxBDAddress;
513
wire    [7:1]   TempRxBDAddress;
514 38 mohor
 
515 272 tadejm
wire            RxStatusWrite;
516 329 igorm
wire            RxBufferFull;
517
wire            RxBufferAlmostEmpty;
518
wire            RxBufferEmpty;
519 272 tadejm
 
520 106 mohor
reg             WB_ACK_O;
521 38 mohor
 
522 261 mohor
wire    [8:0]   RxStatusIn;
523
reg     [8:0]   RxStatusInLatched;
524 42 mohor
 
525 39 mohor
reg WbEn, WbEn_q;
526
reg RxEn, RxEn_q;
527
reg TxEn, TxEn_q;
528 321 igorm
reg r_TxEn_q;
529
reg r_RxEn_q;
530 38 mohor
 
531 39 mohor
wire ram_ce;
532 304 tadejm
wire [3:0]  ram_we;
533 39 mohor
wire ram_oe;
534
reg [7:0]   ram_addr;
535
reg [31:0]  ram_di;
536
wire [31:0] ram_do;
537 38 mohor
 
538 39 mohor
wire StartTxPointerRead;
539
reg  TxPointerRead;
540
reg TxEn_needed;
541 40 mohor
reg RxEn_needed;
542 38 mohor
 
543 40 mohor
wire StartRxPointerRead;
544
reg RxPointerRead;
545 38 mohor
 
546 219 mohor
`ifdef ETH_WISHBONE_B3
547
assign m_wb_bte_o = 2'b00;    // Linear burst
548
`endif
549 39 mohor
 
550 329 igorm
assign m_wb_stb_o = m_wb_cyc_o;
551 219 mohor
 
552 159 mohor
always @ (posedge WB_CLK_I)
553 40 mohor
begin
554 304 tadejm
  WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
555 40 mohor
end
556 39 mohor
 
557 106 mohor
assign WB_DAT_O = ram_do;
558 39 mohor
 
559 41 mohor
// Generic synchronous single-port RAM interface
560 119 mohor
eth_spram_256x32 bd_ram (
561 226 tadejm
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
562 210 mohor
`ifdef ETH_BIST
563 227 tadejm
  ,
564 302 markom
  .mbist_si_i       (mbist_si_i),
565
  .mbist_so_o       (mbist_so_o),
566
  .mbist_ctrl_i       (mbist_ctrl_i)
567 210 mohor
`endif
568 39 mohor
);
569 41 mohor
 
570 39 mohor
assign ram_ce = 1'b1;
571 304 tadejm
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | {4{(TxStatusWrite | RxStatusWrite)}};
572 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
573 39 mohor
 
574
 
575 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
576 38 mohor
begin
577 40 mohor
  if(Reset)
578 39 mohor
    TxEn_needed <=#Tp 1'b0;
579 38 mohor
  else
580 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
581 39 mohor
    TxEn_needed <=#Tp 1'b1;
582
  else
583
  if(TxPointerRead & TxEn & TxEn_q)
584
    TxEn_needed <=#Tp 1'b0;
585 38 mohor
end
586
 
587 39 mohor
// Enabling access to the RAM for three devices.
588 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
589 39 mohor
begin
590 40 mohor
  if(Reset)
591 39 mohor
    begin
592
      WbEn <=#Tp 1'b1;
593
      RxEn <=#Tp 1'b0;
594
      TxEn <=#Tp 1'b0;
595
      ram_addr <=#Tp 8'h0;
596
      ram_di <=#Tp 32'h0;
597 77 mohor
      BDRead <=#Tp 1'b0;
598
      BDWrite <=#Tp 1'b0;
599 39 mohor
    end
600
  else
601
    begin
602
      // Switching between three stages depends on enable signals
603 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
604
        5'b100_10, 5'b100_11 :
605 39 mohor
          begin
606
            WbEn <=#Tp 1'b0;
607
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
608
            TxEn <=#Tp 1'b0;
609 329 igorm
            ram_addr <=#Tp {RxBDAddress, RxPointerRead};
610 39 mohor
            ram_di <=#Tp RxBDDataIn;
611
          end
612
        5'b100_01 :
613
          begin
614
            WbEn <=#Tp 1'b0;
615
            RxEn <=#Tp 1'b0;
616
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
617 329 igorm
            ram_addr <=#Tp {TxBDAddress, TxPointerRead};
618 39 mohor
            ram_di <=#Tp TxBDDataIn;
619
          end
620 90 mohor
        5'b010_00, 5'b010_10 :
621 39 mohor
          begin
622
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
623
            RxEn <=#Tp 1'b0;
624
            TxEn <=#Tp 1'b0;
625
            ram_addr <=#Tp WB_ADR_I[9:2];
626
            ram_di <=#Tp WB_DAT_I;
627 304 tadejm
            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
628
            BDRead <=#Tp (|BDCs) & ~WB_WE_I;
629 39 mohor
          end
630 90 mohor
        5'b010_01, 5'b010_11 :
631 39 mohor
          begin
632
            WbEn <=#Tp 1'b0;
633
            RxEn <=#Tp 1'b0;
634
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
635 329 igorm
            ram_addr <=#Tp {TxBDAddress, TxPointerRead};
636 39 mohor
            ram_di <=#Tp TxBDDataIn;
637
          end
638 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
639 39 mohor
          begin
640
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
641
            RxEn <=#Tp 1'b0;
642
            TxEn <=#Tp 1'b0;
643
            ram_addr <=#Tp WB_ADR_I[9:2];
644
            ram_di <=#Tp WB_DAT_I;
645 304 tadejm
            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
646
            BDRead <=#Tp (|BDCs) & ~WB_WE_I;
647 39 mohor
          end
648
        5'b100_00 :
649
          begin
650
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
651
          end
652
        5'b000_00 :
653
          begin
654
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
655
            RxEn <=#Tp 1'b0;
656
            TxEn <=#Tp 1'b0;
657
            ram_addr <=#Tp WB_ADR_I[9:2];
658
            ram_di <=#Tp WB_DAT_I;
659 304 tadejm
            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
660
            BDRead <=#Tp (|BDCs) & ~WB_WE_I;
661 39 mohor
          end
662
      endcase
663
    end
664
end
665
 
666
 
667
// Delayed stage signals
668 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
669 39 mohor
begin
670 40 mohor
  if(Reset)
671 39 mohor
    begin
672
      WbEn_q <=#Tp 1'b0;
673
      RxEn_q <=#Tp 1'b0;
674
      TxEn_q <=#Tp 1'b0;
675 321 igorm
      r_TxEn_q <=#Tp 1'b0;
676
      r_RxEn_q <=#Tp 1'b0;
677 39 mohor
    end
678
  else
679
    begin
680
      WbEn_q <=#Tp WbEn;
681
      RxEn_q <=#Tp RxEn;
682
      TxEn_q <=#Tp TxEn;
683 323 igorm
      r_TxEn_q <=#Tp r_TxEn;
684 321 igorm
      r_RxEn_q <=#Tp r_RxEn;
685 39 mohor
    end
686
end
687
 
688 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
689 40 mohor
always @ (posedge MTxClk or posedge Reset)
690 38 mohor
begin
691 40 mohor
  if(Reset)
692 38 mohor
    Flop <=#Tp 1'b0;
693
  else
694
  if(TxDone | TxAbort | TxRetry_q)
695
    Flop <=#Tp 1'b0;
696
  else
697
  if(TxUsedData)
698
    Flop <=#Tp ~Flop;
699
end
700
 
701 39 mohor
wire ResetTxBDReady;
702
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
703 38 mohor
 
704
// Latching READY status of the Tx buffer descriptor
705 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
706 38 mohor
begin
707 40 mohor
  if(Reset)
708 38 mohor
    TxBDReady <=#Tp 1'b0;
709
  else
710 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
711
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
712
  else                                                // Only packets larger then 4 bytes are transmitted.
713 39 mohor
  if(ResetTxBDReady)
714 38 mohor
    TxBDReady <=#Tp 1'b0;
715
end
716
 
717
 
718 39 mohor
// Reading the Tx buffer descriptor
719 221 mohor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
720 39 mohor
 
721 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
722 38 mohor
begin
723 40 mohor
  if(Reset)
724 39 mohor
    TxBDRead <=#Tp 1'b1;
725 38 mohor
  else
726 110 mohor
  if(StartTxBDRead)
727 39 mohor
    TxBDRead <=#Tp 1'b1;
728 38 mohor
  else
729 39 mohor
  if(TxBDReady)
730
    TxBDRead <=#Tp 1'b0;
731 38 mohor
end
732
 
733
 
734 39 mohor
// Reading Tx BD pointer
735
assign StartTxPointerRead = TxBDRead & TxBDReady;
736 38 mohor
 
737 39 mohor
// Reading Tx BD Pointer
738 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
739 38 mohor
begin
740 40 mohor
  if(Reset)
741 39 mohor
    TxPointerRead <=#Tp 1'b0;
742 38 mohor
  else
743 39 mohor
  if(StartTxPointerRead)
744
    TxPointerRead <=#Tp 1'b1;
745 38 mohor
  else
746 39 mohor
  if(TxEn_q)
747
    TxPointerRead <=#Tp 1'b0;
748 38 mohor
end
749
 
750
 
751 39 mohor
// Writing status back to the Tx buffer descriptor
752 221 mohor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
753 38 mohor
 
754
 
755
 
756 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
757 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
758 38 mohor
begin
759 40 mohor
  if(Reset)
760 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
761 38 mohor
  else
762 272 tadejm
  if(~TxDone_wb & ~TxAbort_wb)
763
    BlockingTxStatusWrite <=#Tp 1'b0;
764
  else
765 39 mohor
  if(TxStatusWrite)
766
    BlockingTxStatusWrite <=#Tp 1'b1;
767 38 mohor
end
768
 
769
 
770 159 mohor
reg BlockingTxStatusWrite_sync1;
771
reg BlockingTxStatusWrite_sync2;
772 329 igorm
reg BlockingTxStatusWrite_sync3;
773 159 mohor
 
774
// Synchronizing BlockingTxStatusWrite to MTxClk
775
always @ (posedge MTxClk or posedge Reset)
776
begin
777
  if(Reset)
778
    BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
779
  else
780
    BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
781
end
782
 
783
// Synchronizing BlockingTxStatusWrite to MTxClk
784
always @ (posedge MTxClk or posedge Reset)
785
begin
786
  if(Reset)
787
    BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
788
  else
789
    BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
790
end
791
 
792 329 igorm
// Synchronizing BlockingTxStatusWrite to MTxClk
793
always @ (posedge MTxClk or posedge Reset)
794
begin
795
  if(Reset)
796
    BlockingTxStatusWrite_sync3 <=#Tp 1'b0;
797
  else
798
    BlockingTxStatusWrite_sync3 <=#Tp BlockingTxStatusWrite_sync2;
799
end
800 159 mohor
 
801 329 igorm
assign RstDeferLatched = BlockingTxStatusWrite_sync2 & ~BlockingTxStatusWrite_sync3;
802
 
803 39 mohor
// TxBDRead state is activated only once. 
804 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
805 39 mohor
begin
806 40 mohor
  if(Reset)
807 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
808
  else
809 110 mohor
  if(StartTxBDRead)
810 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
811
  else
812 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
813 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
814
end
815 38 mohor
 
816
 
817 39 mohor
// Latching status from the tx buffer descriptor
818
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
819 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
820 38 mohor
begin
821 40 mohor
  if(Reset)
822 60 mohor
    TxStatus <=#Tp 4'h0;
823 38 mohor
  else
824 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
825 60 mohor
    TxStatus <=#Tp ram_do[14:11];
826 38 mohor
end
827
 
828 40 mohor
reg ReadTxDataFromMemory;
829
wire WriteRxDataToMemory;
830 38 mohor
 
831 39 mohor
reg MasterWbTX;
832
reg MasterWbRX;
833
 
834 329 igorm
reg [29:0] m_wb_adr_o;
835 39 mohor
reg        m_wb_cyc_o;
836 96 mohor
reg  [3:0] m_wb_sel_o;
837 39 mohor
reg        m_wb_we_o;
838 40 mohor
 
839 39 mohor
wire TxLengthEq0;
840
wire TxLengthLt4;
841
 
842 150 mohor
reg BlockingIncrementTxPointer;
843 159 mohor
reg [31:2] TxPointerMSB;
844
reg [1:0]  TxPointerLSB;
845
reg [1:0]  TxPointerLSB_rst;
846
reg [31:2] RxPointerMSB;
847
reg [1:0]  RxPointerLSB_rst;
848 39 mohor
 
849 150 mohor
wire RxBurstAcc;
850
wire RxWordAcc;
851
wire RxHalfAcc;
852
wire RxByteAcc;
853
 
854 39 mohor
//Latching length from the buffer descriptor;
855 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
856 38 mohor
begin
857 40 mohor
  if(Reset)
858 39 mohor
    TxLength <=#Tp 16'h0;
859 38 mohor
  else
860 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
861
    TxLength <=#Tp ram_do[31:16];
862 38 mohor
  else
863 39 mohor
  if(MasterWbTX & m_wb_ack_i)
864
    begin
865
      if(TxLengthLt4)
866
        TxLength <=#Tp 16'h0;
867 150 mohor
      else
868 159 mohor
      if(TxPointerLSB_rst==2'h0)
869 96 mohor
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
870 39 mohor
      else
871 159 mohor
      if(TxPointerLSB_rst==2'h1)
872 150 mohor
        TxLength <=#Tp TxLength - 3'h3;    // Length is subtracted at the data request
873
      else
874 159 mohor
      if(TxPointerLSB_rst==2'h2)
875 150 mohor
        TxLength <=#Tp TxLength - 3'h2;    // Length is subtracted at the data request
876
      else
877 159 mohor
      if(TxPointerLSB_rst==2'h3)
878 150 mohor
        TxLength <=#Tp TxLength - 3'h1;    // Length is subtracted at the data request
879 39 mohor
    end
880 38 mohor
end
881
 
882 96 mohor
 
883
 
884 60 mohor
//Latching length from the buffer descriptor;
885
always @ (posedge WB_CLK_I or posedge Reset)
886
begin
887
  if(Reset)
888
    LatchedTxLength <=#Tp 16'h0;
889
  else
890
  if(TxEn & TxEn_q & TxBDRead)
891
    LatchedTxLength <=#Tp ram_do[31:16];
892
end
893
 
894 39 mohor
assign TxLengthEq0 = TxLength == 0;
895
assign TxLengthLt4 = TxLength < 4;
896 38 mohor
 
897 150 mohor
reg cyc_cleared;
898
reg IncrTxPointer;
899 39 mohor
 
900
 
901 159 mohor
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
902
// because TxPointerMSB is only used for word-aligned accesses.
903 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
904 38 mohor
begin
905 40 mohor
  if(Reset)
906 159 mohor
    TxPointerMSB <=#Tp 30'h0;
907 38 mohor
  else
908 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
909 159 mohor
    TxPointerMSB <=#Tp ram_do[31:2];
910 38 mohor
  else
911 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
912 159 mohor
    TxPointerMSB <=#Tp TxPointerMSB + 1'b1;     // TxPointer is word-aligned
913 38 mohor
end
914
 
915 96 mohor
 
916 159 mohor
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
917
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
918
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
919
// set by this two bits.
920 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
921
begin
922
  if(Reset)
923 159 mohor
    TxPointerLSB[1:0] <=#Tp 0;
924 96 mohor
  else
925
  if(TxEn & TxEn_q & TxPointerRead)
926 159 mohor
    TxPointerLSB[1:0] <=#Tp ram_do[1:0];
927 96 mohor
end
928
 
929
 
930 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
931
// After the read access, TxLength needs to be decremented for the number of the valid
932
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
933
// valid so this two bits are reset to zero. 
934 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
935
begin
936
  if(Reset)
937 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
938 150 mohor
  else
939
  if(TxEn & TxEn_q & TxPointerRead)
940 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
941 150 mohor
  else
942
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
943 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
944 150 mohor
end
945 96 mohor
 
946 150 mohor
 
947 159 mohor
reg  [3:0] RxByteSel;
948 39 mohor
wire MasterAccessFinished;
949 38 mohor
 
950 39 mohor
 
951 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
952 38 mohor
begin
953 40 mohor
  if(Reset)
954 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
955 38 mohor
  else
956 39 mohor
  if(MasterAccessFinished)
957
    BlockingIncrementTxPointer <=#Tp 0;
958 38 mohor
  else
959 150 mohor
  if(IncrTxPointer)
960 39 mohor
    BlockingIncrementTxPointer <=#Tp 1'b1;
961 38 mohor
end
962
 
963
 
964 39 mohor
wire TxBufferAlmostFull;
965
wire TxBufferFull;
966
wire TxBufferEmpty;
967
wire TxBufferAlmostEmpty;
968 40 mohor
wire SetReadTxDataFromMemory;
969 39 mohor
 
970 40 mohor
reg BlockReadTxDataFromMemory;
971 39 mohor
 
972 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
973 39 mohor
 
974 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
975 38 mohor
begin
976 40 mohor
  if(Reset)
977
    ReadTxDataFromMemory <=#Tp 1'b0;
978 38 mohor
  else
979 278 mohor
  if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
980 40 mohor
    ReadTxDataFromMemory <=#Tp 1'b0;
981 39 mohor
  else
982 40 mohor
  if(SetReadTxDataFromMemory)
983
    ReadTxDataFromMemory <=#Tp 1'b1;
984 38 mohor
end
985
 
986 226 tadejm
reg tx_burst_en;
987
reg rx_burst_en;
988 221 mohor
 
989 278 mohor
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
990 226 tadejm
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
991 221 mohor
 
992 39 mohor
wire [31:0] TxData_wb;
993
wire ReadTxDataFromFifo_wb;
994 38 mohor
 
995 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
996 38 mohor
begin
997 40 mohor
  if(Reset)
998
    BlockReadTxDataFromMemory <=#Tp 1'b0;
999 38 mohor
  else
1000 278 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
1001 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
1002 219 mohor
  else
1003 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
1004 219 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b0;
1005 39 mohor
end
1006
 
1007
 
1008
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
1009 219 mohor
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
1010
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
1011 226 tadejm
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
1012
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
1013 159 mohor
 
1014 226 tadejm
wire rx_burst;
1015
wire enough_data_in_rxfifo_for_burst;
1016
wire enough_data_in_rxfifo_for_burst_plus1;
1017 229 mohor
 
1018 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
1019 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1020 39 mohor
begin
1021 40 mohor
  if(Reset)
1022 38 mohor
    begin
1023 39 mohor
      MasterWbTX <=#Tp 1'b0;
1024
      MasterWbRX <=#Tp 1'b0;
1025 329 igorm
      m_wb_adr_o <=#Tp 30'h0;
1026 39 mohor
      m_wb_cyc_o <=#Tp 1'b0;
1027
      m_wb_we_o  <=#Tp 1'b0;
1028 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
1029 110 mohor
      cyc_cleared<=#Tp 1'b0;
1030 226 tadejm
      tx_burst_cnt<=#Tp 0;
1031
      rx_burst_cnt<=#Tp 0;
1032 150 mohor
      IncrTxPointer<=#Tp 1'b0;
1033 226 tadejm
      tx_burst_en<=#Tp 1'b1;
1034
      rx_burst_en<=#Tp 1'b0;
1035
      `ifdef ETH_WISHBONE_B3
1036
        m_wb_cti_o <=#Tp 3'b0;
1037
      `endif
1038 38 mohor
    end
1039 39 mohor
  else
1040
    begin
1041
      // Switching between two stages depends on enable signals
1042 229 mohor
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst})  // synopsys parallel_case
1043 226 tadejm
        8'b00_10_00_10,             // Idle and MRB needed
1044 229 mohor
        8'b10_1x_10_1x,             // MRB continues
1045 226 tadejm
        8'b10_10_01_10,             // Clear (previously MR) and MRB needed
1046 229 mohor
        8'b01_1x_01_1x :            // Clear (previously MW) and MRB needed
1047 39 mohor
          begin
1048 226 tadejm
            MasterWbTX <=#Tp 1'b1;  // tx burst
1049
            MasterWbRX <=#Tp 1'b0;
1050
            m_wb_cyc_o <=#Tp 1'b1;
1051
            m_wb_we_o  <=#Tp 1'b0;
1052
            m_wb_sel_o <=#Tp 4'hf;
1053
            cyc_cleared<=#Tp 1'b0;
1054
            IncrTxPointer<=#Tp 1'b1;
1055 329 igorm
            tx_burst_cnt <=#Tp tx_burst_cnt+3'h1;
1056 226 tadejm
            if(tx_burst_cnt==0)
1057 329 igorm
              m_wb_adr_o <=#Tp TxPointerMSB;
1058 226 tadejm
            else
1059 329 igorm
              m_wb_adr_o <=#Tp m_wb_adr_o+1'b1;
1060 226 tadejm
 
1061
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1062
              begin
1063
                tx_burst_en<=#Tp 1'b0;
1064
              `ifdef ETH_WISHBONE_B3
1065
                m_wb_cti_o <=#Tp 3'b111;
1066
              `endif
1067
              end
1068
            else
1069
              begin
1070
              `ifdef ETH_WISHBONE_B3
1071
                m_wb_cti_o <=#Tp 3'b010;
1072
              `endif
1073
              end
1074
          end
1075 229 mohor
        8'b00_x1_00_x1,             // Idle and MWB needed
1076
        8'b01_x1_10_x1,             // MWB continues
1077 226 tadejm
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1078 229 mohor
        8'b10_x1_01_x1 :            // Clear (previously MR) and MWB needed
1079 226 tadejm
          begin
1080
            MasterWbTX <=#Tp 1'b0;  // rx burst
1081 39 mohor
            MasterWbRX <=#Tp 1'b1;
1082 226 tadejm
            m_wb_cyc_o <=#Tp 1'b1;
1083
            m_wb_we_o  <=#Tp 1'b1;
1084
            m_wb_sel_o <=#Tp RxByteSel;
1085
            IncrTxPointer<=#Tp 1'b0;
1086
            cyc_cleared<=#Tp 1'b0;
1087 329 igorm
            rx_burst_cnt <=#Tp rx_burst_cnt+3'h1;
1088 226 tadejm
 
1089
            if(rx_burst_cnt==0)
1090 329 igorm
              m_wb_adr_o <=#Tp RxPointerMSB;
1091 226 tadejm
            else
1092 329 igorm
              m_wb_adr_o <=#Tp m_wb_adr_o+1'b1;
1093 226 tadejm
 
1094
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1095
              begin
1096
                rx_burst_en<=#Tp 1'b0;
1097
              `ifdef ETH_WISHBONE_B3
1098
                m_wb_cti_o <=#Tp 3'b111;
1099
              `endif
1100
              end
1101
            else
1102
              begin
1103
              `ifdef ETH_WISHBONE_B3
1104
                m_wb_cti_o <=#Tp 3'b010;
1105
              `endif
1106
              end
1107
          end
1108 229 mohor
        8'b00_x1_00_x0 :            // idle and MW is needed (data write to rx buffer)
1109 226 tadejm
          begin
1110
            MasterWbTX <=#Tp 1'b0;
1111
            MasterWbRX <=#Tp 1'b1;
1112 329 igorm
            m_wb_adr_o <=#Tp RxPointerMSB;
1113 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1114
            m_wb_we_o  <=#Tp 1'b1;
1115 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1116 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1117 39 mohor
          end
1118 226 tadejm
        8'b00_10_00_00 :            // idle and MR is needed (data read from tx buffer)
1119 39 mohor
          begin
1120 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1121 39 mohor
            MasterWbRX <=#Tp 1'b0;
1122 329 igorm
            m_wb_adr_o <=#Tp TxPointerMSB;
1123 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1124
            m_wb_we_o  <=#Tp 1'b0;
1125 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1126
            IncrTxPointer<=#Tp 1'b1;
1127 39 mohor
          end
1128 226 tadejm
        8'b10_10_01_00,             // MR and MR is needed (data read from tx buffer)
1129 229 mohor
        8'b01_1x_01_0x  :           // MW and MR is needed (data read from tx buffer)
1130 39 mohor
          begin
1131 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1132 39 mohor
            MasterWbRX <=#Tp 1'b0;
1133 329 igorm
            m_wb_adr_o <=#Tp TxPointerMSB;
1134 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1135
            m_wb_we_o  <=#Tp 1'b0;
1136 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1137 110 mohor
            cyc_cleared<=#Tp 1'b0;
1138 150 mohor
            IncrTxPointer<=#Tp 1'b1;
1139 39 mohor
          end
1140 226 tadejm
        8'b01_01_01_00,             // MW and MW needed (data write to rx buffer)
1141 229 mohor
        8'b10_x1_01_x0  :           // MR and MW is needed (data write to rx buffer)
1142 39 mohor
          begin
1143 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1144 39 mohor
            MasterWbRX <=#Tp 1'b1;
1145 329 igorm
            m_wb_adr_o <=#Tp RxPointerMSB;
1146 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1147 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
1148 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1149 110 mohor
            cyc_cleared<=#Tp 1'b0;
1150 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1151 39 mohor
          end
1152 226 tadejm
        8'b01_01_10_00,             // MW and MW needed (cycle is cleared between previous and next access)
1153 229 mohor
        8'b01_1x_10_x0,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1154 226 tadejm
        8'b10_10_10_00,             // MR and MR needed (cycle is cleared between previous and next access)
1155 229 mohor
        8'b10_x1_10_0x :            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1156 39 mohor
          begin
1157 110 mohor
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
1158
            cyc_cleared<=#Tp 1'b1;
1159 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1160 226 tadejm
            tx_burst_cnt<=#Tp 0;
1161
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1162
            rx_burst_cnt<=#Tp 0;
1163
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1164
            `ifdef ETH_WISHBONE_B3
1165
              m_wb_cti_o <=#Tp 3'b0;
1166
            `endif
1167 110 mohor
          end
1168 229 mohor
        8'bxx_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1169
        8'bxx_00_01_00 :            // Between cyc_cleared request was cleared
1170 110 mohor
          begin
1171 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1172 39 mohor
            MasterWbRX <=#Tp 1'b0;
1173
            m_wb_cyc_o <=#Tp 1'b0;
1174 226 tadejm
            cyc_cleared<=#Tp 1'b0;
1175 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1176 226 tadejm
            rx_burst_cnt<=#Tp 0;
1177
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1178
            `ifdef ETH_WISHBONE_B3
1179
              m_wb_cti_o <=#Tp 3'b0;
1180
            `endif
1181 39 mohor
          end
1182 226 tadejm
        8'b00_00_00_00:             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1183 127 mohor
          begin
1184 226 tadejm
            tx_burst_cnt<=#Tp 0;
1185
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1186 127 mohor
          end
1187 226 tadejm
        default:                    // Don't touch
1188 82 mohor
          begin
1189
            MasterWbTX <=#Tp MasterWbTX;
1190
            MasterWbRX <=#Tp MasterWbRX;
1191
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
1192 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
1193 150 mohor
            IncrTxPointer<=#Tp IncrTxPointer;
1194 82 mohor
          end
1195 39 mohor
      endcase
1196
    end
1197 38 mohor
end
1198
 
1199 110 mohor
 
1200 39 mohor
wire TxFifoClear;
1201 96 mohor
 
1202 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1203 38 mohor
 
1204 219 mohor
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
1205 150 mohor
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
1206 96 mohor
          .clk(WB_CLK_I),                                   .reset(Reset),
1207 226 tadejm
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1208 96 mohor
          .clear(TxFifoClear),                              .full(TxBufferFull),
1209
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
1210 150 mohor
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
1211 96 mohor
        );
1212 39 mohor
 
1213
 
1214
reg StartOccured;
1215
reg TxStartFrm_sync1;
1216
reg TxStartFrm_sync2;
1217
reg TxStartFrm_syncb1;
1218
reg TxStartFrm_syncb2;
1219
 
1220
 
1221
 
1222
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1223 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1224 38 mohor
begin
1225 40 mohor
  if(Reset)
1226 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
1227 38 mohor
  else
1228 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1229
    TxStartFrm_wb <=#Tp 1'b1;
1230 38 mohor
  else
1231 39 mohor
  if(TxStartFrm_syncb2)
1232
    TxStartFrm_wb <=#Tp 1'b0;
1233 38 mohor
end
1234
 
1235 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1236 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1237 38 mohor
begin
1238 40 mohor
  if(Reset)
1239 39 mohor
    StartOccured <=#Tp 1'b0;
1240 38 mohor
  else
1241 39 mohor
  if(TxStartFrm_wb)
1242
    StartOccured <=#Tp 1'b1;
1243 38 mohor
  else
1244 39 mohor
  if(ResetTxBDReady)
1245
    StartOccured <=#Tp 1'b0;
1246 38 mohor
end
1247
 
1248 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1249 40 mohor
always @ (posedge MTxClk or posedge Reset)
1250 39 mohor
begin
1251 40 mohor
  if(Reset)
1252 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1253
  else
1254
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1255
end
1256 38 mohor
 
1257 40 mohor
always @ (posedge MTxClk or posedge Reset)
1258 39 mohor
begin
1259 40 mohor
  if(Reset)
1260 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1261
  else
1262
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1263
end
1264
 
1265 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1266 38 mohor
begin
1267 40 mohor
  if(Reset)
1268 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1269 38 mohor
  else
1270 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1271 38 mohor
end
1272
 
1273 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1274 38 mohor
begin
1275 40 mohor
  if(Reset)
1276 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1277 38 mohor
  else
1278 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1279
end
1280
 
1281 40 mohor
always @ (posedge MTxClk or posedge Reset)
1282 39 mohor
begin
1283 40 mohor
  if(Reset)
1284 39 mohor
    TxStartFrm <=#Tp 1'b0;
1285 38 mohor
  else
1286 39 mohor
  if(TxStartFrm_sync2)
1287 61 mohor
    TxStartFrm <=#Tp 1'b1;
1288 39 mohor
  else
1289 278 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
1290 39 mohor
    TxStartFrm <=#Tp 1'b0;
1291 38 mohor
end
1292 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1293 38 mohor
 
1294
 
1295 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1296 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1297 38 mohor
begin
1298 40 mohor
  if(Reset)
1299 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1300 38 mohor
  else
1301 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1302 39 mohor
    TxEndFrm_wb <=#Tp 1'b1;
1303 38 mohor
  else
1304 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1305
    TxEndFrm_wb <=#Tp 1'b0;
1306 38 mohor
end
1307
 
1308
 
1309
// Marks which bytes are valid within the word.
1310 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1311 38 mohor
 
1312 39 mohor
reg LatchValidBytes;
1313
reg LatchValidBytes_q;
1314 38 mohor
 
1315 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1316 38 mohor
begin
1317 40 mohor
  if(Reset)
1318 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1319 38 mohor
  else
1320 39 mohor
  if(TxLengthLt4 & TxBDReady)
1321
    LatchValidBytes <=#Tp 1'b1;
1322 38 mohor
  else
1323 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1324 38 mohor
end
1325
 
1326 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1327 38 mohor
begin
1328 40 mohor
  if(Reset)
1329 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1330 38 mohor
  else
1331 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1332 38 mohor
end
1333
 
1334
 
1335 39 mohor
// Latching valid bytes
1336 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1337 38 mohor
begin
1338 40 mohor
  if(Reset)
1339 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1340 38 mohor
  else
1341 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1342
    TxValidBytesLatched <=#Tp TxValidBytes;
1343
  else
1344
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1345
    TxValidBytesLatched <=#Tp 2'h0;
1346 38 mohor
end
1347
 
1348
 
1349
assign TxIRQEn          = TxStatus[14];
1350 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1351
assign PerPacketPad     = TxStatus[12];
1352
assign PerPacketCrcEn   = TxStatus[11];
1353 38 mohor
 
1354
 
1355 77 mohor
assign RxIRQEn         = RxStatus[14];
1356 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1357 38 mohor
 
1358
 
1359
// Temporary Tx and Rx buffer descriptor address 
1360 329 igorm
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite     & ~WrapTxStatusBit}}   & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
1361
assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0])     | // Using first Rx BD
1362
                              {7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address)
1363 38 mohor
 
1364
 
1365
// Latching Tx buffer descriptor address
1366 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1367 38 mohor
begin
1368 40 mohor
  if(Reset)
1369 329 igorm
    TxBDAddress <=#Tp 7'h0;
1370 321 igorm
  else if (r_TxEn & (~r_TxEn_q))
1371 329 igorm
    TxBDAddress <=#Tp 7'h0;
1372 321 igorm
  else if (TxStatusWrite)
1373 38 mohor
    TxBDAddress <=#Tp TempTxBDAddress;
1374
end
1375
 
1376
 
1377
// Latching Rx buffer descriptor address
1378 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1379 38 mohor
begin
1380 40 mohor
  if(Reset)
1381 329 igorm
    RxBDAddress <=#Tp 7'h0;
1382 321 igorm
  else if(r_RxEn & (~r_RxEn_q))
1383 329 igorm
    RxBDAddress <=#Tp r_TxBDNum[6:0];
1384 321 igorm
  else if(RxStatusWrite)
1385 38 mohor
    RxBDAddress <=#Tp TempRxBDAddress;
1386
end
1387
 
1388 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1389 38 mohor
 
1390 261 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
1391 60 mohor
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1392 38 mohor
 
1393 60 mohor
 
1394 38 mohor
// Signals used for various purposes
1395 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1396 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1397
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1398
 
1399
 
1400
 
1401 39 mohor
// Generating delayed signals
1402 40 mohor
always @ (posedge MTxClk or posedge Reset)
1403 38 mohor
begin
1404 40 mohor
  if(Reset)
1405 39 mohor
    begin
1406
      TxAbort_q      <=#Tp 1'b0;
1407
      TxRetry_q      <=#Tp 1'b0;
1408
      TxUsedData_q   <=#Tp 1'b0;
1409
    end
1410 38 mohor
  else
1411 39 mohor
    begin
1412
      TxAbort_q      <=#Tp TxAbort;
1413
      TxRetry_q      <=#Tp TxRetry;
1414
      TxUsedData_q   <=#Tp TxUsedData;
1415
    end
1416 38 mohor
end
1417
 
1418
// Generating delayed signals
1419 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1420 38 mohor
begin
1421 40 mohor
  if(Reset)
1422 38 mohor
    begin
1423 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1424
      TxAbort_wb_q  <=#Tp 1'b0;
1425 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1426 38 mohor
    end
1427
  else
1428
    begin
1429 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1430
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1431 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1432 38 mohor
    end
1433
end
1434
 
1435
 
1436 219 mohor
reg TxAbortPacketBlocked;
1437
always @ (posedge WB_CLK_I or posedge Reset)
1438
begin
1439
  if(Reset)
1440
    TxAbortPacket <=#Tp 1'b0;
1441
  else
1442 278 mohor
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
1443
     TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
1444 219 mohor
    TxAbortPacket <=#Tp 1'b1;
1445
  else
1446
    TxAbortPacket <=#Tp 1'b0;
1447
end
1448
 
1449
 
1450
always @ (posedge WB_CLK_I or posedge Reset)
1451
begin
1452
  if(Reset)
1453 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1454
  else
1455 272 tadejm
  if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
1456
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1457
  else
1458 278 mohor
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
1459
     TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
1460 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b1;
1461
end
1462
 
1463
 
1464
always @ (posedge WB_CLK_I or posedge Reset)
1465
begin
1466
  if(Reset)
1467 219 mohor
    TxAbortPacketBlocked <=#Tp 1'b0;
1468
  else
1469 280 mohor
  if(!TxAbort_wb & TxAbort_wb_q)
1470
    TxAbortPacketBlocked <=#Tp 1'b0;
1471
  else
1472 219 mohor
  if(TxAbortPacket)
1473
    TxAbortPacketBlocked <=#Tp 1'b1;
1474
end
1475
 
1476
 
1477
reg TxRetryPacketBlocked;
1478
always @ (posedge WB_CLK_I or posedge Reset)
1479
begin
1480
  if(Reset)
1481
    TxRetryPacket <=#Tp 1'b0;
1482
  else
1483 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1484
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1485 219 mohor
    TxRetryPacket <=#Tp 1'b1;
1486
  else
1487
    TxRetryPacket <=#Tp 1'b0;
1488
end
1489
 
1490
 
1491
always @ (posedge WB_CLK_I or posedge Reset)
1492
begin
1493
  if(Reset)
1494 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1495
  else
1496 272 tadejm
  if(StartTxBDRead)
1497
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1498
  else
1499 278 mohor
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1500
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1501 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b1;
1502
end
1503
 
1504
 
1505
always @ (posedge WB_CLK_I or posedge Reset)
1506
begin
1507
  if(Reset)
1508 219 mohor
    TxRetryPacketBlocked <=#Tp 1'b0;
1509
  else
1510 280 mohor
  if(!TxRetry_wb & TxRetry_wb_q)
1511
    TxRetryPacketBlocked <=#Tp 1'b0;
1512
  else
1513 219 mohor
  if(TxRetryPacket)
1514
    TxRetryPacketBlocked <=#Tp 1'b1;
1515
end
1516
 
1517
 
1518 221 mohor
reg TxDonePacketBlocked;
1519
always @ (posedge WB_CLK_I or posedge Reset)
1520
begin
1521
  if(Reset)
1522
    TxDonePacket <=#Tp 1'b0;
1523
  else
1524 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
1525
     TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1526 221 mohor
    TxDonePacket <=#Tp 1'b1;
1527
  else
1528
    TxDonePacket <=#Tp 1'b0;
1529
end
1530
 
1531
 
1532
always @ (posedge WB_CLK_I or posedge Reset)
1533
begin
1534
  if(Reset)
1535
    TxDonePacket_NotCleared <=#Tp 1'b0;
1536
  else
1537 272 tadejm
  if(TxEn & TxEn_q & TxDonePacket_NotCleared)
1538
    TxDonePacket_NotCleared <=#Tp 1'b0;
1539
  else
1540 278 mohor
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) |
1541
     TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
1542 221 mohor
    TxDonePacket_NotCleared <=#Tp 1'b1;
1543
end
1544
 
1545
 
1546
always @ (posedge WB_CLK_I or posedge Reset)
1547
begin
1548
  if(Reset)
1549
    TxDonePacketBlocked <=#Tp 1'b0;
1550
  else
1551 280 mohor
  if(!TxDone_wb & TxDone_wb_q)
1552
    TxDonePacketBlocked <=#Tp 1'b0;
1553
  else
1554 221 mohor
  if(TxDonePacket)
1555
    TxDonePacketBlocked <=#Tp 1'b1;
1556
end
1557
 
1558
 
1559 38 mohor
// Indication of the last word
1560 40 mohor
always @ (posedge MTxClk or posedge Reset)
1561 38 mohor
begin
1562 40 mohor
  if(Reset)
1563 38 mohor
    LastWord <=#Tp 1'b0;
1564
  else
1565
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1566
    LastWord <=#Tp 1'b0;
1567
  else
1568
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1569 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1570 38 mohor
end
1571
 
1572
 
1573
// Tx end frame generation
1574 40 mohor
always @ (posedge MTxClk or posedge Reset)
1575 38 mohor
begin
1576 40 mohor
  if(Reset)
1577 38 mohor
    TxEndFrm <=#Tp 1'b0;
1578
  else
1579 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1580 38 mohor
    TxEndFrm <=#Tp 1'b0;
1581
  else
1582
  if(Flop & LastWord)
1583
    begin
1584 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1585 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1586
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1587
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1588
 
1589
        default : TxEndFrm <=#Tp 1'b0;
1590
      endcase
1591
    end
1592
end
1593
 
1594
 
1595
// Tx data selection (latching)
1596 40 mohor
always @ (posedge MTxClk or posedge Reset)
1597 38 mohor
begin
1598 40 mohor
  if(Reset)
1599 96 mohor
    TxData <=#Tp 0;
1600 38 mohor
  else
1601 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1602 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1603 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1604
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1605
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1606
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1607
    endcase
1608 38 mohor
  else
1609 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1610 96 mohor
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1611
  else
1612 38 mohor
  if(TxUsedData & Flop)
1613
    begin
1614 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1615 226 tadejm
 
1616 82 mohor
        1 : TxData <=#Tp TxDataLatched[23:16];
1617
        2 : TxData <=#Tp TxDataLatched[15:8];
1618
        3 : TxData <=#Tp TxDataLatched[7:0];
1619 38 mohor
      endcase
1620
    end
1621
end
1622
 
1623
 
1624
// Latching tx data
1625 40 mohor
always @ (posedge MTxClk or posedge Reset)
1626 38 mohor
begin
1627 40 mohor
  if(Reset)
1628 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1629
  else
1630 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1631 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1632 38 mohor
end
1633
 
1634
 
1635
// Tx under run
1636 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1637 38 mohor
begin
1638 40 mohor
  if(Reset)
1639 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1640 38 mohor
  else
1641 39 mohor
  if(TxAbortPulse)
1642 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1643
  else
1644
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1645
    TxUnderRun_wb <=#Tp 1'b1;
1646
end
1647
 
1648
 
1649 159 mohor
reg TxUnderRun_sync1;
1650
 
1651 60 mohor
// Tx under run
1652
always @ (posedge MTxClk or posedge Reset)
1653
begin
1654
  if(Reset)
1655 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b0;
1656 43 mohor
  else
1657 60 mohor
  if(TxUnderRun_wb)
1658 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b1;
1659 60 mohor
  else
1660 159 mohor
  if(BlockingTxStatusWrite_sync2)
1661
    TxUnderRun_sync1 <=#Tp 1'b0;
1662
end
1663
 
1664
// Tx under run
1665
always @ (posedge MTxClk or posedge Reset)
1666
begin
1667
  if(Reset)
1668 60 mohor
    TxUnderRun <=#Tp 1'b0;
1669 159 mohor
  else
1670
  if(BlockingTxStatusWrite_sync2)
1671
    TxUnderRun <=#Tp 1'b0;
1672
  else
1673
  if(TxUnderRun_sync1)
1674
    TxUnderRun <=#Tp 1'b1;
1675 38 mohor
end
1676
 
1677
 
1678
// Tx Byte counter
1679 40 mohor
always @ (posedge MTxClk or posedge Reset)
1680 38 mohor
begin
1681 40 mohor
  if(Reset)
1682 38 mohor
    TxByteCnt <=#Tp 2'h0;
1683
  else
1684
  if(TxAbort_q | TxRetry_q)
1685
    TxByteCnt <=#Tp 2'h0;
1686
  else
1687
  if(TxStartFrm & ~TxUsedData)
1688 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1689 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1690
      2'h1 : TxByteCnt <=#Tp 2'h2;
1691
      2'h2 : TxByteCnt <=#Tp 2'h3;
1692
      2'h3 : TxByteCnt <=#Tp 2'h0;
1693
    endcase
1694 38 mohor
  else
1695
  if(TxUsedData & Flop)
1696 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1697 38 mohor
end
1698
 
1699 39 mohor
 
1700 150 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1701
reg ReadTxDataFromFifo_sync1;
1702
reg ReadTxDataFromFifo_sync2;
1703
reg ReadTxDataFromFifo_sync3;
1704
reg ReadTxDataFromFifo_syncb1;
1705
reg ReadTxDataFromFifo_syncb2;
1706
reg ReadTxDataFromFifo_syncb3;
1707
 
1708
 
1709
always @ (posedge MTxClk or posedge Reset)
1710
begin
1711
  if(Reset)
1712
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1713
  else
1714 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1715 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1716 150 mohor
  else
1717
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1718
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1719 38 mohor
end
1720
 
1721 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1722 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1723 38 mohor
begin
1724 40 mohor
  if(Reset)
1725 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1726 38 mohor
  else
1727 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1728
end
1729 38 mohor
 
1730 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1731 38 mohor
begin
1732 40 mohor
  if(Reset)
1733 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1734 38 mohor
  else
1735 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1736 38 mohor
end
1737
 
1738 40 mohor
always @ (posedge MTxClk or posedge Reset)
1739 38 mohor
begin
1740 40 mohor
  if(Reset)
1741 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1742 38 mohor
  else
1743 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1744 38 mohor
end
1745
 
1746 40 mohor
always @ (posedge MTxClk or posedge Reset)
1747 38 mohor
begin
1748 40 mohor
  if(Reset)
1749 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1750 38 mohor
  else
1751 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1752 38 mohor
end
1753
 
1754 150 mohor
always @ (posedge MTxClk or posedge Reset)
1755
begin
1756
  if(Reset)
1757
    ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
1758
  else
1759
    ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
1760
end
1761
 
1762 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1763 38 mohor
begin
1764 40 mohor
  if(Reset)
1765 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1766 38 mohor
  else
1767 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1768 38 mohor
end
1769
 
1770 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1771
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1772 38 mohor
 
1773
 
1774 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1775 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1776 38 mohor
begin
1777 40 mohor
  if(Reset)
1778 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1779 38 mohor
  else
1780 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1781 38 mohor
end
1782
 
1783 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1784 38 mohor
begin
1785 40 mohor
  if(Reset)
1786 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1787 38 mohor
  else
1788 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1789 38 mohor
end
1790
 
1791
 
1792 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1793 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1794 38 mohor
begin
1795 40 mohor
  if(Reset)
1796 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1797 38 mohor
  else
1798 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1799 38 mohor
end
1800
 
1801 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1802 38 mohor
begin
1803 40 mohor
  if(Reset)
1804 39 mohor
    TxDone_wb <=#Tp 1'b0;
1805 38 mohor
  else
1806 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1807 38 mohor
end
1808
 
1809 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1810 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1811 38 mohor
begin
1812 40 mohor
  if(Reset)
1813 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1814 38 mohor
  else
1815 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1816 38 mohor
end
1817
 
1818 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1819 38 mohor
begin
1820 40 mohor
  if(Reset)
1821 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1822
  else
1823 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1824 38 mohor
end
1825
 
1826
 
1827 150 mohor
reg RxAbortSync1;
1828
reg RxAbortSync2;
1829
reg RxAbortSync3;
1830
reg RxAbortSync4;
1831
reg RxAbortSyncb1;
1832
reg RxAbortSyncb2;
1833 39 mohor
 
1834 333 igorm
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 | r_RxEn & ~r_RxEn_q;
1835 150 mohor
 
1836 40 mohor
// Reading the Rx buffer descriptor
1837
always @ (posedge WB_CLK_I or posedge Reset)
1838
begin
1839
  if(Reset)
1840 333 igorm
    RxBDRead <=#Tp 1'b0;
1841 40 mohor
  else
1842 166 mohor
  if(StartRxBDRead & ~RxReady)
1843 40 mohor
    RxBDRead <=#Tp 1'b1;
1844
  else
1845
  if(RxBDReady)
1846
    RxBDRead <=#Tp 1'b0;
1847
end
1848 39 mohor
 
1849
 
1850 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1851
// written to the previous one.
1852
 
1853
// Latching READY status of the Rx buffer descriptor
1854 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1855 38 mohor
begin
1856 40 mohor
  if(Reset)
1857 38 mohor
    RxBDReady <=#Tp 1'b0;
1858
  else
1859 166 mohor
  if(RxPointerRead)
1860 150 mohor
    RxBDReady <=#Tp 1'b0;
1861
  else
1862 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1863
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1864 38 mohor
end
1865
 
1866 40 mohor
// Latching Rx buffer descriptor status
1867
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1868
always @ (posedge WB_CLK_I or posedge Reset)
1869 38 mohor
begin
1870 40 mohor
  if(Reset)
1871 60 mohor
    RxStatus <=#Tp 2'h0;
1872 38 mohor
  else
1873 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1874 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1875 38 mohor
end
1876
 
1877
 
1878 166 mohor
// RxReady generation
1879
always @ (posedge WB_CLK_I or posedge Reset)
1880
begin
1881
  if(Reset)
1882
    RxReady <=#Tp 1'b0;
1883
  else
1884 333 igorm
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)
1885 166 mohor
    RxReady <=#Tp 1'b0;
1886
  else
1887
  if(RxEn & RxEn_q & RxPointerRead)
1888
    RxReady <=#Tp 1'b1;
1889
end
1890 38 mohor
 
1891
 
1892 40 mohor
// Reading Rx BD pointer
1893
 
1894
 
1895
assign StartRxPointerRead = RxBDRead & RxBDReady;
1896
 
1897
// Reading Tx BD Pointer
1898
always @ (posedge WB_CLK_I or posedge Reset)
1899 38 mohor
begin
1900 40 mohor
  if(Reset)
1901
    RxPointerRead <=#Tp 1'b0;
1902 38 mohor
  else
1903 40 mohor
  if(StartRxPointerRead)
1904
    RxPointerRead <=#Tp 1'b1;
1905 38 mohor
  else
1906 166 mohor
  if(RxEn & RxEn_q)
1907 40 mohor
    RxPointerRead <=#Tp 1'b0;
1908 38 mohor
end
1909
 
1910 113 mohor
 
1911 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1912
always @ (posedge WB_CLK_I or posedge Reset)
1913
begin
1914
  if(Reset)
1915 159 mohor
    RxPointerMSB <=#Tp 30'h0;
1916 40 mohor
  else
1917
  if(RxEn & RxEn_q & RxPointerRead)
1918 159 mohor
    RxPointerMSB <=#Tp ram_do[31:2];
1919 40 mohor
  else
1920 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1921 329 igorm
      RxPointerMSB <=#Tp RxPointerMSB + 1'b1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1922 40 mohor
end
1923 38 mohor
 
1924
 
1925 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1926 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1927
begin
1928
  if(Reset)
1929 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp 0;
1930 96 mohor
  else
1931 159 mohor
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
1932
    RxPointerLSB_rst[1:0] <=#Tp 0;
1933 96 mohor
  else
1934
  if(RxEn & RxEn_q & RxPointerRead)
1935 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
1936 96 mohor
end
1937
 
1938
 
1939 159 mohor
always @ (RxPointerLSB_rst)
1940 96 mohor
begin
1941 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1942
    2'h0 : RxByteSel[3:0] = 4'hf;
1943
    2'h1 : RxByteSel[3:0] = 4'h7;
1944
    2'h2 : RxByteSel[3:0] = 4'h3;
1945
    2'h3 : RxByteSel[3:0] = 4'h1;
1946 96 mohor
  endcase
1947
end
1948
 
1949
 
1950
always @ (posedge WB_CLK_I or posedge Reset)
1951
begin
1952
  if(Reset)
1953 40 mohor
    RxEn_needed <=#Tp 1'b0;
1954 38 mohor
  else
1955 166 mohor
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1956 40 mohor
    RxEn_needed <=#Tp 1'b1;
1957 38 mohor
  else
1958 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1959
    RxEn_needed <=#Tp 1'b0;
1960 38 mohor
end
1961
 
1962
 
1963 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1964
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1965 38 mohor
 
1966 40 mohor
reg RxEnableWindow;
1967 38 mohor
 
1968
// Indicating that last byte is being reveived
1969 40 mohor
always @ (posedge MRxClk or posedge Reset)
1970 38 mohor
begin
1971 40 mohor
  if(Reset)
1972 38 mohor
    LastByteIn <=#Tp 1'b0;
1973
  else
1974 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1975 38 mohor
    LastByteIn <=#Tp 1'b0;
1976
  else
1977 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1978 38 mohor
    LastByteIn <=#Tp 1'b1;
1979
end
1980
 
1981 159 mohor
reg ShiftEnded_rck;
1982 40 mohor
reg ShiftEndedSync1;
1983
reg ShiftEndedSync2;
1984 118 mohor
reg ShiftEndedSync3;
1985
reg ShiftEndedSync_c1;
1986
reg ShiftEndedSync_c2;
1987
 
1988 40 mohor
wire StartShiftWillEnd;
1989 96 mohor
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1990 38 mohor
 
1991
// Indicating that data reception will end
1992 40 mohor
always @ (posedge MRxClk or posedge Reset)
1993 38 mohor
begin
1994 40 mohor
  if(Reset)
1995 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1996
  else
1997 159 mohor
  if(ShiftEnded_rck | RxAbort)
1998 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1999
  else
2000 40 mohor
  if(StartShiftWillEnd)
2001 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
2002
end
2003
 
2004
 
2005 40 mohor
 
2006 38 mohor
// Receive byte counter
2007 40 mohor
always @ (posedge MRxClk or posedge Reset)
2008 38 mohor
begin
2009 40 mohor
  if(Reset)
2010 38 mohor
    RxByteCnt <=#Tp 2'h0;
2011
  else
2012 159 mohor
  if(ShiftEnded_rck | RxAbort)
2013 38 mohor
    RxByteCnt <=#Tp 2'h0;
2014 97 lampret
  else
2015 166 mohor
  if(RxValid & RxStartFrm & RxReady)
2016 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2017 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
2018
      2'h1 : RxByteCnt <=#Tp 2'h2;
2019
      2'h2 : RxByteCnt <=#Tp 2'h3;
2020
      2'h3 : RxByteCnt <=#Tp 2'h0;
2021
    endcase
2022 38 mohor
  else
2023 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
2024 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
2025 38 mohor
end
2026
 
2027
 
2028
// Indicates how many bytes are valid within the last word
2029 40 mohor
always @ (posedge MRxClk or posedge Reset)
2030 38 mohor
begin
2031 40 mohor
  if(Reset)
2032 38 mohor
    RxValidBytes <=#Tp 2'h1;
2033
  else
2034 96 mohor
  if(RxValid & RxStartFrm)
2035 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2036 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
2037
      2'h1 : RxValidBytes <=#Tp 2'h2;
2038
      2'h2 : RxValidBytes <=#Tp 2'h3;
2039
      2'h3 : RxValidBytes <=#Tp 2'h0;
2040
    endcase
2041 38 mohor
  else
2042 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2043 329 igorm
    RxValidBytes <=#Tp RxValidBytes + 1'b1;
2044 38 mohor
end
2045
 
2046
 
2047 40 mohor
always @ (posedge MRxClk or posedge Reset)
2048 38 mohor
begin
2049 40 mohor
  if(Reset)
2050
    RxDataLatched1       <=#Tp 24'h0;
2051 38 mohor
  else
2052 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2053 96 mohor
    if(RxStartFrm)
2054 40 mohor
    begin
2055 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2056 96 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2057
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2058
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2059
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2060
      endcase
2061
    end
2062
    else if (RxEnableWindow)
2063
    begin
2064 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2065 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2066
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2067
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2068 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2069
      endcase
2070
    end
2071 38 mohor
end
2072
 
2073 40 mohor
wire SetWriteRxDataToFifo;
2074 38 mohor
 
2075 40 mohor
// Assembling data that will be written to the rx_fifo
2076
always @ (posedge MRxClk or posedge Reset)
2077 38 mohor
begin
2078 40 mohor
  if(Reset)
2079
    RxDataLatched2 <=#Tp 32'h0;
2080 38 mohor
  else
2081 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2082 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
2083 38 mohor
  else
2084 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2085 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2086 82 mohor
 
2087
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2088
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
2089
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
2090 40 mohor
    endcase
2091 38 mohor
end
2092
 
2093
 
2094 40 mohor
reg WriteRxDataToFifoSync1;
2095
reg WriteRxDataToFifoSync2;
2096 150 mohor
reg WriteRxDataToFifoSync3;
2097 38 mohor
 
2098
 
2099 40 mohor
// Indicating start of the reception process
2100 166 mohor
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
2101
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
2102
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
2103 38 mohor
 
2104 150 mohor
always @ (posedge MRxClk or posedge Reset)
2105
begin
2106
  if(Reset)
2107
    WriteRxDataToFifo <=#Tp 1'b0;
2108
  else
2109
  if(SetWriteRxDataToFifo & ~RxAbort)
2110
    WriteRxDataToFifo <=#Tp 1'b1;
2111
  else
2112
  if(WriteRxDataToFifoSync2 | RxAbort)
2113
    WriteRxDataToFifo <=#Tp 1'b0;
2114
end
2115 40 mohor
 
2116 150 mohor
 
2117
 
2118
always @ (posedge WB_CLK_I or posedge Reset)
2119
begin
2120
  if(Reset)
2121
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2122
  else
2123
  if(WriteRxDataToFifo)
2124
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
2125
  else
2126
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2127
end
2128
 
2129
always @ (posedge WB_CLK_I or posedge Reset)
2130
begin
2131
  if(Reset)
2132
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
2133
  else
2134
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
2135
end
2136
 
2137
always @ (posedge WB_CLK_I or posedge Reset)
2138
begin
2139
  if(Reset)
2140
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
2141
  else
2142
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
2143
end
2144
 
2145
wire WriteRxDataToFifo_wb;
2146
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
2147
 
2148
 
2149 90 mohor
reg LatchedRxStartFrm;
2150
reg SyncRxStartFrm;
2151
reg SyncRxStartFrm_q;
2152 150 mohor
reg SyncRxStartFrm_q2;
2153 90 mohor
wire RxFifoReset;
2154 40 mohor
 
2155 90 mohor
always @ (posedge MRxClk or posedge Reset)
2156
begin
2157
  if(Reset)
2158
    LatchedRxStartFrm <=#Tp 0;
2159
  else
2160 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2161 90 mohor
    LatchedRxStartFrm <=#Tp 1;
2162
  else
2163 150 mohor
  if(SyncRxStartFrm_q)
2164 90 mohor
    LatchedRxStartFrm <=#Tp 0;
2165
end
2166
 
2167
 
2168
always @ (posedge WB_CLK_I or posedge Reset)
2169
begin
2170
  if(Reset)
2171
    SyncRxStartFrm <=#Tp 0;
2172
  else
2173
  if(LatchedRxStartFrm)
2174
    SyncRxStartFrm <=#Tp 1;
2175
  else
2176
    SyncRxStartFrm <=#Tp 0;
2177
end
2178
 
2179
 
2180
always @ (posedge WB_CLK_I or posedge Reset)
2181
begin
2182
  if(Reset)
2183
    SyncRxStartFrm_q <=#Tp 0;
2184
  else
2185
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
2186
end
2187
 
2188 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2189
begin
2190
  if(Reset)
2191
    SyncRxStartFrm_q2 <=#Tp 0;
2192
  else
2193
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
2194
end
2195 90 mohor
 
2196
 
2197 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2198 90 mohor
 
2199 150 mohor
 
2200 219 mohor
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
2201 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
2202
         .clk(WB_CLK_I),                                .reset(Reset),
2203 219 mohor
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
2204 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
2205 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
2206 150 mohor
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
2207 88 mohor
        );
2208 40 mohor
 
2209 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2210
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2211 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2212 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2213 40 mohor
 
2214
 
2215
// Generation of the end-of-frame signal
2216
always @ (posedge MRxClk or posedge Reset)
2217 38 mohor
begin
2218 40 mohor
  if(Reset)
2219 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2220 38 mohor
  else
2221 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2222 159 mohor
    ShiftEnded_rck <=#Tp 1'b1;
2223 38 mohor
  else
2224 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2225 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2226 38 mohor
end
2227
 
2228 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2229
begin
2230
  if(Reset)
2231
    ShiftEndedSync1 <=#Tp 1'b0;
2232
  else
2233 159 mohor
    ShiftEndedSync1 <=#Tp ShiftEnded_rck;
2234 40 mohor
end
2235 38 mohor
 
2236 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2237 38 mohor
begin
2238 40 mohor
  if(Reset)
2239
    ShiftEndedSync2 <=#Tp 1'b0;
2240 38 mohor
  else
2241 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
2242 40 mohor
end
2243 38 mohor
 
2244 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2245
begin
2246
  if(Reset)
2247
    ShiftEndedSync3 <=#Tp 1'b0;
2248
  else
2249
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2250
    ShiftEndedSync3 <=#Tp 1'b1;
2251
  else
2252
  if(ShiftEnded)
2253
    ShiftEndedSync3 <=#Tp 1'b0;
2254
end
2255 38 mohor
 
2256 40 mohor
// Generation of the end-of-frame signal
2257
always @ (posedge WB_CLK_I or posedge Reset)
2258 38 mohor
begin
2259 40 mohor
  if(Reset)
2260
    ShiftEnded <=#Tp 1'b0;
2261 38 mohor
  else
2262 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2263 40 mohor
    ShiftEnded <=#Tp 1'b1;
2264 38 mohor
  else
2265 40 mohor
  if(RxStatusWrite)
2266
    ShiftEnded <=#Tp 1'b0;
2267 38 mohor
end
2268
 
2269 118 mohor
always @ (posedge MRxClk or posedge Reset)
2270
begin
2271
  if(Reset)
2272
    ShiftEndedSync_c1 <=#Tp 1'b0;
2273
  else
2274
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
2275
end
2276 38 mohor
 
2277 118 mohor
always @ (posedge MRxClk or posedge Reset)
2278
begin
2279
  if(Reset)
2280
    ShiftEndedSync_c2 <=#Tp 1'b0;
2281
  else
2282
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
2283
end
2284
 
2285 40 mohor
// Generation of the end-of-frame signal
2286
always @ (posedge MRxClk or posedge Reset)
2287 38 mohor
begin
2288 40 mohor
  if(Reset)
2289
    RxEnableWindow <=#Tp 1'b0;
2290 38 mohor
  else
2291 40 mohor
  if(RxStartFrm)
2292
    RxEnableWindow <=#Tp 1'b1;
2293 38 mohor
  else
2294 40 mohor
  if(RxEndFrm | RxAbort)
2295
    RxEnableWindow <=#Tp 1'b0;
2296 38 mohor
end
2297
 
2298
 
2299 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2300 38 mohor
begin
2301 40 mohor
  if(Reset)
2302
    RxAbortSync1 <=#Tp 1'b0;
2303 38 mohor
  else
2304 150 mohor
    RxAbortSync1 <=#Tp RxAbortLatched;
2305 40 mohor
end
2306
 
2307
always @ (posedge WB_CLK_I or posedge Reset)
2308
begin
2309
  if(Reset)
2310
    RxAbortSync2 <=#Tp 1'b0;
2311 38 mohor
  else
2312 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
2313 38 mohor
end
2314
 
2315 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2316
begin
2317
  if(Reset)
2318
    RxAbortSync3 <=#Tp 1'b0;
2319
  else
2320
    RxAbortSync3 <=#Tp RxAbortSync2;
2321
end
2322
 
2323
always @ (posedge WB_CLK_I or posedge Reset)
2324
begin
2325
  if(Reset)
2326
    RxAbortSync4 <=#Tp 1'b0;
2327
  else
2328
    RxAbortSync4 <=#Tp RxAbortSync3;
2329
end
2330
 
2331 40 mohor
always @ (posedge MRxClk or posedge Reset)
2332
begin
2333
  if(Reset)
2334
    RxAbortSyncb1 <=#Tp 1'b0;
2335
  else
2336
    RxAbortSyncb1 <=#Tp RxAbortSync2;
2337
end
2338 38 mohor
 
2339 40 mohor
always @ (posedge MRxClk or posedge Reset)
2340 38 mohor
begin
2341 40 mohor
  if(Reset)
2342
    RxAbortSyncb2 <=#Tp 1'b0;
2343 38 mohor
  else
2344 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
2345 38 mohor
end
2346
 
2347
 
2348 64 mohor
always @ (posedge MRxClk or posedge Reset)
2349
begin
2350
  if(Reset)
2351
    RxAbortLatched <=#Tp 1'b0;
2352
  else
2353 150 mohor
  if(RxAbortSyncb2)
2354
    RxAbortLatched <=#Tp 1'b0;
2355
  else
2356 64 mohor
  if(RxAbort)
2357
    RxAbortLatched <=#Tp 1'b1;
2358
end
2359 40 mohor
 
2360 64 mohor
 
2361 42 mohor
always @ (posedge MRxClk or posedge Reset)
2362
begin
2363
  if(Reset)
2364
    LatchedRxLength[15:0] <=#Tp 16'h0;
2365
  else
2366 150 mohor
  if(LoadRxStatus)
2367 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
2368
end
2369
 
2370
 
2371 261 mohor
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2372 42 mohor
 
2373
always @ (posedge MRxClk or posedge Reset)
2374
begin
2375
  if(Reset)
2376
    RxStatusInLatched <=#Tp 'h0;
2377
  else
2378 150 mohor
  if(LoadRxStatus)
2379 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
2380
end
2381
 
2382
 
2383 60 mohor
// Rx overrun
2384
always @ (posedge WB_CLK_I or posedge Reset)
2385
begin
2386
  if(Reset)
2387
    RxOverrun <=#Tp 1'b0;
2388
  else
2389
  if(RxStatusWrite)
2390
    RxOverrun <=#Tp 1'b0;
2391
  else
2392
  if(RxBufferFull & WriteRxDataToFifo_wb)
2393
    RxOverrun <=#Tp 1'b1;
2394
end
2395 48 mohor
 
2396 77 mohor
 
2397
 
2398
wire TxError;
2399
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2400
 
2401
wire RxError;
2402
 
2403 239 tadejm
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
2404 250 mohor
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
2405
// AddressMiss is identifying that a frame was received because of the promiscous
2406
// mode and is not an error
2407 239 tadejm
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
2408
 
2409 272 tadejm
 
2410
 
2411
reg RxStatusWriteLatched;
2412
reg RxStatusWriteLatched_sync1;
2413
reg RxStatusWriteLatched_sync2;
2414
reg RxStatusWriteLatched_syncb1;
2415
reg RxStatusWriteLatched_syncb2;
2416
 
2417
 
2418
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
2419
always @ (posedge WB_CLK_I or posedge Reset)
2420
begin
2421
  if(Reset)
2422
    RxStatusWriteLatched <=#Tp 1'b0;
2423
  else
2424
  if(RxStatusWriteLatched_syncb2)
2425
    RxStatusWriteLatched <=#Tp 1'b0;
2426
  else
2427
  if(RxStatusWrite)
2428
    RxStatusWriteLatched <=#Tp 1'b1;
2429
end
2430
 
2431
 
2432
always @ (posedge MRxClk or posedge Reset)
2433
begin
2434
  if(Reset)
2435
    begin
2436
      RxStatusWriteLatched_sync1 <=#Tp 1'b0;
2437
      RxStatusWriteLatched_sync2 <=#Tp 1'b0;
2438
    end
2439
  else
2440
    begin
2441
      RxStatusWriteLatched_sync1 <=#Tp RxStatusWriteLatched;
2442
      RxStatusWriteLatched_sync2 <=#Tp RxStatusWriteLatched_sync1;
2443
    end
2444
end
2445
 
2446
 
2447
always @ (posedge WB_CLK_I or posedge Reset)
2448
begin
2449
  if(Reset)
2450
    begin
2451
      RxStatusWriteLatched_syncb1 <=#Tp 1'b0;
2452
      RxStatusWriteLatched_syncb2 <=#Tp 1'b0;
2453
    end
2454
  else
2455
    begin
2456
      RxStatusWriteLatched_syncb1 <=#Tp RxStatusWriteLatched_sync2;
2457
      RxStatusWriteLatched_syncb2 <=#Tp RxStatusWriteLatched_syncb1;
2458
    end
2459
end
2460
 
2461
 
2462
 
2463 77 mohor
// Tx Done Interrupt
2464
always @ (posedge WB_CLK_I or posedge Reset)
2465
begin
2466
  if(Reset)
2467
    TxB_IRQ <=#Tp 1'b0;
2468
  else
2469
  if(TxStatusWrite & TxIRQEn)
2470
    TxB_IRQ <=#Tp ~TxError;
2471
  else
2472
    TxB_IRQ <=#Tp 1'b0;
2473
end
2474
 
2475
 
2476
// Tx Error Interrupt
2477
always @ (posedge WB_CLK_I or posedge Reset)
2478
begin
2479
  if(Reset)
2480
    TxE_IRQ <=#Tp 1'b0;
2481
  else
2482
  if(TxStatusWrite & TxIRQEn)
2483
    TxE_IRQ <=#Tp TxError;
2484
  else
2485
    TxE_IRQ <=#Tp 1'b0;
2486
end
2487
 
2488
 
2489
// Rx Done Interrupt
2490
always @ (posedge WB_CLK_I or posedge Reset)
2491
begin
2492
  if(Reset)
2493
    RxB_IRQ <=#Tp 1'b0;
2494
  else
2495 270 mohor
  if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
2496
    RxB_IRQ <=#Tp (~RxError);
2497 77 mohor
  else
2498
    RxB_IRQ <=#Tp 1'b0;
2499
end
2500
 
2501
 
2502
// Rx Error Interrupt
2503
always @ (posedge WB_CLK_I or posedge Reset)
2504
begin
2505
  if(Reset)
2506
    RxE_IRQ <=#Tp 1'b0;
2507
  else
2508 270 mohor
  if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
2509 77 mohor
    RxE_IRQ <=#Tp RxError;
2510
  else
2511
    RxE_IRQ <=#Tp 1'b0;
2512
end
2513
 
2514
 
2515 166 mohor
// Busy Interrupt
2516 77 mohor
 
2517 166 mohor
reg Busy_IRQ_rck;
2518
reg Busy_IRQ_sync1;
2519
reg Busy_IRQ_sync2;
2520
reg Busy_IRQ_sync3;
2521
reg Busy_IRQ_syncb1;
2522
reg Busy_IRQ_syncb2;
2523 77 mohor
 
2524
 
2525 166 mohor
always @ (posedge MRxClk or posedge Reset)
2526
begin
2527
  if(Reset)
2528
    Busy_IRQ_rck <=#Tp 1'b0;
2529
  else
2530
  if(RxValid & RxStartFrm & ~RxReady)
2531
    Busy_IRQ_rck <=#Tp 1'b1;
2532
  else
2533
  if(Busy_IRQ_syncb2)
2534
    Busy_IRQ_rck <=#Tp 1'b0;
2535
end
2536 77 mohor
 
2537 166 mohor
always @ (posedge WB_CLK_I)
2538
begin
2539
    Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
2540
    Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
2541
    Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
2542
end
2543
 
2544
always @ (posedge MRxClk)
2545
begin
2546
    Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
2547
    Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
2548
end
2549
 
2550
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
2551
 
2552
 
2553 60 mohor
 
2554
 
2555
 
2556 38 mohor
endmodule

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