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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 349

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 38 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 333 igorm
// Revision 1.57  2005/02/21 11:35:33  igorm
45
// Defer indication fixed.
46
//
47 329 igorm
// Revision 1.56  2004/04/30 10:30:00  igorm
48
// Accidently deleted line put back.
49
//
50 323 igorm
// Revision 1.55  2004/04/26 15:26:23  igorm
51
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
52
//   previous update of the core.
53
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
54
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
55
//   register. (thanks to Mathias and Torbjorn)
56
// - Multicast reception was fixed. Thanks to Ulrich Gries
57
//
58 321 igorm
// Revision 1.54  2003/11/12 18:24:59  tadejm
59
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
60
//
61 304 tadejm
// Revision 1.53  2003/10/17 07:46:17  markom
62
// mbist signals updated according to newest convention
63
//
64 302 markom
// Revision 1.52  2003/01/30 14:51:31  mohor
65
// Reset has priority in some flipflops.
66
//
67 280 mohor
// Revision 1.51  2003/01/30 13:36:22  mohor
68
// A new bug (entered with previous update) fixed. When abort occured sometimes
69
// data transmission was blocked.
70
//
71 278 mohor
// Revision 1.50  2003/01/22 13:49:26  tadejm
72
// When control packets were received, they were ignored in some cases.
73
//
74 272 tadejm
// Revision 1.49  2003/01/21 12:09:40  mohor
75
// When receiving normal data frame and RxFlow control was switched on, RXB
76
// interrupt was not set.
77
//
78 270 mohor
// Revision 1.48  2003/01/20 12:05:26  mohor
79
// When in full duplex, transmit was sometimes blocked. Fixed.
80
//
81 269 mohor
// Revision 1.47  2002/11/22 13:26:21  mohor
82
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
83
// anywhere. Removed.
84
//
85 264 mohor
// Revision 1.46  2002/11/22 01:57:06  mohor
86
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
87
// synchronized.
88
//
89 261 mohor
// Revision 1.45  2002/11/19 17:33:34  mohor
90
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
91
// that a frame was received because of the promiscous mode.
92
//
93 250 mohor
// Revision 1.44  2002/11/13 22:21:40  tadejm
94
// RxError is not generated when small frame reception is enabled and small
95
// frames are received.
96
//
97 239 tadejm
// Revision 1.43  2002/10/18 20:53:34  mohor
98
// case changed to casex.
99
//
100 229 mohor
// Revision 1.42  2002/10/18 17:04:20  tadejm
101
// Changed BIST scan signals.
102
//
103 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
104
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
105
//
106 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
107
// TxStatus is written after last access to the TX fifo is finished (in case of abort
108
// or retry). TxDone is fixed.
109
//
110 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
111
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
112
// TxDone and TxRetry are generated after the current WISHBONE access is
113
// finished.
114
//
115 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
116
// BIST added.
117
//
118 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
119
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
120
//
121 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
122
// Reception is possible after RxPointer is read and not after BD is read. For
123
// that reason RxBDReady is changed to RxReady.
124
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
125
// comes, interrupt is generated.
126
//
127 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
128
// Ethernet debug registers removed.
129
//
130 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
131
// Async reset for WB_ACK_O removed (when core was in reset, it was
132
// impossible to access BDs).
133
// RxPointers and TxPointers names changed to be more descriptive.
134
// TxUnderRun synchronized.
135
//
136 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
137
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
138
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
139
// was not used OK.
140
//
141 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
142
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
143
// need to multiply or devide any more.
144
//
145 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
146
// WriteRxDataToMemory signal changed so end of frame (when last word is
147
// written to fifo) is changed.
148
//
149 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
150
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
151
//
152 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
153
// ShiftEnded synchronization changed.
154
//
155 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
156
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
157
//
158 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
159
// RxPointer bug fixed.
160
//
161 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
162
// Previous bug wasn't succesfully removed. Now fixed.
163
//
164 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
165
// Master state machine had a bug when switching from master write to
166
// master read.
167
//
168 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
169
// m_wb_cyc_o signal released after every single transfer.
170
//
171 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
172
// Outputs registered. Reset changed for eth_wishbone module.
173
//
174 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
175
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
176
// bug fixed.
177
//
178 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
179
// Small typo fixed.
180
//
181 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
182
// Any address can be used for Tx and Rx BD pointers. Address does not need
183
// to be aligned.
184
//
185 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
186
// Comments in Slovene language removed.
187
//
188 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
189
// casex changed with case, fifo reset changed.
190
//
191 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
192
// rx_fifo was not always cleared ok. Fixed.
193
//
194 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
195
// Status was not latched correctly sometimes. Fixed.
196
//
197 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
198
// Big Endian problem when sending frames fixed.
199
//
200 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
201
// Byte ordering changed (Big Endian used). casex changed with case because
202
// Xilinx Foundation had problems. Tested in HW. It WORKS.
203
//
204 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
205
// Small fixes for external/internal DMA missmatches.
206
//
207 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
208
// Interrupts changed
209
//
210 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
211
// Status was not written correctly when frames were discarted because of
212
// address mismatch.
213
//
214 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
215
// RxStartFrm cleared when abort or retry comes.
216
//
217 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
218
// Changes that were lost when updating from 1.5 to 1.8 fixed.
219
//
220 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
221
// Addition  of new module eth_addrcheck.v
222
//
223
// Revision 1.7  2002/02/12 17:03:47  mohor
224
// RxOverRun added to statuses.
225
//
226
// Revision 1.6  2002/02/11 09:18:22  mohor
227
// Tx status is written back to the BD.
228
//
229 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
230
// Rx status is written back to the BD.
231
//
232 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
233
// non-DMA host interface added. Select the right configutation in eth_defines.
234
//
235 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
236
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
237
// MHz. Statuses, overrun, control frame transmission and reception still  need
238
// to be fixed.
239
//
240 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
241
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
242
// added.
243
//
244 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
245
// Initial version. Equals to eth_wishbonedma.v at this moment.
246 38 mohor
//
247
//
248
//
249
 
250
`include "eth_defines.v"
251
`include "timescale.v"
252
 
253
 
254
module eth_wishbone
255
   (
256
 
257
    // WISHBONE common
258 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
259 38 mohor
 
260
    // WISHBONE slave
261 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
262 40 mohor
    BDCs,
263 38 mohor
 
264 40 mohor
    Reset,
265
 
266 39 mohor
    // WISHBONE master
267
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
268
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
269
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
270
 
271 219 mohor
`ifdef ETH_WISHBONE_B3
272
    m_wb_cti_o, m_wb_bte_o,
273
`endif
274
 
275 38 mohor
    //TX
276 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
277 150 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
278 38 mohor
    PerPacketPad,
279
 
280
    //RX
281 272 tadejm
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
282 38 mohor
 
283
    // Register
284 321 igorm
    r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
285 38 mohor
 
286
    // Interrupts
287 150 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
288 42 mohor
 
289 60 mohor
    // Rx Status
290 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
291 250 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
292 261 mohor
    ReceivedPauseFrm,
293 60 mohor
 
294
    // Tx Status
295 329 igorm
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost
296 164 mohor
 
297 210 mohor
    // Bist
298
`ifdef ETH_BIST
299 227 tadejm
    ,
300
    // debug chain signals
301 302 markom
    mbist_si_i,       // bist scan serial in
302
    mbist_so_o,       // bist scan serial out
303
    mbist_ctrl_i        // bist chain shift control
304 210 mohor
`endif
305
 
306
 
307
 
308 38 mohor
                );
309
 
310
 
311
parameter Tp = 1;
312 349 olof
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
313
parameter TX_FIFO_DEPTH      = `ETH_TX_FIFO_DEPTH;
314
parameter TX_FIFO_CNT_WIDTH  = `ETH_TX_FIFO_CNT_WIDTH;
315
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
316
parameter RX_FIFO_DEPTH      = `ETH_RX_FIFO_DEPTH;
317
parameter RX_FIFO_CNT_WIDTH  = `ETH_RX_FIFO_CNT_WIDTH;
318 38 mohor
 
319 150 mohor
 
320 38 mohor
// WISHBONE common
321
input           WB_CLK_I;       // WISHBONE clock
322
input  [31:0]   WB_DAT_I;       // WISHBONE data input
323
output [31:0]   WB_DAT_O;       // WISHBONE data output
324
 
325
// WISHBONE slave
326
input   [9:2]   WB_ADR_I;       // WISHBONE address input
327
input           WB_WE_I;        // WISHBONE write enable input
328 304 tadejm
input   [3:0]   BDCs;           // Buffer descriptors are selected
329 38 mohor
output          WB_ACK_O;       // WISHBONE acknowledge output
330
 
331 39 mohor
// WISHBONE master
332 329 igorm
output  [29:0]  m_wb_adr_o;     // 
333 39 mohor
output   [3:0]  m_wb_sel_o;     // 
334
output          m_wb_we_o;      // 
335
output  [31:0]  m_wb_dat_o;     // 
336
output          m_wb_cyc_o;     // 
337
output          m_wb_stb_o;     // 
338
input   [31:0]  m_wb_dat_i;     // 
339
input           m_wb_ack_i;     // 
340
input           m_wb_err_i;     // 
341
 
342 219 mohor
`ifdef ETH_WISHBONE_B3
343
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
344
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
345
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
346
`endif
347
 
348 40 mohor
input           Reset;       // Reset signal
349 39 mohor
 
350 60 mohor
// Rx Status signals
351 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
352
input           LatchedCrcError;  // CRC error
353
input           RxLateCollision;  // Late collision occured while receiving frame
354
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
355
input           DribbleNibble;    // Extra nibble received
356
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
357
input    [15:0] RxLength;         // Length of the incoming frame
358
input           LoadRxStatus;     // Rx status was loaded
359 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
360 250 mohor
input           AddressMiss;      // When a packet is received AddressMiss status is written to the Rx BD
361 261 mohor
input           r_RxFlow;
362 270 mohor
input           r_PassAll;
363 261 mohor
input           ReceivedPauseFrm;
364 39 mohor
 
365 60 mohor
// Tx Status signals
366
input     [3:0] RetryCntLatched;  // Latched Retry Counter
367
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
368
input           LateCollLatched;  // Late collision occured
369
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
370 329 igorm
output          RstDeferLatched;
371 60 mohor
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
372
 
373 38 mohor
// Tx
374
input           MTxClk;         // Transmit clock (from PHY)
375
input           TxUsedData;     // Transmit packet used data
376
input           TxRetry;        // Transmit packet retry
377
input           TxAbort;        // Transmit packet abort
378
input           TxDone;         // Transmission ended
379
output          TxStartFrm;     // Transmit packet start frame
380
output          TxEndFrm;       // Transmit packet end frame
381
output  [7:0]   TxData;         // Transmit packet data byte
382
output          TxUnderRun;     // Transmit packet under-run
383
output          PerPacketCrcEn; // Per packet crc enable
384
output          PerPacketPad;   // Per packet pading
385
 
386
// Rx
387
input           MRxClk;         // Receive clock (from PHY)
388
input   [7:0]   RxData;         // Received data byte (from PHY)
389
input           RxValid;        // 
390
input           RxStartFrm;     // 
391
input           RxEndFrm;       // 
392 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
393 272 tadejm
output          RxStatusWriteLatched_sync2;
394 38 mohor
 
395
//Register
396
input           r_TxEn;         // Transmit enable
397
input           r_RxEn;         // Receive enable
398
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
399
 
400
// Interrupts
401
output TxB_IRQ;
402
output TxE_IRQ;
403
output RxB_IRQ;
404 77 mohor
output RxE_IRQ;
405 38 mohor
output Busy_IRQ;
406
 
407 77 mohor
 
408 210 mohor
// Bist
409
`ifdef ETH_BIST
410 302 markom
input   mbist_si_i;       // bist scan serial in
411
output  mbist_so_o;       // bist scan serial out
412
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
413 210 mohor
`endif
414
 
415 77 mohor
reg TxB_IRQ;
416
reg TxE_IRQ;
417
reg RxB_IRQ;
418
reg RxE_IRQ;
419
 
420 38 mohor
reg             TxStartFrm;
421
reg             TxEndFrm;
422
reg     [7:0]   TxData;
423
 
424
reg             TxUnderRun;
425 60 mohor
reg             TxUnderRun_wb;
426 38 mohor
 
427
reg             TxBDRead;
428 39 mohor
wire            TxStatusWrite;
429 38 mohor
 
430
reg     [1:0]   TxValidBytesLatched;
431
 
432
reg    [15:0]   TxLength;
433 60 mohor
reg    [15:0]   LatchedTxLength;
434
reg   [14:11]   TxStatus;
435 38 mohor
 
436 60 mohor
reg   [14:13]   RxStatus;
437 38 mohor
 
438
reg             TxStartFrm_wb;
439
reg             TxRetry_wb;
440 39 mohor
reg             TxAbort_wb;
441 38 mohor
reg             TxDone_wb;
442
 
443
reg             TxDone_wb_q;
444
reg             TxAbort_wb_q;
445 39 mohor
reg             TxRetry_wb_q;
446 219 mohor
reg             TxRetryPacket;
447 221 mohor
reg             TxRetryPacket_NotCleared;
448
reg             TxDonePacket;
449
reg             TxDonePacket_NotCleared;
450 219 mohor
reg             TxAbortPacket;
451 221 mohor
reg             TxAbortPacket_NotCleared;
452 38 mohor
reg             RxBDReady;
453 166 mohor
reg             RxReady;
454 38 mohor
reg             TxBDReady;
455
 
456
reg             RxBDRead;
457
 
458
reg    [31:0]   TxDataLatched;
459
reg     [1:0]   TxByteCnt;
460
reg             LastWord;
461 39 mohor
reg             ReadTxDataFromFifo_tck;
462 38 mohor
 
463
reg             BlockingTxStatusWrite;
464
reg             BlockingTxBDRead;
465
 
466 40 mohor
reg             Flop;
467 38 mohor
 
468 329 igorm
reg     [7:1]   TxBDAddress;
469
reg     [7:1]   RxBDAddress;
470 38 mohor
 
471
reg             TxRetrySync1;
472
reg             TxAbortSync1;
473 39 mohor
reg             TxDoneSync1;
474 38 mohor
 
475
reg             TxAbort_q;
476
reg             TxRetry_q;
477
reg             TxUsedData_q;
478
 
479
reg    [31:0]   RxDataLatched2;
480 82 mohor
 
481
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
482
 
483 38 mohor
reg     [1:0]   RxValidBytes;
484
reg     [1:0]   RxByteCnt;
485
reg             LastByteIn;
486
reg             ShiftWillEnd;
487
 
488 40 mohor
reg             WriteRxDataToFifo;
489 42 mohor
reg    [15:0]   LatchedRxLength;
490 64 mohor
reg             RxAbortLatched;
491 38 mohor
 
492 40 mohor
reg             ShiftEnded;
493 60 mohor
reg             RxOverrun;
494 38 mohor
 
495 304 tadejm
reg     [3:0]   BDWrite;                    // BD Write Enable for access from WISHBONE side
496 40 mohor
reg             BDRead;                     // BD Read access from WISHBONE side
497 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
498
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
499 38 mohor
 
500 39 mohor
reg             TxEndFrm_wb;
501 38 mohor
 
502 39 mohor
wire            TxRetryPulse;
503 38 mohor
wire            TxDonePulse;
504
wire            TxAbortPulse;
505
 
506
wire            StartRxBDRead;
507
 
508
wire            StartTxBDRead;
509
 
510
wire            TxIRQEn;
511
wire            WrapTxStatusBit;
512
 
513 77 mohor
wire            RxIRQEn;
514 38 mohor
wire            WrapRxStatusBit;
515
 
516
wire    [1:0]   TxValidBytes;
517
 
518 329 igorm
wire    [7:1]   TempTxBDAddress;
519
wire    [7:1]   TempRxBDAddress;
520 38 mohor
 
521 272 tadejm
wire            RxStatusWrite;
522 329 igorm
wire            RxBufferFull;
523
wire            RxBufferAlmostEmpty;
524
wire            RxBufferEmpty;
525 272 tadejm
 
526 106 mohor
reg             WB_ACK_O;
527 38 mohor
 
528 261 mohor
wire    [8:0]   RxStatusIn;
529
reg     [8:0]   RxStatusInLatched;
530 42 mohor
 
531 39 mohor
reg WbEn, WbEn_q;
532
reg RxEn, RxEn_q;
533
reg TxEn, TxEn_q;
534 321 igorm
reg r_TxEn_q;
535
reg r_RxEn_q;
536 38 mohor
 
537 39 mohor
wire ram_ce;
538 304 tadejm
wire [3:0]  ram_we;
539 39 mohor
wire ram_oe;
540
reg [7:0]   ram_addr;
541
reg [31:0]  ram_di;
542
wire [31:0] ram_do;
543 38 mohor
 
544 39 mohor
wire StartTxPointerRead;
545
reg  TxPointerRead;
546
reg TxEn_needed;
547 40 mohor
reg RxEn_needed;
548 38 mohor
 
549 40 mohor
wire StartRxPointerRead;
550
reg RxPointerRead;
551 38 mohor
 
552 219 mohor
`ifdef ETH_WISHBONE_B3
553
assign m_wb_bte_o = 2'b00;    // Linear burst
554
`endif
555 39 mohor
 
556 329 igorm
assign m_wb_stb_o = m_wb_cyc_o;
557 219 mohor
 
558 159 mohor
always @ (posedge WB_CLK_I)
559 40 mohor
begin
560 304 tadejm
  WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
561 40 mohor
end
562 39 mohor
 
563 106 mohor
assign WB_DAT_O = ram_do;
564 39 mohor
 
565 41 mohor
// Generic synchronous single-port RAM interface
566 119 mohor
eth_spram_256x32 bd_ram (
567 226 tadejm
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
568 210 mohor
`ifdef ETH_BIST
569 227 tadejm
  ,
570 302 markom
  .mbist_si_i       (mbist_si_i),
571
  .mbist_so_o       (mbist_so_o),
572
  .mbist_ctrl_i       (mbist_ctrl_i)
573 210 mohor
`endif
574 39 mohor
);
575 41 mohor
 
576 39 mohor
assign ram_ce = 1'b1;
577 304 tadejm
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | {4{(TxStatusWrite | RxStatusWrite)}};
578 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
579 39 mohor
 
580
 
581 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
582 38 mohor
begin
583 40 mohor
  if(Reset)
584 39 mohor
    TxEn_needed <=#Tp 1'b0;
585 38 mohor
  else
586 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
587 39 mohor
    TxEn_needed <=#Tp 1'b1;
588
  else
589
  if(TxPointerRead & TxEn & TxEn_q)
590
    TxEn_needed <=#Tp 1'b0;
591 38 mohor
end
592
 
593 39 mohor
// Enabling access to the RAM for three devices.
594 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
595 39 mohor
begin
596 40 mohor
  if(Reset)
597 39 mohor
    begin
598
      WbEn <=#Tp 1'b1;
599
      RxEn <=#Tp 1'b0;
600
      TxEn <=#Tp 1'b0;
601
      ram_addr <=#Tp 8'h0;
602
      ram_di <=#Tp 32'h0;
603 77 mohor
      BDRead <=#Tp 1'b0;
604
      BDWrite <=#Tp 1'b0;
605 39 mohor
    end
606
  else
607
    begin
608
      // Switching between three stages depends on enable signals
609 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
610
        5'b100_10, 5'b100_11 :
611 39 mohor
          begin
612
            WbEn <=#Tp 1'b0;
613
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
614
            TxEn <=#Tp 1'b0;
615 329 igorm
            ram_addr <=#Tp {RxBDAddress, RxPointerRead};
616 39 mohor
            ram_di <=#Tp RxBDDataIn;
617
          end
618
        5'b100_01 :
619
          begin
620
            WbEn <=#Tp 1'b0;
621
            RxEn <=#Tp 1'b0;
622
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
623 329 igorm
            ram_addr <=#Tp {TxBDAddress, TxPointerRead};
624 39 mohor
            ram_di <=#Tp TxBDDataIn;
625
          end
626 90 mohor
        5'b010_00, 5'b010_10 :
627 39 mohor
          begin
628
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
629
            RxEn <=#Tp 1'b0;
630
            TxEn <=#Tp 1'b0;
631
            ram_addr <=#Tp WB_ADR_I[9:2];
632
            ram_di <=#Tp WB_DAT_I;
633 304 tadejm
            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
634
            BDRead <=#Tp (|BDCs) & ~WB_WE_I;
635 39 mohor
          end
636 90 mohor
        5'b010_01, 5'b010_11 :
637 39 mohor
          begin
638
            WbEn <=#Tp 1'b0;
639
            RxEn <=#Tp 1'b0;
640
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
641 329 igorm
            ram_addr <=#Tp {TxBDAddress, TxPointerRead};
642 39 mohor
            ram_di <=#Tp TxBDDataIn;
643
          end
644 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
645 39 mohor
          begin
646
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
647
            RxEn <=#Tp 1'b0;
648
            TxEn <=#Tp 1'b0;
649
            ram_addr <=#Tp WB_ADR_I[9:2];
650
            ram_di <=#Tp WB_DAT_I;
651 304 tadejm
            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
652
            BDRead <=#Tp (|BDCs) & ~WB_WE_I;
653 39 mohor
          end
654
        5'b100_00 :
655
          begin
656
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
657
          end
658
        5'b000_00 :
659
          begin
660
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
661
            RxEn <=#Tp 1'b0;
662
            TxEn <=#Tp 1'b0;
663
            ram_addr <=#Tp WB_ADR_I[9:2];
664
            ram_di <=#Tp WB_DAT_I;
665 304 tadejm
            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
666
            BDRead <=#Tp (|BDCs) & ~WB_WE_I;
667 39 mohor
          end
668
      endcase
669
    end
670
end
671
 
672
 
673
// Delayed stage signals
674 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
675 39 mohor
begin
676 40 mohor
  if(Reset)
677 39 mohor
    begin
678
      WbEn_q <=#Tp 1'b0;
679
      RxEn_q <=#Tp 1'b0;
680
      TxEn_q <=#Tp 1'b0;
681 321 igorm
      r_TxEn_q <=#Tp 1'b0;
682
      r_RxEn_q <=#Tp 1'b0;
683 39 mohor
    end
684
  else
685
    begin
686
      WbEn_q <=#Tp WbEn;
687
      RxEn_q <=#Tp RxEn;
688
      TxEn_q <=#Tp TxEn;
689 323 igorm
      r_TxEn_q <=#Tp r_TxEn;
690 321 igorm
      r_RxEn_q <=#Tp r_RxEn;
691 39 mohor
    end
692
end
693
 
694 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
695 40 mohor
always @ (posedge MTxClk or posedge Reset)
696 38 mohor
begin
697 40 mohor
  if(Reset)
698 38 mohor
    Flop <=#Tp 1'b0;
699
  else
700
  if(TxDone | TxAbort | TxRetry_q)
701
    Flop <=#Tp 1'b0;
702
  else
703
  if(TxUsedData)
704
    Flop <=#Tp ~Flop;
705
end
706
 
707 39 mohor
wire ResetTxBDReady;
708
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
709 38 mohor
 
710
// Latching READY status of the Tx buffer descriptor
711 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
712 38 mohor
begin
713 40 mohor
  if(Reset)
714 38 mohor
    TxBDReady <=#Tp 1'b0;
715
  else
716 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
717
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
718
  else                                                // Only packets larger then 4 bytes are transmitted.
719 39 mohor
  if(ResetTxBDReady)
720 38 mohor
    TxBDReady <=#Tp 1'b0;
721
end
722
 
723
 
724 39 mohor
// Reading the Tx buffer descriptor
725 221 mohor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
726 39 mohor
 
727 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
728 38 mohor
begin
729 40 mohor
  if(Reset)
730 39 mohor
    TxBDRead <=#Tp 1'b1;
731 38 mohor
  else
732 110 mohor
  if(StartTxBDRead)
733 39 mohor
    TxBDRead <=#Tp 1'b1;
734 38 mohor
  else
735 39 mohor
  if(TxBDReady)
736
    TxBDRead <=#Tp 1'b0;
737 38 mohor
end
738
 
739
 
740 39 mohor
// Reading Tx BD pointer
741
assign StartTxPointerRead = TxBDRead & TxBDReady;
742 38 mohor
 
743 39 mohor
// Reading Tx BD Pointer
744 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
745 38 mohor
begin
746 40 mohor
  if(Reset)
747 39 mohor
    TxPointerRead <=#Tp 1'b0;
748 38 mohor
  else
749 39 mohor
  if(StartTxPointerRead)
750
    TxPointerRead <=#Tp 1'b1;
751 38 mohor
  else
752 39 mohor
  if(TxEn_q)
753
    TxPointerRead <=#Tp 1'b0;
754 38 mohor
end
755
 
756
 
757 39 mohor
// Writing status back to the Tx buffer descriptor
758 221 mohor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
759 38 mohor
 
760
 
761
 
762 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
763 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
764 38 mohor
begin
765 40 mohor
  if(Reset)
766 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
767 38 mohor
  else
768 272 tadejm
  if(~TxDone_wb & ~TxAbort_wb)
769
    BlockingTxStatusWrite <=#Tp 1'b0;
770
  else
771 39 mohor
  if(TxStatusWrite)
772
    BlockingTxStatusWrite <=#Tp 1'b1;
773 38 mohor
end
774
 
775
 
776 159 mohor
reg BlockingTxStatusWrite_sync1;
777
reg BlockingTxStatusWrite_sync2;
778 329 igorm
reg BlockingTxStatusWrite_sync3;
779 159 mohor
 
780
// Synchronizing BlockingTxStatusWrite to MTxClk
781
always @ (posedge MTxClk or posedge Reset)
782
begin
783
  if(Reset)
784
    BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
785
  else
786
    BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
787
end
788
 
789
// Synchronizing BlockingTxStatusWrite to MTxClk
790
always @ (posedge MTxClk or posedge Reset)
791
begin
792
  if(Reset)
793
    BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
794
  else
795
    BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
796
end
797
 
798 329 igorm
// Synchronizing BlockingTxStatusWrite to MTxClk
799
always @ (posedge MTxClk or posedge Reset)
800
begin
801
  if(Reset)
802
    BlockingTxStatusWrite_sync3 <=#Tp 1'b0;
803
  else
804
    BlockingTxStatusWrite_sync3 <=#Tp BlockingTxStatusWrite_sync2;
805
end
806 159 mohor
 
807 329 igorm
assign RstDeferLatched = BlockingTxStatusWrite_sync2 & ~BlockingTxStatusWrite_sync3;
808
 
809 39 mohor
// TxBDRead state is activated only once. 
810 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
811 39 mohor
begin
812 40 mohor
  if(Reset)
813 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
814
  else
815 110 mohor
  if(StartTxBDRead)
816 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
817
  else
818 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
819 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
820
end
821 38 mohor
 
822
 
823 39 mohor
// Latching status from the tx buffer descriptor
824
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
825 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
826 38 mohor
begin
827 40 mohor
  if(Reset)
828 60 mohor
    TxStatus <=#Tp 4'h0;
829 38 mohor
  else
830 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
831 60 mohor
    TxStatus <=#Tp ram_do[14:11];
832 38 mohor
end
833
 
834 40 mohor
reg ReadTxDataFromMemory;
835
wire WriteRxDataToMemory;
836 38 mohor
 
837 39 mohor
reg MasterWbTX;
838
reg MasterWbRX;
839
 
840 329 igorm
reg [29:0] m_wb_adr_o;
841 39 mohor
reg        m_wb_cyc_o;
842 96 mohor
reg  [3:0] m_wb_sel_o;
843 39 mohor
reg        m_wb_we_o;
844 40 mohor
 
845 39 mohor
wire TxLengthEq0;
846
wire TxLengthLt4;
847
 
848 150 mohor
reg BlockingIncrementTxPointer;
849 159 mohor
reg [31:2] TxPointerMSB;
850
reg [1:0]  TxPointerLSB;
851
reg [1:0]  TxPointerLSB_rst;
852
reg [31:2] RxPointerMSB;
853
reg [1:0]  RxPointerLSB_rst;
854 39 mohor
 
855 150 mohor
wire RxBurstAcc;
856
wire RxWordAcc;
857
wire RxHalfAcc;
858
wire RxByteAcc;
859
 
860 39 mohor
//Latching length from the buffer descriptor;
861 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
862 38 mohor
begin
863 40 mohor
  if(Reset)
864 39 mohor
    TxLength <=#Tp 16'h0;
865 38 mohor
  else
866 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
867
    TxLength <=#Tp ram_do[31:16];
868 38 mohor
  else
869 39 mohor
  if(MasterWbTX & m_wb_ack_i)
870
    begin
871
      if(TxLengthLt4)
872
        TxLength <=#Tp 16'h0;
873 150 mohor
      else
874 159 mohor
      if(TxPointerLSB_rst==2'h0)
875 96 mohor
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
876 39 mohor
      else
877 159 mohor
      if(TxPointerLSB_rst==2'h1)
878 150 mohor
        TxLength <=#Tp TxLength - 3'h3;    // Length is subtracted at the data request
879
      else
880 159 mohor
      if(TxPointerLSB_rst==2'h2)
881 150 mohor
        TxLength <=#Tp TxLength - 3'h2;    // Length is subtracted at the data request
882
      else
883 159 mohor
      if(TxPointerLSB_rst==2'h3)
884 150 mohor
        TxLength <=#Tp TxLength - 3'h1;    // Length is subtracted at the data request
885 39 mohor
    end
886 38 mohor
end
887
 
888 96 mohor
 
889
 
890 60 mohor
//Latching length from the buffer descriptor;
891
always @ (posedge WB_CLK_I or posedge Reset)
892
begin
893
  if(Reset)
894
    LatchedTxLength <=#Tp 16'h0;
895
  else
896
  if(TxEn & TxEn_q & TxBDRead)
897
    LatchedTxLength <=#Tp ram_do[31:16];
898
end
899
 
900 39 mohor
assign TxLengthEq0 = TxLength == 0;
901
assign TxLengthLt4 = TxLength < 4;
902 38 mohor
 
903 150 mohor
reg cyc_cleared;
904
reg IncrTxPointer;
905 39 mohor
 
906
 
907 159 mohor
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
908
// because TxPointerMSB is only used for word-aligned accesses.
909 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
910 38 mohor
begin
911 40 mohor
  if(Reset)
912 159 mohor
    TxPointerMSB <=#Tp 30'h0;
913 38 mohor
  else
914 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
915 159 mohor
    TxPointerMSB <=#Tp ram_do[31:2];
916 38 mohor
  else
917 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
918 159 mohor
    TxPointerMSB <=#Tp TxPointerMSB + 1'b1;     // TxPointer is word-aligned
919 38 mohor
end
920
 
921 96 mohor
 
922 159 mohor
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
923
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
924
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
925
// set by this two bits.
926 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
927
begin
928
  if(Reset)
929 159 mohor
    TxPointerLSB[1:0] <=#Tp 0;
930 96 mohor
  else
931
  if(TxEn & TxEn_q & TxPointerRead)
932 159 mohor
    TxPointerLSB[1:0] <=#Tp ram_do[1:0];
933 96 mohor
end
934
 
935
 
936 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
937
// After the read access, TxLength needs to be decremented for the number of the valid
938
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
939
// valid so this two bits are reset to zero. 
940 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
941
begin
942
  if(Reset)
943 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
944 150 mohor
  else
945
  if(TxEn & TxEn_q & TxPointerRead)
946 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
947 150 mohor
  else
948
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
949 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
950 150 mohor
end
951 96 mohor
 
952 150 mohor
 
953 159 mohor
reg  [3:0] RxByteSel;
954 39 mohor
wire MasterAccessFinished;
955 38 mohor
 
956 39 mohor
 
957 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
958 38 mohor
begin
959 40 mohor
  if(Reset)
960 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
961 38 mohor
  else
962 39 mohor
  if(MasterAccessFinished)
963
    BlockingIncrementTxPointer <=#Tp 0;
964 38 mohor
  else
965 150 mohor
  if(IncrTxPointer)
966 39 mohor
    BlockingIncrementTxPointer <=#Tp 1'b1;
967 38 mohor
end
968
 
969
 
970 39 mohor
wire TxBufferAlmostFull;
971
wire TxBufferFull;
972
wire TxBufferEmpty;
973
wire TxBufferAlmostEmpty;
974 40 mohor
wire SetReadTxDataFromMemory;
975 39 mohor
 
976 40 mohor
reg BlockReadTxDataFromMemory;
977 39 mohor
 
978 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
979 39 mohor
 
980 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
981 38 mohor
begin
982 40 mohor
  if(Reset)
983
    ReadTxDataFromMemory <=#Tp 1'b0;
984 38 mohor
  else
985 278 mohor
  if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
986 40 mohor
    ReadTxDataFromMemory <=#Tp 1'b0;
987 39 mohor
  else
988 40 mohor
  if(SetReadTxDataFromMemory)
989
    ReadTxDataFromMemory <=#Tp 1'b1;
990 38 mohor
end
991
 
992 226 tadejm
reg tx_burst_en;
993
reg rx_burst_en;
994 221 mohor
 
995 278 mohor
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
996 226 tadejm
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
997 221 mohor
 
998 39 mohor
wire [31:0] TxData_wb;
999
wire ReadTxDataFromFifo_wb;
1000 38 mohor
 
1001 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1002 38 mohor
begin
1003 40 mohor
  if(Reset)
1004
    BlockReadTxDataFromMemory <=#Tp 1'b0;
1005 38 mohor
  else
1006 278 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
1007 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
1008 219 mohor
  else
1009 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
1010 219 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b0;
1011 39 mohor
end
1012
 
1013
 
1014
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
1015 349 olof
wire [TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
1016
wire [RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
1017 226 tadejm
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
1018
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
1019 159 mohor
 
1020 226 tadejm
wire rx_burst;
1021
wire enough_data_in_rxfifo_for_burst;
1022
wire enough_data_in_rxfifo_for_burst_plus1;
1023 229 mohor
 
1024 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
1025 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1026 39 mohor
begin
1027 40 mohor
  if(Reset)
1028 38 mohor
    begin
1029 39 mohor
      MasterWbTX <=#Tp 1'b0;
1030
      MasterWbRX <=#Tp 1'b0;
1031 329 igorm
      m_wb_adr_o <=#Tp 30'h0;
1032 39 mohor
      m_wb_cyc_o <=#Tp 1'b0;
1033
      m_wb_we_o  <=#Tp 1'b0;
1034 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
1035 110 mohor
      cyc_cleared<=#Tp 1'b0;
1036 226 tadejm
      tx_burst_cnt<=#Tp 0;
1037
      rx_burst_cnt<=#Tp 0;
1038 150 mohor
      IncrTxPointer<=#Tp 1'b0;
1039 226 tadejm
      tx_burst_en<=#Tp 1'b1;
1040
      rx_burst_en<=#Tp 1'b0;
1041
      `ifdef ETH_WISHBONE_B3
1042
        m_wb_cti_o <=#Tp 3'b0;
1043
      `endif
1044 38 mohor
    end
1045 39 mohor
  else
1046
    begin
1047
      // Switching between two stages depends on enable signals
1048 229 mohor
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst})  // synopsys parallel_case
1049 226 tadejm
        8'b00_10_00_10,             // Idle and MRB needed
1050 229 mohor
        8'b10_1x_10_1x,             // MRB continues
1051 226 tadejm
        8'b10_10_01_10,             // Clear (previously MR) and MRB needed
1052 229 mohor
        8'b01_1x_01_1x :            // Clear (previously MW) and MRB needed
1053 39 mohor
          begin
1054 226 tadejm
            MasterWbTX <=#Tp 1'b1;  // tx burst
1055
            MasterWbRX <=#Tp 1'b0;
1056
            m_wb_cyc_o <=#Tp 1'b1;
1057
            m_wb_we_o  <=#Tp 1'b0;
1058
            m_wb_sel_o <=#Tp 4'hf;
1059
            cyc_cleared<=#Tp 1'b0;
1060
            IncrTxPointer<=#Tp 1'b1;
1061 329 igorm
            tx_burst_cnt <=#Tp tx_burst_cnt+3'h1;
1062 226 tadejm
            if(tx_burst_cnt==0)
1063 329 igorm
              m_wb_adr_o <=#Tp TxPointerMSB;
1064 226 tadejm
            else
1065 329 igorm
              m_wb_adr_o <=#Tp m_wb_adr_o+1'b1;
1066 226 tadejm
 
1067
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1068
              begin
1069
                tx_burst_en<=#Tp 1'b0;
1070
              `ifdef ETH_WISHBONE_B3
1071
                m_wb_cti_o <=#Tp 3'b111;
1072
              `endif
1073
              end
1074
            else
1075
              begin
1076
              `ifdef ETH_WISHBONE_B3
1077
                m_wb_cti_o <=#Tp 3'b010;
1078
              `endif
1079
              end
1080
          end
1081 229 mohor
        8'b00_x1_00_x1,             // Idle and MWB needed
1082
        8'b01_x1_10_x1,             // MWB continues
1083 226 tadejm
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1084 229 mohor
        8'b10_x1_01_x1 :            // Clear (previously MR) and MWB needed
1085 226 tadejm
          begin
1086
            MasterWbTX <=#Tp 1'b0;  // rx burst
1087 39 mohor
            MasterWbRX <=#Tp 1'b1;
1088 226 tadejm
            m_wb_cyc_o <=#Tp 1'b1;
1089
            m_wb_we_o  <=#Tp 1'b1;
1090
            m_wb_sel_o <=#Tp RxByteSel;
1091
            IncrTxPointer<=#Tp 1'b0;
1092
            cyc_cleared<=#Tp 1'b0;
1093 329 igorm
            rx_burst_cnt <=#Tp rx_burst_cnt+3'h1;
1094 226 tadejm
 
1095
            if(rx_burst_cnt==0)
1096 329 igorm
              m_wb_adr_o <=#Tp RxPointerMSB;
1097 226 tadejm
            else
1098 329 igorm
              m_wb_adr_o <=#Tp m_wb_adr_o+1'b1;
1099 226 tadejm
 
1100
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1101
              begin
1102
                rx_burst_en<=#Tp 1'b0;
1103
              `ifdef ETH_WISHBONE_B3
1104
                m_wb_cti_o <=#Tp 3'b111;
1105
              `endif
1106
              end
1107
            else
1108
              begin
1109
              `ifdef ETH_WISHBONE_B3
1110
                m_wb_cti_o <=#Tp 3'b010;
1111
              `endif
1112
              end
1113
          end
1114 229 mohor
        8'b00_x1_00_x0 :            // idle and MW is needed (data write to rx buffer)
1115 226 tadejm
          begin
1116
            MasterWbTX <=#Tp 1'b0;
1117
            MasterWbRX <=#Tp 1'b1;
1118 329 igorm
            m_wb_adr_o <=#Tp RxPointerMSB;
1119 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1120
            m_wb_we_o  <=#Tp 1'b1;
1121 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1122 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1123 39 mohor
          end
1124 226 tadejm
        8'b00_10_00_00 :            // idle and MR is needed (data read from tx buffer)
1125 39 mohor
          begin
1126 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1127 39 mohor
            MasterWbRX <=#Tp 1'b0;
1128 329 igorm
            m_wb_adr_o <=#Tp TxPointerMSB;
1129 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1130
            m_wb_we_o  <=#Tp 1'b0;
1131 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1132
            IncrTxPointer<=#Tp 1'b1;
1133 39 mohor
          end
1134 226 tadejm
        8'b10_10_01_00,             // MR and MR is needed (data read from tx buffer)
1135 229 mohor
        8'b01_1x_01_0x  :           // MW and MR is needed (data read from tx buffer)
1136 39 mohor
          begin
1137 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1138 39 mohor
            MasterWbRX <=#Tp 1'b0;
1139 329 igorm
            m_wb_adr_o <=#Tp TxPointerMSB;
1140 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1141
            m_wb_we_o  <=#Tp 1'b0;
1142 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1143 110 mohor
            cyc_cleared<=#Tp 1'b0;
1144 150 mohor
            IncrTxPointer<=#Tp 1'b1;
1145 39 mohor
          end
1146 226 tadejm
        8'b01_01_01_00,             // MW and MW needed (data write to rx buffer)
1147 229 mohor
        8'b10_x1_01_x0  :           // MR and MW is needed (data write to rx buffer)
1148 39 mohor
          begin
1149 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1150 39 mohor
            MasterWbRX <=#Tp 1'b1;
1151 329 igorm
            m_wb_adr_o <=#Tp RxPointerMSB;
1152 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1153 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
1154 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1155 110 mohor
            cyc_cleared<=#Tp 1'b0;
1156 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1157 39 mohor
          end
1158 226 tadejm
        8'b01_01_10_00,             // MW and MW needed (cycle is cleared between previous and next access)
1159 229 mohor
        8'b01_1x_10_x0,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1160 226 tadejm
        8'b10_10_10_00,             // MR and MR needed (cycle is cleared between previous and next access)
1161 229 mohor
        8'b10_x1_10_0x :            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1162 39 mohor
          begin
1163 110 mohor
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
1164
            cyc_cleared<=#Tp 1'b1;
1165 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1166 226 tadejm
            tx_burst_cnt<=#Tp 0;
1167 349 olof
            tx_burst_en<=#Tp txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1168 226 tadejm
            rx_burst_cnt<=#Tp 0;
1169
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1170
            `ifdef ETH_WISHBONE_B3
1171
              m_wb_cti_o <=#Tp 3'b0;
1172
            `endif
1173 110 mohor
          end
1174 229 mohor
        8'bxx_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1175
        8'bxx_00_01_00 :            // Between cyc_cleared request was cleared
1176 110 mohor
          begin
1177 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1178 39 mohor
            MasterWbRX <=#Tp 1'b0;
1179
            m_wb_cyc_o <=#Tp 1'b0;
1180 226 tadejm
            cyc_cleared<=#Tp 1'b0;
1181 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1182 226 tadejm
            rx_burst_cnt<=#Tp 0;
1183
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1184
            `ifdef ETH_WISHBONE_B3
1185
              m_wb_cti_o <=#Tp 3'b0;
1186
            `endif
1187 39 mohor
          end
1188 226 tadejm
        8'b00_00_00_00:             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1189 127 mohor
          begin
1190 226 tadejm
            tx_burst_cnt<=#Tp 0;
1191 349 olof
            tx_burst_en<=#Tp txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1192 127 mohor
          end
1193 226 tadejm
        default:                    // Don't touch
1194 82 mohor
          begin
1195
            MasterWbTX <=#Tp MasterWbTX;
1196
            MasterWbRX <=#Tp MasterWbRX;
1197
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
1198 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
1199 150 mohor
            IncrTxPointer<=#Tp IncrTxPointer;
1200 82 mohor
          end
1201 39 mohor
      endcase
1202
    end
1203 38 mohor
end
1204
 
1205 110 mohor
 
1206 39 mohor
wire TxFifoClear;
1207 96 mohor
 
1208 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1209 38 mohor
 
1210 349 olof
eth_fifo #(.DATA_WIDTH(TX_FIFO_DATA_WIDTH),
1211
           .DEPTH(TX_FIFO_DEPTH),
1212
           .CNT_WIDTH(TX_FIFO_CNT_WIDTH),
1213
           .Tp(Tp))
1214 150 mohor
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
1215 96 mohor
          .clk(WB_CLK_I),                                   .reset(Reset),
1216 226 tadejm
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1217 96 mohor
          .clear(TxFifoClear),                              .full(TxBufferFull),
1218
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
1219 150 mohor
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
1220 96 mohor
        );
1221 39 mohor
 
1222
 
1223
reg StartOccured;
1224
reg TxStartFrm_sync1;
1225
reg TxStartFrm_sync2;
1226
reg TxStartFrm_syncb1;
1227
reg TxStartFrm_syncb2;
1228
 
1229
 
1230
 
1231
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1232 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1233 38 mohor
begin
1234 40 mohor
  if(Reset)
1235 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
1236 38 mohor
  else
1237 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1238
    TxStartFrm_wb <=#Tp 1'b1;
1239 38 mohor
  else
1240 39 mohor
  if(TxStartFrm_syncb2)
1241
    TxStartFrm_wb <=#Tp 1'b0;
1242 38 mohor
end
1243
 
1244 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1245 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1246 38 mohor
begin
1247 40 mohor
  if(Reset)
1248 39 mohor
    StartOccured <=#Tp 1'b0;
1249 38 mohor
  else
1250 39 mohor
  if(TxStartFrm_wb)
1251
    StartOccured <=#Tp 1'b1;
1252 38 mohor
  else
1253 39 mohor
  if(ResetTxBDReady)
1254
    StartOccured <=#Tp 1'b0;
1255 38 mohor
end
1256
 
1257 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1258 40 mohor
always @ (posedge MTxClk or posedge Reset)
1259 39 mohor
begin
1260 40 mohor
  if(Reset)
1261 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1262
  else
1263
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1264
end
1265 38 mohor
 
1266 40 mohor
always @ (posedge MTxClk or posedge Reset)
1267 39 mohor
begin
1268 40 mohor
  if(Reset)
1269 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1270
  else
1271
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1272
end
1273
 
1274 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1275 38 mohor
begin
1276 40 mohor
  if(Reset)
1277 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1278 38 mohor
  else
1279 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1280 38 mohor
end
1281
 
1282 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1283 38 mohor
begin
1284 40 mohor
  if(Reset)
1285 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1286 38 mohor
  else
1287 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1288
end
1289
 
1290 40 mohor
always @ (posedge MTxClk or posedge Reset)
1291 39 mohor
begin
1292 40 mohor
  if(Reset)
1293 39 mohor
    TxStartFrm <=#Tp 1'b0;
1294 38 mohor
  else
1295 39 mohor
  if(TxStartFrm_sync2)
1296 61 mohor
    TxStartFrm <=#Tp 1'b1;
1297 39 mohor
  else
1298 278 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
1299 39 mohor
    TxStartFrm <=#Tp 1'b0;
1300 38 mohor
end
1301 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1302 38 mohor
 
1303
 
1304 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1305 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1306 38 mohor
begin
1307 40 mohor
  if(Reset)
1308 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1309 38 mohor
  else
1310 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1311 39 mohor
    TxEndFrm_wb <=#Tp 1'b1;
1312 38 mohor
  else
1313 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1314
    TxEndFrm_wb <=#Tp 1'b0;
1315 38 mohor
end
1316
 
1317
 
1318
// Marks which bytes are valid within the word.
1319 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1320 38 mohor
 
1321 39 mohor
reg LatchValidBytes;
1322
reg LatchValidBytes_q;
1323 38 mohor
 
1324 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1325 38 mohor
begin
1326 40 mohor
  if(Reset)
1327 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1328 38 mohor
  else
1329 39 mohor
  if(TxLengthLt4 & TxBDReady)
1330
    LatchValidBytes <=#Tp 1'b1;
1331 38 mohor
  else
1332 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1333 38 mohor
end
1334
 
1335 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1336 38 mohor
begin
1337 40 mohor
  if(Reset)
1338 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1339 38 mohor
  else
1340 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1341 38 mohor
end
1342
 
1343
 
1344 39 mohor
// Latching valid bytes
1345 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1346 38 mohor
begin
1347 40 mohor
  if(Reset)
1348 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1349 38 mohor
  else
1350 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1351
    TxValidBytesLatched <=#Tp TxValidBytes;
1352
  else
1353
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1354
    TxValidBytesLatched <=#Tp 2'h0;
1355 38 mohor
end
1356
 
1357
 
1358
assign TxIRQEn          = TxStatus[14];
1359 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1360
assign PerPacketPad     = TxStatus[12];
1361
assign PerPacketCrcEn   = TxStatus[11];
1362 38 mohor
 
1363
 
1364 77 mohor
assign RxIRQEn         = RxStatus[14];
1365 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1366 38 mohor
 
1367
 
1368
// Temporary Tx and Rx buffer descriptor address 
1369 329 igorm
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite     & ~WrapTxStatusBit}}   & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
1370
assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0])     | // Using first Rx BD
1371
                              {7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address)
1372 38 mohor
 
1373
 
1374
// Latching Tx buffer descriptor address
1375 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1376 38 mohor
begin
1377 40 mohor
  if(Reset)
1378 329 igorm
    TxBDAddress <=#Tp 7'h0;
1379 321 igorm
  else if (r_TxEn & (~r_TxEn_q))
1380 329 igorm
    TxBDAddress <=#Tp 7'h0;
1381 321 igorm
  else if (TxStatusWrite)
1382 38 mohor
    TxBDAddress <=#Tp TempTxBDAddress;
1383
end
1384
 
1385
 
1386
// Latching Rx buffer descriptor address
1387 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1388 38 mohor
begin
1389 40 mohor
  if(Reset)
1390 329 igorm
    RxBDAddress <=#Tp 7'h0;
1391 321 igorm
  else if(r_RxEn & (~r_RxEn_q))
1392 329 igorm
    RxBDAddress <=#Tp r_TxBDNum[6:0];
1393 321 igorm
  else if(RxStatusWrite)
1394 38 mohor
    RxBDAddress <=#Tp TempRxBDAddress;
1395
end
1396
 
1397 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1398 38 mohor
 
1399 261 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
1400 60 mohor
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1401 38 mohor
 
1402 60 mohor
 
1403 38 mohor
// Signals used for various purposes
1404 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1405 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1406
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1407
 
1408
 
1409
 
1410 39 mohor
// Generating delayed signals
1411 40 mohor
always @ (posedge MTxClk or posedge Reset)
1412 38 mohor
begin
1413 40 mohor
  if(Reset)
1414 39 mohor
    begin
1415
      TxAbort_q      <=#Tp 1'b0;
1416
      TxRetry_q      <=#Tp 1'b0;
1417
      TxUsedData_q   <=#Tp 1'b0;
1418
    end
1419 38 mohor
  else
1420 39 mohor
    begin
1421
      TxAbort_q      <=#Tp TxAbort;
1422
      TxRetry_q      <=#Tp TxRetry;
1423
      TxUsedData_q   <=#Tp TxUsedData;
1424
    end
1425 38 mohor
end
1426
 
1427
// Generating delayed signals
1428 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1429 38 mohor
begin
1430 40 mohor
  if(Reset)
1431 38 mohor
    begin
1432 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1433
      TxAbort_wb_q  <=#Tp 1'b0;
1434 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1435 38 mohor
    end
1436
  else
1437
    begin
1438 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1439
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1440 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1441 38 mohor
    end
1442
end
1443
 
1444
 
1445 219 mohor
reg TxAbortPacketBlocked;
1446
always @ (posedge WB_CLK_I or posedge Reset)
1447
begin
1448
  if(Reset)
1449
    TxAbortPacket <=#Tp 1'b0;
1450
  else
1451 278 mohor
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
1452
     TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
1453 219 mohor
    TxAbortPacket <=#Tp 1'b1;
1454
  else
1455
    TxAbortPacket <=#Tp 1'b0;
1456
end
1457
 
1458
 
1459
always @ (posedge WB_CLK_I or posedge Reset)
1460
begin
1461
  if(Reset)
1462 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1463
  else
1464 272 tadejm
  if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
1465
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1466
  else
1467 278 mohor
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
1468
     TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
1469 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b1;
1470
end
1471
 
1472
 
1473
always @ (posedge WB_CLK_I or posedge Reset)
1474
begin
1475
  if(Reset)
1476 219 mohor
    TxAbortPacketBlocked <=#Tp 1'b0;
1477
  else
1478 280 mohor
  if(!TxAbort_wb & TxAbort_wb_q)
1479
    TxAbortPacketBlocked <=#Tp 1'b0;
1480
  else
1481 219 mohor
  if(TxAbortPacket)
1482
    TxAbortPacketBlocked <=#Tp 1'b1;
1483
end
1484
 
1485
 
1486
reg TxRetryPacketBlocked;
1487
always @ (posedge WB_CLK_I or posedge Reset)
1488
begin
1489
  if(Reset)
1490
    TxRetryPacket <=#Tp 1'b0;
1491
  else
1492 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1493
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1494 219 mohor
    TxRetryPacket <=#Tp 1'b1;
1495
  else
1496
    TxRetryPacket <=#Tp 1'b0;
1497
end
1498
 
1499
 
1500
always @ (posedge WB_CLK_I or posedge Reset)
1501
begin
1502
  if(Reset)
1503 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1504
  else
1505 272 tadejm
  if(StartTxBDRead)
1506
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1507
  else
1508 278 mohor
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1509
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1510 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b1;
1511
end
1512
 
1513
 
1514
always @ (posedge WB_CLK_I or posedge Reset)
1515
begin
1516
  if(Reset)
1517 219 mohor
    TxRetryPacketBlocked <=#Tp 1'b0;
1518
  else
1519 280 mohor
  if(!TxRetry_wb & TxRetry_wb_q)
1520
    TxRetryPacketBlocked <=#Tp 1'b0;
1521
  else
1522 219 mohor
  if(TxRetryPacket)
1523
    TxRetryPacketBlocked <=#Tp 1'b1;
1524
end
1525
 
1526
 
1527 221 mohor
reg TxDonePacketBlocked;
1528
always @ (posedge WB_CLK_I or posedge Reset)
1529
begin
1530
  if(Reset)
1531
    TxDonePacket <=#Tp 1'b0;
1532
  else
1533 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
1534
     TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1535 221 mohor
    TxDonePacket <=#Tp 1'b1;
1536
  else
1537
    TxDonePacket <=#Tp 1'b0;
1538
end
1539
 
1540
 
1541
always @ (posedge WB_CLK_I or posedge Reset)
1542
begin
1543
  if(Reset)
1544
    TxDonePacket_NotCleared <=#Tp 1'b0;
1545
  else
1546 272 tadejm
  if(TxEn & TxEn_q & TxDonePacket_NotCleared)
1547
    TxDonePacket_NotCleared <=#Tp 1'b0;
1548
  else
1549 278 mohor
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) |
1550
     TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
1551 221 mohor
    TxDonePacket_NotCleared <=#Tp 1'b1;
1552
end
1553
 
1554
 
1555
always @ (posedge WB_CLK_I or posedge Reset)
1556
begin
1557
  if(Reset)
1558
    TxDonePacketBlocked <=#Tp 1'b0;
1559
  else
1560 280 mohor
  if(!TxDone_wb & TxDone_wb_q)
1561
    TxDonePacketBlocked <=#Tp 1'b0;
1562
  else
1563 221 mohor
  if(TxDonePacket)
1564
    TxDonePacketBlocked <=#Tp 1'b1;
1565
end
1566
 
1567
 
1568 38 mohor
// Indication of the last word
1569 40 mohor
always @ (posedge MTxClk or posedge Reset)
1570 38 mohor
begin
1571 40 mohor
  if(Reset)
1572 38 mohor
    LastWord <=#Tp 1'b0;
1573
  else
1574
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1575
    LastWord <=#Tp 1'b0;
1576
  else
1577
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1578 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1579 38 mohor
end
1580
 
1581
 
1582
// Tx end frame generation
1583 40 mohor
always @ (posedge MTxClk or posedge Reset)
1584 38 mohor
begin
1585 40 mohor
  if(Reset)
1586 38 mohor
    TxEndFrm <=#Tp 1'b0;
1587
  else
1588 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1589 38 mohor
    TxEndFrm <=#Tp 1'b0;
1590
  else
1591
  if(Flop & LastWord)
1592
    begin
1593 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1594 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1595
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1596
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1597
 
1598
        default : TxEndFrm <=#Tp 1'b0;
1599
      endcase
1600
    end
1601
end
1602
 
1603
 
1604
// Tx data selection (latching)
1605 40 mohor
always @ (posedge MTxClk or posedge Reset)
1606 38 mohor
begin
1607 40 mohor
  if(Reset)
1608 96 mohor
    TxData <=#Tp 0;
1609 38 mohor
  else
1610 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1611 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1612 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1613
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1614
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1615
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1616
    endcase
1617 38 mohor
  else
1618 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1619 96 mohor
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1620
  else
1621 38 mohor
  if(TxUsedData & Flop)
1622
    begin
1623 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1624 226 tadejm
 
1625 82 mohor
        1 : TxData <=#Tp TxDataLatched[23:16];
1626
        2 : TxData <=#Tp TxDataLatched[15:8];
1627
        3 : TxData <=#Tp TxDataLatched[7:0];
1628 38 mohor
      endcase
1629
    end
1630
end
1631
 
1632
 
1633
// Latching tx data
1634 40 mohor
always @ (posedge MTxClk or posedge Reset)
1635 38 mohor
begin
1636 40 mohor
  if(Reset)
1637 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1638
  else
1639 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1640 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1641 38 mohor
end
1642
 
1643
 
1644
// Tx under run
1645 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1646 38 mohor
begin
1647 40 mohor
  if(Reset)
1648 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1649 38 mohor
  else
1650 39 mohor
  if(TxAbortPulse)
1651 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1652
  else
1653
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1654
    TxUnderRun_wb <=#Tp 1'b1;
1655
end
1656
 
1657
 
1658 159 mohor
reg TxUnderRun_sync1;
1659
 
1660 60 mohor
// Tx under run
1661
always @ (posedge MTxClk or posedge Reset)
1662
begin
1663
  if(Reset)
1664 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b0;
1665 43 mohor
  else
1666 60 mohor
  if(TxUnderRun_wb)
1667 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b1;
1668 60 mohor
  else
1669 159 mohor
  if(BlockingTxStatusWrite_sync2)
1670
    TxUnderRun_sync1 <=#Tp 1'b0;
1671
end
1672
 
1673
// Tx under run
1674
always @ (posedge MTxClk or posedge Reset)
1675
begin
1676
  if(Reset)
1677 60 mohor
    TxUnderRun <=#Tp 1'b0;
1678 159 mohor
  else
1679
  if(BlockingTxStatusWrite_sync2)
1680
    TxUnderRun <=#Tp 1'b0;
1681
  else
1682
  if(TxUnderRun_sync1)
1683
    TxUnderRun <=#Tp 1'b1;
1684 38 mohor
end
1685
 
1686
 
1687
// Tx Byte counter
1688 40 mohor
always @ (posedge MTxClk or posedge Reset)
1689 38 mohor
begin
1690 40 mohor
  if(Reset)
1691 38 mohor
    TxByteCnt <=#Tp 2'h0;
1692
  else
1693
  if(TxAbort_q | TxRetry_q)
1694
    TxByteCnt <=#Tp 2'h0;
1695
  else
1696
  if(TxStartFrm & ~TxUsedData)
1697 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1698 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1699
      2'h1 : TxByteCnt <=#Tp 2'h2;
1700
      2'h2 : TxByteCnt <=#Tp 2'h3;
1701
      2'h3 : TxByteCnt <=#Tp 2'h0;
1702
    endcase
1703 38 mohor
  else
1704
  if(TxUsedData & Flop)
1705 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1706 38 mohor
end
1707
 
1708 39 mohor
 
1709 150 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1710
reg ReadTxDataFromFifo_sync1;
1711
reg ReadTxDataFromFifo_sync2;
1712
reg ReadTxDataFromFifo_sync3;
1713
reg ReadTxDataFromFifo_syncb1;
1714
reg ReadTxDataFromFifo_syncb2;
1715
reg ReadTxDataFromFifo_syncb3;
1716
 
1717
 
1718
always @ (posedge MTxClk or posedge Reset)
1719
begin
1720
  if(Reset)
1721
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1722
  else
1723 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1724 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1725 150 mohor
  else
1726
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1727
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1728 38 mohor
end
1729
 
1730 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1731 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1732 38 mohor
begin
1733 40 mohor
  if(Reset)
1734 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1735 38 mohor
  else
1736 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1737
end
1738 38 mohor
 
1739 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1740 38 mohor
begin
1741 40 mohor
  if(Reset)
1742 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1743 38 mohor
  else
1744 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1745 38 mohor
end
1746
 
1747 40 mohor
always @ (posedge MTxClk or posedge Reset)
1748 38 mohor
begin
1749 40 mohor
  if(Reset)
1750 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1751 38 mohor
  else
1752 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1753 38 mohor
end
1754
 
1755 40 mohor
always @ (posedge MTxClk or posedge Reset)
1756 38 mohor
begin
1757 40 mohor
  if(Reset)
1758 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1759 38 mohor
  else
1760 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1761 38 mohor
end
1762
 
1763 150 mohor
always @ (posedge MTxClk or posedge Reset)
1764
begin
1765
  if(Reset)
1766
    ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
1767
  else
1768
    ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
1769
end
1770
 
1771 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1772 38 mohor
begin
1773 40 mohor
  if(Reset)
1774 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1775 38 mohor
  else
1776 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1777 38 mohor
end
1778
 
1779 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1780
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1781 38 mohor
 
1782
 
1783 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1784 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1785 38 mohor
begin
1786 40 mohor
  if(Reset)
1787 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1788 38 mohor
  else
1789 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1790 38 mohor
end
1791
 
1792 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1793 38 mohor
begin
1794 40 mohor
  if(Reset)
1795 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1796 38 mohor
  else
1797 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1798 38 mohor
end
1799
 
1800
 
1801 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1802 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1803 38 mohor
begin
1804 40 mohor
  if(Reset)
1805 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1806 38 mohor
  else
1807 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1808 38 mohor
end
1809
 
1810 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1811 38 mohor
begin
1812 40 mohor
  if(Reset)
1813 39 mohor
    TxDone_wb <=#Tp 1'b0;
1814 38 mohor
  else
1815 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1816 38 mohor
end
1817
 
1818 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1819 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1820 38 mohor
begin
1821 40 mohor
  if(Reset)
1822 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1823 38 mohor
  else
1824 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1825 38 mohor
end
1826
 
1827 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1828 38 mohor
begin
1829 40 mohor
  if(Reset)
1830 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1831
  else
1832 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1833 38 mohor
end
1834
 
1835
 
1836 150 mohor
reg RxAbortSync1;
1837
reg RxAbortSync2;
1838
reg RxAbortSync3;
1839
reg RxAbortSync4;
1840
reg RxAbortSyncb1;
1841
reg RxAbortSyncb2;
1842 39 mohor
 
1843 333 igorm
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 | r_RxEn & ~r_RxEn_q;
1844 150 mohor
 
1845 40 mohor
// Reading the Rx buffer descriptor
1846
always @ (posedge WB_CLK_I or posedge Reset)
1847
begin
1848
  if(Reset)
1849 333 igorm
    RxBDRead <=#Tp 1'b0;
1850 40 mohor
  else
1851 166 mohor
  if(StartRxBDRead & ~RxReady)
1852 40 mohor
    RxBDRead <=#Tp 1'b1;
1853
  else
1854
  if(RxBDReady)
1855
    RxBDRead <=#Tp 1'b0;
1856
end
1857 39 mohor
 
1858
 
1859 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1860
// written to the previous one.
1861
 
1862
// Latching READY status of the Rx buffer descriptor
1863 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1864 38 mohor
begin
1865 40 mohor
  if(Reset)
1866 38 mohor
    RxBDReady <=#Tp 1'b0;
1867
  else
1868 166 mohor
  if(RxPointerRead)
1869 150 mohor
    RxBDReady <=#Tp 1'b0;
1870
  else
1871 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1872
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1873 38 mohor
end
1874
 
1875 40 mohor
// Latching Rx buffer descriptor status
1876
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1877
always @ (posedge WB_CLK_I or posedge Reset)
1878 38 mohor
begin
1879 40 mohor
  if(Reset)
1880 60 mohor
    RxStatus <=#Tp 2'h0;
1881 38 mohor
  else
1882 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1883 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1884 38 mohor
end
1885
 
1886
 
1887 166 mohor
// RxReady generation
1888
always @ (posedge WB_CLK_I or posedge Reset)
1889
begin
1890
  if(Reset)
1891
    RxReady <=#Tp 1'b0;
1892
  else
1893 333 igorm
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)
1894 166 mohor
    RxReady <=#Tp 1'b0;
1895
  else
1896
  if(RxEn & RxEn_q & RxPointerRead)
1897
    RxReady <=#Tp 1'b1;
1898
end
1899 38 mohor
 
1900
 
1901 40 mohor
// Reading Rx BD pointer
1902
 
1903
 
1904
assign StartRxPointerRead = RxBDRead & RxBDReady;
1905
 
1906
// Reading Tx BD Pointer
1907
always @ (posedge WB_CLK_I or posedge Reset)
1908 38 mohor
begin
1909 40 mohor
  if(Reset)
1910
    RxPointerRead <=#Tp 1'b0;
1911 38 mohor
  else
1912 40 mohor
  if(StartRxPointerRead)
1913
    RxPointerRead <=#Tp 1'b1;
1914 38 mohor
  else
1915 166 mohor
  if(RxEn & RxEn_q)
1916 40 mohor
    RxPointerRead <=#Tp 1'b0;
1917 38 mohor
end
1918
 
1919 113 mohor
 
1920 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1921
always @ (posedge WB_CLK_I or posedge Reset)
1922
begin
1923
  if(Reset)
1924 159 mohor
    RxPointerMSB <=#Tp 30'h0;
1925 40 mohor
  else
1926
  if(RxEn & RxEn_q & RxPointerRead)
1927 159 mohor
    RxPointerMSB <=#Tp ram_do[31:2];
1928 40 mohor
  else
1929 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1930 329 igorm
      RxPointerMSB <=#Tp RxPointerMSB + 1'b1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1931 40 mohor
end
1932 38 mohor
 
1933
 
1934 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1935 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1936
begin
1937
  if(Reset)
1938 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp 0;
1939 96 mohor
  else
1940 159 mohor
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
1941
    RxPointerLSB_rst[1:0] <=#Tp 0;
1942 96 mohor
  else
1943
  if(RxEn & RxEn_q & RxPointerRead)
1944 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
1945 96 mohor
end
1946
 
1947
 
1948 159 mohor
always @ (RxPointerLSB_rst)
1949 96 mohor
begin
1950 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1951
    2'h0 : RxByteSel[3:0] = 4'hf;
1952
    2'h1 : RxByteSel[3:0] = 4'h7;
1953
    2'h2 : RxByteSel[3:0] = 4'h3;
1954
    2'h3 : RxByteSel[3:0] = 4'h1;
1955 96 mohor
  endcase
1956
end
1957
 
1958
 
1959
always @ (posedge WB_CLK_I or posedge Reset)
1960
begin
1961
  if(Reset)
1962 40 mohor
    RxEn_needed <=#Tp 1'b0;
1963 38 mohor
  else
1964 166 mohor
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1965 40 mohor
    RxEn_needed <=#Tp 1'b1;
1966 38 mohor
  else
1967 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1968
    RxEn_needed <=#Tp 1'b0;
1969 38 mohor
end
1970
 
1971
 
1972 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1973
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1974 38 mohor
 
1975 40 mohor
reg RxEnableWindow;
1976 38 mohor
 
1977
// Indicating that last byte is being reveived
1978 40 mohor
always @ (posedge MRxClk or posedge Reset)
1979 38 mohor
begin
1980 40 mohor
  if(Reset)
1981 38 mohor
    LastByteIn <=#Tp 1'b0;
1982
  else
1983 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1984 38 mohor
    LastByteIn <=#Tp 1'b0;
1985
  else
1986 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1987 38 mohor
    LastByteIn <=#Tp 1'b1;
1988
end
1989
 
1990 159 mohor
reg ShiftEnded_rck;
1991 40 mohor
reg ShiftEndedSync1;
1992
reg ShiftEndedSync2;
1993 118 mohor
reg ShiftEndedSync3;
1994
reg ShiftEndedSync_c1;
1995
reg ShiftEndedSync_c2;
1996
 
1997 40 mohor
wire StartShiftWillEnd;
1998 96 mohor
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1999 38 mohor
 
2000
// Indicating that data reception will end
2001 40 mohor
always @ (posedge MRxClk or posedge Reset)
2002 38 mohor
begin
2003 40 mohor
  if(Reset)
2004 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
2005
  else
2006 159 mohor
  if(ShiftEnded_rck | RxAbort)
2007 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
2008
  else
2009 40 mohor
  if(StartShiftWillEnd)
2010 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
2011
end
2012
 
2013
 
2014 40 mohor
 
2015 38 mohor
// Receive byte counter
2016 40 mohor
always @ (posedge MRxClk or posedge Reset)
2017 38 mohor
begin
2018 40 mohor
  if(Reset)
2019 38 mohor
    RxByteCnt <=#Tp 2'h0;
2020
  else
2021 159 mohor
  if(ShiftEnded_rck | RxAbort)
2022 38 mohor
    RxByteCnt <=#Tp 2'h0;
2023 97 lampret
  else
2024 166 mohor
  if(RxValid & RxStartFrm & RxReady)
2025 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2026 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
2027
      2'h1 : RxByteCnt <=#Tp 2'h2;
2028
      2'h2 : RxByteCnt <=#Tp 2'h3;
2029
      2'h3 : RxByteCnt <=#Tp 2'h0;
2030
    endcase
2031 38 mohor
  else
2032 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
2033 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
2034 38 mohor
end
2035
 
2036
 
2037
// Indicates how many bytes are valid within the last word
2038 40 mohor
always @ (posedge MRxClk or posedge Reset)
2039 38 mohor
begin
2040 40 mohor
  if(Reset)
2041 38 mohor
    RxValidBytes <=#Tp 2'h1;
2042
  else
2043 96 mohor
  if(RxValid & RxStartFrm)
2044 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2045 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
2046
      2'h1 : RxValidBytes <=#Tp 2'h2;
2047
      2'h2 : RxValidBytes <=#Tp 2'h3;
2048
      2'h3 : RxValidBytes <=#Tp 2'h0;
2049
    endcase
2050 38 mohor
  else
2051 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2052 329 igorm
    RxValidBytes <=#Tp RxValidBytes + 1'b1;
2053 38 mohor
end
2054
 
2055
 
2056 40 mohor
always @ (posedge MRxClk or posedge Reset)
2057 38 mohor
begin
2058 40 mohor
  if(Reset)
2059
    RxDataLatched1       <=#Tp 24'h0;
2060 38 mohor
  else
2061 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2062 96 mohor
    if(RxStartFrm)
2063 40 mohor
    begin
2064 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2065 96 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2066
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2067
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2068
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2069
      endcase
2070
    end
2071
    else if (RxEnableWindow)
2072
    begin
2073 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2074 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2075
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2076
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2077 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2078
      endcase
2079
    end
2080 38 mohor
end
2081
 
2082 40 mohor
wire SetWriteRxDataToFifo;
2083 38 mohor
 
2084 40 mohor
// Assembling data that will be written to the rx_fifo
2085
always @ (posedge MRxClk or posedge Reset)
2086 38 mohor
begin
2087 40 mohor
  if(Reset)
2088
    RxDataLatched2 <=#Tp 32'h0;
2089 38 mohor
  else
2090 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2091 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
2092 38 mohor
  else
2093 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2094 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2095 82 mohor
 
2096
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2097
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
2098
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
2099 40 mohor
    endcase
2100 38 mohor
end
2101
 
2102
 
2103 40 mohor
reg WriteRxDataToFifoSync1;
2104
reg WriteRxDataToFifoSync2;
2105 150 mohor
reg WriteRxDataToFifoSync3;
2106 38 mohor
 
2107
 
2108 40 mohor
// Indicating start of the reception process
2109 166 mohor
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
2110
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
2111
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
2112 38 mohor
 
2113 150 mohor
always @ (posedge MRxClk or posedge Reset)
2114
begin
2115
  if(Reset)
2116
    WriteRxDataToFifo <=#Tp 1'b0;
2117
  else
2118
  if(SetWriteRxDataToFifo & ~RxAbort)
2119
    WriteRxDataToFifo <=#Tp 1'b1;
2120
  else
2121
  if(WriteRxDataToFifoSync2 | RxAbort)
2122
    WriteRxDataToFifo <=#Tp 1'b0;
2123
end
2124 40 mohor
 
2125 150 mohor
 
2126
 
2127
always @ (posedge WB_CLK_I or posedge Reset)
2128
begin
2129
  if(Reset)
2130
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2131
  else
2132
  if(WriteRxDataToFifo)
2133
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
2134
  else
2135
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2136
end
2137
 
2138
always @ (posedge WB_CLK_I or posedge Reset)
2139
begin
2140
  if(Reset)
2141
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
2142
  else
2143
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
2144
end
2145
 
2146
always @ (posedge WB_CLK_I or posedge Reset)
2147
begin
2148
  if(Reset)
2149
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
2150
  else
2151
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
2152
end
2153
 
2154
wire WriteRxDataToFifo_wb;
2155
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
2156
 
2157
 
2158 90 mohor
reg LatchedRxStartFrm;
2159
reg SyncRxStartFrm;
2160
reg SyncRxStartFrm_q;
2161 150 mohor
reg SyncRxStartFrm_q2;
2162 90 mohor
wire RxFifoReset;
2163 40 mohor
 
2164 90 mohor
always @ (posedge MRxClk or posedge Reset)
2165
begin
2166
  if(Reset)
2167
    LatchedRxStartFrm <=#Tp 0;
2168
  else
2169 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2170 90 mohor
    LatchedRxStartFrm <=#Tp 1;
2171
  else
2172 150 mohor
  if(SyncRxStartFrm_q)
2173 90 mohor
    LatchedRxStartFrm <=#Tp 0;
2174
end
2175
 
2176
 
2177
always @ (posedge WB_CLK_I or posedge Reset)
2178
begin
2179
  if(Reset)
2180
    SyncRxStartFrm <=#Tp 0;
2181
  else
2182
  if(LatchedRxStartFrm)
2183
    SyncRxStartFrm <=#Tp 1;
2184
  else
2185
    SyncRxStartFrm <=#Tp 0;
2186
end
2187
 
2188
 
2189
always @ (posedge WB_CLK_I or posedge Reset)
2190
begin
2191
  if(Reset)
2192
    SyncRxStartFrm_q <=#Tp 0;
2193
  else
2194
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
2195
end
2196
 
2197 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2198
begin
2199
  if(Reset)
2200
    SyncRxStartFrm_q2 <=#Tp 0;
2201
  else
2202
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
2203
end
2204 90 mohor
 
2205
 
2206 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2207 90 mohor
 
2208 349 olof
eth_fifo #(.DATA_WIDTH(RX_FIFO_DATA_WIDTH),
2209
           .DEPTH(RX_FIFO_DEPTH),
2210
           .CNT_WIDTH(RX_FIFO_CNT_WIDTH),
2211
           .Tp(Tp))
2212 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
2213
         .clk(WB_CLK_I),                                .reset(Reset),
2214 219 mohor
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
2215 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
2216 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
2217 150 mohor
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
2218 88 mohor
        );
2219 40 mohor
 
2220 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2221
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2222 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2223 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2224 40 mohor
 
2225
 
2226
// Generation of the end-of-frame signal
2227
always @ (posedge MRxClk or posedge Reset)
2228 38 mohor
begin
2229 40 mohor
  if(Reset)
2230 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2231 38 mohor
  else
2232 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2233 159 mohor
    ShiftEnded_rck <=#Tp 1'b1;
2234 38 mohor
  else
2235 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2236 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2237 38 mohor
end
2238
 
2239 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2240
begin
2241
  if(Reset)
2242
    ShiftEndedSync1 <=#Tp 1'b0;
2243
  else
2244 159 mohor
    ShiftEndedSync1 <=#Tp ShiftEnded_rck;
2245 40 mohor
end
2246 38 mohor
 
2247 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2248 38 mohor
begin
2249 40 mohor
  if(Reset)
2250
    ShiftEndedSync2 <=#Tp 1'b0;
2251 38 mohor
  else
2252 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
2253 40 mohor
end
2254 38 mohor
 
2255 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2256
begin
2257
  if(Reset)
2258
    ShiftEndedSync3 <=#Tp 1'b0;
2259
  else
2260
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2261
    ShiftEndedSync3 <=#Tp 1'b1;
2262
  else
2263
  if(ShiftEnded)
2264
    ShiftEndedSync3 <=#Tp 1'b0;
2265
end
2266 38 mohor
 
2267 40 mohor
// Generation of the end-of-frame signal
2268
always @ (posedge WB_CLK_I or posedge Reset)
2269 38 mohor
begin
2270 40 mohor
  if(Reset)
2271
    ShiftEnded <=#Tp 1'b0;
2272 38 mohor
  else
2273 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2274 40 mohor
    ShiftEnded <=#Tp 1'b1;
2275 38 mohor
  else
2276 40 mohor
  if(RxStatusWrite)
2277
    ShiftEnded <=#Tp 1'b0;
2278 38 mohor
end
2279
 
2280 118 mohor
always @ (posedge MRxClk or posedge Reset)
2281
begin
2282
  if(Reset)
2283
    ShiftEndedSync_c1 <=#Tp 1'b0;
2284
  else
2285
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
2286
end
2287 38 mohor
 
2288 118 mohor
always @ (posedge MRxClk or posedge Reset)
2289
begin
2290
  if(Reset)
2291
    ShiftEndedSync_c2 <=#Tp 1'b0;
2292
  else
2293
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
2294
end
2295
 
2296 40 mohor
// Generation of the end-of-frame signal
2297
always @ (posedge MRxClk or posedge Reset)
2298 38 mohor
begin
2299 40 mohor
  if(Reset)
2300
    RxEnableWindow <=#Tp 1'b0;
2301 38 mohor
  else
2302 40 mohor
  if(RxStartFrm)
2303
    RxEnableWindow <=#Tp 1'b1;
2304 38 mohor
  else
2305 40 mohor
  if(RxEndFrm | RxAbort)
2306
    RxEnableWindow <=#Tp 1'b0;
2307 38 mohor
end
2308
 
2309
 
2310 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2311 38 mohor
begin
2312 40 mohor
  if(Reset)
2313
    RxAbortSync1 <=#Tp 1'b0;
2314 38 mohor
  else
2315 150 mohor
    RxAbortSync1 <=#Tp RxAbortLatched;
2316 40 mohor
end
2317
 
2318
always @ (posedge WB_CLK_I or posedge Reset)
2319
begin
2320
  if(Reset)
2321
    RxAbortSync2 <=#Tp 1'b0;
2322 38 mohor
  else
2323 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
2324 38 mohor
end
2325
 
2326 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2327
begin
2328
  if(Reset)
2329
    RxAbortSync3 <=#Tp 1'b0;
2330
  else
2331
    RxAbortSync3 <=#Tp RxAbortSync2;
2332
end
2333
 
2334
always @ (posedge WB_CLK_I or posedge Reset)
2335
begin
2336
  if(Reset)
2337
    RxAbortSync4 <=#Tp 1'b0;
2338
  else
2339
    RxAbortSync4 <=#Tp RxAbortSync3;
2340
end
2341
 
2342 40 mohor
always @ (posedge MRxClk or posedge Reset)
2343
begin
2344
  if(Reset)
2345
    RxAbortSyncb1 <=#Tp 1'b0;
2346
  else
2347
    RxAbortSyncb1 <=#Tp RxAbortSync2;
2348
end
2349 38 mohor
 
2350 40 mohor
always @ (posedge MRxClk or posedge Reset)
2351 38 mohor
begin
2352 40 mohor
  if(Reset)
2353
    RxAbortSyncb2 <=#Tp 1'b0;
2354 38 mohor
  else
2355 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
2356 38 mohor
end
2357
 
2358
 
2359 64 mohor
always @ (posedge MRxClk or posedge Reset)
2360
begin
2361
  if(Reset)
2362
    RxAbortLatched <=#Tp 1'b0;
2363
  else
2364 150 mohor
  if(RxAbortSyncb2)
2365
    RxAbortLatched <=#Tp 1'b0;
2366
  else
2367 64 mohor
  if(RxAbort)
2368
    RxAbortLatched <=#Tp 1'b1;
2369
end
2370 40 mohor
 
2371 64 mohor
 
2372 42 mohor
always @ (posedge MRxClk or posedge Reset)
2373
begin
2374
  if(Reset)
2375
    LatchedRxLength[15:0] <=#Tp 16'h0;
2376
  else
2377 150 mohor
  if(LoadRxStatus)
2378 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
2379
end
2380
 
2381
 
2382 261 mohor
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2383 42 mohor
 
2384
always @ (posedge MRxClk or posedge Reset)
2385
begin
2386
  if(Reset)
2387
    RxStatusInLatched <=#Tp 'h0;
2388
  else
2389 150 mohor
  if(LoadRxStatus)
2390 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
2391
end
2392
 
2393
 
2394 60 mohor
// Rx overrun
2395
always @ (posedge WB_CLK_I or posedge Reset)
2396
begin
2397
  if(Reset)
2398
    RxOverrun <=#Tp 1'b0;
2399
  else
2400
  if(RxStatusWrite)
2401
    RxOverrun <=#Tp 1'b0;
2402
  else
2403
  if(RxBufferFull & WriteRxDataToFifo_wb)
2404
    RxOverrun <=#Tp 1'b1;
2405
end
2406 48 mohor
 
2407 77 mohor
 
2408
 
2409
wire TxError;
2410
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2411
 
2412
wire RxError;
2413
 
2414 239 tadejm
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
2415 250 mohor
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
2416
// AddressMiss is identifying that a frame was received because of the promiscous
2417
// mode and is not an error
2418 239 tadejm
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
2419
 
2420 272 tadejm
 
2421
 
2422
reg RxStatusWriteLatched;
2423
reg RxStatusWriteLatched_sync1;
2424
reg RxStatusWriteLatched_sync2;
2425
reg RxStatusWriteLatched_syncb1;
2426
reg RxStatusWriteLatched_syncb2;
2427
 
2428
 
2429
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
2430
always @ (posedge WB_CLK_I or posedge Reset)
2431
begin
2432
  if(Reset)
2433
    RxStatusWriteLatched <=#Tp 1'b0;
2434
  else
2435
  if(RxStatusWriteLatched_syncb2)
2436
    RxStatusWriteLatched <=#Tp 1'b0;
2437
  else
2438
  if(RxStatusWrite)
2439
    RxStatusWriteLatched <=#Tp 1'b1;
2440
end
2441
 
2442
 
2443
always @ (posedge MRxClk or posedge Reset)
2444
begin
2445
  if(Reset)
2446
    begin
2447
      RxStatusWriteLatched_sync1 <=#Tp 1'b0;
2448
      RxStatusWriteLatched_sync2 <=#Tp 1'b0;
2449
    end
2450
  else
2451
    begin
2452
      RxStatusWriteLatched_sync1 <=#Tp RxStatusWriteLatched;
2453
      RxStatusWriteLatched_sync2 <=#Tp RxStatusWriteLatched_sync1;
2454
    end
2455
end
2456
 
2457
 
2458
always @ (posedge WB_CLK_I or posedge Reset)
2459
begin
2460
  if(Reset)
2461
    begin
2462
      RxStatusWriteLatched_syncb1 <=#Tp 1'b0;
2463
      RxStatusWriteLatched_syncb2 <=#Tp 1'b0;
2464
    end
2465
  else
2466
    begin
2467
      RxStatusWriteLatched_syncb1 <=#Tp RxStatusWriteLatched_sync2;
2468
      RxStatusWriteLatched_syncb2 <=#Tp RxStatusWriteLatched_syncb1;
2469
    end
2470
end
2471
 
2472
 
2473
 
2474 77 mohor
// Tx Done Interrupt
2475
always @ (posedge WB_CLK_I or posedge Reset)
2476
begin
2477
  if(Reset)
2478
    TxB_IRQ <=#Tp 1'b0;
2479
  else
2480
  if(TxStatusWrite & TxIRQEn)
2481
    TxB_IRQ <=#Tp ~TxError;
2482
  else
2483
    TxB_IRQ <=#Tp 1'b0;
2484
end
2485
 
2486
 
2487
// Tx Error Interrupt
2488
always @ (posedge WB_CLK_I or posedge Reset)
2489
begin
2490
  if(Reset)
2491
    TxE_IRQ <=#Tp 1'b0;
2492
  else
2493
  if(TxStatusWrite & TxIRQEn)
2494
    TxE_IRQ <=#Tp TxError;
2495
  else
2496
    TxE_IRQ <=#Tp 1'b0;
2497
end
2498
 
2499
 
2500
// Rx Done Interrupt
2501
always @ (posedge WB_CLK_I or posedge Reset)
2502
begin
2503
  if(Reset)
2504
    RxB_IRQ <=#Tp 1'b0;
2505
  else
2506 270 mohor
  if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
2507
    RxB_IRQ <=#Tp (~RxError);
2508 77 mohor
  else
2509
    RxB_IRQ <=#Tp 1'b0;
2510
end
2511
 
2512
 
2513
// Rx Error Interrupt
2514
always @ (posedge WB_CLK_I or posedge Reset)
2515
begin
2516
  if(Reset)
2517
    RxE_IRQ <=#Tp 1'b0;
2518
  else
2519 270 mohor
  if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
2520 77 mohor
    RxE_IRQ <=#Tp RxError;
2521
  else
2522
    RxE_IRQ <=#Tp 1'b0;
2523
end
2524
 
2525
 
2526 166 mohor
// Busy Interrupt
2527 77 mohor
 
2528 166 mohor
reg Busy_IRQ_rck;
2529
reg Busy_IRQ_sync1;
2530
reg Busy_IRQ_sync2;
2531
reg Busy_IRQ_sync3;
2532
reg Busy_IRQ_syncb1;
2533
reg Busy_IRQ_syncb2;
2534 77 mohor
 
2535
 
2536 166 mohor
always @ (posedge MRxClk or posedge Reset)
2537
begin
2538
  if(Reset)
2539
    Busy_IRQ_rck <=#Tp 1'b0;
2540
  else
2541
  if(RxValid & RxStartFrm & ~RxReady)
2542
    Busy_IRQ_rck <=#Tp 1'b1;
2543
  else
2544
  if(Busy_IRQ_syncb2)
2545
    Busy_IRQ_rck <=#Tp 1'b0;
2546
end
2547 77 mohor
 
2548 166 mohor
always @ (posedge WB_CLK_I)
2549
begin
2550
    Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
2551
    Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
2552
    Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
2553
end
2554
 
2555
always @ (posedge MRxClk)
2556
begin
2557
    Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
2558
    Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
2559
end
2560
 
2561
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
2562
 
2563
 
2564 60 mohor
 
2565
 
2566
 
2567 38 mohor
endmodule

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