OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 354

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 38 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 333 igorm
// Revision 1.57  2005/02/21 11:35:33  igorm
45
// Defer indication fixed.
46
//
47 329 igorm
// Revision 1.56  2004/04/30 10:30:00  igorm
48
// Accidently deleted line put back.
49
//
50 323 igorm
// Revision 1.55  2004/04/26 15:26:23  igorm
51
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
52
//   previous update of the core.
53
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
54
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
55
//   register. (thanks to Mathias and Torbjorn)
56
// - Multicast reception was fixed. Thanks to Ulrich Gries
57
//
58 321 igorm
// Revision 1.54  2003/11/12 18:24:59  tadejm
59
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
60
//
61 304 tadejm
// Revision 1.53  2003/10/17 07:46:17  markom
62
// mbist signals updated according to newest convention
63
//
64 302 markom
// Revision 1.52  2003/01/30 14:51:31  mohor
65
// Reset has priority in some flipflops.
66
//
67 280 mohor
// Revision 1.51  2003/01/30 13:36:22  mohor
68
// A new bug (entered with previous update) fixed. When abort occured sometimes
69
// data transmission was blocked.
70
//
71 278 mohor
// Revision 1.50  2003/01/22 13:49:26  tadejm
72
// When control packets were received, they were ignored in some cases.
73
//
74 272 tadejm
// Revision 1.49  2003/01/21 12:09:40  mohor
75
// When receiving normal data frame and RxFlow control was switched on, RXB
76
// interrupt was not set.
77
//
78 270 mohor
// Revision 1.48  2003/01/20 12:05:26  mohor
79
// When in full duplex, transmit was sometimes blocked. Fixed.
80
//
81 269 mohor
// Revision 1.47  2002/11/22 13:26:21  mohor
82
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
83
// anywhere. Removed.
84
//
85 264 mohor
// Revision 1.46  2002/11/22 01:57:06  mohor
86
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
87
// synchronized.
88
//
89 261 mohor
// Revision 1.45  2002/11/19 17:33:34  mohor
90
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
91
// that a frame was received because of the promiscous mode.
92
//
93 250 mohor
// Revision 1.44  2002/11/13 22:21:40  tadejm
94
// RxError is not generated when small frame reception is enabled and small
95
// frames are received.
96
//
97 239 tadejm
// Revision 1.43  2002/10/18 20:53:34  mohor
98
// case changed to casex.
99
//
100 229 mohor
// Revision 1.42  2002/10/18 17:04:20  tadejm
101
// Changed BIST scan signals.
102
//
103 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
104
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
105
//
106 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
107
// TxStatus is written after last access to the TX fifo is finished (in case of abort
108
// or retry). TxDone is fixed.
109
//
110 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
111
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
112
// TxDone and TxRetry are generated after the current WISHBONE access is
113
// finished.
114
//
115 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
116
// BIST added.
117
//
118 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
119
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
120
//
121 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
122
// Reception is possible after RxPointer is read and not after BD is read. For
123
// that reason RxBDReady is changed to RxReady.
124
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
125
// comes, interrupt is generated.
126
//
127 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
128
// Ethernet debug registers removed.
129
//
130 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
131
// Async reset for WB_ACK_O removed (when core was in reset, it was
132
// impossible to access BDs).
133
// RxPointers and TxPointers names changed to be more descriptive.
134
// TxUnderRun synchronized.
135
//
136 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
137
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
138
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
139
// was not used OK.
140
//
141 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
142
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
143
// need to multiply or devide any more.
144
//
145 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
146
// WriteRxDataToMemory signal changed so end of frame (when last word is
147
// written to fifo) is changed.
148
//
149 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
150
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
151
//
152 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
153
// ShiftEnded synchronization changed.
154
//
155 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
156
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
157
//
158 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
159
// RxPointer bug fixed.
160
//
161 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
162
// Previous bug wasn't succesfully removed. Now fixed.
163
//
164 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
165
// Master state machine had a bug when switching from master write to
166
// master read.
167
//
168 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
169
// m_wb_cyc_o signal released after every single transfer.
170
//
171 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
172
// Outputs registered. Reset changed for eth_wishbone module.
173
//
174 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
175
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
176
// bug fixed.
177
//
178 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
179
// Small typo fixed.
180
//
181 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
182
// Any address can be used for Tx and Rx BD pointers. Address does not need
183
// to be aligned.
184
//
185 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
186
// Comments in Slovene language removed.
187
//
188 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
189
// casex changed with case, fifo reset changed.
190
//
191 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
192
// rx_fifo was not always cleared ok. Fixed.
193
//
194 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
195
// Status was not latched correctly sometimes. Fixed.
196
//
197 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
198
// Big Endian problem when sending frames fixed.
199
//
200 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
201
// Byte ordering changed (Big Endian used). casex changed with case because
202
// Xilinx Foundation had problems. Tested in HW. It WORKS.
203
//
204 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
205
// Small fixes for external/internal DMA missmatches.
206
//
207 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
208
// Interrupts changed
209
//
210 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
211
// Status was not written correctly when frames were discarted because of
212
// address mismatch.
213
//
214 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
215
// RxStartFrm cleared when abort or retry comes.
216
//
217 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
218
// Changes that were lost when updating from 1.5 to 1.8 fixed.
219
//
220 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
221
// Addition  of new module eth_addrcheck.v
222
//
223
// Revision 1.7  2002/02/12 17:03:47  mohor
224
// RxOverRun added to statuses.
225
//
226
// Revision 1.6  2002/02/11 09:18:22  mohor
227
// Tx status is written back to the BD.
228
//
229 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
230
// Rx status is written back to the BD.
231
//
232 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
233
// non-DMA host interface added. Select the right configutation in eth_defines.
234
//
235 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
236
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
237
// MHz. Statuses, overrun, control frame transmission and reception still  need
238
// to be fixed.
239
//
240 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
241
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
242
// added.
243
//
244 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
245
// Initial version. Equals to eth_wishbonedma.v at this moment.
246 38 mohor
//
247
//
248
//
249
 
250
`include "eth_defines.v"
251
`include "timescale.v"
252
 
253
 
254
module eth_wishbone
255 354 olof
  (
256 38 mohor
 
257 354 olof
   // WISHBONE common
258
   WB_CLK_I, WB_DAT_I, WB_DAT_O,
259 38 mohor
 
260 354 olof
   // WISHBONE slave
261
   WB_ADR_I, WB_WE_I, WB_ACK_O,
262
   BDCs,
263 38 mohor
 
264 354 olof
   Reset,
265 40 mohor
 
266 354 olof
   // WISHBONE master
267
   m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
268
   m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
269
   m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
270 39 mohor
 
271 219 mohor
`ifdef ETH_WISHBONE_B3
272 354 olof
   m_wb_cti_o, m_wb_bte_o,
273 219 mohor
`endif
274
 
275 354 olof
   //TX
276
   MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
277
   TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
278
   PerPacketPad,
279 38 mohor
 
280 354 olof
   //RX
281
   MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
282
   RxStatusWriteLatched_sync2,
283
 
284
   // Register
285
   r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
286 38 mohor
 
287 354 olof
   // Interrupts
288
   TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
289
 
290
   // Rx Status
291
   InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
292
   ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
293
   AddressMiss,
294
   ReceivedPauseFrm,
295
 
296
   // Tx Status
297
   RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched,
298
   CarrierSenseLost
299 164 mohor
 
300 354 olof
   // Bist
301 210 mohor
`ifdef ETH_BIST
302 354 olof
   ,
303
   // debug chain signals
304
   mbist_si_i,       // bist scan serial in
305
   mbist_so_o,       // bist scan serial out
306
   mbist_ctrl_i        // bist chain shift control
307 210 mohor
`endif
308
 
309
 
310 38 mohor
 
311 354 olof
   );
312 38 mohor
 
313 349 olof
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
314
parameter TX_FIFO_DEPTH      = `ETH_TX_FIFO_DEPTH;
315
parameter TX_FIFO_CNT_WIDTH  = `ETH_TX_FIFO_CNT_WIDTH;
316
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
317
parameter RX_FIFO_DEPTH      = `ETH_RX_FIFO_DEPTH;
318
parameter RX_FIFO_CNT_WIDTH  = `ETH_RX_FIFO_CNT_WIDTH;
319 38 mohor
 
320
// WISHBONE common
321
input           WB_CLK_I;       // WISHBONE clock
322
input  [31:0]   WB_DAT_I;       // WISHBONE data input
323
output [31:0]   WB_DAT_O;       // WISHBONE data output
324
 
325
// WISHBONE slave
326
input   [9:2]   WB_ADR_I;       // WISHBONE address input
327
input           WB_WE_I;        // WISHBONE write enable input
328 304 tadejm
input   [3:0]   BDCs;           // Buffer descriptors are selected
329 38 mohor
output          WB_ACK_O;       // WISHBONE acknowledge output
330
 
331 39 mohor
// WISHBONE master
332 329 igorm
output  [29:0]  m_wb_adr_o;     // 
333 39 mohor
output   [3:0]  m_wb_sel_o;     // 
334
output          m_wb_we_o;      // 
335
output  [31:0]  m_wb_dat_o;     // 
336
output          m_wb_cyc_o;     // 
337
output          m_wb_stb_o;     // 
338
input   [31:0]  m_wb_dat_i;     // 
339
input           m_wb_ack_i;     // 
340
input           m_wb_err_i;     // 
341
 
342 219 mohor
`ifdef ETH_WISHBONE_B3
343
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
344
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
345
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
346
`endif
347
 
348 40 mohor
input           Reset;       // Reset signal
349 39 mohor
 
350 60 mohor
// Rx Status signals
351 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
352
input           LatchedCrcError;  // CRC error
353
input           RxLateCollision;  // Late collision occured while receiving frame
354 354 olof
input           ShortFrame;       // Frame shorter then the minimum size
355
                                  // (r_MinFL) was received while small
356
                                  // packets are enabled (r_RecSmall)
357 42 mohor
input           DribbleNibble;    // Extra nibble received
358
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
359
input    [15:0] RxLength;         // Length of the incoming frame
360
input           LoadRxStatus;     // Rx status was loaded
361 354 olof
input           ReceivedPacketGood;  // Received packet's length and CRC are
362
                                     // good
363
input           AddressMiss;      // When a packet is received AddressMiss
364
                                  // status is written to the Rx BD
365 261 mohor
input           r_RxFlow;
366 270 mohor
input           r_PassAll;
367 261 mohor
input           ReceivedPauseFrm;
368 39 mohor
 
369 60 mohor
// Tx Status signals
370
input     [3:0] RetryCntLatched;  // Latched Retry Counter
371 354 olof
input           RetryLimit;       // Retry limit reached (Retry Max value +1
372
                                  // attempts were made)
373 60 mohor
input           LateCollLatched;  // Late collision occured
374 354 olof
input           DeferLatched;     // Defer indication (Frame was defered
375
                                  // before sucessfully sent)
376 329 igorm
output          RstDeferLatched;
377 354 olof
input           CarrierSenseLost; // Carrier Sense was lost during the
378
                                  // frame transmission
379 60 mohor
 
380 38 mohor
// Tx
381
input           MTxClk;         // Transmit clock (from PHY)
382
input           TxUsedData;     // Transmit packet used data
383
input           TxRetry;        // Transmit packet retry
384
input           TxAbort;        // Transmit packet abort
385
input           TxDone;         // Transmission ended
386
output          TxStartFrm;     // Transmit packet start frame
387
output          TxEndFrm;       // Transmit packet end frame
388
output  [7:0]   TxData;         // Transmit packet data byte
389
output          TxUnderRun;     // Transmit packet under-run
390
output          PerPacketCrcEn; // Per packet crc enable
391
output          PerPacketPad;   // Per packet pading
392
 
393
// Rx
394
input           MRxClk;         // Receive clock (from PHY)
395
input   [7:0]   RxData;         // Received data byte (from PHY)
396
input           RxValid;        // 
397
input           RxStartFrm;     // 
398
input           RxEndFrm;       // 
399 354 olof
input           RxAbort;        // This signal is set when address doesn't
400
                                // match.
401 272 tadejm
output          RxStatusWriteLatched_sync2;
402 38 mohor
 
403
//Register
404
input           r_TxEn;         // Transmit enable
405
input           r_RxEn;         // Receive enable
406
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
407
 
408
// Interrupts
409
output TxB_IRQ;
410
output TxE_IRQ;
411
output RxB_IRQ;
412 77 mohor
output RxE_IRQ;
413 38 mohor
output Busy_IRQ;
414
 
415 77 mohor
 
416 210 mohor
// Bist
417
`ifdef ETH_BIST
418 302 markom
input   mbist_si_i;       // bist scan serial in
419
output  mbist_so_o;       // bist scan serial out
420 354 olof
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
421 210 mohor
`endif
422
 
423 77 mohor
reg TxB_IRQ;
424
reg TxE_IRQ;
425
reg RxB_IRQ;
426
reg RxE_IRQ;
427
 
428 38 mohor
reg             TxStartFrm;
429
reg             TxEndFrm;
430
reg     [7:0]   TxData;
431
 
432
reg             TxUnderRun;
433 60 mohor
reg             TxUnderRun_wb;
434 38 mohor
 
435
reg             TxBDRead;
436 39 mohor
wire            TxStatusWrite;
437 38 mohor
 
438
reg     [1:0]   TxValidBytesLatched;
439
 
440
reg    [15:0]   TxLength;
441 60 mohor
reg    [15:0]   LatchedTxLength;
442
reg   [14:11]   TxStatus;
443 38 mohor
 
444 60 mohor
reg   [14:13]   RxStatus;
445 38 mohor
 
446
reg             TxStartFrm_wb;
447
reg             TxRetry_wb;
448 39 mohor
reg             TxAbort_wb;
449 38 mohor
reg             TxDone_wb;
450
 
451
reg             TxDone_wb_q;
452
reg             TxAbort_wb_q;
453 39 mohor
reg             TxRetry_wb_q;
454 219 mohor
reg             TxRetryPacket;
455 221 mohor
reg             TxRetryPacket_NotCleared;
456
reg             TxDonePacket;
457
reg             TxDonePacket_NotCleared;
458 219 mohor
reg             TxAbortPacket;
459 221 mohor
reg             TxAbortPacket_NotCleared;
460 38 mohor
reg             RxBDReady;
461 166 mohor
reg             RxReady;
462 38 mohor
reg             TxBDReady;
463
 
464
reg             RxBDRead;
465
 
466
reg    [31:0]   TxDataLatched;
467
reg     [1:0]   TxByteCnt;
468
reg             LastWord;
469 39 mohor
reg             ReadTxDataFromFifo_tck;
470 38 mohor
 
471
reg             BlockingTxStatusWrite;
472
reg             BlockingTxBDRead;
473
 
474 40 mohor
reg             Flop;
475 38 mohor
 
476 329 igorm
reg     [7:1]   TxBDAddress;
477
reg     [7:1]   RxBDAddress;
478 38 mohor
 
479
reg             TxRetrySync1;
480
reg             TxAbortSync1;
481 39 mohor
reg             TxDoneSync1;
482 38 mohor
 
483
reg             TxAbort_q;
484
reg             TxRetry_q;
485
reg             TxUsedData_q;
486
 
487
reg    [31:0]   RxDataLatched2;
488 82 mohor
 
489
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
490
 
491 38 mohor
reg     [1:0]   RxValidBytes;
492
reg     [1:0]   RxByteCnt;
493
reg             LastByteIn;
494
reg             ShiftWillEnd;
495
 
496 40 mohor
reg             WriteRxDataToFifo;
497 42 mohor
reg    [15:0]   LatchedRxLength;
498 64 mohor
reg             RxAbortLatched;
499 38 mohor
 
500 40 mohor
reg             ShiftEnded;
501 60 mohor
reg             RxOverrun;
502 38 mohor
 
503 304 tadejm
reg     [3:0]   BDWrite;                    // BD Write Enable for access from WISHBONE side
504 40 mohor
reg             BDRead;                     // BD Read access from WISHBONE side
505 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
506
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
507 38 mohor
 
508 39 mohor
reg             TxEndFrm_wb;
509 38 mohor
 
510 39 mohor
wire            TxRetryPulse;
511 38 mohor
wire            TxDonePulse;
512
wire            TxAbortPulse;
513
 
514
wire            StartRxBDRead;
515
 
516
wire            StartTxBDRead;
517
 
518
wire            TxIRQEn;
519
wire            WrapTxStatusBit;
520
 
521 77 mohor
wire            RxIRQEn;
522 38 mohor
wire            WrapRxStatusBit;
523
 
524
wire    [1:0]   TxValidBytes;
525
 
526 329 igorm
wire    [7:1]   TempTxBDAddress;
527
wire    [7:1]   TempRxBDAddress;
528 38 mohor
 
529 272 tadejm
wire            RxStatusWrite;
530 329 igorm
wire            RxBufferFull;
531
wire            RxBufferAlmostEmpty;
532
wire            RxBufferEmpty;
533 272 tadejm
 
534 106 mohor
reg             WB_ACK_O;
535 38 mohor
 
536 261 mohor
wire    [8:0]   RxStatusIn;
537
reg     [8:0]   RxStatusInLatched;
538 42 mohor
 
539 39 mohor
reg WbEn, WbEn_q;
540
reg RxEn, RxEn_q;
541
reg TxEn, TxEn_q;
542 321 igorm
reg r_TxEn_q;
543
reg r_RxEn_q;
544 38 mohor
 
545 39 mohor
wire ram_ce;
546 304 tadejm
wire [3:0]  ram_we;
547 39 mohor
wire ram_oe;
548
reg [7:0]   ram_addr;
549
reg [31:0]  ram_di;
550
wire [31:0] ram_do;
551 38 mohor
 
552 39 mohor
wire StartTxPointerRead;
553 354 olof
reg TxPointerRead;
554 39 mohor
reg TxEn_needed;
555 40 mohor
reg RxEn_needed;
556 38 mohor
 
557 40 mohor
wire StartRxPointerRead;
558
reg RxPointerRead;
559 38 mohor
 
560 354 olof
// RX shift ending signals
561
reg ShiftEnded_rck;
562
reg ShiftEndedSync1;
563
reg ShiftEndedSync2;
564
reg ShiftEndedSync3;
565
reg ShiftEndedSync_c1;
566
reg ShiftEndedSync_c2;
567
 
568
wire StartShiftWillEnd;
569
 
570
reg StartOccured;
571
reg TxStartFrm_sync1;
572
reg TxStartFrm_sync2;
573
reg TxStartFrm_syncb1;
574
reg TxStartFrm_syncb2;
575
 
576
wire TxFifoClear;
577
wire TxBufferAlmostFull;
578
wire TxBufferFull;
579
wire TxBufferEmpty;
580
wire TxBufferAlmostEmpty;
581
wire SetReadTxDataFromMemory;
582
reg BlockReadTxDataFromMemory;
583
 
584
reg tx_burst_en;
585
reg rx_burst_en;
586
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
587
 
588
wire ReadTxDataFromMemory_2;
589
wire tx_burst;
590
 
591
wire [31:0] TxData_wb;
592
wire ReadTxDataFromFifo_wb;
593
 
594
wire [TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
595
wire [RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
596
 
597
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
598
 
599
wire rx_burst;
600
wire enough_data_in_rxfifo_for_burst;
601
wire enough_data_in_rxfifo_for_burst_plus1;
602
 
603
reg ReadTxDataFromMemory;
604
wire WriteRxDataToMemory;
605
 
606
reg MasterWbTX;
607
reg MasterWbRX;
608
 
609
reg [29:0] m_wb_adr_o;
610
reg        m_wb_cyc_o;
611
reg  [3:0] m_wb_sel_o;
612
reg        m_wb_we_o;
613
 
614
wire TxLengthEq0;
615
wire TxLengthLt4;
616
 
617
reg BlockingIncrementTxPointer;
618
reg [31:2] TxPointerMSB;
619
reg [1:0]  TxPointerLSB;
620
reg [1:0]  TxPointerLSB_rst;
621
reg [31:2] RxPointerMSB;
622
reg [1:0]  RxPointerLSB_rst;
623
 
624
wire RxBurstAcc;
625
wire RxWordAcc;
626
wire RxHalfAcc;
627
wire RxByteAcc;
628
 
629
wire ResetTxBDReady;
630
reg BlockingTxStatusWrite_sync1;
631
reg BlockingTxStatusWrite_sync2;
632
reg BlockingTxStatusWrite_sync3;
633
 
634
reg cyc_cleared;
635
reg IncrTxPointer;
636
 
637
reg  [3:0] RxByteSel;
638
wire MasterAccessFinished;
639
 
640
reg LatchValidBytes;
641
reg LatchValidBytes_q;
642
 
643
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
644
reg ReadTxDataFromFifo_sync1;
645
reg ReadTxDataFromFifo_sync2;
646
reg ReadTxDataFromFifo_sync3;
647
reg ReadTxDataFromFifo_syncb1;
648
reg ReadTxDataFromFifo_syncb2;
649
reg ReadTxDataFromFifo_syncb3;
650
 
651
reg RxAbortSync1;
652
reg RxAbortSync2;
653
reg RxAbortSync3;
654
reg RxAbortSync4;
655
reg RxAbortSyncb1;
656
reg RxAbortSyncb2;
657
 
658
reg RxEnableWindow;
659
 
660
wire SetWriteRxDataToFifo;
661
 
662
reg WriteRxDataToFifoSync1;
663
reg WriteRxDataToFifoSync2;
664
reg WriteRxDataToFifoSync3;
665
 
666
wire WriteRxDataToFifo_wb;
667
 
668
reg LatchedRxStartFrm;
669
reg SyncRxStartFrm;
670
reg SyncRxStartFrm_q;
671
reg SyncRxStartFrm_q2;
672
wire RxFifoReset;
673
 
674
wire TxError;
675
wire RxError;
676
 
677
reg RxStatusWriteLatched;
678
reg RxStatusWriteLatched_sync1;
679
reg RxStatusWriteLatched_sync2;
680
reg RxStatusWriteLatched_syncb1;
681
reg RxStatusWriteLatched_syncb2;
682
 
683 219 mohor
`ifdef ETH_WISHBONE_B3
684
assign m_wb_bte_o = 2'b00;    // Linear burst
685
`endif
686 39 mohor
 
687 329 igorm
assign m_wb_stb_o = m_wb_cyc_o;
688 219 mohor
 
689 159 mohor
always @ (posedge WB_CLK_I)
690 40 mohor
begin
691 352 olof
  WB_ACK_O <= (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
692 40 mohor
end
693 39 mohor
 
694 106 mohor
assign WB_DAT_O = ram_do;
695 39 mohor
 
696 41 mohor
// Generic synchronous single-port RAM interface
697 354 olof
eth_spram_256x32
698
     bd_ram
699
     (
700
      .clk     (WB_CLK_I),
701
      .rst     (Reset),
702
      .ce      (ram_ce),
703
      .we      (ram_we),
704
      .oe      (ram_oe),
705
      .addr    (ram_addr),
706
      .di      (ram_di),
707
      .do      (ram_do)
708 210 mohor
`ifdef ETH_BIST
709 354 olof
      ,
710
      .mbist_si_i       (mbist_si_i),
711
      .mbist_so_o       (mbist_so_o),
712
      .mbist_ctrl_i       (mbist_ctrl_i)
713 210 mohor
`endif
714 354 olof
      );
715 41 mohor
 
716 39 mohor
assign ram_ce = 1'b1;
717 354 olof
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) |
718
                {4{(TxStatusWrite | RxStatusWrite)}};
719
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q &
720
                (TxBDRead | TxPointerRead) | RxEn & RxEn_q &
721
                (RxBDRead | RxPointerRead);
722 39 mohor
 
723
 
724 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
725 38 mohor
begin
726 40 mohor
  if(Reset)
727 352 olof
    TxEn_needed <= 1'b0;
728 38 mohor
  else
729 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
730 352 olof
    TxEn_needed <= 1'b1;
731 39 mohor
  else
732
  if(TxPointerRead & TxEn & TxEn_q)
733 352 olof
    TxEn_needed <= 1'b0;
734 38 mohor
end
735
 
736 39 mohor
// Enabling access to the RAM for three devices.
737 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
738 39 mohor
begin
739 40 mohor
  if(Reset)
740 39 mohor
    begin
741 352 olof
      WbEn <= 1'b1;
742
      RxEn <= 1'b0;
743
      TxEn <= 1'b0;
744
      ram_addr <= 8'h0;
745
      ram_di <= 32'h0;
746
      BDRead <= 1'b0;
747
      BDWrite <= 1'b0;
748 39 mohor
    end
749
  else
750
    begin
751
      // Switching between three stages depends on enable signals
752 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
753
        5'b100_10, 5'b100_11 :
754 39 mohor
          begin
755 352 olof
            WbEn <= 1'b0;
756
            RxEn <= 1'b1;  // wb access stage and r_RxEn is enabled
757
            TxEn <= 1'b0;
758
            ram_addr <= {RxBDAddress, RxPointerRead};
759
            ram_di <= RxBDDataIn;
760 39 mohor
          end
761
        5'b100_01 :
762
          begin
763 352 olof
            WbEn <= 1'b0;
764
            RxEn <= 1'b0;
765 354 olof
            TxEn <= 1'b1;  // wb access stage, r_RxEn is disabled but
766
                           // r_TxEn is enabled
767 352 olof
            ram_addr <= {TxBDAddress, TxPointerRead};
768
            ram_di <= TxBDDataIn;
769 39 mohor
          end
770 90 mohor
        5'b010_00, 5'b010_10 :
771 39 mohor
          begin
772 352 olof
            WbEn <= 1'b1;  // RxEn access stage and r_TxEn is disabled
773
            RxEn <= 1'b0;
774
            TxEn <= 1'b0;
775
            ram_addr <= WB_ADR_I[9:2];
776
            ram_di <= WB_DAT_I;
777
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
778
            BDRead <= (|BDCs) & ~WB_WE_I;
779 39 mohor
          end
780 90 mohor
        5'b010_01, 5'b010_11 :
781 39 mohor
          begin
782 352 olof
            WbEn <= 1'b0;
783
            RxEn <= 1'b0;
784
            TxEn <= 1'b1;  // RxEn access stage and r_TxEn is enabled
785
            ram_addr <= {TxBDAddress, TxPointerRead};
786
            ram_di <= TxBDDataIn;
787 39 mohor
          end
788 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
789 39 mohor
          begin
790 354 olof
            WbEn <= 1'b1;  // TxEn access stage (we always go to wb
791
                           // access stage)
792 352 olof
            RxEn <= 1'b0;
793
            TxEn <= 1'b0;
794
            ram_addr <= WB_ADR_I[9:2];
795
            ram_di <= WB_DAT_I;
796
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
797
            BDRead <= (|BDCs) & ~WB_WE_I;
798 39 mohor
          end
799
        5'b100_00 :
800
          begin
801 354 olof
            WbEn <= 1'b0;  // WbEn access stage and there is no need
802
                           // for other stages. WbEn needs to be
803
                           // switched off for a bit
804 39 mohor
          end
805
        5'b000_00 :
806
          begin
807 352 olof
            WbEn <= 1'b1;  // Idle state. We go to WbEn access stage.
808
            RxEn <= 1'b0;
809
            TxEn <= 1'b0;
810
            ram_addr <= WB_ADR_I[9:2];
811
            ram_di <= WB_DAT_I;
812
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
813
            BDRead <= (|BDCs) & ~WB_WE_I;
814 39 mohor
          end
815
      endcase
816
    end
817
end
818
 
819
 
820
// Delayed stage signals
821 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
822 39 mohor
begin
823 40 mohor
  if(Reset)
824 39 mohor
    begin
825 352 olof
      WbEn_q <= 1'b0;
826
      RxEn_q <= 1'b0;
827
      TxEn_q <= 1'b0;
828
      r_TxEn_q <= 1'b0;
829
      r_RxEn_q <= 1'b0;
830 39 mohor
    end
831
  else
832
    begin
833 352 olof
      WbEn_q <= WbEn;
834
      RxEn_q <= RxEn;
835
      TxEn_q <= TxEn;
836
      r_TxEn_q <= r_TxEn;
837
      r_RxEn_q <= r_RxEn;
838 39 mohor
    end
839
end
840
 
841 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
842 40 mohor
always @ (posedge MTxClk or posedge Reset)
843 38 mohor
begin
844 40 mohor
  if(Reset)
845 352 olof
    Flop <= 1'b0;
846 38 mohor
  else
847
  if(TxDone | TxAbort | TxRetry_q)
848 352 olof
    Flop <= 1'b0;
849 38 mohor
  else
850
  if(TxUsedData)
851 352 olof
    Flop <= ~Flop;
852 38 mohor
end
853
 
854 39 mohor
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
855 38 mohor
 
856
// Latching READY status of the Tx buffer descriptor
857 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
858 38 mohor
begin
859 40 mohor
  if(Reset)
860 352 olof
    TxBDReady <= 1'b0;
861 38 mohor
  else
862 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
863 354 olof
    // TxBDReady is sampled only once at the beginning.
864
    TxBDReady <= ram_do[15] & (ram_do[31:16] > 4);
865
  else
866
  // Only packets larger then 4 bytes are transmitted.
867 39 mohor
  if(ResetTxBDReady)
868 352 olof
    TxBDReady <= 1'b0;
869 38 mohor
end
870
 
871 39 mohor
// Reading the Tx buffer descriptor
872 354 olof
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) &
873
                       ~BlockingTxBDRead & ~TxBDReady;
874 39 mohor
 
875 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
876 38 mohor
begin
877 40 mohor
  if(Reset)
878 352 olof
    TxBDRead <= 1'b1;
879 38 mohor
  else
880 110 mohor
  if(StartTxBDRead)
881 352 olof
    TxBDRead <= 1'b1;
882 38 mohor
  else
883 39 mohor
  if(TxBDReady)
884 352 olof
    TxBDRead <= 1'b0;
885 38 mohor
end
886
 
887 39 mohor
// Reading Tx BD pointer
888
assign StartTxPointerRead = TxBDRead & TxBDReady;
889 38 mohor
 
890 39 mohor
// Reading Tx BD Pointer
891 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
892 38 mohor
begin
893 40 mohor
  if(Reset)
894 352 olof
    TxPointerRead <= 1'b0;
895 38 mohor
  else
896 39 mohor
  if(StartTxPointerRead)
897 352 olof
    TxPointerRead <= 1'b1;
898 38 mohor
  else
899 39 mohor
  if(TxEn_q)
900 352 olof
    TxPointerRead <= 1'b0;
901 38 mohor
end
902
 
903
 
904 39 mohor
// Writing status back to the Tx buffer descriptor
905 354 olof
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) &
906
                       TxEn & TxEn_q & ~BlockingTxStatusWrite;
907 38 mohor
 
908
 
909 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
910 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
911 38 mohor
begin
912 40 mohor
  if(Reset)
913 352 olof
    BlockingTxStatusWrite <= 1'b0;
914 38 mohor
  else
915 272 tadejm
  if(~TxDone_wb & ~TxAbort_wb)
916 352 olof
    BlockingTxStatusWrite <= 1'b0;
917 272 tadejm
  else
918 39 mohor
  if(TxStatusWrite)
919 352 olof
    BlockingTxStatusWrite <= 1'b1;
920 38 mohor
end
921
 
922
 
923 159 mohor
// Synchronizing BlockingTxStatusWrite to MTxClk
924
always @ (posedge MTxClk or posedge Reset)
925
begin
926
  if(Reset)
927 352 olof
    BlockingTxStatusWrite_sync1 <= 1'b0;
928 159 mohor
  else
929 352 olof
    BlockingTxStatusWrite_sync1 <= BlockingTxStatusWrite;
930 159 mohor
end
931
 
932
// Synchronizing BlockingTxStatusWrite to MTxClk
933
always @ (posedge MTxClk or posedge Reset)
934
begin
935
  if(Reset)
936 352 olof
    BlockingTxStatusWrite_sync2 <= 1'b0;
937 159 mohor
  else
938 352 olof
    BlockingTxStatusWrite_sync2 <= BlockingTxStatusWrite_sync1;
939 159 mohor
end
940
 
941 329 igorm
// Synchronizing BlockingTxStatusWrite to MTxClk
942
always @ (posedge MTxClk or posedge Reset)
943
begin
944
  if(Reset)
945 352 olof
    BlockingTxStatusWrite_sync3 <= 1'b0;
946 329 igorm
  else
947 352 olof
    BlockingTxStatusWrite_sync3 <= BlockingTxStatusWrite_sync2;
948 329 igorm
end
949 159 mohor
 
950 354 olof
assign RstDeferLatched = BlockingTxStatusWrite_sync2 &
951
                         ~BlockingTxStatusWrite_sync3;
952 329 igorm
 
953 39 mohor
// TxBDRead state is activated only once. 
954 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
955 39 mohor
begin
956 40 mohor
  if(Reset)
957 352 olof
    BlockingTxBDRead <= 1'b0;
958 39 mohor
  else
959 110 mohor
  if(StartTxBDRead)
960 352 olof
    BlockingTxBDRead <= 1'b1;
961 39 mohor
  else
962 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
963 352 olof
    BlockingTxBDRead <= 1'b0;
964 39 mohor
end
965 38 mohor
 
966
 
967 39 mohor
// Latching status from the tx buffer descriptor
968 354 olof
// Data is avaliable one cycle after the access is started (at that time
969
// signal TxEn is not active)
970 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
971 38 mohor
begin
972 40 mohor
  if(Reset)
973 352 olof
    TxStatus <= 4'h0;
974 38 mohor
  else
975 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
976 352 olof
    TxStatus <= ram_do[14:11];
977 38 mohor
end
978
 
979
 
980 39 mohor
 
981
//Latching length from the buffer descriptor;
982 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
983 38 mohor
begin
984 40 mohor
  if(Reset)
985 352 olof
    TxLength <= 16'h0;
986 38 mohor
  else
987 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
988 352 olof
    TxLength <= ram_do[31:16];
989 38 mohor
  else
990 39 mohor
  if(MasterWbTX & m_wb_ack_i)
991
    begin
992
      if(TxLengthLt4)
993 352 olof
        TxLength <= 16'h0;
994 354 olof
      else if(TxPointerLSB_rst==2'h0)
995
        TxLength <= TxLength - 3'h4;    // Length is subtracted at
996
                                        // the data request
997
      else if(TxPointerLSB_rst==2'h1)
998
        TxLength <= TxLength - 3'h3;     // Length is subtracted
999
                                         // at the data request
1000
      else if(TxPointerLSB_rst==2'h2)
1001
        TxLength <= TxLength - 3'h2;     // Length is subtracted
1002
                                         // at the data request
1003
      else if(TxPointerLSB_rst==2'h3)
1004
        TxLength <= TxLength - 3'h1;     // Length is subtracted
1005
                                         // at the data request
1006 39 mohor
    end
1007 38 mohor
end
1008
 
1009 60 mohor
//Latching length from the buffer descriptor;
1010
always @ (posedge WB_CLK_I or posedge Reset)
1011
begin
1012
  if(Reset)
1013 352 olof
    LatchedTxLength <= 16'h0;
1014 60 mohor
  else
1015
  if(TxEn & TxEn_q & TxBDRead)
1016 352 olof
    LatchedTxLength <= ram_do[31:16];
1017 60 mohor
end
1018
 
1019 39 mohor
assign TxLengthEq0 = TxLength == 0;
1020
assign TxLengthLt4 = TxLength < 4;
1021 38 mohor
 
1022 39 mohor
 
1023 354 olof
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are
1024
// latched because TxPointerMSB is only used for word-aligned accesses.
1025 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1026 38 mohor
begin
1027 40 mohor
  if(Reset)
1028 352 olof
    TxPointerMSB <= 30'h0;
1029 38 mohor
  else
1030 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
1031 352 olof
    TxPointerMSB <= ram_do[31:2];
1032 38 mohor
  else
1033 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
1034 354 olof
      // TxPointer is word-aligned
1035
    TxPointerMSB <= TxPointerMSB + 1'b1;
1036 38 mohor
end
1037
 
1038 96 mohor
 
1039 354 olof
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are
1040
// performed, valid data does not necesserly start at byte 0 (could be byte
1041
// 0, 1, 2 or 3). This signals are used for proper selection of the start
1042
// byte (TxData and TxByteCnt) are set by this two bits.
1043 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1044
begin
1045
  if(Reset)
1046 352 olof
    TxPointerLSB[1:0] <= 0;
1047 96 mohor
  else
1048
  if(TxEn & TxEn_q & TxPointerRead)
1049 352 olof
    TxPointerLSB[1:0] <= ram_do[1:0];
1050 96 mohor
end
1051
 
1052
 
1053 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
1054 354 olof
// After the read access, TxLength needs to be decremented for the number of
1055
// the valid bytes (1 to 4 bytes are valid in the first word). After the
1056
// first read all bytes are valid so this two bits are reset to zero. 
1057 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1058
begin
1059
  if(Reset)
1060 352 olof
    TxPointerLSB_rst[1:0] <= 0;
1061 150 mohor
  else
1062
  if(TxEn & TxEn_q & TxPointerRead)
1063 352 olof
    TxPointerLSB_rst[1:0] <= ram_do[1:0];
1064 150 mohor
  else
1065 354 olof
// After first access pointer is word alligned
1066
  if(MasterWbTX & m_wb_ack_i)
1067 352 olof
    TxPointerLSB_rst[1:0] <= 0;
1068 150 mohor
end
1069 96 mohor
 
1070 150 mohor
 
1071 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1072 38 mohor
begin
1073 40 mohor
  if(Reset)
1074 352 olof
    BlockingIncrementTxPointer <= 0;
1075 38 mohor
  else
1076 39 mohor
  if(MasterAccessFinished)
1077 352 olof
    BlockingIncrementTxPointer <= 0;
1078 38 mohor
  else
1079 150 mohor
  if(IncrTxPointer)
1080 352 olof
    BlockingIncrementTxPointer <= 1'b1;
1081 38 mohor
end
1082
 
1083
 
1084 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
1085 39 mohor
 
1086 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1087 38 mohor
begin
1088 40 mohor
  if(Reset)
1089 352 olof
    ReadTxDataFromMemory <= 1'b0;
1090 38 mohor
  else
1091 278 mohor
  if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
1092 352 olof
    ReadTxDataFromMemory <= 1'b0;
1093 39 mohor
  else
1094 40 mohor
  if(SetReadTxDataFromMemory)
1095 352 olof
    ReadTxDataFromMemory <= 1'b1;
1096 38 mohor
end
1097
 
1098 354 olof
assign ReadTxDataFromMemory_2 = ReadTxDataFromMemory &
1099
                                ~BlockReadTxDataFromMemory;
1100 221 mohor
 
1101 354 olof
assign tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
1102 221 mohor
 
1103 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1104 38 mohor
begin
1105 40 mohor
  if(Reset)
1106 352 olof
    BlockReadTxDataFromMemory <= 1'b0;
1107 38 mohor
  else
1108 354 olof
  if((TxBufferAlmostFull | TxLength <= 4) & MasterWbTX & (~cyc_cleared) &
1109
     (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
1110 352 olof
    BlockReadTxDataFromMemory <= 1'b1;
1111 219 mohor
  else
1112 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
1113 352 olof
    BlockReadTxDataFromMemory <= 1'b0;
1114 39 mohor
end
1115
 
1116
 
1117
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
1118 159 mohor
 
1119 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
1120 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1121 39 mohor
begin
1122 40 mohor
  if(Reset)
1123 38 mohor
    begin
1124 352 olof
      MasterWbTX <= 1'b0;
1125
      MasterWbRX <= 1'b0;
1126
      m_wb_adr_o <= 30'h0;
1127
      m_wb_cyc_o <= 1'b0;
1128
      m_wb_we_o  <= 1'b0;
1129
      m_wb_sel_o <= 4'h0;
1130
      cyc_cleared<= 1'b0;
1131
      tx_burst_cnt<= 0;
1132
      rx_burst_cnt<= 0;
1133
      IncrTxPointer<= 1'b0;
1134
      tx_burst_en<= 1'b1;
1135
      rx_burst_en<= 1'b0;
1136 354 olof
`ifdef ETH_WISHBONE_B3
1137
      m_wb_cti_o <= 3'b0;
1138
`endif
1139 38 mohor
    end
1140 39 mohor
  else
1141
    begin
1142
      // Switching between two stages depends on enable signals
1143 354 olof
      casex ({MasterWbTX,
1144
             MasterWbRX,
1145
             ReadTxDataFromMemory_2,
1146
             WriteRxDataToMemory,
1147
             MasterAccessFinished,
1148
             cyc_cleared,
1149
             tx_burst,
1150
             rx_burst})  // synopsys parallel_case
1151
 
1152
        8'b00_10_00_10, // Idle and MRB needed
1153
        8'b10_1x_10_1x, // MRB continues
1154
        8'b10_10_01_10, // Clear (previously MR) and MRB needed
1155
        8'b01_1x_01_1x :// Clear (previously MW) and MRB needed
1156 39 mohor
          begin
1157 352 olof
            MasterWbTX <= 1'b1;  // tx burst
1158
            MasterWbRX <= 1'b0;
1159
            m_wb_cyc_o <= 1'b1;
1160
            m_wb_we_o  <= 1'b0;
1161
            m_wb_sel_o <= 4'hf;
1162
            cyc_cleared<= 1'b0;
1163
            IncrTxPointer<= 1'b1;
1164
            tx_burst_cnt <= tx_burst_cnt+3'h1;
1165 226 tadejm
            if(tx_burst_cnt==0)
1166 352 olof
              m_wb_adr_o <= TxPointerMSB;
1167 226 tadejm
            else
1168 354 olof
              m_wb_adr_o <= m_wb_adr_o + 1'b1;
1169 226 tadejm
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1170
              begin
1171 352 olof
                tx_burst_en<= 1'b0;
1172 354 olof
`ifdef ETH_WISHBONE_B3
1173 352 olof
                m_wb_cti_o <= 3'b111;
1174 354 olof
`endif
1175 226 tadejm
              end
1176
            else
1177
              begin
1178 354 olof
`ifdef ETH_WISHBONE_B3
1179 352 olof
                m_wb_cti_o <= 3'b010;
1180 354 olof
`endif
1181 226 tadejm
              end
1182
          end
1183 229 mohor
        8'b00_x1_00_x1,             // Idle and MWB needed
1184
        8'b01_x1_10_x1,             // MWB continues
1185 226 tadejm
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1186 229 mohor
        8'b10_x1_01_x1 :            // Clear (previously MR) and MWB needed
1187 226 tadejm
          begin
1188 352 olof
            MasterWbTX <= 1'b0;  // rx burst
1189
            MasterWbRX <= 1'b1;
1190
            m_wb_cyc_o <= 1'b1;
1191
            m_wb_we_o  <= 1'b1;
1192
            m_wb_sel_o <= RxByteSel;
1193
            IncrTxPointer<= 1'b0;
1194
            cyc_cleared<= 1'b0;
1195
            rx_burst_cnt <= rx_burst_cnt+3'h1;
1196 226 tadejm
 
1197
            if(rx_burst_cnt==0)
1198 352 olof
              m_wb_adr_o <= RxPointerMSB;
1199 226 tadejm
            else
1200 352 olof
              m_wb_adr_o <= m_wb_adr_o+1'b1;
1201 226 tadejm
 
1202
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1203
              begin
1204 352 olof
                rx_burst_en<= 1'b0;
1205 354 olof
 `ifdef ETH_WISHBONE_B3
1206 352 olof
                m_wb_cti_o <= 3'b111;
1207 354 olof
 `endif
1208 226 tadejm
              end
1209
            else
1210
              begin
1211 354 olof
 `ifdef ETH_WISHBONE_B3
1212 352 olof
                m_wb_cti_o <= 3'b010;
1213 354 olof
 `endif
1214 226 tadejm
              end
1215
          end
1216 354 olof
        8'b00_x1_00_x0 :// idle and MW is needed (data write to rx buffer)
1217 226 tadejm
          begin
1218 352 olof
            MasterWbTX <= 1'b0;
1219
            MasterWbRX <= 1'b1;
1220
            m_wb_adr_o <= RxPointerMSB;
1221
            m_wb_cyc_o <= 1'b1;
1222
            m_wb_we_o  <= 1'b1;
1223
            m_wb_sel_o <= RxByteSel;
1224
            IncrTxPointer<= 1'b0;
1225 39 mohor
          end
1226 354 olof
        8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer)
1227 39 mohor
          begin
1228 352 olof
            MasterWbTX <= 1'b1;
1229
            MasterWbRX <= 1'b0;
1230
            m_wb_adr_o <= TxPointerMSB;
1231
            m_wb_cyc_o <= 1'b1;
1232
            m_wb_we_o  <= 1'b0;
1233
            m_wb_sel_o <= 4'hf;
1234
            IncrTxPointer<= 1'b1;
1235 39 mohor
          end
1236 354 olof
        8'b10_10_01_00,// MR and MR is needed (data read from tx buffer)
1237
        8'b01_1x_01_0x  :// MW and MR is needed (data read from tx buffer)
1238 39 mohor
          begin
1239 352 olof
            MasterWbTX <= 1'b1;
1240
            MasterWbRX <= 1'b0;
1241
            m_wb_adr_o <= TxPointerMSB;
1242
            m_wb_cyc_o <= 1'b1;
1243
            m_wb_we_o  <= 1'b0;
1244
            m_wb_sel_o <= 4'hf;
1245
            cyc_cleared<= 1'b0;
1246
            IncrTxPointer<= 1'b1;
1247 39 mohor
          end
1248 354 olof
        8'b01_01_01_00,// MW and MW needed (data write to rx buffer)
1249
        8'b10_x1_01_x0  :// MR and MW is needed (data write to rx buffer)
1250 39 mohor
          begin
1251 352 olof
            MasterWbTX <= 1'b0;
1252
            MasterWbRX <= 1'b1;
1253
            m_wb_adr_o <= RxPointerMSB;
1254
            m_wb_cyc_o <= 1'b1;
1255
            m_wb_we_o  <= 1'b1;
1256
            m_wb_sel_o <= RxByteSel;
1257
            cyc_cleared<= 1'b0;
1258
            IncrTxPointer<= 1'b0;
1259 39 mohor
          end
1260 354 olof
        8'b01_01_10_00,// MW and MW needed (cycle is cleared between
1261
                      // previous and next access)
1262
        8'b01_1x_10_x0,// MW and MW or MR or MRB needed (cycle is
1263
                    // cleared between previous and next access)
1264
        8'b10_10_10_00,// MR and MR needed (cycle is cleared between
1265
                       // previous and next access)
1266
        8'b10_x1_10_0x :// MR and MR or MW or MWB (cycle is cleared
1267
                       // between previous and next access)
1268 39 mohor
          begin
1269 354 olof
            m_wb_cyc_o <= 1'b0;// whatever and master read or write is
1270
                               // needed. We need to clear m_wb_cyc_o
1271
                               // before next access is started
1272 352 olof
            cyc_cleared<= 1'b1;
1273
            IncrTxPointer<= 1'b0;
1274
            tx_burst_cnt<= 0;
1275
            tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1276
            rx_burst_cnt<= 0;
1277
            rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1278 354 olof
`ifdef ETH_WISHBONE_B3
1279 352 olof
              m_wb_cti_o <= 3'b0;
1280 354 olof
`endif
1281 110 mohor
          end
1282 354 olof
        8'bxx_00_10_00,// whatever and no master read or write is needed
1283
                       // (ack or err comes finishing previous access)
1284
        8'bxx_00_01_00 : // Between cyc_cleared request was cleared
1285 110 mohor
          begin
1286 352 olof
            MasterWbTX <= 1'b0;
1287
            MasterWbRX <= 1'b0;
1288
            m_wb_cyc_o <= 1'b0;
1289
            cyc_cleared<= 1'b0;
1290
            IncrTxPointer<= 1'b0;
1291
            rx_burst_cnt<= 0;
1292 354 olof
            // Counter is not decremented, yet, so plus1 is used.
1293
            rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 :
1294
                                       enough_data_in_rxfifo_for_burst;
1295
`ifdef ETH_WISHBONE_B3
1296
            m_wb_cti_o <= 3'b0;
1297
`endif
1298 39 mohor
          end
1299 354 olof
        8'b00_00_00_00:  // whatever and no master read or write is needed
1300
                         // (ack or err comes finishing previous access)
1301 127 mohor
          begin
1302 352 olof
            tx_burst_cnt<= 0;
1303
            tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1304 127 mohor
          end
1305 226 tadejm
        default:                    // Don't touch
1306 82 mohor
          begin
1307 352 olof
            MasterWbTX <= MasterWbTX;
1308
            MasterWbRX <= MasterWbRX;
1309
            m_wb_cyc_o <= m_wb_cyc_o;
1310
            m_wb_sel_o <= m_wb_sel_o;
1311
            IncrTxPointer<= IncrTxPointer;
1312 82 mohor
          end
1313 39 mohor
      endcase
1314
    end
1315 38 mohor
end
1316
 
1317 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1318 38 mohor
 
1319 354 olof
eth_fifo
1320
     #(
1321
       .DATA_WIDTH(TX_FIFO_DATA_WIDTH),
1322
       .DEPTH(TX_FIFO_DEPTH),
1323
       .CNT_WIDTH(TX_FIFO_CNT_WIDTH))
1324
tx_fifo (
1325
       .data_in(m_wb_dat_i),
1326
       .data_out(TxData_wb),
1327
       .clk(WB_CLK_I),
1328
       .reset(Reset),
1329
       .write(MasterWbTX & m_wb_ack_i),
1330
       .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1331
       .clear(TxFifoClear),
1332
       .full(TxBufferFull),
1333
       .almost_full(TxBufferAlmostFull),
1334
       .almost_empty(TxBufferAlmostEmpty),
1335
       .empty(TxBufferEmpty),
1336
       .cnt(txfifo_cnt)
1337
       );
1338 39 mohor
 
1339 354 olof
// Start: Generation of the TxStartFrm_wb which is then synchronized to the
1340
// MTxClk
1341 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1342 38 mohor
begin
1343 40 mohor
  if(Reset)
1344 352 olof
    TxStartFrm_wb <= 1'b0;
1345 38 mohor
  else
1346 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1347 352 olof
    TxStartFrm_wb <= 1'b1;
1348 38 mohor
  else
1349 39 mohor
  if(TxStartFrm_syncb2)
1350 352 olof
    TxStartFrm_wb <= 1'b0;
1351 38 mohor
end
1352
 
1353 354 olof
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's
1354
// blocked.
1355 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1356 38 mohor
begin
1357 40 mohor
  if(Reset)
1358 352 olof
    StartOccured <= 1'b0;
1359 38 mohor
  else
1360 39 mohor
  if(TxStartFrm_wb)
1361 352 olof
    StartOccured <= 1'b1;
1362 38 mohor
  else
1363 39 mohor
  if(ResetTxBDReady)
1364 352 olof
    StartOccured <= 1'b0;
1365 38 mohor
end
1366
 
1367 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1368 40 mohor
always @ (posedge MTxClk or posedge Reset)
1369 39 mohor
begin
1370 40 mohor
  if(Reset)
1371 352 olof
    TxStartFrm_sync1 <= 1'b0;
1372 39 mohor
  else
1373 352 olof
    TxStartFrm_sync1 <= TxStartFrm_wb;
1374 39 mohor
end
1375 38 mohor
 
1376 40 mohor
always @ (posedge MTxClk or posedge Reset)
1377 39 mohor
begin
1378 40 mohor
  if(Reset)
1379 352 olof
    TxStartFrm_sync2 <= 1'b0;
1380 39 mohor
  else
1381 352 olof
    TxStartFrm_sync2 <= TxStartFrm_sync1;
1382 39 mohor
end
1383
 
1384 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1385 38 mohor
begin
1386 40 mohor
  if(Reset)
1387 352 olof
    TxStartFrm_syncb1 <= 1'b0;
1388 38 mohor
  else
1389 352 olof
    TxStartFrm_syncb1 <= TxStartFrm_sync2;
1390 38 mohor
end
1391
 
1392 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1393 38 mohor
begin
1394 40 mohor
  if(Reset)
1395 352 olof
    TxStartFrm_syncb2 <= 1'b0;
1396 38 mohor
  else
1397 352 olof
    TxStartFrm_syncb2 <= TxStartFrm_syncb1;
1398 39 mohor
end
1399
 
1400 40 mohor
always @ (posedge MTxClk or posedge Reset)
1401 39 mohor
begin
1402 40 mohor
  if(Reset)
1403 352 olof
    TxStartFrm <= 1'b0;
1404 38 mohor
  else
1405 39 mohor
  if(TxStartFrm_sync2)
1406 352 olof
    TxStartFrm <= 1'b1;
1407 39 mohor
  else
1408 354 olof
  if(TxUsedData_q | ~TxStartFrm_sync2 &
1409
     (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
1410 352 olof
    TxStartFrm <= 1'b0;
1411 38 mohor
end
1412 354 olof
// End: Generation of the TxStartFrm_wb which is then synchronized to the
1413
// MTxClk
1414 38 mohor
 
1415
 
1416 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1417 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1418 38 mohor
begin
1419 40 mohor
  if(Reset)
1420 352 olof
    TxEndFrm_wb <= 1'b0;
1421 38 mohor
  else
1422 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1423 352 olof
    TxEndFrm_wb <= 1'b1;
1424 38 mohor
  else
1425 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1426 352 olof
    TxEndFrm_wb <= 1'b0;
1427 38 mohor
end
1428
 
1429
// Marks which bytes are valid within the word.
1430 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1431 38 mohor
 
1432
 
1433 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1434 38 mohor
begin
1435 40 mohor
  if(Reset)
1436 352 olof
    LatchValidBytes <= 1'b0;
1437 38 mohor
  else
1438 39 mohor
  if(TxLengthLt4 & TxBDReady)
1439 352 olof
    LatchValidBytes <= 1'b1;
1440 38 mohor
  else
1441 352 olof
    LatchValidBytes <= 1'b0;
1442 38 mohor
end
1443
 
1444 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1445 38 mohor
begin
1446 40 mohor
  if(Reset)
1447 352 olof
    LatchValidBytes_q <= 1'b0;
1448 38 mohor
  else
1449 352 olof
    LatchValidBytes_q <= LatchValidBytes;
1450 38 mohor
end
1451
 
1452
 
1453 39 mohor
// Latching valid bytes
1454 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1455 38 mohor
begin
1456 40 mohor
  if(Reset)
1457 352 olof
    TxValidBytesLatched <= 2'h0;
1458 38 mohor
  else
1459 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1460 352 olof
    TxValidBytesLatched <= TxValidBytes;
1461 39 mohor
  else
1462
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1463 352 olof
    TxValidBytesLatched <= 2'h0;
1464 38 mohor
end
1465
 
1466
 
1467
assign TxIRQEn          = TxStatus[14];
1468 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1469
assign PerPacketPad     = TxStatus[12];
1470
assign PerPacketCrcEn   = TxStatus[11];
1471 38 mohor
 
1472
 
1473 77 mohor
assign RxIRQEn         = RxStatus[14];
1474 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1475 38 mohor
 
1476
 
1477 354 olof
// Temporary Tx and Rx buffer descriptor address
1478
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite  & ~WrapTxStatusBit}} &
1479
                              (TxBDAddress + 1'b1); // Tx BD increment or wrap
1480
                                                    // (last BD)
1481 38 mohor
 
1482 354 olof
assign TempRxBDAddress[7:1] =
1483
  {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
1484
  {7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1); // Using next Rx BD
1485
                                                // (increment address)
1486 38 mohor
 
1487
// Latching Tx buffer descriptor address
1488 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1489 38 mohor
begin
1490 40 mohor
  if(Reset)
1491 352 olof
    TxBDAddress <= 7'h0;
1492 321 igorm
  else if (r_TxEn & (~r_TxEn_q))
1493 352 olof
    TxBDAddress <= 7'h0;
1494 321 igorm
  else if (TxStatusWrite)
1495 352 olof
    TxBDAddress <= TempTxBDAddress;
1496 38 mohor
end
1497
 
1498
// Latching Rx buffer descriptor address
1499 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1500 38 mohor
begin
1501 40 mohor
  if(Reset)
1502 352 olof
    RxBDAddress <= 7'h0;
1503 321 igorm
  else if(r_RxEn & (~r_RxEn_q))
1504 352 olof
    RxBDAddress <= r_TxBDNum[6:0];
1505 321 igorm
  else if(RxStatusWrite)
1506 352 olof
    RxBDAddress <= TempRxBDAddress;
1507 38 mohor
end
1508
 
1509 354 olof
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0],
1510
                                RetryLimit, LateCollLatched, DeferLatched,
1511
                                CarrierSenseLost};
1512 38 mohor
 
1513 261 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
1514 60 mohor
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1515 38 mohor
 
1516 60 mohor
 
1517 38 mohor
// Signals used for various purposes
1518 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1519 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1520
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1521
 
1522
 
1523 39 mohor
// Generating delayed signals
1524 40 mohor
always @ (posedge MTxClk or posedge Reset)
1525 38 mohor
begin
1526 40 mohor
  if(Reset)
1527 39 mohor
    begin
1528 352 olof
      TxAbort_q      <= 1'b0;
1529
      TxRetry_q      <= 1'b0;
1530
      TxUsedData_q   <= 1'b0;
1531 39 mohor
    end
1532 38 mohor
  else
1533 39 mohor
    begin
1534 352 olof
      TxAbort_q      <= TxAbort;
1535
      TxRetry_q      <= TxRetry;
1536
      TxUsedData_q   <= TxUsedData;
1537 39 mohor
    end
1538 38 mohor
end
1539
 
1540
// Generating delayed signals
1541 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1542 38 mohor
begin
1543 40 mohor
  if(Reset)
1544 38 mohor
    begin
1545 352 olof
      TxDone_wb_q   <= 1'b0;
1546
      TxAbort_wb_q  <= 1'b0;
1547
      TxRetry_wb_q  <= 1'b0;
1548 38 mohor
    end
1549
  else
1550
    begin
1551 352 olof
      TxDone_wb_q   <= TxDone_wb;
1552
      TxAbort_wb_q  <= TxAbort_wb;
1553
      TxRetry_wb_q  <= TxRetry_wb;
1554 38 mohor
    end
1555
end
1556
 
1557
 
1558 219 mohor
reg TxAbortPacketBlocked;
1559
always @ (posedge WB_CLK_I or posedge Reset)
1560
begin
1561
  if(Reset)
1562 352 olof
    TxAbortPacket <= 1'b0;
1563 219 mohor
  else
1564 354 olof
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
1565
    (~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
1566
    (~TxAbortPacketBlocked))
1567 352 olof
    TxAbortPacket <= 1'b1;
1568 219 mohor
  else
1569 352 olof
    TxAbortPacket <= 1'b0;
1570 219 mohor
end
1571
 
1572
 
1573
always @ (posedge WB_CLK_I or posedge Reset)
1574
begin
1575
  if(Reset)
1576 352 olof
    TxAbortPacket_NotCleared <= 1'b0;
1577 221 mohor
  else
1578 272 tadejm
  if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
1579 352 olof
    TxAbortPacket_NotCleared <= 1'b0;
1580 272 tadejm
  else
1581 354 olof
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
1582
     (~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
1583
     (~TxAbortPacketBlocked))
1584 352 olof
    TxAbortPacket_NotCleared <= 1'b1;
1585 221 mohor
end
1586
 
1587
 
1588
always @ (posedge WB_CLK_I or posedge Reset)
1589
begin
1590
  if(Reset)
1591 352 olof
    TxAbortPacketBlocked <= 1'b0;
1592 219 mohor
  else
1593 280 mohor
  if(!TxAbort_wb & TxAbort_wb_q)
1594 352 olof
    TxAbortPacketBlocked <= 1'b0;
1595 280 mohor
  else
1596 219 mohor
  if(TxAbortPacket)
1597 352 olof
    TxAbortPacketBlocked <= 1'b1;
1598 219 mohor
end
1599
 
1600
 
1601
reg TxRetryPacketBlocked;
1602
always @ (posedge WB_CLK_I or posedge Reset)
1603
begin
1604
  if(Reset)
1605 352 olof
    TxRetryPacket <= 1'b0;
1606 219 mohor
  else
1607 354 olof
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1608
     !TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1609 352 olof
    TxRetryPacket <= 1'b1;
1610 219 mohor
  else
1611 352 olof
    TxRetryPacket <= 1'b0;
1612 219 mohor
end
1613
 
1614
 
1615
always @ (posedge WB_CLK_I or posedge Reset)
1616
begin
1617
  if(Reset)
1618 352 olof
    TxRetryPacket_NotCleared <= 1'b0;
1619 221 mohor
  else
1620 272 tadejm
  if(StartTxBDRead)
1621 352 olof
    TxRetryPacket_NotCleared <= 1'b0;
1622 272 tadejm
  else
1623 354 olof
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1624
     !TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1625 352 olof
    TxRetryPacket_NotCleared <= 1'b1;
1626 221 mohor
end
1627
 
1628
 
1629
always @ (posedge WB_CLK_I or posedge Reset)
1630
begin
1631
  if(Reset)
1632 352 olof
    TxRetryPacketBlocked <= 1'b0;
1633 219 mohor
  else
1634 280 mohor
  if(!TxRetry_wb & TxRetry_wb_q)
1635 352 olof
    TxRetryPacketBlocked <= 1'b0;
1636 280 mohor
  else
1637 219 mohor
  if(TxRetryPacket)
1638 352 olof
    TxRetryPacketBlocked <= 1'b1;
1639 219 mohor
end
1640
 
1641
 
1642 221 mohor
reg TxDonePacketBlocked;
1643
always @ (posedge WB_CLK_I or posedge Reset)
1644
begin
1645
  if(Reset)
1646 352 olof
    TxDonePacket <= 1'b0;
1647 221 mohor
  else
1648 354 olof
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1649
     !TxDonePacketBlocked | TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1650 352 olof
    TxDonePacket <= 1'b1;
1651 221 mohor
  else
1652 352 olof
    TxDonePacket <= 1'b0;
1653 221 mohor
end
1654
 
1655
 
1656
always @ (posedge WB_CLK_I or posedge Reset)
1657
begin
1658
  if(Reset)
1659 352 olof
    TxDonePacket_NotCleared <= 1'b0;
1660 221 mohor
  else
1661 272 tadejm
  if(TxEn & TxEn_q & TxDonePacket_NotCleared)
1662 352 olof
    TxDonePacket_NotCleared <= 1'b0;
1663 272 tadejm
  else
1664 354 olof
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1665
     (~TxDonePacketBlocked) | TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
1666 352 olof
    TxDonePacket_NotCleared <= 1'b1;
1667 221 mohor
end
1668
 
1669
 
1670
always @ (posedge WB_CLK_I or posedge Reset)
1671
begin
1672
  if(Reset)
1673 352 olof
    TxDonePacketBlocked <= 1'b0;
1674 221 mohor
  else
1675 280 mohor
  if(!TxDone_wb & TxDone_wb_q)
1676 352 olof
    TxDonePacketBlocked <= 1'b0;
1677 280 mohor
  else
1678 221 mohor
  if(TxDonePacket)
1679 352 olof
    TxDonePacketBlocked <= 1'b1;
1680 221 mohor
end
1681
 
1682
 
1683 38 mohor
// Indication of the last word
1684 40 mohor
always @ (posedge MTxClk or posedge Reset)
1685 38 mohor
begin
1686 40 mohor
  if(Reset)
1687 352 olof
    LastWord <= 1'b0;
1688 38 mohor
  else
1689
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1690 352 olof
    LastWord <= 1'b0;
1691 38 mohor
  else
1692
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1693 352 olof
    LastWord <= TxEndFrm_wb;
1694 38 mohor
end
1695
 
1696
 
1697
// Tx end frame generation
1698 40 mohor
always @ (posedge MTxClk or posedge Reset)
1699 38 mohor
begin
1700 40 mohor
  if(Reset)
1701 352 olof
    TxEndFrm <= 1'b0;
1702 38 mohor
  else
1703 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1704 352 olof
    TxEndFrm <= 1'b0;
1705 38 mohor
  else
1706
  if(Flop & LastWord)
1707
    begin
1708 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1709 352 olof
        1 : TxEndFrm <= TxByteCnt == 2'h0;
1710
        2 : TxEndFrm <= TxByteCnt == 2'h1;
1711
        3 : TxEndFrm <= TxByteCnt == 2'h2;
1712
 
1713
        default : TxEndFrm <= 1'b0;
1714 38 mohor
      endcase
1715
    end
1716
end
1717
 
1718
 
1719
// Tx data selection (latching)
1720 40 mohor
always @ (posedge MTxClk or posedge Reset)
1721 38 mohor
begin
1722 40 mohor
  if(Reset)
1723 352 olof
    TxData <= 0;
1724 38 mohor
  else
1725 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1726 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1727 354 olof
      2'h0 : TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
1728
      2'h1 : TxData <= TxData_wb[23:16];// Big Endian Byte Ordering
1729
      2'h2 : TxData <= TxData_wb[15:08];// Big Endian Byte Ordering
1730
      2'h3 : TxData <= TxData_wb[07:00];// Big Endian Byte Ordering
1731 96 mohor
    endcase
1732 38 mohor
  else
1733 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1734 354 olof
    TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
1735 96 mohor
  else
1736 38 mohor
  if(TxUsedData & Flop)
1737
    begin
1738 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1739 354 olof
 
1740 352 olof
        1 : TxData <= TxDataLatched[23:16];
1741
        2 : TxData <= TxDataLatched[15:8];
1742
        3 : TxData <= TxDataLatched[7:0];
1743 38 mohor
      endcase
1744
    end
1745
end
1746
 
1747
 
1748
// Latching tx data
1749 40 mohor
always @ (posedge MTxClk or posedge Reset)
1750 38 mohor
begin
1751 40 mohor
  if(Reset)
1752 352 olof
    TxDataLatched[31:0] <= 32'h0;
1753 38 mohor
  else
1754 354 olof
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 |
1755
     TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1756 352 olof
    TxDataLatched[31:0] <= TxData_wb[31:0];
1757 38 mohor
end
1758
 
1759
 
1760
// Tx under run
1761 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1762 38 mohor
begin
1763 40 mohor
  if(Reset)
1764 352 olof
    TxUnderRun_wb <= 1'b0;
1765 38 mohor
  else
1766 39 mohor
  if(TxAbortPulse)
1767 352 olof
    TxUnderRun_wb <= 1'b0;
1768 60 mohor
  else
1769
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1770 352 olof
    TxUnderRun_wb <= 1'b1;
1771 60 mohor
end
1772
 
1773
 
1774 159 mohor
reg TxUnderRun_sync1;
1775
 
1776 60 mohor
// Tx under run
1777
always @ (posedge MTxClk or posedge Reset)
1778
begin
1779
  if(Reset)
1780 352 olof
    TxUnderRun_sync1 <= 1'b0;
1781 43 mohor
  else
1782 60 mohor
  if(TxUnderRun_wb)
1783 352 olof
    TxUnderRun_sync1 <= 1'b1;
1784 60 mohor
  else
1785 159 mohor
  if(BlockingTxStatusWrite_sync2)
1786 352 olof
    TxUnderRun_sync1 <= 1'b0;
1787 159 mohor
end
1788
 
1789
// Tx under run
1790
always @ (posedge MTxClk or posedge Reset)
1791
begin
1792
  if(Reset)
1793 352 olof
    TxUnderRun <= 1'b0;
1794 159 mohor
  else
1795
  if(BlockingTxStatusWrite_sync2)
1796 352 olof
    TxUnderRun <= 1'b0;
1797 159 mohor
  else
1798
  if(TxUnderRun_sync1)
1799 352 olof
    TxUnderRun <= 1'b1;
1800 38 mohor
end
1801
 
1802
 
1803
// Tx Byte counter
1804 40 mohor
always @ (posedge MTxClk or posedge Reset)
1805 38 mohor
begin
1806 40 mohor
  if(Reset)
1807 352 olof
    TxByteCnt <= 2'h0;
1808 38 mohor
  else
1809
  if(TxAbort_q | TxRetry_q)
1810 352 olof
    TxByteCnt <= 2'h0;
1811 38 mohor
  else
1812
  if(TxStartFrm & ~TxUsedData)
1813 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1814 352 olof
      2'h0 : TxByteCnt <= 2'h1;
1815
      2'h1 : TxByteCnt <= 2'h2;
1816
      2'h2 : TxByteCnt <= 2'h3;
1817
      2'h3 : TxByteCnt <= 2'h0;
1818 96 mohor
    endcase
1819 38 mohor
  else
1820
  if(TxUsedData & Flop)
1821 352 olof
    TxByteCnt <= TxByteCnt + 1'b1;
1822 38 mohor
end
1823
 
1824 39 mohor
 
1825 150 mohor
always @ (posedge MTxClk or posedge Reset)
1826
begin
1827
  if(Reset)
1828 352 olof
    ReadTxDataFromFifo_tck <= 1'b0;
1829 150 mohor
  else
1830 354 olof
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 &
1831
     ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1832 352 olof
     ReadTxDataFromFifo_tck <= 1'b1;
1833 150 mohor
  else
1834
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1835 352 olof
    ReadTxDataFromFifo_tck <= 1'b0;
1836 38 mohor
end
1837
 
1838 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1839 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1840 38 mohor
begin
1841 40 mohor
  if(Reset)
1842 352 olof
    ReadTxDataFromFifo_sync1 <= 1'b0;
1843 38 mohor
  else
1844 352 olof
    ReadTxDataFromFifo_sync1 <= ReadTxDataFromFifo_tck;
1845 39 mohor
end
1846 38 mohor
 
1847 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1848 38 mohor
begin
1849 40 mohor
  if(Reset)
1850 352 olof
    ReadTxDataFromFifo_sync2 <= 1'b0;
1851 38 mohor
  else
1852 352 olof
    ReadTxDataFromFifo_sync2 <= ReadTxDataFromFifo_sync1;
1853 38 mohor
end
1854
 
1855 40 mohor
always @ (posedge MTxClk or posedge Reset)
1856 38 mohor
begin
1857 40 mohor
  if(Reset)
1858 352 olof
    ReadTxDataFromFifo_syncb1 <= 1'b0;
1859 38 mohor
  else
1860 352 olof
    ReadTxDataFromFifo_syncb1 <= ReadTxDataFromFifo_sync2;
1861 38 mohor
end
1862
 
1863 40 mohor
always @ (posedge MTxClk or posedge Reset)
1864 38 mohor
begin
1865 40 mohor
  if(Reset)
1866 352 olof
    ReadTxDataFromFifo_syncb2 <= 1'b0;
1867 38 mohor
  else
1868 352 olof
    ReadTxDataFromFifo_syncb2 <= ReadTxDataFromFifo_syncb1;
1869 38 mohor
end
1870
 
1871 150 mohor
always @ (posedge MTxClk or posedge Reset)
1872
begin
1873
  if(Reset)
1874 352 olof
    ReadTxDataFromFifo_syncb3 <= 1'b0;
1875 150 mohor
  else
1876 352 olof
    ReadTxDataFromFifo_syncb3 <= ReadTxDataFromFifo_syncb2;
1877 150 mohor
end
1878
 
1879 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1880 38 mohor
begin
1881 40 mohor
  if(Reset)
1882 352 olof
    ReadTxDataFromFifo_sync3 <= 1'b0;
1883 38 mohor
  else
1884 352 olof
    ReadTxDataFromFifo_sync3 <= ReadTxDataFromFifo_sync2;
1885 38 mohor
end
1886
 
1887 354 olof
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 &
1888
                               ~ReadTxDataFromFifo_sync3;
1889
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization
1890
// to the WB_CLK_I
1891 38 mohor
 
1892
 
1893 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1894 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1895 38 mohor
begin
1896 40 mohor
  if(Reset)
1897 352 olof
    TxRetrySync1 <= 1'b0;
1898 38 mohor
  else
1899 352 olof
    TxRetrySync1 <= TxRetry;
1900 38 mohor
end
1901
 
1902 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1903 38 mohor
begin
1904 40 mohor
  if(Reset)
1905 352 olof
    TxRetry_wb <= 1'b0;
1906 38 mohor
  else
1907 352 olof
    TxRetry_wb <= TxRetrySync1;
1908 38 mohor
end
1909
 
1910
 
1911 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1912 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1913 38 mohor
begin
1914 40 mohor
  if(Reset)
1915 352 olof
    TxDoneSync1 <= 1'b0;
1916 38 mohor
  else
1917 352 olof
    TxDoneSync1 <= TxDone;
1918 38 mohor
end
1919
 
1920 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1921 38 mohor
begin
1922 40 mohor
  if(Reset)
1923 352 olof
    TxDone_wb <= 1'b0;
1924 38 mohor
  else
1925 352 olof
    TxDone_wb <= TxDoneSync1;
1926 38 mohor
end
1927
 
1928 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1929 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1930 38 mohor
begin
1931 40 mohor
  if(Reset)
1932 352 olof
    TxAbortSync1 <= 1'b0;
1933 38 mohor
  else
1934 352 olof
    TxAbortSync1 <= TxAbort;
1935 38 mohor
end
1936
 
1937 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1938 38 mohor
begin
1939 40 mohor
  if(Reset)
1940 352 olof
    TxAbort_wb <= 1'b0;
1941 38 mohor
  else
1942 352 olof
    TxAbort_wb <= TxAbortSync1;
1943 38 mohor
end
1944
 
1945
 
1946 354 olof
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 |
1947
                       r_RxEn & ~r_RxEn_q;
1948 39 mohor
 
1949 40 mohor
// Reading the Rx buffer descriptor
1950
always @ (posedge WB_CLK_I or posedge Reset)
1951
begin
1952
  if(Reset)
1953 352 olof
    RxBDRead <= 1'b0;
1954 40 mohor
  else
1955 166 mohor
  if(StartRxBDRead & ~RxReady)
1956 352 olof
    RxBDRead <= 1'b1;
1957 40 mohor
  else
1958
  if(RxBDReady)
1959 352 olof
    RxBDRead <= 1'b0;
1960 40 mohor
end
1961 39 mohor
 
1962
 
1963 354 olof
// Reading of the next receive buffer descriptor starts after reception status
1964
// is written to the previous one.
1965 38 mohor
 
1966
// Latching READY status of the Rx buffer descriptor
1967 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1968 38 mohor
begin
1969 40 mohor
  if(Reset)
1970 352 olof
    RxBDReady <= 1'b0;
1971 38 mohor
  else
1972 166 mohor
  if(RxPointerRead)
1973 352 olof
    RxBDReady <= 1'b0;
1974 150 mohor
  else
1975 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1976 354 olof
    RxBDReady <= ram_do[15];// RxBDReady is sampled only once at the beginning
1977 38 mohor
end
1978
 
1979 40 mohor
// Latching Rx buffer descriptor status
1980 354 olof
// Data is avaliable one cycle after the access is started (at that time
1981
// signal RxEn is not active)
1982 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1983 38 mohor
begin
1984 40 mohor
  if(Reset)
1985 352 olof
    RxStatus <= 2'h0;
1986 38 mohor
  else
1987 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1988 352 olof
    RxStatus <= ram_do[14:13];
1989 38 mohor
end
1990
 
1991
 
1992 166 mohor
// RxReady generation
1993
always @ (posedge WB_CLK_I or posedge Reset)
1994
begin
1995
  if(Reset)
1996 352 olof
    RxReady <= 1'b0;
1997 354 olof
  else if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)
1998 352 olof
    RxReady <= 1'b0;
1999 354 olof
  else if(RxEn & RxEn_q & RxPointerRead)
2000 352 olof
    RxReady <= 1'b1;
2001 166 mohor
end
2002 38 mohor
 
2003
 
2004 40 mohor
// Reading Rx BD pointer
2005
assign StartRxPointerRead = RxBDRead & RxBDReady;
2006
 
2007
// Reading Tx BD Pointer
2008
always @ (posedge WB_CLK_I or posedge Reset)
2009 38 mohor
begin
2010 40 mohor
  if(Reset)
2011 352 olof
    RxPointerRead <= 1'b0;
2012 38 mohor
  else
2013 40 mohor
  if(StartRxPointerRead)
2014 352 olof
    RxPointerRead <= 1'b1;
2015 38 mohor
  else
2016 166 mohor
  if(RxEn & RxEn_q)
2017 352 olof
    RxPointerRead <= 1'b0;
2018 38 mohor
end
2019
 
2020 113 mohor
 
2021 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
2022
always @ (posedge WB_CLK_I or posedge Reset)
2023
begin
2024
  if(Reset)
2025 352 olof
    RxPointerMSB <= 30'h0;
2026 40 mohor
  else
2027
  if(RxEn & RxEn_q & RxPointerRead)
2028 352 olof
    RxPointerMSB <= ram_do[31:2];
2029 40 mohor
  else
2030 113 mohor
  if(MasterWbRX & m_wb_ack_i)
2031 354 olof
      RxPointerMSB <= RxPointerMSB + 1'b1; // Word access (always word access.
2032
                                           // m_wb_sel_o are used for
2033
                                           // selecting bytes)
2034 40 mohor
end
2035 38 mohor
 
2036
 
2037 354 olof
//Latching last addresses from buffer descriptor (used as byte-half-word
2038
//indicator);
2039 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2040
begin
2041
  if(Reset)
2042 352 olof
    RxPointerLSB_rst[1:0] <= 0;
2043 96 mohor
  else
2044 354 olof
  if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active
2045 352 olof
    RxPointerLSB_rst[1:0] <= 0;
2046 96 mohor
  else
2047
  if(RxEn & RxEn_q & RxPointerRead)
2048 352 olof
    RxPointerLSB_rst[1:0] <= ram_do[1:0];
2049 96 mohor
end
2050
 
2051
 
2052 159 mohor
always @ (RxPointerLSB_rst)
2053 96 mohor
begin
2054 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
2055
    2'h0 : RxByteSel[3:0] = 4'hf;
2056
    2'h1 : RxByteSel[3:0] = 4'h7;
2057
    2'h2 : RxByteSel[3:0] = 4'h3;
2058
    2'h3 : RxByteSel[3:0] = 4'h1;
2059 96 mohor
  endcase
2060
end
2061
 
2062
 
2063
always @ (posedge WB_CLK_I or posedge Reset)
2064
begin
2065
  if(Reset)
2066 352 olof
    RxEn_needed <= 1'b0;
2067 354 olof
  else if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
2068 352 olof
    RxEn_needed <= 1'b1;
2069 354 olof
  else if(RxPointerRead & RxEn & RxEn_q)
2070 352 olof
    RxEn_needed <= 1'b0;
2071 38 mohor
end
2072
 
2073
 
2074 354 olof
// Reception status is written back to the buffer descriptor after the end
2075
// of frame is detected.
2076 40 mohor
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
2077 38 mohor
 
2078
 
2079
// Indicating that last byte is being reveived
2080 40 mohor
always @ (posedge MRxClk or posedge Reset)
2081 38 mohor
begin
2082 40 mohor
  if(Reset)
2083 352 olof
    LastByteIn <= 1'b0;
2084 38 mohor
  else
2085 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
2086 352 olof
    LastByteIn <= 1'b0;
2087 38 mohor
  else
2088 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
2089 352 olof
    LastByteIn <= 1'b1;
2090 38 mohor
end
2091
 
2092 354 olof
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) &
2093
                           RxEnableWindow;
2094 118 mohor
 
2095 38 mohor
// Indicating that data reception will end
2096 40 mohor
always @ (posedge MRxClk or posedge Reset)
2097 38 mohor
begin
2098 40 mohor
  if(Reset)
2099 352 olof
    ShiftWillEnd <= 1'b0;
2100 38 mohor
  else
2101 159 mohor
  if(ShiftEnded_rck | RxAbort)
2102 352 olof
    ShiftWillEnd <= 1'b0;
2103 38 mohor
  else
2104 40 mohor
  if(StartShiftWillEnd)
2105 352 olof
    ShiftWillEnd <= 1'b1;
2106 38 mohor
end
2107
 
2108
 
2109
// Receive byte counter
2110 40 mohor
always @ (posedge MRxClk or posedge Reset)
2111 38 mohor
begin
2112 40 mohor
  if(Reset)
2113 352 olof
    RxByteCnt <= 2'h0;
2114 38 mohor
  else
2115 159 mohor
  if(ShiftEnded_rck | RxAbort)
2116 352 olof
    RxByteCnt <= 2'h0;
2117 97 lampret
  else
2118 166 mohor
  if(RxValid & RxStartFrm & RxReady)
2119 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2120 352 olof
      2'h0 : RxByteCnt <= 2'h1;
2121
      2'h1 : RxByteCnt <= 2'h2;
2122
      2'h2 : RxByteCnt <= 2'h3;
2123
      2'h3 : RxByteCnt <= 2'h0;
2124 96 mohor
    endcase
2125 38 mohor
  else
2126 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
2127 352 olof
    RxByteCnt <= RxByteCnt + 1'b1;
2128 38 mohor
end
2129
 
2130
 
2131
// Indicates how many bytes are valid within the last word
2132 40 mohor
always @ (posedge MRxClk or posedge Reset)
2133 38 mohor
begin
2134 40 mohor
  if(Reset)
2135 352 olof
    RxValidBytes <= 2'h1;
2136 38 mohor
  else
2137 96 mohor
  if(RxValid & RxStartFrm)
2138 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2139 352 olof
      2'h0 : RxValidBytes <= 2'h1;
2140
      2'h1 : RxValidBytes <= 2'h2;
2141
      2'h2 : RxValidBytes <= 2'h3;
2142
      2'h3 : RxValidBytes <= 2'h0;
2143 96 mohor
    endcase
2144 38 mohor
  else
2145 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2146 352 olof
    RxValidBytes <= RxValidBytes + 1'b1;
2147 38 mohor
end
2148
 
2149
 
2150 40 mohor
always @ (posedge MRxClk or posedge Reset)
2151 38 mohor
begin
2152 40 mohor
  if(Reset)
2153 352 olof
    RxDataLatched1       <= 24'h0;
2154 38 mohor
  else
2155 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2156 96 mohor
    if(RxStartFrm)
2157 40 mohor
    begin
2158 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2159 354 olof
        // Big Endian Byte Ordering
2160
        2'h0:        RxDataLatched1[31:24] <= RxData;
2161 352 olof
        2'h1:        RxDataLatched1[23:16] <= RxData;
2162
        2'h2:        RxDataLatched1[15:8]  <= RxData;
2163
        2'h3:        RxDataLatched1        <= RxDataLatched1;
2164 96 mohor
      endcase
2165
    end
2166
    else if (RxEnableWindow)
2167
    begin
2168 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2169 354 olof
        // Big Endian Byte Ordering
2170
        2'h0:        RxDataLatched1[31:24] <= RxData;
2171 352 olof
        2'h1:        RxDataLatched1[23:16] <= RxData;
2172
        2'h2:        RxDataLatched1[15:8]  <= RxData;
2173
        2'h3:        RxDataLatched1        <= RxDataLatched1;
2174 40 mohor
      endcase
2175
    end
2176 38 mohor
end
2177
 
2178 40 mohor
// Assembling data that will be written to the rx_fifo
2179
always @ (posedge MRxClk or posedge Reset)
2180 38 mohor
begin
2181 40 mohor
  if(Reset)
2182 352 olof
    RxDataLatched2 <= 32'h0;
2183 38 mohor
  else
2184 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2185 354 olof
    // Big Endian Byte Ordering
2186
    RxDataLatched2 <= {RxDataLatched1[31:8], RxData};
2187 38 mohor
  else
2188 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2189 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2190 354 olof
      // Big Endian Byte Ordering
2191
 
2192 352 olof
      1 : RxDataLatched2 <= {RxDataLatched1[31:24], 24'h0};
2193
      2 : RxDataLatched2 <= {RxDataLatched1[31:16], 16'h0};
2194
      3 : RxDataLatched2 <= {RxDataLatched1[31:8],   8'h0};
2195 40 mohor
    endcase
2196 38 mohor
end
2197
 
2198
 
2199 40 mohor
// Indicating start of the reception process
2200 354 olof
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm &
2201
                              RxEnableWindow & (&RxByteCnt))
2202
                              |(RxValid & RxReady &  RxStartFrm &
2203
                              (&RxPointerLSB_rst))
2204
                              |(ShiftWillEnd & LastByteIn & (&RxByteCnt));
2205 38 mohor
 
2206 150 mohor
always @ (posedge MRxClk or posedge Reset)
2207
begin
2208
  if(Reset)
2209 352 olof
    WriteRxDataToFifo <= 1'b0;
2210 150 mohor
  else
2211
  if(SetWriteRxDataToFifo & ~RxAbort)
2212 352 olof
    WriteRxDataToFifo <= 1'b1;
2213 150 mohor
  else
2214
  if(WriteRxDataToFifoSync2 | RxAbort)
2215 352 olof
    WriteRxDataToFifo <= 1'b0;
2216 150 mohor
end
2217 40 mohor
 
2218 150 mohor
 
2219
always @ (posedge WB_CLK_I or posedge Reset)
2220
begin
2221
  if(Reset)
2222 352 olof
    WriteRxDataToFifoSync1 <= 1'b0;
2223 150 mohor
  else
2224
  if(WriteRxDataToFifo)
2225 352 olof
    WriteRxDataToFifoSync1 <= 1'b1;
2226 150 mohor
  else
2227 352 olof
    WriteRxDataToFifoSync1 <= 1'b0;
2228 150 mohor
end
2229
 
2230
always @ (posedge WB_CLK_I or posedge Reset)
2231
begin
2232
  if(Reset)
2233 352 olof
    WriteRxDataToFifoSync2 <= 1'b0;
2234 150 mohor
  else
2235 352 olof
    WriteRxDataToFifoSync2 <= WriteRxDataToFifoSync1;
2236 150 mohor
end
2237
 
2238
always @ (posedge WB_CLK_I or posedge Reset)
2239
begin
2240
  if(Reset)
2241 352 olof
    WriteRxDataToFifoSync3 <= 1'b0;
2242 150 mohor
  else
2243 352 olof
    WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2;
2244 150 mohor
end
2245
 
2246
 
2247 354 olof
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 &
2248
                              ~WriteRxDataToFifoSync3;
2249 150 mohor
 
2250 40 mohor
 
2251 90 mohor
always @ (posedge MRxClk or posedge Reset)
2252
begin
2253
  if(Reset)
2254 352 olof
    LatchedRxStartFrm <= 0;
2255 90 mohor
  else
2256 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2257 352 olof
    LatchedRxStartFrm <= 1;
2258 90 mohor
  else
2259 150 mohor
  if(SyncRxStartFrm_q)
2260 352 olof
    LatchedRxStartFrm <= 0;
2261 90 mohor
end
2262
 
2263
 
2264
always @ (posedge WB_CLK_I or posedge Reset)
2265
begin
2266
  if(Reset)
2267 352 olof
    SyncRxStartFrm <= 0;
2268 90 mohor
  else
2269
  if(LatchedRxStartFrm)
2270 352 olof
    SyncRxStartFrm <= 1;
2271 90 mohor
  else
2272 352 olof
    SyncRxStartFrm <= 0;
2273 90 mohor
end
2274
 
2275
 
2276
always @ (posedge WB_CLK_I or posedge Reset)
2277
begin
2278
  if(Reset)
2279 352 olof
    SyncRxStartFrm_q <= 0;
2280 90 mohor
  else
2281 352 olof
    SyncRxStartFrm_q <= SyncRxStartFrm;
2282 90 mohor
end
2283
 
2284 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2285
begin
2286
  if(Reset)
2287 352 olof
    SyncRxStartFrm_q2 <= 0;
2288 150 mohor
  else
2289 352 olof
    SyncRxStartFrm_q2 <= SyncRxStartFrm_q;
2290 150 mohor
end
2291 90 mohor
 
2292
 
2293 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2294 90 mohor
 
2295 354 olof
eth_fifo #(
2296
           .DATA_WIDTH(RX_FIFO_DATA_WIDTH),
2297
           .DEPTH(RX_FIFO_DEPTH),
2298
           .CNT_WIDTH(RX_FIFO_CNT_WIDTH))
2299
rx_fifo (
2300
         .clk            (WB_CLK_I),
2301
         .reset          (Reset),
2302
         // Inputs
2303
         .data_in        (RxDataLatched2),
2304
         .write          (WriteRxDataToFifo_wb & ~RxBufferFull),
2305
         .read           (MasterWbRX & m_wb_ack_i),
2306
         .clear          (RxFifoReset),
2307
         // Outputs
2308
         .data_out       (m_wb_dat_o),
2309
         .full           (RxBufferFull),
2310
         .almost_full    (),
2311
         .almost_empty   (RxBufferAlmostEmpty),
2312
         .empty          (RxBufferEmpty),
2313
         .cnt            (rxfifo_cnt)
2314 88 mohor
        );
2315 40 mohor
 
2316 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2317
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2318 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2319 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2320 40 mohor
 
2321
 
2322
// Generation of the end-of-frame signal
2323
always @ (posedge MRxClk or posedge Reset)
2324 38 mohor
begin
2325 40 mohor
  if(Reset)
2326 352 olof
    ShiftEnded_rck <= 1'b0;
2327 38 mohor
  else
2328 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2329 352 olof
    ShiftEnded_rck <= 1'b1;
2330 38 mohor
  else
2331 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2332 352 olof
    ShiftEnded_rck <= 1'b0;
2333 38 mohor
end
2334
 
2335 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2336
begin
2337
  if(Reset)
2338 352 olof
    ShiftEndedSync1 <= 1'b0;
2339 40 mohor
  else
2340 352 olof
    ShiftEndedSync1 <= ShiftEnded_rck;
2341 40 mohor
end
2342 38 mohor
 
2343 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2344 38 mohor
begin
2345 40 mohor
  if(Reset)
2346 352 olof
    ShiftEndedSync2 <= 1'b0;
2347 38 mohor
  else
2348 352 olof
    ShiftEndedSync2 <= ShiftEndedSync1;
2349 40 mohor
end
2350 38 mohor
 
2351 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2352
begin
2353
  if(Reset)
2354 352 olof
    ShiftEndedSync3 <= 1'b0;
2355 118 mohor
  else
2356
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2357 352 olof
    ShiftEndedSync3 <= 1'b1;
2358 118 mohor
  else
2359
  if(ShiftEnded)
2360 352 olof
    ShiftEndedSync3 <= 1'b0;
2361 118 mohor
end
2362 38 mohor
 
2363 40 mohor
// Generation of the end-of-frame signal
2364
always @ (posedge WB_CLK_I or posedge Reset)
2365 38 mohor
begin
2366 40 mohor
  if(Reset)
2367 352 olof
    ShiftEnded <= 1'b0;
2368 38 mohor
  else
2369 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2370 352 olof
    ShiftEnded <= 1'b1;
2371 38 mohor
  else
2372 40 mohor
  if(RxStatusWrite)
2373 352 olof
    ShiftEnded <= 1'b0;
2374 38 mohor
end
2375
 
2376 118 mohor
always @ (posedge MRxClk or posedge Reset)
2377
begin
2378
  if(Reset)
2379 352 olof
    ShiftEndedSync_c1 <= 1'b0;
2380 118 mohor
  else
2381 352 olof
    ShiftEndedSync_c1 <= ShiftEndedSync2;
2382 118 mohor
end
2383 38 mohor
 
2384 118 mohor
always @ (posedge MRxClk or posedge Reset)
2385
begin
2386
  if(Reset)
2387 352 olof
    ShiftEndedSync_c2 <= 1'b0;
2388 118 mohor
  else
2389 352 olof
    ShiftEndedSync_c2 <= ShiftEndedSync_c1;
2390 118 mohor
end
2391
 
2392 40 mohor
// Generation of the end-of-frame signal
2393
always @ (posedge MRxClk or posedge Reset)
2394 38 mohor
begin
2395 40 mohor
  if(Reset)
2396 352 olof
    RxEnableWindow <= 1'b0;
2397 354 olof
  else if(RxStartFrm)
2398 352 olof
    RxEnableWindow <= 1'b1;
2399 354 olof
  else if(RxEndFrm | RxAbort)
2400 352 olof
    RxEnableWindow <= 1'b0;
2401 38 mohor
end
2402
 
2403
 
2404 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2405 38 mohor
begin
2406 40 mohor
  if(Reset)
2407 352 olof
    RxAbortSync1 <= 1'b0;
2408 38 mohor
  else
2409 352 olof
    RxAbortSync1 <= RxAbortLatched;
2410 40 mohor
end
2411
 
2412
always @ (posedge WB_CLK_I or posedge Reset)
2413
begin
2414
  if(Reset)
2415 352 olof
    RxAbortSync2 <= 1'b0;
2416 38 mohor
  else
2417 352 olof
    RxAbortSync2 <= RxAbortSync1;
2418 38 mohor
end
2419
 
2420 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2421
begin
2422
  if(Reset)
2423 352 olof
    RxAbortSync3 <= 1'b0;
2424 150 mohor
  else
2425 352 olof
    RxAbortSync3 <= RxAbortSync2;
2426 150 mohor
end
2427
 
2428
always @ (posedge WB_CLK_I or posedge Reset)
2429
begin
2430
  if(Reset)
2431 352 olof
    RxAbortSync4 <= 1'b0;
2432 150 mohor
  else
2433 352 olof
    RxAbortSync4 <= RxAbortSync3;
2434 150 mohor
end
2435
 
2436 40 mohor
always @ (posedge MRxClk or posedge Reset)
2437
begin
2438
  if(Reset)
2439 352 olof
    RxAbortSyncb1 <= 1'b0;
2440 40 mohor
  else
2441 352 olof
    RxAbortSyncb1 <= RxAbortSync2;
2442 40 mohor
end
2443 38 mohor
 
2444 40 mohor
always @ (posedge MRxClk or posedge Reset)
2445 38 mohor
begin
2446 40 mohor
  if(Reset)
2447 352 olof
    RxAbortSyncb2 <= 1'b0;
2448 38 mohor
  else
2449 352 olof
    RxAbortSyncb2 <= RxAbortSyncb1;
2450 38 mohor
end
2451
 
2452
 
2453 64 mohor
always @ (posedge MRxClk or posedge Reset)
2454
begin
2455
  if(Reset)
2456 352 olof
    RxAbortLatched <= 1'b0;
2457 64 mohor
  else
2458 150 mohor
  if(RxAbortSyncb2)
2459 352 olof
    RxAbortLatched <= 1'b0;
2460 150 mohor
  else
2461 64 mohor
  if(RxAbort)
2462 352 olof
    RxAbortLatched <= 1'b1;
2463 64 mohor
end
2464 40 mohor
 
2465 64 mohor
 
2466 42 mohor
always @ (posedge MRxClk or posedge Reset)
2467
begin
2468
  if(Reset)
2469 352 olof
    LatchedRxLength[15:0] <= 16'h0;
2470 42 mohor
  else
2471 150 mohor
  if(LoadRxStatus)
2472 352 olof
    LatchedRxLength[15:0] <= RxLength[15:0];
2473 42 mohor
end
2474
 
2475
 
2476 354 olof
assign RxStatusIn = {ReceivedPauseFrm,
2477
                     AddressMiss,
2478
                     RxOverrun,
2479
                     InvalidSymbol,
2480
                     DribbleNibble,
2481
                     ReceivedPacketTooBig,
2482
                     ShortFrame,
2483
                     LatchedCrcError,
2484
                     RxLateCollision};
2485 42 mohor
 
2486
always @ (posedge MRxClk or posedge Reset)
2487
begin
2488
  if(Reset)
2489 352 olof
    RxStatusInLatched <= 'h0;
2490 42 mohor
  else
2491 150 mohor
  if(LoadRxStatus)
2492 352 olof
    RxStatusInLatched <= RxStatusIn;
2493 42 mohor
end
2494
 
2495
 
2496 60 mohor
// Rx overrun
2497
always @ (posedge WB_CLK_I or posedge Reset)
2498
begin
2499
  if(Reset)
2500 352 olof
    RxOverrun <= 1'b0;
2501 354 olof
  else if(RxStatusWrite)
2502 352 olof
    RxOverrun <= 1'b0;
2503 354 olof
  else if(RxBufferFull & WriteRxDataToFifo_wb)
2504 352 olof
    RxOverrun <= 1'b1;
2505 60 mohor
end
2506 48 mohor
 
2507 77 mohor
 
2508
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2509
 
2510
 
2511 239 tadejm
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
2512 250 mohor
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
2513 354 olof
// AddressMiss is identifying that a frame was received because of the
2514
// promiscous mode and is not an error
2515 239 tadejm
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
2516
 
2517 272 tadejm
 
2518 354 olof
// Latching and synchronizing RxStatusWrite signal. This signal is used for
2519
// clearing the ReceivedPauseFrm signal
2520 272 tadejm
always @ (posedge WB_CLK_I or posedge Reset)
2521
begin
2522
  if(Reset)
2523 352 olof
    RxStatusWriteLatched <= 1'b0;
2524 272 tadejm
  else
2525
  if(RxStatusWriteLatched_syncb2)
2526 352 olof
    RxStatusWriteLatched <= 1'b0;
2527 272 tadejm
  else
2528
  if(RxStatusWrite)
2529 352 olof
    RxStatusWriteLatched <= 1'b1;
2530 272 tadejm
end
2531
 
2532
 
2533
always @ (posedge MRxClk or posedge Reset)
2534
begin
2535
  if(Reset)
2536
    begin
2537 352 olof
      RxStatusWriteLatched_sync1 <= 1'b0;
2538
      RxStatusWriteLatched_sync2 <= 1'b0;
2539 272 tadejm
    end
2540
  else
2541
    begin
2542 352 olof
      RxStatusWriteLatched_sync1 <= RxStatusWriteLatched;
2543
      RxStatusWriteLatched_sync2 <= RxStatusWriteLatched_sync1;
2544 272 tadejm
    end
2545
end
2546
 
2547
 
2548
always @ (posedge WB_CLK_I or posedge Reset)
2549
begin
2550
  if(Reset)
2551
    begin
2552 352 olof
      RxStatusWriteLatched_syncb1 <= 1'b0;
2553
      RxStatusWriteLatched_syncb2 <= 1'b0;
2554 272 tadejm
    end
2555
  else
2556
    begin
2557 352 olof
      RxStatusWriteLatched_syncb1 <= RxStatusWriteLatched_sync2;
2558
      RxStatusWriteLatched_syncb2 <= RxStatusWriteLatched_syncb1;
2559 272 tadejm
    end
2560
end
2561
 
2562
 
2563 77 mohor
// Tx Done Interrupt
2564
always @ (posedge WB_CLK_I or posedge Reset)
2565
begin
2566
  if(Reset)
2567 352 olof
    TxB_IRQ <= 1'b0;