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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 360

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 38 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 333 igorm
// Revision 1.57  2005/02/21 11:35:33  igorm
45
// Defer indication fixed.
46
//
47 329 igorm
// Revision 1.56  2004/04/30 10:30:00  igorm
48
// Accidently deleted line put back.
49
//
50 323 igorm
// Revision 1.55  2004/04/26 15:26:23  igorm
51
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
52
//   previous update of the core.
53
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
54
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
55
//   register. (thanks to Mathias and Torbjorn)
56
// - Multicast reception was fixed. Thanks to Ulrich Gries
57
//
58 321 igorm
// Revision 1.54  2003/11/12 18:24:59  tadejm
59
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
60
//
61 304 tadejm
// Revision 1.53  2003/10/17 07:46:17  markom
62
// mbist signals updated according to newest convention
63
//
64 302 markom
// Revision 1.52  2003/01/30 14:51:31  mohor
65
// Reset has priority in some flipflops.
66
//
67 280 mohor
// Revision 1.51  2003/01/30 13:36:22  mohor
68
// A new bug (entered with previous update) fixed. When abort occured sometimes
69
// data transmission was blocked.
70
//
71 278 mohor
// Revision 1.50  2003/01/22 13:49:26  tadejm
72
// When control packets were received, they were ignored in some cases.
73
//
74 272 tadejm
// Revision 1.49  2003/01/21 12:09:40  mohor
75
// When receiving normal data frame and RxFlow control was switched on, RXB
76
// interrupt was not set.
77
//
78 270 mohor
// Revision 1.48  2003/01/20 12:05:26  mohor
79
// When in full duplex, transmit was sometimes blocked. Fixed.
80
//
81 269 mohor
// Revision 1.47  2002/11/22 13:26:21  mohor
82
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
83
// anywhere. Removed.
84
//
85 264 mohor
// Revision 1.46  2002/11/22 01:57:06  mohor
86
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
87
// synchronized.
88
//
89 261 mohor
// Revision 1.45  2002/11/19 17:33:34  mohor
90
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
91
// that a frame was received because of the promiscous mode.
92
//
93 250 mohor
// Revision 1.44  2002/11/13 22:21:40  tadejm
94
// RxError is not generated when small frame reception is enabled and small
95
// frames are received.
96
//
97 239 tadejm
// Revision 1.43  2002/10/18 20:53:34  mohor
98
// case changed to casex.
99
//
100 229 mohor
// Revision 1.42  2002/10/18 17:04:20  tadejm
101
// Changed BIST scan signals.
102
//
103 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
104
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
105
//
106 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
107
// TxStatus is written after last access to the TX fifo is finished (in case of abort
108
// or retry). TxDone is fixed.
109
//
110 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
111
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
112
// TxDone and TxRetry are generated after the current WISHBONE access is
113
// finished.
114
//
115 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
116
// BIST added.
117
//
118 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
119
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
120
//
121 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
122
// Reception is possible after RxPointer is read and not after BD is read. For
123
// that reason RxBDReady is changed to RxReady.
124
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
125
// comes, interrupt is generated.
126
//
127 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
128
// Ethernet debug registers removed.
129
//
130 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
131
// Async reset for WB_ACK_O removed (when core was in reset, it was
132
// impossible to access BDs).
133
// RxPointers and TxPointers names changed to be more descriptive.
134
// TxUnderRun synchronized.
135
//
136 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
137
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
138
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
139
// was not used OK.
140
//
141 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
142
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
143
// need to multiply or devide any more.
144
//
145 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
146
// WriteRxDataToMemory signal changed so end of frame (when last word is
147
// written to fifo) is changed.
148
//
149 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
150
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
151
//
152 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
153
// ShiftEnded synchronization changed.
154
//
155 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
156
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
157
//
158 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
159
// RxPointer bug fixed.
160
//
161 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
162
// Previous bug wasn't succesfully removed. Now fixed.
163
//
164 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
165
// Master state machine had a bug when switching from master write to
166
// master read.
167
//
168 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
169
// m_wb_cyc_o signal released after every single transfer.
170
//
171 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
172
// Outputs registered. Reset changed for eth_wishbone module.
173
//
174 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
175
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
176
// bug fixed.
177
//
178 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
179
// Small typo fixed.
180
//
181 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
182
// Any address can be used for Tx and Rx BD pointers. Address does not need
183
// to be aligned.
184
//
185 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
186
// Comments in Slovene language removed.
187
//
188 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
189
// casex changed with case, fifo reset changed.
190
//
191 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
192
// rx_fifo was not always cleared ok. Fixed.
193
//
194 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
195
// Status was not latched correctly sometimes. Fixed.
196
//
197 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
198
// Big Endian problem when sending frames fixed.
199
//
200 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
201
// Byte ordering changed (Big Endian used). casex changed with case because
202
// Xilinx Foundation had problems. Tested in HW. It WORKS.
203
//
204 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
205
// Small fixes for external/internal DMA missmatches.
206
//
207 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
208
// Interrupts changed
209
//
210 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
211
// Status was not written correctly when frames were discarted because of
212
// address mismatch.
213
//
214 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
215
// RxStartFrm cleared when abort or retry comes.
216
//
217 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
218
// Changes that were lost when updating from 1.5 to 1.8 fixed.
219
//
220 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
221
// Addition  of new module eth_addrcheck.v
222
//
223
// Revision 1.7  2002/02/12 17:03:47  mohor
224
// RxOverRun added to statuses.
225
//
226
// Revision 1.6  2002/02/11 09:18:22  mohor
227
// Tx status is written back to the BD.
228
//
229 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
230
// Rx status is written back to the BD.
231
//
232 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
233
// non-DMA host interface added. Select the right configutation in eth_defines.
234
//
235 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
236
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
237
// MHz. Statuses, overrun, control frame transmission and reception still  need
238
// to be fixed.
239
//
240 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
241
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
242
// added.
243
//
244 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
245
// Initial version. Equals to eth_wishbonedma.v at this moment.
246 38 mohor
//
247
//
248
//
249
 
250 356 olof
`include "ethmac_defines.v"
251 38 mohor
`include "timescale.v"
252
 
253
 
254
module eth_wishbone
255 354 olof
  (
256 38 mohor
 
257 354 olof
   // WISHBONE common
258
   WB_CLK_I, WB_DAT_I, WB_DAT_O,
259 38 mohor
 
260 354 olof
   // WISHBONE slave
261
   WB_ADR_I, WB_WE_I, WB_ACK_O,
262
   BDCs,
263 38 mohor
 
264 354 olof
   Reset,
265 40 mohor
 
266 354 olof
   // WISHBONE master
267
   m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
268
   m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
269
   m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
270 39 mohor
 
271 219 mohor
`ifdef ETH_WISHBONE_B3
272 354 olof
   m_wb_cti_o, m_wb_bte_o,
273 219 mohor
`endif
274
 
275 354 olof
   //TX
276
   MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
277
   TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
278
   PerPacketPad,
279 38 mohor
 
280 354 olof
   //RX
281
   MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
282
   RxStatusWriteLatched_sync2,
283
 
284
   // Register
285
   r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
286 38 mohor
 
287 354 olof
   // Interrupts
288
   TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
289
 
290
   // Rx Status
291
   InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
292
   ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
293
   AddressMiss,
294
   ReceivedPauseFrm,
295
 
296
   // Tx Status
297
   RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched,
298
   CarrierSenseLost
299 164 mohor
 
300 354 olof
   // Bist
301 210 mohor
`ifdef ETH_BIST
302 354 olof
   ,
303
   // debug chain signals
304
   mbist_si_i,       // bist scan serial in
305
   mbist_so_o,       // bist scan serial out
306
   mbist_ctrl_i        // bist chain shift control
307 210 mohor
`endif
308
 
309 360 olof
`ifdef WISHBONE_DEBUG
310
   ,
311
   dbg_dat0
312
`endif
313 210 mohor
 
314 38 mohor
 
315 354 olof
   );
316 38 mohor
 
317 349 olof
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
318
parameter TX_FIFO_DEPTH      = `ETH_TX_FIFO_DEPTH;
319
parameter TX_FIFO_CNT_WIDTH  = `ETH_TX_FIFO_CNT_WIDTH;
320
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
321
parameter RX_FIFO_DEPTH      = `ETH_RX_FIFO_DEPTH;
322
parameter RX_FIFO_CNT_WIDTH  = `ETH_RX_FIFO_CNT_WIDTH;
323 38 mohor
 
324
// WISHBONE common
325
input           WB_CLK_I;       // WISHBONE clock
326
input  [31:0]   WB_DAT_I;       // WISHBONE data input
327
output [31:0]   WB_DAT_O;       // WISHBONE data output
328
 
329
// WISHBONE slave
330
input   [9:2]   WB_ADR_I;       // WISHBONE address input
331
input           WB_WE_I;        // WISHBONE write enable input
332 304 tadejm
input   [3:0]   BDCs;           // Buffer descriptors are selected
333 38 mohor
output          WB_ACK_O;       // WISHBONE acknowledge output
334
 
335 39 mohor
// WISHBONE master
336 329 igorm
output  [29:0]  m_wb_adr_o;     // 
337 39 mohor
output   [3:0]  m_wb_sel_o;     // 
338
output          m_wb_we_o;      // 
339
output  [31:0]  m_wb_dat_o;     // 
340
output          m_wb_cyc_o;     // 
341
output          m_wb_stb_o;     // 
342
input   [31:0]  m_wb_dat_i;     // 
343
input           m_wb_ack_i;     // 
344
input           m_wb_err_i;     // 
345
 
346 219 mohor
`ifdef ETH_WISHBONE_B3
347
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
348
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
349
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
350
`endif
351
 
352 40 mohor
input           Reset;       // Reset signal
353 39 mohor
 
354 60 mohor
// Rx Status signals
355 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
356
input           LatchedCrcError;  // CRC error
357
input           RxLateCollision;  // Late collision occured while receiving frame
358 354 olof
input           ShortFrame;       // Frame shorter then the minimum size
359
                                  // (r_MinFL) was received while small
360
                                  // packets are enabled (r_RecSmall)
361 42 mohor
input           DribbleNibble;    // Extra nibble received
362
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
363
input    [15:0] RxLength;         // Length of the incoming frame
364
input           LoadRxStatus;     // Rx status was loaded
365 354 olof
input           ReceivedPacketGood;  // Received packet's length and CRC are
366
                                     // good
367
input           AddressMiss;      // When a packet is received AddressMiss
368
                                  // status is written to the Rx BD
369 261 mohor
input           r_RxFlow;
370 270 mohor
input           r_PassAll;
371 261 mohor
input           ReceivedPauseFrm;
372 39 mohor
 
373 60 mohor
// Tx Status signals
374
input     [3:0] RetryCntLatched;  // Latched Retry Counter
375 354 olof
input           RetryLimit;       // Retry limit reached (Retry Max value +1
376
                                  // attempts were made)
377 60 mohor
input           LateCollLatched;  // Late collision occured
378 354 olof
input           DeferLatched;     // Defer indication (Frame was defered
379
                                  // before sucessfully sent)
380 329 igorm
output          RstDeferLatched;
381 354 olof
input           CarrierSenseLost; // Carrier Sense was lost during the
382
                                  // frame transmission
383 60 mohor
 
384 38 mohor
// Tx
385
input           MTxClk;         // Transmit clock (from PHY)
386
input           TxUsedData;     // Transmit packet used data
387
input           TxRetry;        // Transmit packet retry
388
input           TxAbort;        // Transmit packet abort
389
input           TxDone;         // Transmission ended
390
output          TxStartFrm;     // Transmit packet start frame
391
output          TxEndFrm;       // Transmit packet end frame
392
output  [7:0]   TxData;         // Transmit packet data byte
393
output          TxUnderRun;     // Transmit packet under-run
394
output          PerPacketCrcEn; // Per packet crc enable
395
output          PerPacketPad;   // Per packet pading
396
 
397
// Rx
398
input           MRxClk;         // Receive clock (from PHY)
399
input   [7:0]   RxData;         // Received data byte (from PHY)
400
input           RxValid;        // 
401
input           RxStartFrm;     // 
402
input           RxEndFrm;       // 
403 354 olof
input           RxAbort;        // This signal is set when address doesn't
404
                                // match.
405 272 tadejm
output          RxStatusWriteLatched_sync2;
406 38 mohor
 
407
//Register
408
input           r_TxEn;         // Transmit enable
409
input           r_RxEn;         // Receive enable
410
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
411
 
412
// Interrupts
413
output TxB_IRQ;
414
output TxE_IRQ;
415
output RxB_IRQ;
416 77 mohor
output RxE_IRQ;
417 38 mohor
output Busy_IRQ;
418
 
419 77 mohor
 
420 210 mohor
// Bist
421
`ifdef ETH_BIST
422 302 markom
input   mbist_si_i;       // bist scan serial in
423
output  mbist_so_o;       // bist scan serial out
424 354 olof
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
425 210 mohor
`endif
426
 
427 360 olof
`ifdef WISHBONE_DEBUG
428
   output [31:0]                        dbg_dat0;
429
`endif
430
 
431
 
432 77 mohor
reg TxB_IRQ;
433
reg TxE_IRQ;
434
reg RxB_IRQ;
435
reg RxE_IRQ;
436
 
437 38 mohor
reg             TxStartFrm;
438
reg             TxEndFrm;
439
reg     [7:0]   TxData;
440
 
441
reg             TxUnderRun;
442 60 mohor
reg             TxUnderRun_wb;
443 38 mohor
 
444
reg             TxBDRead;
445 39 mohor
wire            TxStatusWrite;
446 38 mohor
 
447
reg     [1:0]   TxValidBytesLatched;
448
 
449
reg    [15:0]   TxLength;
450 60 mohor
reg    [15:0]   LatchedTxLength;
451
reg   [14:11]   TxStatus;
452 38 mohor
 
453 60 mohor
reg   [14:13]   RxStatus;
454 38 mohor
 
455
reg             TxStartFrm_wb;
456
reg             TxRetry_wb;
457 39 mohor
reg             TxAbort_wb;
458 38 mohor
reg             TxDone_wb;
459
 
460
reg             TxDone_wb_q;
461
reg             TxAbort_wb_q;
462 39 mohor
reg             TxRetry_wb_q;
463 219 mohor
reg             TxRetryPacket;
464 221 mohor
reg             TxRetryPacket_NotCleared;
465
reg             TxDonePacket;
466
reg             TxDonePacket_NotCleared;
467 219 mohor
reg             TxAbortPacket;
468 221 mohor
reg             TxAbortPacket_NotCleared;
469 38 mohor
reg             RxBDReady;
470 166 mohor
reg             RxReady;
471 38 mohor
reg             TxBDReady;
472
 
473
reg             RxBDRead;
474
 
475
reg    [31:0]   TxDataLatched;
476
reg     [1:0]   TxByteCnt;
477
reg             LastWord;
478 39 mohor
reg             ReadTxDataFromFifo_tck;
479 38 mohor
 
480
reg             BlockingTxStatusWrite;
481
reg             BlockingTxBDRead;
482
 
483 40 mohor
reg             Flop;
484 38 mohor
 
485 329 igorm
reg     [7:1]   TxBDAddress;
486
reg     [7:1]   RxBDAddress;
487 38 mohor
 
488
reg             TxRetrySync1;
489
reg             TxAbortSync1;
490 39 mohor
reg             TxDoneSync1;
491 38 mohor
 
492
reg             TxAbort_q;
493
reg             TxRetry_q;
494
reg             TxUsedData_q;
495
 
496
reg    [31:0]   RxDataLatched2;
497 82 mohor
 
498
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
499
 
500 38 mohor
reg     [1:0]   RxValidBytes;
501
reg     [1:0]   RxByteCnt;
502
reg             LastByteIn;
503
reg             ShiftWillEnd;
504
 
505 40 mohor
reg             WriteRxDataToFifo;
506 42 mohor
reg    [15:0]   LatchedRxLength;
507 64 mohor
reg             RxAbortLatched;
508 38 mohor
 
509 40 mohor
reg             ShiftEnded;
510 60 mohor
reg             RxOverrun;
511 38 mohor
 
512 304 tadejm
reg     [3:0]   BDWrite;                    // BD Write Enable for access from WISHBONE side
513 40 mohor
reg             BDRead;                     // BD Read access from WISHBONE side
514 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
515
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
516 38 mohor
 
517 39 mohor
reg             TxEndFrm_wb;
518 38 mohor
 
519 39 mohor
wire            TxRetryPulse;
520 38 mohor
wire            TxDonePulse;
521
wire            TxAbortPulse;
522
 
523
wire            StartRxBDRead;
524
 
525
wire            StartTxBDRead;
526
 
527
wire            TxIRQEn;
528
wire            WrapTxStatusBit;
529
 
530 77 mohor
wire            RxIRQEn;
531 38 mohor
wire            WrapRxStatusBit;
532
 
533
wire    [1:0]   TxValidBytes;
534
 
535 329 igorm
wire    [7:1]   TempTxBDAddress;
536
wire    [7:1]   TempRxBDAddress;
537 38 mohor
 
538 272 tadejm
wire            RxStatusWrite;
539 329 igorm
wire            RxBufferFull;
540
wire            RxBufferAlmostEmpty;
541
wire            RxBufferEmpty;
542 272 tadejm
 
543 106 mohor
reg             WB_ACK_O;
544 38 mohor
 
545 261 mohor
wire    [8:0]   RxStatusIn;
546
reg     [8:0]   RxStatusInLatched;
547 42 mohor
 
548 39 mohor
reg WbEn, WbEn_q;
549
reg RxEn, RxEn_q;
550
reg TxEn, TxEn_q;
551 321 igorm
reg r_TxEn_q;
552
reg r_RxEn_q;
553 38 mohor
 
554 39 mohor
wire ram_ce;
555 304 tadejm
wire [3:0]  ram_we;
556 39 mohor
wire ram_oe;
557
reg [7:0]   ram_addr;
558
reg [31:0]  ram_di;
559
wire [31:0] ram_do;
560 38 mohor
 
561 39 mohor
wire StartTxPointerRead;
562 354 olof
reg TxPointerRead;
563 39 mohor
reg TxEn_needed;
564 40 mohor
reg RxEn_needed;
565 38 mohor
 
566 40 mohor
wire StartRxPointerRead;
567 355 olof
reg RxPointerRead;
568 38 mohor
 
569 354 olof
// RX shift ending signals
570
reg ShiftEnded_rck;
571
reg ShiftEndedSync1;
572
reg ShiftEndedSync2;
573
reg ShiftEndedSync3;
574
reg ShiftEndedSync_c1;
575
reg ShiftEndedSync_c2;
576
 
577
wire StartShiftWillEnd;
578
 
579
reg StartOccured;
580
reg TxStartFrm_sync1;
581
reg TxStartFrm_sync2;
582
reg TxStartFrm_syncb1;
583
reg TxStartFrm_syncb2;
584
 
585
wire TxFifoClear;
586
wire TxBufferAlmostFull;
587
wire TxBufferFull;
588
wire TxBufferEmpty;
589
wire TxBufferAlmostEmpty;
590
wire SetReadTxDataFromMemory;
591
reg BlockReadTxDataFromMemory;
592
 
593
reg tx_burst_en;
594
reg rx_burst_en;
595
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
596
 
597
wire ReadTxDataFromMemory_2;
598
wire tx_burst;
599
 
600
wire [31:0] TxData_wb;
601
wire ReadTxDataFromFifo_wb;
602
 
603
wire [TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
604
wire [RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
605
 
606
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
607
 
608
wire rx_burst;
609
wire enough_data_in_rxfifo_for_burst;
610
wire enough_data_in_rxfifo_for_burst_plus1;
611
 
612
reg ReadTxDataFromMemory;
613
wire WriteRxDataToMemory;
614
 
615
reg MasterWbTX;
616
reg MasterWbRX;
617
 
618
reg [29:0] m_wb_adr_o;
619
reg        m_wb_cyc_o;
620
reg  [3:0] m_wb_sel_o;
621
reg        m_wb_we_o;
622
 
623
wire TxLengthEq0;
624
wire TxLengthLt4;
625
 
626
reg BlockingIncrementTxPointer;
627
reg [31:2] TxPointerMSB;
628
reg [1:0]  TxPointerLSB;
629
reg [1:0]  TxPointerLSB_rst;
630
reg [31:2] RxPointerMSB;
631
reg [1:0]  RxPointerLSB_rst;
632
 
633
wire RxBurstAcc;
634
wire RxWordAcc;
635
wire RxHalfAcc;
636
wire RxByteAcc;
637
 
638
wire ResetTxBDReady;
639
reg BlockingTxStatusWrite_sync1;
640
reg BlockingTxStatusWrite_sync2;
641
reg BlockingTxStatusWrite_sync3;
642
 
643
reg cyc_cleared;
644
reg IncrTxPointer;
645
 
646
reg  [3:0] RxByteSel;
647
wire MasterAccessFinished;
648
 
649
reg LatchValidBytes;
650
reg LatchValidBytes_q;
651
 
652
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
653
reg ReadTxDataFromFifo_sync1;
654
reg ReadTxDataFromFifo_sync2;
655
reg ReadTxDataFromFifo_sync3;
656
reg ReadTxDataFromFifo_syncb1;
657
reg ReadTxDataFromFifo_syncb2;
658
reg ReadTxDataFromFifo_syncb3;
659
 
660
reg RxAbortSync1;
661
reg RxAbortSync2;
662
reg RxAbortSync3;
663
reg RxAbortSync4;
664
reg RxAbortSyncb1;
665
reg RxAbortSyncb2;
666
 
667
reg RxEnableWindow;
668
 
669
wire SetWriteRxDataToFifo;
670
 
671
reg WriteRxDataToFifoSync1;
672
reg WriteRxDataToFifoSync2;
673
reg WriteRxDataToFifoSync3;
674
 
675
wire WriteRxDataToFifo_wb;
676
 
677
reg LatchedRxStartFrm;
678
reg SyncRxStartFrm;
679
reg SyncRxStartFrm_q;
680
reg SyncRxStartFrm_q2;
681
wire RxFifoReset;
682
 
683
wire TxError;
684
wire RxError;
685
 
686
reg RxStatusWriteLatched;
687
reg RxStatusWriteLatched_sync1;
688
reg RxStatusWriteLatched_sync2;
689
reg RxStatusWriteLatched_syncb1;
690
reg RxStatusWriteLatched_syncb2;
691
 
692 219 mohor
`ifdef ETH_WISHBONE_B3
693
assign m_wb_bte_o = 2'b00;    // Linear burst
694
`endif
695 39 mohor
 
696 329 igorm
assign m_wb_stb_o = m_wb_cyc_o;
697 219 mohor
 
698 159 mohor
always @ (posedge WB_CLK_I)
699 40 mohor
begin
700 352 olof
  WB_ACK_O <= (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
701 40 mohor
end
702 39 mohor
 
703 106 mohor
assign WB_DAT_O = ram_do;
704 39 mohor
 
705 41 mohor
// Generic synchronous single-port RAM interface
706 354 olof
eth_spram_256x32
707
     bd_ram
708
     (
709
      .clk     (WB_CLK_I),
710
      .rst     (Reset),
711
      .ce      (ram_ce),
712
      .we      (ram_we),
713
      .oe      (ram_oe),
714
      .addr    (ram_addr),
715
      .di      (ram_di),
716 358 olof
      .dato    (ram_do)
717 210 mohor
`ifdef ETH_BIST
718 354 olof
      ,
719
      .mbist_si_i       (mbist_si_i),
720
      .mbist_so_o       (mbist_so_o),
721
      .mbist_ctrl_i       (mbist_ctrl_i)
722 210 mohor
`endif
723 354 olof
      );
724 41 mohor
 
725 39 mohor
assign ram_ce = 1'b1;
726 354 olof
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) |
727
                {4{(TxStatusWrite | RxStatusWrite)}};
728
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q &
729
                (TxBDRead | TxPointerRead) | RxEn & RxEn_q &
730
                (RxBDRead | RxPointerRead);
731 39 mohor
 
732
 
733 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
734 38 mohor
begin
735 40 mohor
  if(Reset)
736 352 olof
    TxEn_needed <= 1'b0;
737 38 mohor
  else
738 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
739 352 olof
    TxEn_needed <= 1'b1;
740 39 mohor
  else
741
  if(TxPointerRead & TxEn & TxEn_q)
742 352 olof
    TxEn_needed <= 1'b0;
743 38 mohor
end
744
 
745 39 mohor
// Enabling access to the RAM for three devices.
746 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
747 39 mohor
begin
748 40 mohor
  if(Reset)
749 39 mohor
    begin
750 352 olof
      WbEn <= 1'b1;
751
      RxEn <= 1'b0;
752
      TxEn <= 1'b0;
753
      ram_addr <= 8'h0;
754
      ram_di <= 32'h0;
755
      BDRead <= 1'b0;
756 359 olof
      BDWrite <= 0;
757 39 mohor
    end
758
  else
759
    begin
760
      // Switching between three stages depends on enable signals
761 355 olof
     /* verilator lint_off CASEINCOMPLETE */ // JB
762 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
763
        5'b100_10, 5'b100_11 :
764 39 mohor
          begin
765 352 olof
            WbEn <= 1'b0;
766
            RxEn <= 1'b1;  // wb access stage and r_RxEn is enabled
767
            TxEn <= 1'b0;
768
            ram_addr <= {RxBDAddress, RxPointerRead};
769
            ram_di <= RxBDDataIn;
770 39 mohor
          end
771
        5'b100_01 :
772
          begin
773 352 olof
            WbEn <= 1'b0;
774
            RxEn <= 1'b0;
775 354 olof
            TxEn <= 1'b1;  // wb access stage, r_RxEn is disabled but
776
                           // r_TxEn is enabled
777 352 olof
            ram_addr <= {TxBDAddress, TxPointerRead};
778
            ram_di <= TxBDDataIn;
779 39 mohor
          end
780 90 mohor
        5'b010_00, 5'b010_10 :
781 39 mohor
          begin
782 352 olof
            WbEn <= 1'b1;  // RxEn access stage and r_TxEn is disabled
783
            RxEn <= 1'b0;
784
            TxEn <= 1'b0;
785
            ram_addr <= WB_ADR_I[9:2];
786
            ram_di <= WB_DAT_I;
787
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
788
            BDRead <= (|BDCs) & ~WB_WE_I;
789 39 mohor
          end
790 90 mohor
        5'b010_01, 5'b010_11 :
791 39 mohor
          begin
792 352 olof
            WbEn <= 1'b0;
793
            RxEn <= 1'b0;
794
            TxEn <= 1'b1;  // RxEn access stage and r_TxEn is enabled
795
            ram_addr <= {TxBDAddress, TxPointerRead};
796
            ram_di <= TxBDDataIn;
797 39 mohor
          end
798 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
799 39 mohor
          begin
800 354 olof
            WbEn <= 1'b1;  // TxEn access stage (we always go to wb
801
                           // access stage)
802 352 olof
            RxEn <= 1'b0;
803
            TxEn <= 1'b0;
804
            ram_addr <= WB_ADR_I[9:2];
805
            ram_di <= WB_DAT_I;
806
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
807
            BDRead <= (|BDCs) & ~WB_WE_I;
808 39 mohor
          end
809
        5'b100_00 :
810
          begin
811 354 olof
            WbEn <= 1'b0;  // WbEn access stage and there is no need
812
                           // for other stages. WbEn needs to be
813
                           // switched off for a bit
814 39 mohor
          end
815
        5'b000_00 :
816
          begin
817 352 olof
            WbEn <= 1'b1;  // Idle state. We go to WbEn access stage.
818
            RxEn <= 1'b0;
819
            TxEn <= 1'b0;
820
            ram_addr <= WB_ADR_I[9:2];
821
            ram_di <= WB_DAT_I;
822
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
823
            BDRead <= (|BDCs) & ~WB_WE_I;
824 39 mohor
          end
825
      endcase
826 355 olof
      /* verilator lint_on CASEINCOMPLETE */
827 39 mohor
    end
828
end
829
 
830
 
831
// Delayed stage signals
832 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
833 39 mohor
begin
834 40 mohor
  if(Reset)
835 39 mohor
    begin
836 352 olof
      WbEn_q <= 1'b0;
837
      RxEn_q <= 1'b0;
838
      TxEn_q <= 1'b0;
839
      r_TxEn_q <= 1'b0;
840
      r_RxEn_q <= 1'b0;
841 39 mohor
    end
842
  else
843
    begin
844 352 olof
      WbEn_q <= WbEn;
845
      RxEn_q <= RxEn;
846
      TxEn_q <= TxEn;
847
      r_TxEn_q <= r_TxEn;
848
      r_RxEn_q <= r_RxEn;
849 39 mohor
    end
850
end
851
 
852 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
853 40 mohor
always @ (posedge MTxClk or posedge Reset)
854 38 mohor
begin
855 40 mohor
  if(Reset)
856 352 olof
    Flop <= 1'b0;
857 38 mohor
  else
858
  if(TxDone | TxAbort | TxRetry_q)
859 352 olof
    Flop <= 1'b0;
860 38 mohor
  else
861
  if(TxUsedData)
862 352 olof
    Flop <= ~Flop;
863 38 mohor
end
864
 
865 39 mohor
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
866 38 mohor
 
867
// Latching READY status of the Tx buffer descriptor
868 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
869 38 mohor
begin
870 40 mohor
  if(Reset)
871 352 olof
    TxBDReady <= 1'b0;
872 38 mohor
  else
873 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
874 354 olof
    // TxBDReady is sampled only once at the beginning.
875
    TxBDReady <= ram_do[15] & (ram_do[31:16] > 4);
876
  else
877
  // Only packets larger then 4 bytes are transmitted.
878 39 mohor
  if(ResetTxBDReady)
879 352 olof
    TxBDReady <= 1'b0;
880 38 mohor
end
881
 
882 39 mohor
// Reading the Tx buffer descriptor
883 354 olof
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) &
884
                       ~BlockingTxBDRead & ~TxBDReady;
885 39 mohor
 
886 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
887 38 mohor
begin
888 40 mohor
  if(Reset)
889 352 olof
    TxBDRead <= 1'b1;
890 38 mohor
  else
891 110 mohor
  if(StartTxBDRead)
892 352 olof
    TxBDRead <= 1'b1;
893 38 mohor
  else
894 39 mohor
  if(TxBDReady)
895 352 olof
    TxBDRead <= 1'b0;
896 38 mohor
end
897
 
898 39 mohor
// Reading Tx BD pointer
899
assign StartTxPointerRead = TxBDRead & TxBDReady;
900 38 mohor
 
901 39 mohor
// Reading Tx BD Pointer
902 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
903 38 mohor
begin
904 40 mohor
  if(Reset)
905 352 olof
    TxPointerRead <= 1'b0;
906 38 mohor
  else
907 39 mohor
  if(StartTxPointerRead)
908 352 olof
    TxPointerRead <= 1'b1;
909 38 mohor
  else
910 39 mohor
  if(TxEn_q)
911 352 olof
    TxPointerRead <= 1'b0;
912 38 mohor
end
913
 
914
 
915 39 mohor
// Writing status back to the Tx buffer descriptor
916 354 olof
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) &
917
                       TxEn & TxEn_q & ~BlockingTxStatusWrite;
918 38 mohor
 
919
 
920 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
921 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
922 38 mohor
begin
923 40 mohor
  if(Reset)
924 352 olof
    BlockingTxStatusWrite <= 1'b0;
925 38 mohor
  else
926 272 tadejm
  if(~TxDone_wb & ~TxAbort_wb)
927 352 olof
    BlockingTxStatusWrite <= 1'b0;
928 272 tadejm
  else
929 39 mohor
  if(TxStatusWrite)
930 352 olof
    BlockingTxStatusWrite <= 1'b1;
931 38 mohor
end
932
 
933
 
934 159 mohor
// Synchronizing BlockingTxStatusWrite to MTxClk
935
always @ (posedge MTxClk or posedge Reset)
936
begin
937
  if(Reset)
938 352 olof
    BlockingTxStatusWrite_sync1 <= 1'b0;
939 159 mohor
  else
940 352 olof
    BlockingTxStatusWrite_sync1 <= BlockingTxStatusWrite;
941 159 mohor
end
942
 
943
// Synchronizing BlockingTxStatusWrite to MTxClk
944
always @ (posedge MTxClk or posedge Reset)
945
begin
946
  if(Reset)
947 352 olof
    BlockingTxStatusWrite_sync2 <= 1'b0;
948 159 mohor
  else
949 352 olof
    BlockingTxStatusWrite_sync2 <= BlockingTxStatusWrite_sync1;
950 159 mohor
end
951
 
952 329 igorm
// Synchronizing BlockingTxStatusWrite to MTxClk
953
always @ (posedge MTxClk or posedge Reset)
954
begin
955
  if(Reset)
956 352 olof
    BlockingTxStatusWrite_sync3 <= 1'b0;
957 329 igorm
  else
958 352 olof
    BlockingTxStatusWrite_sync3 <= BlockingTxStatusWrite_sync2;
959 329 igorm
end
960 159 mohor
 
961 354 olof
assign RstDeferLatched = BlockingTxStatusWrite_sync2 &
962
                         ~BlockingTxStatusWrite_sync3;
963 329 igorm
 
964 39 mohor
// TxBDRead state is activated only once. 
965 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
966 39 mohor
begin
967 40 mohor
  if(Reset)
968 352 olof
    BlockingTxBDRead <= 1'b0;
969 39 mohor
  else
970 110 mohor
  if(StartTxBDRead)
971 352 olof
    BlockingTxBDRead <= 1'b1;
972 39 mohor
  else
973 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
974 352 olof
    BlockingTxBDRead <= 1'b0;
975 39 mohor
end
976 38 mohor
 
977
 
978 39 mohor
// Latching status from the tx buffer descriptor
979 354 olof
// Data is avaliable one cycle after the access is started (at that time
980
// signal TxEn is not active)
981 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
982 38 mohor
begin
983 40 mohor
  if(Reset)
984 352 olof
    TxStatus <= 4'h0;
985 38 mohor
  else
986 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
987 352 olof
    TxStatus <= ram_do[14:11];
988 38 mohor
end
989
 
990
 
991 39 mohor
 
992
//Latching length from the buffer descriptor;
993 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
994 38 mohor
begin
995 40 mohor
  if(Reset)
996 352 olof
    TxLength <= 16'h0;
997 38 mohor
  else
998 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
999 352 olof
    TxLength <= ram_do[31:16];
1000 38 mohor
  else
1001 39 mohor
  if(MasterWbTX & m_wb_ack_i)
1002
    begin
1003
      if(TxLengthLt4)
1004 352 olof
        TxLength <= 16'h0;
1005 354 olof
      else if(TxPointerLSB_rst==2'h0)
1006 359 olof
        TxLength <= TxLength - 16'd4;    // Length is subtracted at
1007 354 olof
                                        // the data request
1008
      else if(TxPointerLSB_rst==2'h1)
1009 359 olof
        TxLength <= TxLength - 16'd3;    // Length is subtracted
1010 354 olof
                                         // at the data request
1011
      else if(TxPointerLSB_rst==2'h2)
1012 359 olof
        TxLength <= TxLength - 16'd2;    // Length is subtracted
1013 354 olof
                                         // at the data request
1014
      else if(TxPointerLSB_rst==2'h3)
1015 359 olof
        TxLength <= TxLength - 16'd1;    // Length is subtracted
1016 354 olof
                                         // at the data request
1017 39 mohor
    end
1018 38 mohor
end
1019
 
1020 60 mohor
//Latching length from the buffer descriptor;
1021
always @ (posedge WB_CLK_I or posedge Reset)
1022
begin
1023
  if(Reset)
1024 352 olof
    LatchedTxLength <= 16'h0;
1025 60 mohor
  else
1026
  if(TxEn & TxEn_q & TxBDRead)
1027 352 olof
    LatchedTxLength <= ram_do[31:16];
1028 60 mohor
end
1029
 
1030 39 mohor
assign TxLengthEq0 = TxLength == 0;
1031
assign TxLengthLt4 = TxLength < 4;
1032 38 mohor
 
1033 39 mohor
 
1034 354 olof
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are
1035
// latched because TxPointerMSB is only used for word-aligned accesses.
1036 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1037 38 mohor
begin
1038 40 mohor
  if(Reset)
1039 352 olof
    TxPointerMSB <= 30'h0;
1040 38 mohor
  else
1041 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
1042 352 olof
    TxPointerMSB <= ram_do[31:2];
1043 38 mohor
  else
1044 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
1045 354 olof
      // TxPointer is word-aligned
1046
    TxPointerMSB <= TxPointerMSB + 1'b1;
1047 38 mohor
end
1048
 
1049 96 mohor
 
1050 354 olof
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are
1051
// performed, valid data does not necesserly start at byte 0 (could be byte
1052
// 0, 1, 2 or 3). This signals are used for proper selection of the start
1053
// byte (TxData and TxByteCnt) are set by this two bits.
1054 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1055
begin
1056
  if(Reset)
1057 352 olof
    TxPointerLSB[1:0] <= 0;
1058 96 mohor
  else
1059
  if(TxEn & TxEn_q & TxPointerRead)
1060 352 olof
    TxPointerLSB[1:0] <= ram_do[1:0];
1061 96 mohor
end
1062
 
1063
 
1064 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
1065 354 olof
// After the read access, TxLength needs to be decremented for the number of
1066
// the valid bytes (1 to 4 bytes are valid in the first word). After the
1067
// first read all bytes are valid so this two bits are reset to zero. 
1068 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1069
begin
1070
  if(Reset)
1071 352 olof
    TxPointerLSB_rst[1:0] <= 0;
1072 150 mohor
  else
1073
  if(TxEn & TxEn_q & TxPointerRead)
1074 352 olof
    TxPointerLSB_rst[1:0] <= ram_do[1:0];
1075 150 mohor
  else
1076 354 olof
// After first access pointer is word alligned
1077
  if(MasterWbTX & m_wb_ack_i)
1078 352 olof
    TxPointerLSB_rst[1:0] <= 0;
1079 150 mohor
end
1080 96 mohor
 
1081 150 mohor
 
1082 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1083 38 mohor
begin
1084 40 mohor
  if(Reset)
1085 352 olof
    BlockingIncrementTxPointer <= 0;
1086 38 mohor
  else
1087 39 mohor
  if(MasterAccessFinished)
1088 352 olof
    BlockingIncrementTxPointer <= 0;
1089 38 mohor
  else
1090 150 mohor
  if(IncrTxPointer)
1091 352 olof
    BlockingIncrementTxPointer <= 1'b1;
1092 38 mohor
end
1093
 
1094
 
1095 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
1096 39 mohor
 
1097 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1098 38 mohor
begin
1099 40 mohor
  if(Reset)
1100 352 olof
    ReadTxDataFromMemory <= 1'b0;
1101 38 mohor
  else
1102 278 mohor
  if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
1103 352 olof
    ReadTxDataFromMemory <= 1'b0;
1104 39 mohor
  else
1105 40 mohor
  if(SetReadTxDataFromMemory)
1106 352 olof
    ReadTxDataFromMemory <= 1'b1;
1107 38 mohor
end
1108
 
1109 354 olof
assign ReadTxDataFromMemory_2 = ReadTxDataFromMemory &
1110
                                ~BlockReadTxDataFromMemory;
1111 221 mohor
 
1112 354 olof
assign tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
1113 221 mohor
 
1114 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1115 38 mohor
begin
1116 40 mohor
  if(Reset)
1117 352 olof
    BlockReadTxDataFromMemory <= 1'b0;
1118 38 mohor
  else
1119 354 olof
  if((TxBufferAlmostFull | TxLength <= 4) & MasterWbTX & (~cyc_cleared) &
1120
     (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
1121 352 olof
    BlockReadTxDataFromMemory <= 1'b1;
1122 219 mohor
  else
1123 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
1124 352 olof
    BlockReadTxDataFromMemory <= 1'b0;
1125 39 mohor
end
1126
 
1127
 
1128
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
1129 159 mohor
 
1130 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
1131 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1132 39 mohor
begin
1133 40 mohor
  if(Reset)
1134 38 mohor
    begin
1135 352 olof
      MasterWbTX <= 1'b0;
1136
      MasterWbRX <= 1'b0;
1137
      m_wb_adr_o <= 30'h0;
1138
      m_wb_cyc_o <= 1'b0;
1139
      m_wb_we_o  <= 1'b0;
1140
      m_wb_sel_o <= 4'h0;
1141
      cyc_cleared<= 1'b0;
1142
      tx_burst_cnt<= 0;
1143
      rx_burst_cnt<= 0;
1144
      IncrTxPointer<= 1'b0;
1145
      tx_burst_en<= 1'b1;
1146
      rx_burst_en<= 1'b0;
1147 354 olof
`ifdef ETH_WISHBONE_B3
1148
      m_wb_cti_o <= 3'b0;
1149
`endif
1150 38 mohor
    end
1151 39 mohor
  else
1152
    begin
1153
      // Switching between two stages depends on enable signals
1154 359 olof
      casez ({MasterWbTX,
1155 354 olof
             MasterWbRX,
1156
             ReadTxDataFromMemory_2,
1157
             WriteRxDataToMemory,
1158
             MasterAccessFinished,
1159
             cyc_cleared,
1160
             tx_burst,
1161
             rx_burst})  // synopsys parallel_case
1162
 
1163
        8'b00_10_00_10, // Idle and MRB needed
1164 359 olof
        8'b10_1?_10_1?, // MRB continues
1165 354 olof
        8'b10_10_01_10, // Clear (previously MR) and MRB needed
1166 359 olof
        8'b01_1?_01_1?: // Clear (previously MW) and MRB needed
1167 39 mohor
          begin
1168 352 olof
            MasterWbTX <= 1'b1;  // tx burst
1169
            MasterWbRX <= 1'b0;
1170
            m_wb_cyc_o <= 1'b1;
1171
            m_wb_we_o  <= 1'b0;
1172
            m_wb_sel_o <= 4'hf;
1173
            cyc_cleared<= 1'b0;
1174
            IncrTxPointer<= 1'b1;
1175
            tx_burst_cnt <= tx_burst_cnt+3'h1;
1176 226 tadejm
            if(tx_burst_cnt==0)
1177 352 olof
              m_wb_adr_o <= TxPointerMSB;
1178 226 tadejm
            else
1179 354 olof
              m_wb_adr_o <= m_wb_adr_o + 1'b1;
1180 226 tadejm
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1181
              begin
1182 352 olof
                tx_burst_en<= 1'b0;
1183 354 olof
`ifdef ETH_WISHBONE_B3
1184 352 olof
                m_wb_cti_o <= 3'b111;
1185 354 olof
`endif
1186 226 tadejm
              end
1187
            else
1188
              begin
1189 354 olof
`ifdef ETH_WISHBONE_B3
1190 352 olof
                m_wb_cti_o <= 3'b010;
1191 354 olof
`endif
1192 226 tadejm
              end
1193
          end
1194 359 olof
        8'b00_?1_00_?1,             // Idle and MWB needed
1195
        8'b01_?1_10_?1,             // MWB continues
1196 226 tadejm
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1197 359 olof
        8'b10_?1_01_?1 :            // Clear (previously MR) and MWB needed
1198 226 tadejm
          begin
1199 352 olof
            MasterWbTX <= 1'b0;  // rx burst
1200
            MasterWbRX <= 1'b1;
1201
            m_wb_cyc_o <= 1'b1;
1202
            m_wb_we_o  <= 1'b1;
1203
            m_wb_sel_o <= RxByteSel;
1204
            IncrTxPointer<= 1'b0;
1205
            cyc_cleared<= 1'b0;
1206
            rx_burst_cnt <= rx_burst_cnt+3'h1;
1207 226 tadejm
 
1208
            if(rx_burst_cnt==0)
1209 352 olof
              m_wb_adr_o <= RxPointerMSB;
1210 226 tadejm
            else
1211 352 olof
              m_wb_adr_o <= m_wb_adr_o+1'b1;
1212 226 tadejm
 
1213
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1214
              begin
1215 352 olof
                rx_burst_en<= 1'b0;
1216 354 olof
 `ifdef ETH_WISHBONE_B3
1217 352 olof
                m_wb_cti_o <= 3'b111;
1218 354 olof
 `endif
1219 226 tadejm
              end
1220
            else
1221
              begin
1222 354 olof
 `ifdef ETH_WISHBONE_B3
1223 352 olof
                m_wb_cti_o <= 3'b010;
1224 354 olof
 `endif
1225 226 tadejm
              end
1226
          end
1227 359 olof
        8'b00_?1_00_?0 :// idle and MW is needed (data write to rx buffer)
1228 226 tadejm
          begin
1229 352 olof
            MasterWbTX <= 1'b0;
1230
            MasterWbRX <= 1'b1;
1231
            m_wb_adr_o <= RxPointerMSB;
1232
            m_wb_cyc_o <= 1'b1;
1233
            m_wb_we_o  <= 1'b1;
1234
            m_wb_sel_o <= RxByteSel;
1235
            IncrTxPointer<= 1'b0;
1236 39 mohor
          end
1237 354 olof
        8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer)
1238 39 mohor
          begin
1239 352 olof
            MasterWbTX <= 1'b1;
1240
            MasterWbRX <= 1'b0;
1241
            m_wb_adr_o <= TxPointerMSB;
1242
            m_wb_cyc_o <= 1'b1;
1243
            m_wb_we_o  <= 1'b0;
1244
            m_wb_sel_o <= 4'hf;
1245
            IncrTxPointer<= 1'b1;
1246 39 mohor
          end
1247 354 olof
        8'b10_10_01_00,// MR and MR is needed (data read from tx buffer)
1248 359 olof
        8'b01_1?_01_0?  :// MW and MR is needed (data read from tx buffer)
1249 39 mohor
          begin
1250 352 olof
            MasterWbTX <= 1'b1;
1251
            MasterWbRX <= 1'b0;
1252
            m_wb_adr_o <= TxPointerMSB;
1253
            m_wb_cyc_o <= 1'b1;
1254
            m_wb_we_o  <= 1'b0;
1255
            m_wb_sel_o <= 4'hf;
1256
            cyc_cleared<= 1'b0;
1257
            IncrTxPointer<= 1'b1;
1258 39 mohor
          end
1259 354 olof
        8'b01_01_01_00,// MW and MW needed (data write to rx buffer)
1260 359 olof
        8'b10_?1_01_?0 :// MR and MW is needed (data write to rx buffer)
1261 39 mohor
          begin
1262 352 olof
            MasterWbTX <= 1'b0;
1263
            MasterWbRX <= 1'b1;
1264
            m_wb_adr_o <= RxPointerMSB;
1265
            m_wb_cyc_o <= 1'b1;
1266
            m_wb_we_o  <= 1'b1;
1267
            m_wb_sel_o <= RxByteSel;
1268
            cyc_cleared<= 1'b0;
1269
            IncrTxPointer<= 1'b0;
1270 39 mohor
          end
1271 354 olof
        8'b01_01_10_00,// MW and MW needed (cycle is cleared between
1272
                      // previous and next access)
1273 359 olof
        8'b01_1?_10_?0,// MW and MW or MR or MRB needed (cycle is
1274 354 olof
                    // cleared between previous and next access)
1275
        8'b10_10_10_00,// MR and MR needed (cycle is cleared between
1276
                       // previous and next access)
1277 359 olof
        8'b10_?1_10_0? :// MR and MR or MW or MWB (cycle is cleared
1278 354 olof
                       // between previous and next access)
1279 39 mohor
          begin
1280 354 olof
            m_wb_cyc_o <= 1'b0;// whatever and master read or write is
1281
                               // needed. We need to clear m_wb_cyc_o
1282
                               // before next access is started
1283 352 olof
            cyc_cleared<= 1'b1;
1284
            IncrTxPointer<= 1'b0;
1285
            tx_burst_cnt<= 0;
1286
            tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1287
            rx_burst_cnt<= 0;
1288
            rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1289 354 olof
`ifdef ETH_WISHBONE_B3
1290 352 olof
              m_wb_cti_o <= 3'b0;
1291 354 olof
`endif
1292 110 mohor
          end
1293 359 olof
        8'b??_00_10_00,// whatever and no master read or write is needed
1294 354 olof
                       // (ack or err comes finishing previous access)
1295 359 olof
        8'b??_00_01_00 : // Between cyc_cleared request was cleared
1296 110 mohor
          begin
1297 352 olof
            MasterWbTX <= 1'b0;
1298
            MasterWbRX <= 1'b0;
1299
            m_wb_cyc_o <= 1'b0;
1300
            cyc_cleared<= 1'b0;
1301
            IncrTxPointer<= 1'b0;
1302
            rx_burst_cnt<= 0;
1303 354 olof
            // Counter is not decremented, yet, so plus1 is used.
1304
            rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 :
1305
                                       enough_data_in_rxfifo_for_burst;
1306
`ifdef ETH_WISHBONE_B3
1307
            m_wb_cti_o <= 3'b0;
1308
`endif
1309 39 mohor
          end
1310 354 olof
        8'b00_00_00_00:  // whatever and no master read or write is needed
1311
                         // (ack or err comes finishing previous access)
1312 127 mohor
          begin
1313 352 olof
            tx_burst_cnt<= 0;
1314
            tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1315 127 mohor
          end
1316 226 tadejm
        default:                    // Don't touch
1317 82 mohor
          begin
1318 352 olof
            MasterWbTX <= MasterWbTX;
1319
            MasterWbRX <= MasterWbRX;
1320
            m_wb_cyc_o <= m_wb_cyc_o;
1321
            m_wb_sel_o <= m_wb_sel_o;
1322
            IncrTxPointer<= IncrTxPointer;
1323 82 mohor
          end
1324 39 mohor
      endcase
1325
    end
1326 38 mohor
end
1327
 
1328 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1329 38 mohor
 
1330 354 olof
eth_fifo
1331
     #(
1332
       .DATA_WIDTH(TX_FIFO_DATA_WIDTH),
1333
       .DEPTH(TX_FIFO_DEPTH),
1334
       .CNT_WIDTH(TX_FIFO_CNT_WIDTH))
1335
tx_fifo (
1336
       .data_in(m_wb_dat_i),
1337
       .data_out(TxData_wb),
1338
       .clk(WB_CLK_I),
1339
       .reset(Reset),
1340
       .write(MasterWbTX & m_wb_ack_i),
1341
       .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1342
       .clear(TxFifoClear),
1343
       .full(TxBufferFull),
1344
       .almost_full(TxBufferAlmostFull),
1345
       .almost_empty(TxBufferAlmostEmpty),
1346
       .empty(TxBufferEmpty),
1347
       .cnt(txfifo_cnt)
1348
       );
1349 39 mohor
 
1350 354 olof
// Start: Generation of the TxStartFrm_wb which is then synchronized to the
1351
// MTxClk
1352 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1353 38 mohor
begin
1354 40 mohor
  if(Reset)
1355 352 olof
    TxStartFrm_wb <= 1'b0;
1356 38 mohor
  else
1357 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1358 352 olof
    TxStartFrm_wb <= 1'b1;
1359 38 mohor
  else
1360 39 mohor
  if(TxStartFrm_syncb2)
1361 352 olof
    TxStartFrm_wb <= 1'b0;
1362 38 mohor
end
1363
 
1364 354 olof
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's
1365
// blocked.
1366 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1367 38 mohor
begin
1368 40 mohor
  if(Reset)
1369 352 olof
    StartOccured <= 1'b0;
1370 38 mohor
  else
1371 39 mohor
  if(TxStartFrm_wb)
1372 352 olof
    StartOccured <= 1'b1;
1373 38 mohor
  else
1374 39 mohor
  if(ResetTxBDReady)
1375 352 olof
    StartOccured <= 1'b0;
1376 38 mohor
end
1377
 
1378 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1379 40 mohor
always @ (posedge MTxClk or posedge Reset)
1380 39 mohor
begin
1381 40 mohor
  if(Reset)
1382 352 olof
    TxStartFrm_sync1 <= 1'b0;
1383 39 mohor
  else
1384 352 olof
    TxStartFrm_sync1 <= TxStartFrm_wb;
1385 39 mohor
end
1386 38 mohor
 
1387 40 mohor
always @ (posedge MTxClk or posedge Reset)
1388 39 mohor
begin
1389 40 mohor
  if(Reset)
1390 352 olof
    TxStartFrm_sync2 <= 1'b0;
1391 39 mohor
  else
1392 352 olof
    TxStartFrm_sync2 <= TxStartFrm_sync1;
1393 39 mohor
end
1394
 
1395 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1396 38 mohor
begin
1397 40 mohor
  if(Reset)
1398 352 olof
    TxStartFrm_syncb1 <= 1'b0;
1399 38 mohor
  else
1400 352 olof
    TxStartFrm_syncb1 <= TxStartFrm_sync2;
1401 38 mohor
end
1402
 
1403 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1404 38 mohor
begin
1405 40 mohor
  if(Reset)
1406 352 olof
    TxStartFrm_syncb2 <= 1'b0;
1407 38 mohor
  else
1408 352 olof
    TxStartFrm_syncb2 <= TxStartFrm_syncb1;
1409 39 mohor
end
1410
 
1411 40 mohor
always @ (posedge MTxClk or posedge Reset)
1412 39 mohor
begin
1413 40 mohor
  if(Reset)
1414 352 olof
    TxStartFrm <= 1'b0;
1415 38 mohor
  else
1416 39 mohor
  if(TxStartFrm_sync2)
1417 352 olof
    TxStartFrm <= 1'b1;
1418 39 mohor
  else
1419 354 olof
  if(TxUsedData_q | ~TxStartFrm_sync2 &
1420
     (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
1421 352 olof
    TxStartFrm <= 1'b0;
1422 38 mohor
end
1423 354 olof
// End: Generation of the TxStartFrm_wb which is then synchronized to the
1424
// MTxClk
1425 38 mohor
 
1426
 
1427 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1428 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1429 38 mohor
begin
1430 40 mohor
  if(Reset)
1431 352 olof
    TxEndFrm_wb <= 1'b0;
1432 38 mohor
  else
1433 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1434 352 olof
    TxEndFrm_wb <= 1'b1;
1435 38 mohor
  else
1436 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1437 352 olof
    TxEndFrm_wb <= 1'b0;
1438 38 mohor
end
1439
 
1440
// Marks which bytes are valid within the word.
1441 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1442 38 mohor
 
1443
 
1444 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1445 38 mohor
begin
1446 40 mohor
  if(Reset)
1447 352 olof
    LatchValidBytes <= 1'b0;
1448 38 mohor
  else
1449 39 mohor
  if(TxLengthLt4 & TxBDReady)
1450 352 olof
    LatchValidBytes <= 1'b1;
1451 38 mohor
  else
1452 352 olof
    LatchValidBytes <= 1'b0;
1453 38 mohor
end
1454
 
1455 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1456 38 mohor
begin
1457 40 mohor
  if(Reset)
1458 352 olof
    LatchValidBytes_q <= 1'b0;
1459 38 mohor
  else
1460 352 olof
    LatchValidBytes_q <= LatchValidBytes;
1461 38 mohor
end
1462
 
1463
 
1464 39 mohor
// Latching valid bytes
1465 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1466 38 mohor
begin
1467 40 mohor
  if(Reset)
1468 352 olof
    TxValidBytesLatched <= 2'h0;
1469 38 mohor
  else
1470 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1471 352 olof
    TxValidBytesLatched <= TxValidBytes;
1472 39 mohor
  else
1473
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1474 352 olof
    TxValidBytesLatched <= 2'h0;
1475 38 mohor
end
1476
 
1477
 
1478
assign TxIRQEn          = TxStatus[14];
1479 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1480
assign PerPacketPad     = TxStatus[12];
1481
assign PerPacketCrcEn   = TxStatus[11];
1482 38 mohor
 
1483
 
1484 77 mohor
assign RxIRQEn         = RxStatus[14];
1485 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1486 38 mohor
 
1487
 
1488 354 olof
// Temporary Tx and Rx buffer descriptor address
1489
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite  & ~WrapTxStatusBit}} &
1490
                              (TxBDAddress + 1'b1); // Tx BD increment or wrap
1491
                                                    // (last BD)
1492 38 mohor
 
1493 354 olof
assign TempRxBDAddress[7:1] =
1494
  {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
1495
  {7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1); // Using next Rx BD
1496
                                                // (increment address)
1497 38 mohor
 
1498
// Latching Tx buffer descriptor address
1499 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1500 38 mohor
begin
1501 40 mohor
  if(Reset)
1502 352 olof
    TxBDAddress <= 7'h0;
1503 321 igorm
  else if (r_TxEn & (~r_TxEn_q))
1504 352 olof
    TxBDAddress <= 7'h0;
1505 321 igorm
  else if (TxStatusWrite)
1506 352 olof
    TxBDAddress <= TempTxBDAddress;
1507 38 mohor
end
1508
 
1509
// Latching Rx buffer descriptor address
1510 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1511 38 mohor
begin
1512 40 mohor
  if(Reset)
1513 352 olof
    RxBDAddress <= 7'h0;
1514 321 igorm
  else if(r_RxEn & (~r_RxEn_q))
1515 352 olof
    RxBDAddress <= r_TxBDNum[6:0];
1516 321 igorm
  else if(RxStatusWrite)
1517 352 olof
    RxBDAddress <= TempRxBDAddress;
1518 38 mohor
end
1519
 
1520 354 olof
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0],
1521
                                RetryLimit, LateCollLatched, DeferLatched,
1522
                                CarrierSenseLost};
1523 38 mohor
 
1524 261 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
1525 60 mohor
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1526 38 mohor
 
1527 60 mohor
 
1528 38 mohor
// Signals used for various purposes
1529 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1530 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1531
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1532
 
1533
 
1534 39 mohor
// Generating delayed signals
1535 40 mohor
always @ (posedge MTxClk or posedge Reset)
1536 38 mohor
begin
1537 40 mohor
  if(Reset)
1538 39 mohor
    begin
1539 352 olof
      TxAbort_q      <= 1'b0;
1540
      TxRetry_q      <= 1'b0;
1541
      TxUsedData_q   <= 1'b0;
1542 39 mohor
    end
1543 38 mohor
  else
1544 39 mohor
    begin
1545 352 olof
      TxAbort_q      <= TxAbort;
1546
      TxRetry_q      <= TxRetry;
1547
      TxUsedData_q   <= TxUsedData;
1548 39 mohor
    end
1549 38 mohor
end
1550
 
1551
// Generating delayed signals
1552 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1553 38 mohor
begin
1554 40 mohor
  if(Reset)
1555 38 mohor
    begin
1556 352 olof
      TxDone_wb_q   <= 1'b0;
1557
      TxAbort_wb_q  <= 1'b0;
1558
      TxRetry_wb_q  <= 1'b0;
1559 38 mohor
    end
1560
  else
1561
    begin
1562 352 olof
      TxDone_wb_q   <= TxDone_wb;
1563
      TxAbort_wb_q  <= TxAbort_wb;
1564
      TxRetry_wb_q  <= TxRetry_wb;
1565 38 mohor
    end
1566
end
1567
 
1568
 
1569 219 mohor
reg TxAbortPacketBlocked;
1570
always @ (posedge WB_CLK_I or posedge Reset)
1571
begin
1572
  if(Reset)
1573 352 olof
    TxAbortPacket <= 1'b0;
1574 219 mohor
  else
1575 354 olof
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
1576
    (~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
1577
    (~TxAbortPacketBlocked))
1578 352 olof
    TxAbortPacket <= 1'b1;
1579 219 mohor
  else
1580 352 olof
    TxAbortPacket <= 1'b0;
1581 219 mohor
end
1582
 
1583
 
1584
always @ (posedge WB_CLK_I or posedge Reset)
1585
begin
1586
  if(Reset)
1587 352 olof
    TxAbortPacket_NotCleared <= 1'b0;
1588 221 mohor
  else
1589 272 tadejm
  if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
1590 352 olof
    TxAbortPacket_NotCleared <= 1'b0;
1591 272 tadejm
  else
1592 354 olof
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
1593
     (~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
1594
     (~TxAbortPacketBlocked))
1595 352 olof
    TxAbortPacket_NotCleared <= 1'b1;
1596 221 mohor
end
1597
 
1598
 
1599
always @ (posedge WB_CLK_I or posedge Reset)
1600
begin
1601
  if(Reset)
1602 352 olof
    TxAbortPacketBlocked <= 1'b0;
1603 219 mohor
  else
1604 280 mohor
  if(!TxAbort_wb & TxAbort_wb_q)
1605 352 olof
    TxAbortPacketBlocked <= 1'b0;
1606 280 mohor
  else
1607 219 mohor
  if(TxAbortPacket)
1608 352 olof
    TxAbortPacketBlocked <= 1'b1;
1609 219 mohor
end
1610
 
1611
 
1612
reg TxRetryPacketBlocked;
1613
always @ (posedge WB_CLK_I or posedge Reset)
1614
begin
1615
  if(Reset)
1616 352 olof
    TxRetryPacket <= 1'b0;
1617 219 mohor
  else
1618 354 olof
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1619
     !TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1620 352 olof
    TxRetryPacket <= 1'b1;
1621 219 mohor
  else
1622 352 olof
    TxRetryPacket <= 1'b0;
1623 219 mohor
end
1624
 
1625
 
1626
always @ (posedge WB_CLK_I or posedge Reset)
1627
begin
1628
  if(Reset)
1629 352 olof
    TxRetryPacket_NotCleared <= 1'b0;
1630 221 mohor
  else
1631 272 tadejm
  if(StartTxBDRead)
1632 352 olof
    TxRetryPacket_NotCleared <= 1'b0;
1633 272 tadejm
  else
1634 354 olof
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1635
     !TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1636 352 olof
    TxRetryPacket_NotCleared <= 1'b1;
1637 221 mohor
end
1638
 
1639
 
1640
always @ (posedge WB_CLK_I or posedge Reset)
1641
begin
1642
  if(Reset)
1643 352 olof
    TxRetryPacketBlocked <= 1'b0;
1644 219 mohor
  else
1645 280 mohor
  if(!TxRetry_wb & TxRetry_wb_q)
1646 352 olof
    TxRetryPacketBlocked <= 1'b0;
1647 280 mohor
  else
1648 219 mohor
  if(TxRetryPacket)
1649 352 olof
    TxRetryPacketBlocked <= 1'b1;
1650 219 mohor
end
1651
 
1652
 
1653 221 mohor
reg TxDonePacketBlocked;
1654
always @ (posedge WB_CLK_I or posedge Reset)
1655
begin
1656
  if(Reset)
1657 352 olof
    TxDonePacket <= 1'b0;
1658 221 mohor
  else
1659 354 olof
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1660
     !TxDonePacketBlocked | TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1661 352 olof
    TxDonePacket <= 1'b1;
1662 221 mohor
  else
1663 352 olof
    TxDonePacket <= 1'b0;
1664 221 mohor
end
1665
 
1666
 
1667
always @ (posedge WB_CLK_I or posedge Reset)
1668
begin
1669
  if(Reset)
1670 352 olof
    TxDonePacket_NotCleared <= 1'b0;
1671 221 mohor
  else
1672 272 tadejm
  if(TxEn & TxEn_q & TxDonePacket_NotCleared)
1673 352 olof
    TxDonePacket_NotCleared <= 1'b0;
1674 272 tadejm
  else
1675 354 olof
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1676
     (~TxDonePacketBlocked) | TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
1677 352 olof
    TxDonePacket_NotCleared <= 1'b1;
1678 221 mohor
end
1679
 
1680
 
1681
always @ (posedge WB_CLK_I or posedge Reset)
1682
begin
1683
  if(Reset)
1684 352 olof
    TxDonePacketBlocked <= 1'b0;
1685 221 mohor
  else
1686 280 mohor
  if(!TxDone_wb & TxDone_wb_q)
1687 352 olof
    TxDonePacketBlocked <= 1'b0;
1688 280 mohor
  else
1689 221 mohor
  if(TxDonePacket)
1690 352 olof
    TxDonePacketBlocked <= 1'b1;
1691 221 mohor
end
1692
 
1693
 
1694 38 mohor
// Indication of the last word
1695 40 mohor
always @ (posedge MTxClk or posedge Reset)
1696 38 mohor
begin
1697 40 mohor
  if(Reset)
1698 352 olof
    LastWord <= 1'b0;
1699 38 mohor
  else
1700
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1701 352 olof
    LastWord <= 1'b0;
1702 38 mohor
  else
1703
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1704 352 olof
    LastWord <= TxEndFrm_wb;
1705 38 mohor
end
1706
 
1707
 
1708
// Tx end frame generation
1709 40 mohor
always @ (posedge MTxClk or posedge Reset)
1710 38 mohor
begin
1711 40 mohor
  if(Reset)
1712 352 olof
    TxEndFrm <= 1'b0;
1713 38 mohor
  else
1714 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1715 352 olof
    TxEndFrm <= 1'b0;
1716 38 mohor
  else
1717
  if(Flop & LastWord)
1718
    begin
1719 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1720 352 olof
        1 : TxEndFrm <= TxByteCnt == 2'h0;
1721
        2 : TxEndFrm <= TxByteCnt == 2'h1;
1722
        3 : TxEndFrm <= TxByteCnt == 2'h2;
1723
 
1724
        default : TxEndFrm <= 1'b0;
1725 38 mohor
      endcase
1726
    end
1727
end
1728
 
1729
 
1730
// Tx data selection (latching)
1731 40 mohor
always @ (posedge MTxClk or posedge Reset)
1732 38 mohor
begin
1733 40 mohor
  if(Reset)
1734 352 olof
    TxData <= 0;
1735 38 mohor
  else
1736 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1737 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1738 354 olof
      2'h0 : TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
1739
      2'h1 : TxData <= TxData_wb[23:16];// Big Endian Byte Ordering
1740
      2'h2 : TxData <= TxData_wb[15:08];// Big Endian Byte Ordering
1741
      2'h3 : TxData <= TxData_wb[07:00];// Big Endian Byte Ordering
1742 96 mohor
    endcase
1743 38 mohor
  else
1744 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1745 354 olof
    TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
1746 96 mohor
  else
1747 38 mohor
  if(TxUsedData & Flop)
1748
    begin
1749 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1750 354 olof
 
1751 352 olof
        1 : TxData <= TxDataLatched[23:16];
1752
        2 : TxData <= TxDataLatched[15:8];
1753
        3 : TxData <= TxDataLatched[7:0];
1754 38 mohor
      endcase
1755
    end
1756
end
1757
 
1758
 
1759
// Latching tx data
1760 40 mohor
always @ (posedge MTxClk or posedge Reset)
1761 38 mohor
begin
1762 40 mohor
  if(Reset)
1763 352 olof
    TxDataLatched[31:0] <= 32'h0;
1764 38 mohor
  else
1765 354 olof
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 |
1766
     TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1767 352 olof
    TxDataLatched[31:0] <= TxData_wb[31:0];
1768 38 mohor
end
1769
 
1770
 
1771
// Tx under run
1772 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1773 38 mohor
begin
1774 40 mohor
  if(Reset)
1775 352 olof
    TxUnderRun_wb <= 1'b0;
1776 38 mohor
  else
1777 39 mohor
  if(TxAbortPulse)
1778 352 olof
    TxUnderRun_wb <= 1'b0;
1779 60 mohor
  else
1780
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1781 352 olof
    TxUnderRun_wb <= 1'b1;
1782 60 mohor
end
1783
 
1784
 
1785 159 mohor
reg TxUnderRun_sync1;
1786
 
1787 60 mohor
// Tx under run
1788
always @ (posedge MTxClk or posedge Reset)
1789
begin
1790
  if(Reset)
1791 352 olof
    TxUnderRun_sync1 <= 1'b0;
1792 43 mohor
  else
1793 60 mohor
  if(TxUnderRun_wb)
1794 352 olof
    TxUnderRun_sync1 <= 1'b1;
1795 60 mohor
  else
1796 159 mohor
  if(BlockingTxStatusWrite_sync2)
1797 352 olof
    TxUnderRun_sync1 <= 1'b0;
1798 159 mohor
end
1799
 
1800
// Tx under run
1801
always @ (posedge MTxClk or posedge Reset)
1802
begin
1803
  if(Reset)
1804 352 olof
    TxUnderRun <= 1'b0;
1805 159 mohor
  else
1806
  if(BlockingTxStatusWrite_sync2)
1807 352 olof
    TxUnderRun <= 1'b0;
1808 159 mohor
  else
1809
  if(TxUnderRun_sync1)
1810 352 olof
    TxUnderRun <= 1'b1;
1811 38 mohor
end
1812
 
1813
 
1814
// Tx Byte counter
1815 40 mohor
always @ (posedge MTxClk or posedge Reset)
1816 38 mohor
begin
1817 40 mohor
  if(Reset)
1818 352 olof
    TxByteCnt <= 2'h0;
1819 38 mohor
  else
1820
  if(TxAbort_q | TxRetry_q)
1821 352 olof
    TxByteCnt <= 2'h0;
1822 38 mohor
  else
1823
  if(TxStartFrm & ~TxUsedData)
1824 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1825 352 olof
      2'h0 : TxByteCnt <= 2'h1;
1826
      2'h1 : TxByteCnt <= 2'h2;
1827
      2'h2 : TxByteCnt <= 2'h3;
1828
      2'h3 : TxByteCnt <= 2'h0;
1829 96 mohor
    endcase
1830 38 mohor
  else
1831
  if(TxUsedData & Flop)
1832 352 olof
    TxByteCnt <= TxByteCnt + 1'b1;
1833 38 mohor
end
1834
 
1835 39 mohor
 
1836 150 mohor
always @ (posedge MTxClk or posedge Reset)
1837
begin
1838
  if(Reset)
1839 352 olof
    ReadTxDataFromFifo_tck <= 1'b0;
1840 150 mohor
  else
1841 354 olof
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 &
1842
     ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1843 352 olof
     ReadTxDataFromFifo_tck <= 1'b1;
1844 150 mohor
  else
1845
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1846 352 olof
    ReadTxDataFromFifo_tck <= 1'b0;
1847 38 mohor
end
1848
 
1849 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1850 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1851 38 mohor
begin
1852 40 mohor
  if(Reset)
1853 352 olof
    ReadTxDataFromFifo_sync1 <= 1'b0;
1854 38 mohor
  else
1855 352 olof
    ReadTxDataFromFifo_sync1 <= ReadTxDataFromFifo_tck;
1856 39 mohor
end
1857 38 mohor
 
1858 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1859 38 mohor
begin
1860 40 mohor
  if(Reset)
1861 352 olof
    ReadTxDataFromFifo_sync2 <= 1'b0;
1862 38 mohor
  else
1863 352 olof
    ReadTxDataFromFifo_sync2 <= ReadTxDataFromFifo_sync1;
1864 38 mohor
end
1865
 
1866 40 mohor
always @ (posedge MTxClk or posedge Reset)
1867 38 mohor
begin
1868 40 mohor
  if(Reset)
1869 352 olof
    ReadTxDataFromFifo_syncb1 <= 1'b0;
1870 38 mohor
  else
1871 352 olof
    ReadTxDataFromFifo_syncb1 <= ReadTxDataFromFifo_sync2;
1872 38 mohor
end
1873
 
1874 40 mohor
always @ (posedge MTxClk or posedge Reset)
1875 38 mohor
begin
1876 40 mohor
  if(Reset)
1877 352 olof
    ReadTxDataFromFifo_syncb2 <= 1'b0;
1878 38 mohor
  else
1879 352 olof
    ReadTxDataFromFifo_syncb2 <= ReadTxDataFromFifo_syncb1;
1880 38 mohor
end
1881
 
1882 150 mohor
always @ (posedge MTxClk or posedge Reset)
1883
begin
1884
  if(Reset)
1885 352 olof
    ReadTxDataFromFifo_syncb3 <= 1'b0;
1886 150 mohor
  else
1887 352 olof
    ReadTxDataFromFifo_syncb3 <= ReadTxDataFromFifo_syncb2;
1888 150 mohor
end
1889
 
1890 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1891 38 mohor
begin
1892 40 mohor
  if(Reset)
1893 352 olof
    ReadTxDataFromFifo_sync3 <= 1'b0;
1894 38 mohor
  else
1895 352 olof
    ReadTxDataFromFifo_sync3 <= ReadTxDataFromFifo_sync2;
1896 38 mohor
end
1897
 
1898 354 olof
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 &
1899
                               ~ReadTxDataFromFifo_sync3;
1900
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization
1901
// to the WB_CLK_I
1902 38 mohor
 
1903
 
1904 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1905 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1906 38 mohor
begin
1907 40 mohor
  if(Reset)
1908 352 olof
    TxRetrySync1 <= 1'b0;
1909 38 mohor
  else
1910 352 olof
    TxRetrySync1 <= TxRetry;
1911 38 mohor
end
1912
 
1913 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1914 38 mohor
begin
1915 40 mohor
  if(Reset)
1916 352 olof
    TxRetry_wb <= 1'b0;
1917 38 mohor
  else
1918 352 olof
    TxRetry_wb <= TxRetrySync1;
1919 38 mohor
end
1920
 
1921
 
1922 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1923 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1924 38 mohor
begin
1925 40 mohor
  if(Reset)
1926 352 olof
    TxDoneSync1 <= 1'b0;
1927 38 mohor
  else
1928 352 olof
    TxDoneSync1 <= TxDone;
1929 38 mohor
end
1930
 
1931 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1932 38 mohor
begin
1933 40 mohor
  if(Reset)
1934 352 olof
    TxDone_wb <= 1'b0;
1935 38 mohor
  else
1936 352 olof
    TxDone_wb <= TxDoneSync1;
1937 38 mohor
end
1938
 
1939 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1940 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1941 38 mohor
begin
1942 40 mohor
  if(Reset)
1943 352 olof
    TxAbortSync1 <= 1'b0;
1944 38 mohor
  else
1945 352 olof
    TxAbortSync1 <= TxAbort;
1946 38 mohor
end
1947
 
1948 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1949 38 mohor
begin
1950 40 mohor
  if(Reset)
1951 352 olof
    TxAbort_wb <= 1'b0;
1952 38 mohor
  else
1953 352 olof
    TxAbort_wb <= TxAbortSync1;
1954 38 mohor
end
1955
 
1956
 
1957 354 olof
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 |
1958
                       r_RxEn & ~r_RxEn_q;
1959 39 mohor
 
1960 40 mohor
// Reading the Rx buffer descriptor
1961
always @ (posedge WB_CLK_I or posedge Reset)
1962
begin
1963
  if(Reset)
1964 352 olof
    RxBDRead <= 1'b0;
1965 40 mohor
  else
1966 166 mohor
  if(StartRxBDRead & ~RxReady)
1967 352 olof
    RxBDRead <= 1'b1;
1968 40 mohor
  else
1969
  if(RxBDReady)
1970 352 olof
    RxBDRead <= 1'b0;
1971 40 mohor
end
1972 39 mohor
 
1973
 
1974 354 olof
// Reading of the next receive buffer descriptor starts after reception status
1975
// is written to the previous one.
1976 38 mohor
 
1977
// Latching READY status of the Rx buffer descriptor
1978 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1979 38 mohor
begin
1980 40 mohor
  if(Reset)
1981 352 olof
    RxBDReady <= 1'b0;
1982 38 mohor
  else
1983 166 mohor
  if(RxPointerRead)
1984 352 olof
    RxBDReady <= 1'b0;
1985 150 mohor
  else
1986 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1987 354 olof
    RxBDReady <= ram_do[15];// RxBDReady is sampled only once at the beginning
1988 38 mohor
end
1989
 
1990 40 mohor
// Latching Rx buffer descriptor status
1991 354 olof
// Data is avaliable one cycle after the access is started (at that time
1992
// signal RxEn is not active)
1993 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1994 38 mohor
begin
1995 40 mohor
  if(Reset)
1996 352 olof
    RxStatus <= 2'h0;
1997 38 mohor
  else
1998 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1999 352 olof
    RxStatus <= ram_do[14:13];
2000 38 mohor
end
2001
 
2002
 
2003 166 mohor
// RxReady generation
2004
always @ (posedge WB_CLK_I or posedge Reset)
2005
begin
2006
  if(Reset)
2007 352 olof
    RxReady <= 1'b0;
2008 354 olof
  else if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)
2009 352 olof
    RxReady <= 1'b0;
2010 354 olof
  else if(RxEn & RxEn_q & RxPointerRead)
2011 352 olof
    RxReady <= 1'b1;
2012 166 mohor
end
2013 38 mohor
 
2014
 
2015 40 mohor
// Reading Rx BD pointer
2016
assign StartRxPointerRead = RxBDRead & RxBDReady;
2017
 
2018
// Reading Tx BD Pointer
2019
always @ (posedge WB_CLK_I or posedge Reset)
2020 38 mohor
begin
2021 40 mohor
  if(Reset)
2022 352 olof
    RxPointerRead <= 1'b0;
2023 38 mohor
  else
2024 40 mohor
  if(StartRxPointerRead)
2025 352 olof
    RxPointerRead <= 1'b1;
2026 38 mohor
  else
2027 166 mohor
  if(RxEn & RxEn_q)
2028 352 olof
    RxPointerRead <= 1'b0;
2029 38 mohor
end
2030
 
2031 113 mohor
 
2032 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
2033
always @ (posedge WB_CLK_I or posedge Reset)
2034
begin
2035
  if(Reset)
2036 352 olof
    RxPointerMSB <= 30'h0;
2037 40 mohor
  else
2038
  if(RxEn & RxEn_q & RxPointerRead)
2039 352 olof
    RxPointerMSB <= ram_do[31:2];
2040 40 mohor
  else
2041 113 mohor
  if(MasterWbRX & m_wb_ack_i)
2042 354 olof
      RxPointerMSB <= RxPointerMSB + 1'b1; // Word access (always word access.
2043
                                           // m_wb_sel_o are used for
2044
                                           // selecting bytes)
2045 40 mohor
end
2046 38 mohor
 
2047
 
2048 354 olof
//Latching last addresses from buffer descriptor (used as byte-half-word
2049
//indicator);
2050 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2051
begin
2052
  if(Reset)
2053 352 olof
    RxPointerLSB_rst[1:0] <= 0;
2054 96 mohor
  else
2055 354 olof
  if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active
2056 352 olof
    RxPointerLSB_rst[1:0] <= 0;
2057 96 mohor
  else
2058
  if(RxEn & RxEn_q & RxPointerRead)
2059 352 olof
    RxPointerLSB_rst[1:0] <= ram_do[1:0];
2060 96 mohor
end
2061
 
2062
 
2063 159 mohor
always @ (RxPointerLSB_rst)
2064 96 mohor
begin
2065 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
2066
    2'h0 : RxByteSel[3:0] = 4'hf;
2067
    2'h1 : RxByteSel[3:0] = 4'h7;
2068
    2'h2 : RxByteSel[3:0] = 4'h3;
2069
    2'h3 : RxByteSel[3:0] = 4'h1;
2070 96 mohor
  endcase
2071
end
2072
 
2073
 
2074
always @ (posedge WB_CLK_I or posedge Reset)
2075
begin
2076
  if(Reset)
2077 352 olof
    RxEn_needed <= 1'b0;
2078 354 olof
  else if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
2079 352 olof
    RxEn_needed <= 1'b1;
2080 354 olof
  else if(RxPointerRead & RxEn & RxEn_q)
2081 352 olof
    RxEn_needed <= 1'b0;
2082 38 mohor
end
2083
 
2084
 
2085 354 olof
// Reception status is written back to the buffer descriptor after the end
2086
// of frame is detected.
2087 40 mohor
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
2088 38 mohor
 
2089
 
2090
// Indicating that last byte is being reveived
2091 40 mohor
always @ (posedge MRxClk or posedge Reset)
2092 38 mohor
begin
2093 40 mohor
  if(Reset)
2094 352 olof
    LastByteIn <= 1'b0;
2095 38 mohor
  else
2096 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
2097 352 olof
    LastByteIn <= 1'b0;
2098 38 mohor
  else
2099 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
2100 352 olof
    LastByteIn <= 1'b1;
2101 38 mohor
end
2102
 
2103 354 olof
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) &
2104
                           RxEnableWindow;
2105 118 mohor
 
2106 38 mohor
// Indicating that data reception will end
2107 40 mohor
always @ (posedge MRxClk or posedge Reset)
2108 38 mohor
begin
2109 40 mohor
  if(Reset)
2110 352 olof
    ShiftWillEnd <= 1'b0;
2111 38 mohor
  else
2112 159 mohor
  if(ShiftEnded_rck | RxAbort)
2113 352 olof
    ShiftWillEnd <= 1'b0;
2114 38 mohor
  else
2115 40 mohor
  if(StartShiftWillEnd)
2116 352 olof
    ShiftWillEnd <= 1'b1;
2117 38 mohor
end
2118
 
2119
 
2120
// Receive byte counter
2121 40 mohor
always @ (posedge MRxClk or posedge Reset)
2122 38 mohor
begin
2123 40 mohor
  if(Reset)
2124 352 olof
    RxByteCnt <= 2'h0;
2125 38 mohor
  else
2126 159 mohor
  if(ShiftEnded_rck | RxAbort)
2127 352 olof
    RxByteCnt <= 2'h0;
2128 97 lampret
  else
2129 166 mohor
  if(RxValid & RxStartFrm & RxReady)
2130 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2131 352 olof
      2'h0 : RxByteCnt <= 2'h1;
2132
      2'h1 : RxByteCnt <= 2'h2;
2133
      2'h2 : RxByteCnt <= 2'h3;
2134
      2'h3 : RxByteCnt <= 2'h0;
2135 96 mohor
    endcase
2136 38 mohor
  else
2137 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
2138 352 olof
    RxByteCnt <= RxByteCnt + 1'b1;
2139 38 mohor
end
2140
 
2141
 
2142
// Indicates how many bytes are valid within the last word
2143 40 mohor
always @ (posedge MRxClk or posedge Reset)
2144 38 mohor
begin
2145 40 mohor
  if(Reset)
2146 352 olof
    RxValidBytes <= 2'h1;
2147 38 mohor
  else
2148 96 mohor
  if(RxValid & RxStartFrm)
2149 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2150 352 olof
      2'h0 : RxValidBytes <= 2'h1;
2151
      2'h1 : RxValidBytes <= 2'h2;
2152
      2'h2 : RxValidBytes <= 2'h3;
2153
      2'h3 : RxValidBytes <= 2'h0;
2154 96 mohor
    endcase
2155 38 mohor
  else
2156 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2157 352 olof
    RxValidBytes <= RxValidBytes + 1'b1;
2158 38 mohor
end
2159
 
2160
 
2161 40 mohor
always @ (posedge MRxClk or posedge Reset)
2162 38 mohor
begin
2163 40 mohor
  if(Reset)
2164 352 olof
    RxDataLatched1       <= 24'h0;
2165 38 mohor
  else
2166 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2167 96 mohor
    if(RxStartFrm)
2168 40 mohor
    begin
2169 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2170 354 olof
        // Big Endian Byte Ordering
2171
        2'h0:        RxDataLatched1[31:24] <= RxData;
2172 352 olof
        2'h1:        RxDataLatched1[23:16] <= RxData;
2173
        2'h2:        RxDataLatched1[15:8]  <= RxData;
2174
        2'h3:        RxDataLatched1        <= RxDataLatched1;
2175 96 mohor
      endcase
2176
    end
2177
    else if (RxEnableWindow)
2178
    begin
2179 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2180 354 olof
        // Big Endian Byte Ordering
2181
        2'h0:        RxDataLatched1[31:24] <= RxData;
2182 352 olof
        2'h1:        RxDataLatched1[23:16] <= RxData;
2183
        2'h2:        RxDataLatched1[15:8]  <= RxData;
2184
        2'h3:        RxDataLatched1        <= RxDataLatched1;
2185 40 mohor
      endcase
2186
    end
2187 38 mohor
end
2188
 
2189 40 mohor
// Assembling data that will be written to the rx_fifo
2190
always @ (posedge MRxClk or posedge Reset)
2191 38 mohor
begin
2192 40 mohor
  if(Reset)
2193 352 olof
    RxDataLatched2 <= 32'h0;
2194 38 mohor
  else
2195 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2196 354 olof
    // Big Endian Byte Ordering
2197
    RxDataLatched2 <= {RxDataLatched1[31:8], RxData};
2198 38 mohor
  else
2199 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2200 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2201 354 olof
      // Big Endian Byte Ordering
2202
 
2203 352 olof
      1 : RxDataLatched2 <= {RxDataLatched1[31:24], 24'h0};
2204
      2 : RxDataLatched2 <= {RxDataLatched1[31:16], 16'h0};
2205
      3 : RxDataLatched2 <= {RxDataLatched1[31:8],   8'h0};
2206 40 mohor
    endcase
2207 38 mohor
end
2208
 
2209
 
2210 40 mohor
// Indicating start of the reception process
2211 354 olof
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm &
2212
                              RxEnableWindow & (&RxByteCnt))
2213
                              |(RxValid & RxReady &  RxStartFrm &
2214
                              (&RxPointerLSB_rst))
2215
                              |(ShiftWillEnd & LastByteIn & (&RxByteCnt));
2216 38 mohor
 
2217 150 mohor
always @ (posedge MRxClk or posedge Reset)
2218
begin
2219
  if(Reset)
2220 352 olof
    WriteRxDataToFifo <= 1'b0;
2221 150 mohor
  else
2222
  if(SetWriteRxDataToFifo & ~RxAbort)
2223 352 olof
    WriteRxDataToFifo <= 1'b1;
2224 150 mohor
  else
2225
  if(WriteRxDataToFifoSync2 | RxAbort)
2226 352 olof
    WriteRxDataToFifo <= 1'b0;
2227 150 mohor
end
2228 40 mohor
 
2229 150 mohor
 
2230
always @ (posedge WB_CLK_I or posedge Reset)
2231
begin
2232
  if(Reset)
2233 352 olof
    WriteRxDataToFifoSync1 <= 1'b0;
2234 150 mohor
  else
2235
  if(WriteRxDataToFifo)
2236 352 olof
    WriteRxDataToFifoSync1 <= 1'b1;
2237 150 mohor
  else
2238 352 olof
    WriteRxDataToFifoSync1 <= 1'b0;
2239 150 mohor
end
2240
 
2241
always @ (posedge WB_CLK_I or posedge Reset)
2242
begin
2243
  if(Reset)
2244 352 olof
    WriteRxDataToFifoSync2 <= 1'b0;
2245 150 mohor
  else
2246 352 olof
    WriteRxDataToFifoSync2 <= WriteRxDataToFifoSync1;
2247 150 mohor
end
2248
 
2249
always @ (posedge WB_CLK_I or posedge Reset)
2250
begin
2251
  if(Reset)
2252 352 olof
    WriteRxDataToFifoSync3 <= 1'b0;
2253 150 mohor
  else
2254 352 olof
    WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2;
2255 150 mohor
end
2256
 
2257
 
2258 354 olof
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 &
2259
                              ~WriteRxDataToFifoSync3;
2260 150 mohor
 
2261 40 mohor
 
2262 90 mohor
always @ (posedge MRxClk or posedge Reset)
2263
begin
2264
  if(Reset)
2265 352 olof
    LatchedRxStartFrm <= 0;
2266 90 mohor
  else
2267 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2268 352 olof
    LatchedRxStartFrm <= 1;
2269 90 mohor
  else
2270 150 mohor
  if(SyncRxStartFrm_q)
2271 352 olof
    LatchedRxStartFrm <= 0;
2272 90 mohor
end
2273
 
2274
 
2275
always @ (posedge WB_CLK_I or posedge Reset)
2276
begin
2277
  if(Reset)
2278 352 olof
    SyncRxStartFrm <= 0;
2279 90 mohor
  else
2280
  if(LatchedRxStartFrm)
2281 352 olof
    SyncRxStartFrm <= 1;
2282 90 mohor
  else
2283 352 olof
    SyncRxStartFrm <= 0;
2284 90 mohor
end
2285
 
2286
 
2287
always @ (posedge WB_CLK_I or posedge Reset)
2288
begin
2289
  if(Reset)
2290 352 olof
    SyncRxStartFrm_q <= 0;
2291 90 mohor
  else
2292 352 olof
    SyncRxStartFrm_q <= SyncRxStartFrm;
2293 90 mohor
end
2294
 
2295 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2296
begin
2297
  if(Reset)
2298 352 olof
    SyncRxStartFrm_q2 <= 0;
2299 150 mohor
  else
2300 352 olof
    SyncRxStartFrm_q2 <= SyncRxStartFrm_q;
2301 150 mohor
end
2302 90 mohor
 
2303
 
2304 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2305 90 mohor
 
2306 354 olof
eth_fifo #(
2307
           .DATA_WIDTH(RX_FIFO_DATA_WIDTH),
2308
           .DEPTH(RX_FIFO_DEPTH),
2309
           .CNT_WIDTH(RX_FIFO_CNT_WIDTH))
2310
rx_fifo (
2311
         .clk            (WB_CLK_I),
2312
         .reset          (Reset),
2313
         // Inputs
2314
         .data_in        (RxDataLatched2),
2315
         .write          (WriteRxDataToFifo_wb & ~RxBufferFull),
2316
         .read           (MasterWbRX & m_wb_ack_i),
2317
         .clear          (RxFifoReset),
2318
         // Outputs
2319
         .data_out       (m_wb_dat_o),
2320
         .full           (RxBufferFull),
2321
         .almost_full    (),
2322
         .almost_empty   (RxBufferAlmostEmpty),
2323
         .empty          (RxBufferEmpty),
2324
         .cnt            (rxfifo_cnt)
2325 88 mohor
        );
2326 40 mohor
 
2327 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2328
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2329 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2330 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2331 40 mohor
 
2332
 
2333
// Generation of the end-of-frame signal
2334
always @ (posedge MRxClk or posedge Reset)
2335 38 mohor
begin
2336 40 mohor
  if(Reset)
2337 352 olof
    ShiftEnded_rck <= 1'b0;
2338 38 mohor
  else
2339 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2340 352 olof
    ShiftEnded_rck <= 1'b1;
2341 38 mohor
  else
2342 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2343 352 olof
    ShiftEnded_rck <= 1'b0;
2344 38 mohor
end
2345
 
2346 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2347
begin
2348
  if(Reset)
2349 352 olof
    ShiftEndedSync1 <= 1'b0;
2350 40 mohor
  else
2351 352 olof
    ShiftEndedSync1 <= ShiftEnded_rck;
2352 40 mohor
end
2353 38 mohor
 
2354 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2355 38 mohor
begin
2356 40 mohor
  if(Reset)
2357 352 olof
    ShiftEndedSync2 <= 1'b0;
2358 38 mohor
  else
2359 352 olof
    ShiftEndedSync2 <= ShiftEndedSync1;
2360 40 mohor
end
2361 38 mohor
 
2362 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2363
begin
2364
  if(Reset)
2365 352 olof
    ShiftEndedSync3 <= 1'b0;
2366 118 mohor
  else
2367
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2368 352 olof
    ShiftEndedSync3 <= 1'b1;
2369 118 mohor
  else
2370
  if(ShiftEnded)
2371 352 olof
    ShiftEndedSync3 <= 1'b0;
2372 118 mohor
end
2373 38 mohor
 
2374 40 mohor
// Generation of the end-of-frame signal
2375
always @ (posedge WB_CLK_I or posedge Reset)
2376 38 mohor
begin
2377 40 mohor
  if(Reset)
2378 352 olof
    ShiftEnded <= 1'b0;
2379 38 mohor
  else
2380 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2381 352 olof
    ShiftEnded <= 1'b1;
2382 38 mohor
  else
2383 40 mohor
  if(RxStatusWrite)
2384 352 olof
    ShiftEnded <= 1'b0;
2385 38 mohor
end
2386
 
2387 118 mohor
always @ (posedge MRxClk or posedge Reset)
2388
begin
2389
  if(Reset)
2390 352 olof
    ShiftEndedSync_c1 <= 1'b0;
2391 118 mohor
  else
2392 352 olof
    ShiftEndedSync_c1 <= ShiftEndedSync2;
2393 118 mohor
end
2394 38 mohor
 
2395 118 mohor
always @ (posedge MRxClk or posedge Reset)
2396
begin
2397
  if(Reset)
2398 352 olof
    ShiftEndedSync_c2 <= 1'b0;
2399 118 mohor
  else
2400 352 olof
    ShiftEndedSync_c2 <= ShiftEndedSync_c1;
2401 118 mohor
end
2402
 
2403 40 mohor
// Generation of the end-of-frame signal
2404
always @ (posedge MRxClk or posedge Reset)
2405 38 mohor
begin
2406 40 mohor
  if(Reset)
2407 352 olof
    RxEnableWindow <= 1'b0;
2408 354 olof
  else if(RxStartFrm)
2409 352 olof
    RxEnableWindow <= 1'b1;
2410 354 olof
  else if(RxEndFrm | RxAbort)
2411 352 olof
    RxEnableWindow <= 1'b0;
2412 38 mohor
end
2413
 
2414
 
2415 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2416 38 mohor
begin
2417 40 mohor
  if(Reset)
2418 352 olof
    RxAbortSync1 <= 1'b0;
2419 38 mohor
  else
2420 352 olof
    RxAbortSync1 <= RxAbortLatched;
2421 40 mohor
end
2422
 
2423
always @ (posedge WB_CLK_I or posedge Reset)
2424
begin
2425
  if(Reset)
2426 352 olof
    RxAbortSync2 <= 1'b0;
2427 38 mohor
  else
2428 352 olof
    RxAbortSync2 <= RxAbortSync1;
2429 38 mohor
end
2430
 
2431 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2432
begin
2433
  if(Reset)
2434 352 olof
    RxAbortSync3 <= 1'b0;
2435 150 mohor
  else
2436 352 olof
    RxAbortSync3 <= RxAbortSync2;
2437 150 mohor
end
2438
 
2439
always @ (posedge WB_CLK_I or posedge Reset)
2440
begin
2441
  if(Reset)
2442 352 olof
    RxAbortSync4 <= 1'b0;
2443 150 mohor
  else
2444 352 olof
    RxAbortSync4 <= RxAbortSync3;
2445 150 mohor
end
2446
 
2447 40 mohor
always @ (posedge MRxClk or posedge Reset)
2448
begin
2449
  if(Reset)
2450 352 olof
    RxAbortSyncb1 <= 1'b0;
2451 40 mohor
  else
2452 352 olof
    RxAbortSyncb1 <= RxAbortSync2;
2453 40 mohor
end
2454 38 mohor
 
2455 40 mohor
always @ (posedge MRxClk or posedge Reset)
2456 38 mohor
begin
2457 40 mohor
  if(Reset)
2458 352 olof
    RxAbortSyncb2 <= 1'b0;
2459 38 mohor
  else
2460 352 olof
    RxAbortSyncb2 <= RxAbortSyncb1;
2461 38 mohor
end
2462
 
2463
 
2464 64 mohor
always @ (posedge MRxClk or posedge Reset)
2465
begin
2466
  if(Reset)
2467 352 olof
    RxAbortLatched <= 1'b0;
2468 64 mohor
  else
2469 150 mohor
  if(RxAbortSyncb2)
2470 352 olof
    RxAbortLatched <= 1'b0;
2471 150 mohor
  else
2472 64 mohor
  if(RxAbort)
2473 352 olof
    RxAbortLatched <= 1'b1;
2474 64 mohor
end
2475 40 mohor
 
2476 64 mohor
 
2477 42 mohor
always @ (posedge MRxClk or posedge Reset)
2478
begin
2479
  if(Reset)
2480 352 olof
    LatchedRxLength[15:0] <= 16'h0;
2481 42 mohor
  else
2482 150 mohor
  if(LoadRxStatus)
2483 352 olof
    LatchedRxLength[15:0] <= RxLength[15:0];
2484 42 mohor
end
2485
 
2486
 
2487 354 olof
assign RxStatusIn = {ReceivedPauseFrm,
2488
                     AddressMiss,
2489
                     RxOverrun,
2490
                     InvalidSymbol,
2491
                     DribbleNibble,
2492
                     ReceivedPacketTooBig,
2493
                     ShortFrame,
2494
                     LatchedCrcError,
2495
                     RxLateCollision};
2496 42 mohor
 
2497
always @ (posedge MRxClk or posedge Reset)
2498
begin
2499
  if(Reset)
2500 352 olof
    RxStatusInLatched <= 'h0;
2501 42 mohor
  else
2502 150 mohor
  if(LoadRxStatus)
2503 352 olof
    RxStatusInLatched <= RxStatusIn;
2504 42 mohor
end
2505
 
2506
 
2507 60 mohor
// Rx overrun
2508
always @ (posedge WB_CLK_I or posedge Reset)
2509
begin
2510
  if(Reset)
2511 352 olof
    RxOverrun <= 1'b0;
2512 354 olof
  else if(RxStatusWrite)
2513 352 olof
    RxOverrun <= 1'b0;
2514 354 olof
  else if(RxBufferFull & WriteRxDataToFifo_wb)
2515 352 olof
    RxOverrun <= 1'b1;
2516 60 mohor
end
2517 48 mohor
 
2518 77 mohor
 
2519
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2520
 
2521
 
2522 239 tadejm
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
2523 250 mohor
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
2524 354 olof
// AddressMiss is identifying that a frame was received because of the
2525
// promiscous mode and is not an error
2526 239 tadejm
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
2527
 
2528 272 tadejm
 
2529 354 olof
// Latching and synchronizing RxStatusWrite signal. This signal is used for
2530
// clearing the ReceivedPauseFrm signal
2531 272 tadejm
always @ (posedge WB_CLK_I or posedge Reset)
2532
begin
2533
  if(Reset)
2534 352 olof
    RxStatusWriteLatched <= 1'b0;
2535 272 tadejm
  else
2536
  if(RxStatusWriteLatched_syncb2)
2537 352 olof
    RxStatusWriteLatched <= 1'b0;
2538 272 tadejm
  else
2539
  if(RxStatusWrite)
2540 352 olof
    RxStatusWriteLatched <= 1'b1;
2541 272 tadejm
end
2542
 
2543
 
2544
always @ (posedge MRxClk or posedge Reset)
2545
begin
2546
  if(Reset)
2547