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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 368

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 38 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 333 igorm
// Revision 1.57  2005/02/21 11:35:33  igorm
45
// Defer indication fixed.
46
//
47 329 igorm
// Revision 1.56  2004/04/30 10:30:00  igorm
48
// Accidently deleted line put back.
49
//
50 323 igorm
// Revision 1.55  2004/04/26 15:26:23  igorm
51
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
52
//   previous update of the core.
53
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
54
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
55
//   register. (thanks to Mathias and Torbjorn)
56
// - Multicast reception was fixed. Thanks to Ulrich Gries
57
//
58 321 igorm
// Revision 1.54  2003/11/12 18:24:59  tadejm
59
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
60
//
61 304 tadejm
// Revision 1.53  2003/10/17 07:46:17  markom
62
// mbist signals updated according to newest convention
63
//
64 302 markom
// Revision 1.52  2003/01/30 14:51:31  mohor
65
// Reset has priority in some flipflops.
66
//
67 280 mohor
// Revision 1.51  2003/01/30 13:36:22  mohor
68
// A new bug (entered with previous update) fixed. When abort occured sometimes
69
// data transmission was blocked.
70
//
71 278 mohor
// Revision 1.50  2003/01/22 13:49:26  tadejm
72
// When control packets were received, they were ignored in some cases.
73
//
74 272 tadejm
// Revision 1.49  2003/01/21 12:09:40  mohor
75
// When receiving normal data frame and RxFlow control was switched on, RXB
76
// interrupt was not set.
77
//
78 270 mohor
// Revision 1.48  2003/01/20 12:05:26  mohor
79
// When in full duplex, transmit was sometimes blocked. Fixed.
80
//
81 269 mohor
// Revision 1.47  2002/11/22 13:26:21  mohor
82
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
83
// anywhere. Removed.
84
//
85 264 mohor
// Revision 1.46  2002/11/22 01:57:06  mohor
86
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
87
// synchronized.
88
//
89 261 mohor
// Revision 1.45  2002/11/19 17:33:34  mohor
90
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
91
// that a frame was received because of the promiscous mode.
92
//
93 250 mohor
// Revision 1.44  2002/11/13 22:21:40  tadejm
94
// RxError is not generated when small frame reception is enabled and small
95
// frames are received.
96
//
97 239 tadejm
// Revision 1.43  2002/10/18 20:53:34  mohor
98
// case changed to casex.
99
//
100 229 mohor
// Revision 1.42  2002/10/18 17:04:20  tadejm
101
// Changed BIST scan signals.
102
//
103 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
104
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
105
//
106 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
107
// TxStatus is written after last access to the TX fifo is finished (in case of abort
108
// or retry). TxDone is fixed.
109
//
110 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
111
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
112
// TxDone and TxRetry are generated after the current WISHBONE access is
113
// finished.
114
//
115 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
116
// BIST added.
117
//
118 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
119
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
120
//
121 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
122
// Reception is possible after RxPointer is read and not after BD is read. For
123
// that reason RxBDReady is changed to RxReady.
124
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
125
// comes, interrupt is generated.
126
//
127 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
128
// Ethernet debug registers removed.
129
//
130 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
131
// Async reset for WB_ACK_O removed (when core was in reset, it was
132
// impossible to access BDs).
133
// RxPointers and TxPointers names changed to be more descriptive.
134
// TxUnderRun synchronized.
135
//
136 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
137
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
138
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
139
// was not used OK.
140
//
141 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
142
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
143
// need to multiply or devide any more.
144
//
145 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
146
// WriteRxDataToMemory signal changed so end of frame (when last word is
147
// written to fifo) is changed.
148
//
149 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
150
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
151
//
152 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
153
// ShiftEnded synchronization changed.
154
//
155 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
156
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
157
//
158 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
159
// RxPointer bug fixed.
160
//
161 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
162
// Previous bug wasn't succesfully removed. Now fixed.
163
//
164 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
165
// Master state machine had a bug when switching from master write to
166
// master read.
167
//
168 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
169
// m_wb_cyc_o signal released after every single transfer.
170
//
171 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
172
// Outputs registered. Reset changed for eth_wishbone module.
173
//
174 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
175
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
176
// bug fixed.
177
//
178 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
179
// Small typo fixed.
180
//
181 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
182
// Any address can be used for Tx and Rx BD pointers. Address does not need
183
// to be aligned.
184
//
185 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
186
// Comments in Slovene language removed.
187
//
188 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
189
// casex changed with case, fifo reset changed.
190
//
191 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
192
// rx_fifo was not always cleared ok. Fixed.
193
//
194 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
195
// Status was not latched correctly sometimes. Fixed.
196
//
197 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
198
// Big Endian problem when sending frames fixed.
199
//
200 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
201
// Byte ordering changed (Big Endian used). casex changed with case because
202
// Xilinx Foundation had problems. Tested in HW. It WORKS.
203
//
204 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
205
// Small fixes for external/internal DMA missmatches.
206
//
207 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
208
// Interrupts changed
209
//
210 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
211
// Status was not written correctly when frames were discarted because of
212
// address mismatch.
213
//
214 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
215
// RxStartFrm cleared when abort or retry comes.
216
//
217 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
218
// Changes that were lost when updating from 1.5 to 1.8 fixed.
219
//
220 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
221
// Addition  of new module eth_addrcheck.v
222
//
223
// Revision 1.7  2002/02/12 17:03:47  mohor
224
// RxOverRun added to statuses.
225
//
226
// Revision 1.6  2002/02/11 09:18:22  mohor
227
// Tx status is written back to the BD.
228
//
229 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
230
// Rx status is written back to the BD.
231
//
232 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
233
// non-DMA host interface added. Select the right configutation in eth_defines.
234
//
235 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
236
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
237
// MHz. Statuses, overrun, control frame transmission and reception still  need
238
// to be fixed.
239
//
240 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
241
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
242
// added.
243
//
244 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
245
// Initial version. Equals to eth_wishbonedma.v at this moment.
246 38 mohor
//
247
//
248
//
249
 
250 356 olof
`include "ethmac_defines.v"
251 38 mohor
`include "timescale.v"
252
 
253
 
254
module eth_wishbone
255 354 olof
  (
256 38 mohor
 
257 354 olof
   // WISHBONE common
258
   WB_CLK_I, WB_DAT_I, WB_DAT_O,
259 38 mohor
 
260 354 olof
   // WISHBONE slave
261
   WB_ADR_I, WB_WE_I, WB_ACK_O,
262
   BDCs,
263 38 mohor
 
264 354 olof
   Reset,
265 40 mohor
 
266 354 olof
   // WISHBONE master
267
   m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
268
   m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
269
   m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
270 39 mohor
 
271 354 olof
   m_wb_cti_o, m_wb_bte_o,
272 219 mohor
 
273 354 olof
   //TX
274
   MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
275
   TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
276
   PerPacketPad,
277 38 mohor
 
278 354 olof
   //RX
279
   MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
280
   RxStatusWriteLatched_sync2,
281
 
282
   // Register
283
   r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
284 38 mohor
 
285 354 olof
   // Interrupts
286
   TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
287
 
288
   // Rx Status
289
   InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
290
   ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
291
   AddressMiss,
292
   ReceivedPauseFrm,
293
 
294
   // Tx Status
295
   RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched,
296
   CarrierSenseLost
297 164 mohor
 
298 354 olof
   // Bist
299 210 mohor
`ifdef ETH_BIST
300 354 olof
   ,
301
   // debug chain signals
302
   mbist_si_i,       // bist scan serial in
303
   mbist_so_o,       // bist scan serial out
304
   mbist_ctrl_i        // bist chain shift control
305 210 mohor
`endif
306
 
307 360 olof
`ifdef WISHBONE_DEBUG
308
   ,
309
   dbg_dat0
310
`endif
311 210 mohor
 
312 38 mohor
 
313 354 olof
   );
314 38 mohor
 
315 349 olof
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
316
parameter TX_FIFO_DEPTH      = `ETH_TX_FIFO_DEPTH;
317
parameter TX_FIFO_CNT_WIDTH  = `ETH_TX_FIFO_CNT_WIDTH;
318
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
319
parameter RX_FIFO_DEPTH      = `ETH_RX_FIFO_DEPTH;
320
parameter RX_FIFO_CNT_WIDTH  = `ETH_RX_FIFO_CNT_WIDTH;
321 38 mohor
 
322
// WISHBONE common
323
input           WB_CLK_I;       // WISHBONE clock
324
input  [31:0]   WB_DAT_I;       // WISHBONE data input
325
output [31:0]   WB_DAT_O;       // WISHBONE data output
326
 
327
// WISHBONE slave
328
input   [9:2]   WB_ADR_I;       // WISHBONE address input
329
input           WB_WE_I;        // WISHBONE write enable input
330 304 tadejm
input   [3:0]   BDCs;           // Buffer descriptors are selected
331 38 mohor
output          WB_ACK_O;       // WISHBONE acknowledge output
332
 
333 39 mohor
// WISHBONE master
334 329 igorm
output  [29:0]  m_wb_adr_o;     // 
335 39 mohor
output   [3:0]  m_wb_sel_o;     // 
336
output          m_wb_we_o;      // 
337
output  [31:0]  m_wb_dat_o;     // 
338
output          m_wb_cyc_o;     // 
339
output          m_wb_stb_o;     // 
340
input   [31:0]  m_wb_dat_i;     // 
341
input           m_wb_ack_i;     // 
342
input           m_wb_err_i;     // 
343
 
344 219 mohor
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
345
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
346
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
347
 
348 40 mohor
input           Reset;       // Reset signal
349 39 mohor
 
350 60 mohor
// Rx Status signals
351 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
352
input           LatchedCrcError;  // CRC error
353
input           RxLateCollision;  // Late collision occured while receiving frame
354 354 olof
input           ShortFrame;       // Frame shorter then the minimum size
355
                                  // (r_MinFL) was received while small
356
                                  // packets are enabled (r_RecSmall)
357 42 mohor
input           DribbleNibble;    // Extra nibble received
358
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
359
input    [15:0] RxLength;         // Length of the incoming frame
360
input           LoadRxStatus;     // Rx status was loaded
361 354 olof
input           ReceivedPacketGood;  // Received packet's length and CRC are
362
                                     // good
363
input           AddressMiss;      // When a packet is received AddressMiss
364
                                  // status is written to the Rx BD
365 261 mohor
input           r_RxFlow;
366 270 mohor
input           r_PassAll;
367 261 mohor
input           ReceivedPauseFrm;
368 39 mohor
 
369 60 mohor
// Tx Status signals
370
input     [3:0] RetryCntLatched;  // Latched Retry Counter
371 354 olof
input           RetryLimit;       // Retry limit reached (Retry Max value +1
372
                                  // attempts were made)
373 60 mohor
input           LateCollLatched;  // Late collision occured
374 354 olof
input           DeferLatched;     // Defer indication (Frame was defered
375
                                  // before sucessfully sent)
376 329 igorm
output          RstDeferLatched;
377 354 olof
input           CarrierSenseLost; // Carrier Sense was lost during the
378
                                  // frame transmission
379 60 mohor
 
380 38 mohor
// Tx
381
input           MTxClk;         // Transmit clock (from PHY)
382
input           TxUsedData;     // Transmit packet used data
383
input           TxRetry;        // Transmit packet retry
384
input           TxAbort;        // Transmit packet abort
385
input           TxDone;         // Transmission ended
386
output          TxStartFrm;     // Transmit packet start frame
387
output          TxEndFrm;       // Transmit packet end frame
388
output  [7:0]   TxData;         // Transmit packet data byte
389
output          TxUnderRun;     // Transmit packet under-run
390
output          PerPacketCrcEn; // Per packet crc enable
391
output          PerPacketPad;   // Per packet pading
392
 
393
// Rx
394
input           MRxClk;         // Receive clock (from PHY)
395
input   [7:0]   RxData;         // Received data byte (from PHY)
396
input           RxValid;        // 
397
input           RxStartFrm;     // 
398
input           RxEndFrm;       // 
399 354 olof
input           RxAbort;        // This signal is set when address doesn't
400
                                // match.
401 272 tadejm
output          RxStatusWriteLatched_sync2;
402 38 mohor
 
403
//Register
404
input           r_TxEn;         // Transmit enable
405
input           r_RxEn;         // Receive enable
406
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
407
 
408
// Interrupts
409
output TxB_IRQ;
410
output TxE_IRQ;
411
output RxB_IRQ;
412 77 mohor
output RxE_IRQ;
413 38 mohor
output Busy_IRQ;
414
 
415 77 mohor
 
416 210 mohor
// Bist
417
`ifdef ETH_BIST
418 302 markom
input   mbist_si_i;       // bist scan serial in
419
output  mbist_so_o;       // bist scan serial out
420 354 olof
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
421 210 mohor
`endif
422
 
423 360 olof
`ifdef WISHBONE_DEBUG
424 367 olof
   output [31:0]                       dbg_dat0;
425 360 olof
`endif
426
 
427
 
428 77 mohor
reg TxB_IRQ;
429
reg TxE_IRQ;
430
reg RxB_IRQ;
431
reg RxE_IRQ;
432
 
433 38 mohor
reg             TxStartFrm;
434
reg             TxEndFrm;
435
reg     [7:0]   TxData;
436
 
437
reg             TxUnderRun;
438 60 mohor
reg             TxUnderRun_wb;
439 38 mohor
 
440
reg             TxBDRead;
441 39 mohor
wire            TxStatusWrite;
442 38 mohor
 
443
reg     [1:0]   TxValidBytesLatched;
444
 
445
reg    [15:0]   TxLength;
446 60 mohor
reg    [15:0]   LatchedTxLength;
447
reg   [14:11]   TxStatus;
448 38 mohor
 
449 60 mohor
reg   [14:13]   RxStatus;
450 38 mohor
 
451
reg             TxStartFrm_wb;
452
reg             TxRetry_wb;
453 39 mohor
reg             TxAbort_wb;
454 38 mohor
reg             TxDone_wb;
455
 
456
reg             TxDone_wb_q;
457
reg             TxAbort_wb_q;
458 39 mohor
reg             TxRetry_wb_q;
459 219 mohor
reg             TxRetryPacket;
460 221 mohor
reg             TxRetryPacket_NotCleared;
461
reg             TxDonePacket;
462
reg             TxDonePacket_NotCleared;
463 219 mohor
reg             TxAbortPacket;
464 221 mohor
reg             TxAbortPacket_NotCleared;
465 38 mohor
reg             RxBDReady;
466 166 mohor
reg             RxReady;
467 38 mohor
reg             TxBDReady;
468
 
469
reg             RxBDRead;
470
 
471
reg    [31:0]   TxDataLatched;
472
reg     [1:0]   TxByteCnt;
473
reg             LastWord;
474 39 mohor
reg             ReadTxDataFromFifo_tck;
475 38 mohor
 
476
reg             BlockingTxStatusWrite;
477
reg             BlockingTxBDRead;
478
 
479 40 mohor
reg             Flop;
480 38 mohor
 
481 329 igorm
reg     [7:1]   TxBDAddress;
482
reg     [7:1]   RxBDAddress;
483 38 mohor
 
484
reg             TxRetrySync1;
485
reg             TxAbortSync1;
486 39 mohor
reg             TxDoneSync1;
487 38 mohor
 
488
reg             TxAbort_q;
489
reg             TxRetry_q;
490
reg             TxUsedData_q;
491
 
492
reg    [31:0]   RxDataLatched2;
493 82 mohor
 
494
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
495
 
496 38 mohor
reg     [1:0]   RxValidBytes;
497
reg     [1:0]   RxByteCnt;
498
reg             LastByteIn;
499
reg             ShiftWillEnd;
500
 
501 40 mohor
reg             WriteRxDataToFifo;
502 42 mohor
reg    [15:0]   LatchedRxLength;
503 64 mohor
reg             RxAbortLatched;
504 38 mohor
 
505 40 mohor
reg             ShiftEnded;
506 60 mohor
reg             RxOverrun;
507 38 mohor
 
508 304 tadejm
reg     [3:0]   BDWrite;                    // BD Write Enable for access from WISHBONE side
509 40 mohor
reg             BDRead;                     // BD Read access from WISHBONE side
510 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
511
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
512 38 mohor
 
513 39 mohor
reg             TxEndFrm_wb;
514 38 mohor
 
515 39 mohor
wire            TxRetryPulse;
516 38 mohor
wire            TxDonePulse;
517
wire            TxAbortPulse;
518
 
519
wire            StartRxBDRead;
520
 
521
wire            StartTxBDRead;
522
 
523
wire            TxIRQEn;
524
wire            WrapTxStatusBit;
525
 
526 77 mohor
wire            RxIRQEn;
527 38 mohor
wire            WrapRxStatusBit;
528
 
529
wire    [1:0]   TxValidBytes;
530
 
531 329 igorm
wire    [7:1]   TempTxBDAddress;
532
wire    [7:1]   TempRxBDAddress;
533 38 mohor
 
534 272 tadejm
wire            RxStatusWrite;
535 329 igorm
wire            RxBufferFull;
536
wire            RxBufferAlmostEmpty;
537
wire            RxBufferEmpty;
538 272 tadejm
 
539 106 mohor
reg             WB_ACK_O;
540 38 mohor
 
541 261 mohor
wire    [8:0]   RxStatusIn;
542
reg     [8:0]   RxStatusInLatched;
543 42 mohor
 
544 39 mohor
reg WbEn, WbEn_q;
545
reg RxEn, RxEn_q;
546
reg TxEn, TxEn_q;
547 321 igorm
reg r_TxEn_q;
548
reg r_RxEn_q;
549 38 mohor
 
550 39 mohor
wire ram_ce;
551 304 tadejm
wire [3:0]  ram_we;
552 39 mohor
wire ram_oe;
553
reg [7:0]   ram_addr;
554
reg [31:0]  ram_di;
555
wire [31:0] ram_do;
556 38 mohor
 
557 39 mohor
wire StartTxPointerRead;
558 354 olof
reg TxPointerRead;
559 39 mohor
reg TxEn_needed;
560 40 mohor
reg RxEn_needed;
561 38 mohor
 
562 40 mohor
wire StartRxPointerRead;
563 355 olof
reg RxPointerRead;
564 38 mohor
 
565 354 olof
// RX shift ending signals
566
reg ShiftEnded_rck;
567
reg ShiftEndedSync1;
568
reg ShiftEndedSync2;
569
reg ShiftEndedSync3;
570
reg ShiftEndedSync_c1;
571
reg ShiftEndedSync_c2;
572
 
573
wire StartShiftWillEnd;
574
 
575
reg StartOccured;
576
reg TxStartFrm_sync1;
577
reg TxStartFrm_sync2;
578
reg TxStartFrm_syncb1;
579
reg TxStartFrm_syncb2;
580
 
581
wire TxFifoClear;
582
wire TxBufferAlmostFull;
583
wire TxBufferFull;
584
wire TxBufferEmpty;
585
wire TxBufferAlmostEmpty;
586
wire SetReadTxDataFromMemory;
587
reg BlockReadTxDataFromMemory;
588
 
589
reg tx_burst_en;
590
reg rx_burst_en;
591
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
592
 
593
wire ReadTxDataFromMemory_2;
594
wire tx_burst;
595
 
596
wire [31:0] TxData_wb;
597
wire ReadTxDataFromFifo_wb;
598
 
599
wire [TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
600
wire [RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
601
 
602
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
603
 
604
wire rx_burst;
605
wire enough_data_in_rxfifo_for_burst;
606
wire enough_data_in_rxfifo_for_burst_plus1;
607
 
608
reg ReadTxDataFromMemory;
609
wire WriteRxDataToMemory;
610
 
611
reg MasterWbTX;
612
reg MasterWbRX;
613
 
614
reg [29:0] m_wb_adr_o;
615
reg        m_wb_cyc_o;
616
reg  [3:0] m_wb_sel_o;
617
reg        m_wb_we_o;
618
 
619
wire TxLengthEq0;
620
wire TxLengthLt4;
621
 
622
reg BlockingIncrementTxPointer;
623
reg [31:2] TxPointerMSB;
624
reg [1:0]  TxPointerLSB;
625
reg [1:0]  TxPointerLSB_rst;
626
reg [31:2] RxPointerMSB;
627
reg [1:0]  RxPointerLSB_rst;
628
 
629
wire RxBurstAcc;
630
wire RxWordAcc;
631
wire RxHalfAcc;
632
wire RxByteAcc;
633
 
634
wire ResetTxBDReady;
635
reg BlockingTxStatusWrite_sync1;
636
reg BlockingTxStatusWrite_sync2;
637
reg BlockingTxStatusWrite_sync3;
638
 
639
reg cyc_cleared;
640
reg IncrTxPointer;
641
 
642
reg  [3:0] RxByteSel;
643
wire MasterAccessFinished;
644
 
645
reg LatchValidBytes;
646
reg LatchValidBytes_q;
647
 
648
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
649
reg ReadTxDataFromFifo_sync1;
650
reg ReadTxDataFromFifo_sync2;
651
reg ReadTxDataFromFifo_sync3;
652
reg ReadTxDataFromFifo_syncb1;
653
reg ReadTxDataFromFifo_syncb2;
654
reg ReadTxDataFromFifo_syncb3;
655
 
656
reg RxAbortSync1;
657
reg RxAbortSync2;
658
reg RxAbortSync3;
659
reg RxAbortSync4;
660
reg RxAbortSyncb1;
661
reg RxAbortSyncb2;
662
 
663
reg RxEnableWindow;
664
 
665
wire SetWriteRxDataToFifo;
666
 
667
reg WriteRxDataToFifoSync1;
668
reg WriteRxDataToFifoSync2;
669
reg WriteRxDataToFifoSync3;
670
 
671
wire WriteRxDataToFifo_wb;
672
 
673
reg LatchedRxStartFrm;
674
reg SyncRxStartFrm;
675
reg SyncRxStartFrm_q;
676
reg SyncRxStartFrm_q2;
677
wire RxFifoReset;
678
 
679
wire TxError;
680
wire RxError;
681
 
682
reg RxStatusWriteLatched;
683
reg RxStatusWriteLatched_sync1;
684
reg RxStatusWriteLatched_sync2;
685
reg RxStatusWriteLatched_syncb1;
686
reg RxStatusWriteLatched_syncb2;
687
 
688 219 mohor
assign m_wb_bte_o = 2'b00;    // Linear burst
689 39 mohor
 
690 329 igorm
assign m_wb_stb_o = m_wb_cyc_o;
691 219 mohor
 
692 159 mohor
always @ (posedge WB_CLK_I)
693 40 mohor
begin
694 352 olof
  WB_ACK_O <= (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
695 40 mohor
end
696 39 mohor
 
697 106 mohor
assign WB_DAT_O = ram_do;
698 39 mohor
 
699 41 mohor
// Generic synchronous single-port RAM interface
700 354 olof
eth_spram_256x32
701
     bd_ram
702
     (
703
      .clk     (WB_CLK_I),
704
      .rst     (Reset),
705
      .ce      (ram_ce),
706
      .we      (ram_we),
707
      .oe      (ram_oe),
708
      .addr    (ram_addr),
709
      .di      (ram_di),
710 358 olof
      .dato    (ram_do)
711 210 mohor
`ifdef ETH_BIST
712 354 olof
      ,
713
      .mbist_si_i       (mbist_si_i),
714
      .mbist_so_o       (mbist_so_o),
715
      .mbist_ctrl_i       (mbist_ctrl_i)
716 210 mohor
`endif
717 354 olof
      );
718 41 mohor
 
719 39 mohor
assign ram_ce = 1'b1;
720 354 olof
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) |
721
                {4{(TxStatusWrite | RxStatusWrite)}};
722
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q &
723
                (TxBDRead | TxPointerRead) | RxEn & RxEn_q &
724
                (RxBDRead | RxPointerRead);
725 39 mohor
 
726
 
727 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
728 38 mohor
begin
729 40 mohor
  if(Reset)
730 352 olof
    TxEn_needed <= 1'b0;
731 38 mohor
  else
732 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
733 352 olof
    TxEn_needed <= 1'b1;
734 39 mohor
  else
735
  if(TxPointerRead & TxEn & TxEn_q)
736 352 olof
    TxEn_needed <= 1'b0;
737 38 mohor
end
738
 
739 39 mohor
// Enabling access to the RAM for three devices.
740 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
741 39 mohor
begin
742 40 mohor
  if(Reset)
743 39 mohor
    begin
744 352 olof
      WbEn <= 1'b1;
745
      RxEn <= 1'b0;
746
      TxEn <= 1'b0;
747
      ram_addr <= 8'h0;
748
      ram_di <= 32'h0;
749
      BDRead <= 1'b0;
750 359 olof
      BDWrite <= 0;
751 39 mohor
    end
752
  else
753
    begin
754
      // Switching between three stages depends on enable signals
755 355 olof
     /* verilator lint_off CASEINCOMPLETE */ // JB
756 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
757
        5'b100_10, 5'b100_11 :
758 39 mohor
          begin
759 352 olof
            WbEn <= 1'b0;
760
            RxEn <= 1'b1;  // wb access stage and r_RxEn is enabled
761
            TxEn <= 1'b0;
762
            ram_addr <= {RxBDAddress, RxPointerRead};
763
            ram_di <= RxBDDataIn;
764 39 mohor
          end
765
        5'b100_01 :
766
          begin
767 352 olof
            WbEn <= 1'b0;
768
            RxEn <= 1'b0;
769 354 olof
            TxEn <= 1'b1;  // wb access stage, r_RxEn is disabled but
770
                           // r_TxEn is enabled
771 352 olof
            ram_addr <= {TxBDAddress, TxPointerRead};
772
            ram_di <= TxBDDataIn;
773 39 mohor
          end
774 90 mohor
        5'b010_00, 5'b010_10 :
775 39 mohor
          begin
776 352 olof
            WbEn <= 1'b1;  // RxEn access stage and r_TxEn is disabled
777
            RxEn <= 1'b0;
778
            TxEn <= 1'b0;
779
            ram_addr <= WB_ADR_I[9:2];
780
            ram_di <= WB_DAT_I;
781
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
782
            BDRead <= (|BDCs) & ~WB_WE_I;
783 39 mohor
          end
784 90 mohor
        5'b010_01, 5'b010_11 :
785 39 mohor
          begin
786 352 olof
            WbEn <= 1'b0;
787
            RxEn <= 1'b0;
788
            TxEn <= 1'b1;  // RxEn access stage and r_TxEn is enabled
789
            ram_addr <= {TxBDAddress, TxPointerRead};
790
            ram_di <= TxBDDataIn;
791 39 mohor
          end
792 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
793 39 mohor
          begin
794 354 olof
            WbEn <= 1'b1;  // TxEn access stage (we always go to wb
795
                           // access stage)
796 352 olof
            RxEn <= 1'b0;
797
            TxEn <= 1'b0;
798
            ram_addr <= WB_ADR_I[9:2];
799
            ram_di <= WB_DAT_I;
800
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
801
            BDRead <= (|BDCs) & ~WB_WE_I;
802 39 mohor
          end
803
        5'b100_00 :
804
          begin
805 354 olof
            WbEn <= 1'b0;  // WbEn access stage and there is no need
806
                           // for other stages. WbEn needs to be
807
                           // switched off for a bit
808 39 mohor
          end
809
        5'b000_00 :
810
          begin
811 352 olof
            WbEn <= 1'b1;  // Idle state. We go to WbEn access stage.
812
            RxEn <= 1'b0;
813
            TxEn <= 1'b0;
814
            ram_addr <= WB_ADR_I[9:2];
815
            ram_di <= WB_DAT_I;
816
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
817
            BDRead <= (|BDCs) & ~WB_WE_I;
818 39 mohor
          end
819
      endcase
820 355 olof
      /* verilator lint_on CASEINCOMPLETE */
821 39 mohor
    end
822
end
823
 
824
 
825
// Delayed stage signals
826 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
827 39 mohor
begin
828 40 mohor
  if(Reset)
829 39 mohor
    begin
830 352 olof
      WbEn_q <= 1'b0;
831
      RxEn_q <= 1'b0;
832
      TxEn_q <= 1'b0;
833
      r_TxEn_q <= 1'b0;
834
      r_RxEn_q <= 1'b0;
835 39 mohor
    end
836
  else
837
    begin
838 352 olof
      WbEn_q <= WbEn;
839
      RxEn_q <= RxEn;
840
      TxEn_q <= TxEn;
841
      r_TxEn_q <= r_TxEn;
842
      r_RxEn_q <= r_RxEn;
843 39 mohor
    end
844
end
845
 
846 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
847 40 mohor
always @ (posedge MTxClk or posedge Reset)
848 38 mohor
begin
849 40 mohor
  if(Reset)
850 352 olof
    Flop <= 1'b0;
851 38 mohor
  else
852
  if(TxDone | TxAbort | TxRetry_q)
853 352 olof
    Flop <= 1'b0;
854 38 mohor
  else
855
  if(TxUsedData)
856 352 olof
    Flop <= ~Flop;
857 38 mohor
end
858
 
859 39 mohor
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
860 38 mohor
 
861
// Latching READY status of the Tx buffer descriptor
862 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
863 38 mohor
begin
864 40 mohor
  if(Reset)
865 352 olof
    TxBDReady <= 1'b0;
866 38 mohor
  else
867 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
868 354 olof
    // TxBDReady is sampled only once at the beginning.
869
    TxBDReady <= ram_do[15] & (ram_do[31:16] > 4);
870
  else
871
  // Only packets larger then 4 bytes are transmitted.
872 39 mohor
  if(ResetTxBDReady)
873 352 olof
    TxBDReady <= 1'b0;
874 38 mohor
end
875
 
876 39 mohor
// Reading the Tx buffer descriptor
877 354 olof
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) &
878
                       ~BlockingTxBDRead & ~TxBDReady;
879 39 mohor
 
880 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
881 38 mohor
begin
882 40 mohor
  if(Reset)
883 352 olof
    TxBDRead <= 1'b1;
884 38 mohor
  else
885 110 mohor
  if(StartTxBDRead)
886 352 olof
    TxBDRead <= 1'b1;
887 38 mohor
  else
888 39 mohor
  if(TxBDReady)
889 352 olof
    TxBDRead <= 1'b0;
890 38 mohor
end
891
 
892 39 mohor
// Reading Tx BD pointer
893
assign StartTxPointerRead = TxBDRead & TxBDReady;
894 38 mohor
 
895 39 mohor
// Reading Tx BD Pointer
896 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
897 38 mohor
begin
898 40 mohor
  if(Reset)
899 352 olof
    TxPointerRead <= 1'b0;
900 38 mohor
  else
901 39 mohor
  if(StartTxPointerRead)
902 352 olof
    TxPointerRead <= 1'b1;
903 38 mohor
  else
904 39 mohor
  if(TxEn_q)
905 352 olof
    TxPointerRead <= 1'b0;
906 38 mohor
end
907
 
908
 
909 39 mohor
// Writing status back to the Tx buffer descriptor
910 354 olof
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) &
911
                       TxEn & TxEn_q & ~BlockingTxStatusWrite;
912 38 mohor
 
913
 
914 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
915 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
916 38 mohor
begin
917 40 mohor
  if(Reset)
918 352 olof
    BlockingTxStatusWrite <= 1'b0;
919 38 mohor
  else
920 272 tadejm
  if(~TxDone_wb & ~TxAbort_wb)
921 352 olof
    BlockingTxStatusWrite <= 1'b0;
922 272 tadejm
  else
923 39 mohor
  if(TxStatusWrite)
924 352 olof
    BlockingTxStatusWrite <= 1'b1;
925 38 mohor
end
926
 
927
 
928 159 mohor
// Synchronizing BlockingTxStatusWrite to MTxClk
929
always @ (posedge MTxClk or posedge Reset)
930
begin
931
  if(Reset)
932 352 olof
    BlockingTxStatusWrite_sync1 <= 1'b0;
933 159 mohor
  else
934 352 olof
    BlockingTxStatusWrite_sync1 <= BlockingTxStatusWrite;
935 159 mohor
end
936
 
937
// Synchronizing BlockingTxStatusWrite to MTxClk
938
always @ (posedge MTxClk or posedge Reset)
939
begin
940
  if(Reset)
941 352 olof
    BlockingTxStatusWrite_sync2 <= 1'b0;
942 159 mohor
  else
943 352 olof
    BlockingTxStatusWrite_sync2 <= BlockingTxStatusWrite_sync1;
944 159 mohor
end
945
 
946 329 igorm
// Synchronizing BlockingTxStatusWrite to MTxClk
947
always @ (posedge MTxClk or posedge Reset)
948
begin
949
  if(Reset)
950 352 olof
    BlockingTxStatusWrite_sync3 <= 1'b0;
951 329 igorm
  else
952 352 olof
    BlockingTxStatusWrite_sync3 <= BlockingTxStatusWrite_sync2;
953 329 igorm
end
954 159 mohor
 
955 354 olof
assign RstDeferLatched = BlockingTxStatusWrite_sync2 &
956
                         ~BlockingTxStatusWrite_sync3;
957 329 igorm
 
958 39 mohor
// TxBDRead state is activated only once. 
959 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
960 39 mohor
begin
961 40 mohor
  if(Reset)
962 352 olof
    BlockingTxBDRead <= 1'b0;
963 39 mohor
  else
964 110 mohor
  if(StartTxBDRead)
965 352 olof
    BlockingTxBDRead <= 1'b1;
966 39 mohor
  else
967 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
968 352 olof
    BlockingTxBDRead <= 1'b0;
969 39 mohor
end
970 38 mohor
 
971
 
972 39 mohor
// Latching status from the tx buffer descriptor
973 354 olof
// Data is avaliable one cycle after the access is started (at that time
974
// signal TxEn is not active)
975 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
976 38 mohor
begin
977 40 mohor
  if(Reset)
978 352 olof
    TxStatus <= 4'h0;
979 38 mohor
  else
980 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
981 352 olof
    TxStatus <= ram_do[14:11];
982 38 mohor
end
983
 
984
 
985 39 mohor
 
986
//Latching length from the buffer descriptor;
987 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
988 38 mohor
begin
989 40 mohor
  if(Reset)
990 352 olof
    TxLength <= 16'h0;
991 38 mohor
  else
992 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
993 352 olof
    TxLength <= ram_do[31:16];
994 38 mohor
  else
995 39 mohor
  if(MasterWbTX & m_wb_ack_i)
996
    begin
997
      if(TxLengthLt4)
998 352 olof
        TxLength <= 16'h0;
999 354 olof
      else if(TxPointerLSB_rst==2'h0)
1000 359 olof
        TxLength <= TxLength - 16'd4;    // Length is subtracted at
1001 354 olof
                                        // the data request
1002
      else if(TxPointerLSB_rst==2'h1)
1003 359 olof
        TxLength <= TxLength - 16'd3;    // Length is subtracted
1004 354 olof
                                         // at the data request
1005
      else if(TxPointerLSB_rst==2'h2)
1006 359 olof
        TxLength <= TxLength - 16'd2;    // Length is subtracted
1007 354 olof
                                         // at the data request
1008
      else if(TxPointerLSB_rst==2'h3)
1009 359 olof
        TxLength <= TxLength - 16'd1;    // Length is subtracted
1010 354 olof
                                         // at the data request
1011 39 mohor
    end
1012 38 mohor
end
1013
 
1014 60 mohor
//Latching length from the buffer descriptor;
1015
always @ (posedge WB_CLK_I or posedge Reset)
1016
begin
1017
  if(Reset)
1018 352 olof
    LatchedTxLength <= 16'h0;
1019 60 mohor
  else
1020
  if(TxEn & TxEn_q & TxBDRead)
1021 352 olof
    LatchedTxLength <= ram_do[31:16];
1022 60 mohor
end
1023
 
1024 39 mohor
assign TxLengthEq0 = TxLength == 0;
1025
assign TxLengthLt4 = TxLength < 4;
1026 38 mohor
 
1027 39 mohor
 
1028 354 olof
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are
1029
// latched because TxPointerMSB is only used for word-aligned accesses.
1030 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1031 38 mohor
begin
1032 40 mohor
  if(Reset)
1033 352 olof
    TxPointerMSB <= 30'h0;
1034 38 mohor
  else
1035 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
1036 352 olof
    TxPointerMSB <= ram_do[31:2];
1037 38 mohor
  else
1038 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
1039 354 olof
      // TxPointer is word-aligned
1040
    TxPointerMSB <= TxPointerMSB + 1'b1;
1041 38 mohor
end
1042
 
1043 96 mohor
 
1044 354 olof
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are
1045
// performed, valid data does not necesserly start at byte 0 (could be byte
1046
// 0, 1, 2 or 3). This signals are used for proper selection of the start
1047
// byte (TxData and TxByteCnt) are set by this two bits.
1048 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1049
begin
1050
  if(Reset)
1051 352 olof
    TxPointerLSB[1:0] <= 0;
1052 96 mohor
  else
1053
  if(TxEn & TxEn_q & TxPointerRead)
1054 352 olof
    TxPointerLSB[1:0] <= ram_do[1:0];
1055 96 mohor
end
1056
 
1057
 
1058 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
1059 354 olof
// After the read access, TxLength needs to be decremented for the number of
1060
// the valid bytes (1 to 4 bytes are valid in the first word). After the
1061
// first read all bytes are valid so this two bits are reset to zero. 
1062 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1063
begin
1064
  if(Reset)
1065 352 olof
    TxPointerLSB_rst[1:0] <= 0;
1066 150 mohor
  else
1067
  if(TxEn & TxEn_q & TxPointerRead)
1068 352 olof
    TxPointerLSB_rst[1:0] <= ram_do[1:0];
1069 150 mohor
  else
1070 354 olof
// After first access pointer is word alligned
1071
  if(MasterWbTX & m_wb_ack_i)
1072 352 olof
    TxPointerLSB_rst[1:0] <= 0;
1073 150 mohor
end
1074 96 mohor
 
1075 150 mohor
 
1076 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1077 38 mohor
begin
1078 40 mohor
  if(Reset)
1079 352 olof
    BlockingIncrementTxPointer <= 0;
1080 38 mohor
  else
1081 39 mohor
  if(MasterAccessFinished)
1082 352 olof
    BlockingIncrementTxPointer <= 0;
1083 38 mohor
  else
1084 150 mohor
  if(IncrTxPointer)
1085 352 olof
    BlockingIncrementTxPointer <= 1'b1;
1086 38 mohor
end
1087
 
1088
 
1089 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
1090 39 mohor
 
1091 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1092 38 mohor
begin
1093 40 mohor
  if(Reset)
1094 352 olof
    ReadTxDataFromMemory <= 1'b0;
1095 38 mohor
  else
1096 278 mohor
  if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
1097 352 olof
    ReadTxDataFromMemory <= 1'b0;
1098 39 mohor
  else
1099 40 mohor
  if(SetReadTxDataFromMemory)
1100 352 olof
    ReadTxDataFromMemory <= 1'b1;
1101 38 mohor
end
1102
 
1103 354 olof
assign ReadTxDataFromMemory_2 = ReadTxDataFromMemory &
1104
                                ~BlockReadTxDataFromMemory;
1105 221 mohor
 
1106 354 olof
assign tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
1107 221 mohor
 
1108 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1109 38 mohor
begin
1110 40 mohor
  if(Reset)
1111 352 olof
    BlockReadTxDataFromMemory <= 1'b0;
1112 38 mohor
  else
1113 354 olof
  if((TxBufferAlmostFull | TxLength <= 4) & MasterWbTX & (~cyc_cleared) &
1114
     (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
1115 352 olof
    BlockReadTxDataFromMemory <= 1'b1;
1116 219 mohor
  else
1117 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
1118 352 olof
    BlockReadTxDataFromMemory <= 1'b0;
1119 39 mohor
end
1120
 
1121
 
1122
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
1123 159 mohor
 
1124 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
1125 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1126 39 mohor
begin
1127 40 mohor
  if(Reset)
1128 38 mohor
    begin
1129 352 olof
      MasterWbTX <= 1'b0;
1130
      MasterWbRX <= 1'b0;
1131
      m_wb_adr_o <= 30'h0;
1132
      m_wb_cyc_o <= 1'b0;
1133
      m_wb_we_o  <= 1'b0;
1134
      m_wb_sel_o <= 4'h0;
1135
      cyc_cleared<= 1'b0;
1136
      tx_burst_cnt<= 0;
1137
      rx_burst_cnt<= 0;
1138
      IncrTxPointer<= 1'b0;
1139
      tx_burst_en<= 1'b1;
1140
      rx_burst_en<= 1'b0;
1141 354 olof
      m_wb_cti_o <= 3'b0;
1142 38 mohor
    end
1143 39 mohor
  else
1144
    begin
1145
      // Switching between two stages depends on enable signals
1146 359 olof
      casez ({MasterWbTX,
1147 354 olof
             MasterWbRX,
1148
             ReadTxDataFromMemory_2,
1149
             WriteRxDataToMemory,
1150
             MasterAccessFinished,
1151
             cyc_cleared,
1152
             tx_burst,
1153
             rx_burst})  // synopsys parallel_case
1154
 
1155
        8'b00_10_00_10, // Idle and MRB needed
1156 359 olof
        8'b10_1?_10_1?, // MRB continues
1157 354 olof
        8'b10_10_01_10, // Clear (previously MR) and MRB needed
1158 359 olof
        8'b01_1?_01_1?: // Clear (previously MW) and MRB needed
1159 39 mohor
          begin
1160 352 olof
            MasterWbTX <= 1'b1;  // tx burst
1161
            MasterWbRX <= 1'b0;
1162
            m_wb_cyc_o <= 1'b1;
1163
            m_wb_we_o  <= 1'b0;
1164
            m_wb_sel_o <= 4'hf;
1165
            cyc_cleared<= 1'b0;
1166
            IncrTxPointer<= 1'b1;
1167
            tx_burst_cnt <= tx_burst_cnt+3'h1;
1168 226 tadejm
            if(tx_burst_cnt==0)
1169 352 olof
              m_wb_adr_o <= TxPointerMSB;
1170 226 tadejm
            else
1171 354 olof
              m_wb_adr_o <= m_wb_adr_o + 1'b1;
1172 226 tadejm
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1173
              begin
1174 352 olof
                tx_burst_en<= 1'b0;
1175
                m_wb_cti_o <= 3'b111;
1176 226 tadejm
              end
1177
            else
1178
              begin
1179 352 olof
                m_wb_cti_o <= 3'b010;
1180 226 tadejm
              end
1181
          end
1182 359 olof
        8'b00_?1_00_?1,             // Idle and MWB needed
1183
        8'b01_?1_10_?1,             // MWB continues
1184 226 tadejm
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1185 359 olof
        8'b10_?1_01_?1 :            // Clear (previously MR) and MWB needed
1186 226 tadejm
          begin
1187 352 olof
            MasterWbTX <= 1'b0;  // rx burst
1188
            MasterWbRX <= 1'b1;
1189
            m_wb_cyc_o <= 1'b1;
1190
            m_wb_we_o  <= 1'b1;
1191
            m_wb_sel_o <= RxByteSel;
1192
            IncrTxPointer<= 1'b0;
1193
            cyc_cleared<= 1'b0;
1194
            rx_burst_cnt <= rx_burst_cnt+3'h1;
1195 226 tadejm
 
1196
            if(rx_burst_cnt==0)
1197 352 olof
              m_wb_adr_o <= RxPointerMSB;
1198 226 tadejm
            else
1199 352 olof
              m_wb_adr_o <= m_wb_adr_o+1'b1;
1200 226 tadejm
 
1201
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1202
              begin
1203 352 olof
                rx_burst_en<= 1'b0;
1204
                m_wb_cti_o <= 3'b111;
1205 226 tadejm
              end
1206
            else
1207
              begin
1208 352 olof
                m_wb_cti_o <= 3'b010;
1209 226 tadejm
              end
1210
          end
1211 359 olof
        8'b00_?1_00_?0 :// idle and MW is needed (data write to rx buffer)
1212 226 tadejm
          begin
1213 352 olof
            MasterWbTX <= 1'b0;
1214
            MasterWbRX <= 1'b1;
1215
            m_wb_adr_o <= RxPointerMSB;
1216
            m_wb_cyc_o <= 1'b1;
1217
            m_wb_we_o  <= 1'b1;
1218
            m_wb_sel_o <= RxByteSel;
1219
            IncrTxPointer<= 1'b0;
1220 39 mohor
          end
1221 354 olof
        8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer)
1222 39 mohor
          begin
1223 352 olof
            MasterWbTX <= 1'b1;
1224
            MasterWbRX <= 1'b0;
1225
            m_wb_adr_o <= TxPointerMSB;
1226
            m_wb_cyc_o <= 1'b1;
1227
            m_wb_we_o  <= 1'b0;
1228
            m_wb_sel_o <= 4'hf;
1229
            IncrTxPointer<= 1'b1;
1230 39 mohor
          end
1231 354 olof
        8'b10_10_01_00,// MR and MR is needed (data read from tx buffer)
1232 359 olof
        8'b01_1?_01_0?  :// MW and MR is needed (data read from tx buffer)
1233 39 mohor
          begin
1234 352 olof
            MasterWbTX <= 1'b1;
1235
            MasterWbRX <= 1'b0;
1236
            m_wb_adr_o <= TxPointerMSB;
1237
            m_wb_cyc_o <= 1'b1;
1238
            m_wb_we_o  <= 1'b0;
1239
            m_wb_sel_o <= 4'hf;
1240
            cyc_cleared<= 1'b0;
1241
            IncrTxPointer<= 1'b1;
1242 39 mohor
          end
1243 354 olof
        8'b01_01_01_00,// MW and MW needed (data write to rx buffer)
1244 359 olof
        8'b10_?1_01_?0 :// MR and MW is needed (data write to rx buffer)
1245 39 mohor
          begin
1246 352 olof
            MasterWbTX <= 1'b0;
1247
            MasterWbRX <= 1'b1;
1248
            m_wb_adr_o <= RxPointerMSB;
1249
            m_wb_cyc_o <= 1'b1;
1250
            m_wb_we_o  <= 1'b1;
1251
            m_wb_sel_o <= RxByteSel;
1252
            cyc_cleared<= 1'b0;
1253
            IncrTxPointer<= 1'b0;
1254 39 mohor
          end
1255 354 olof
        8'b01_01_10_00,// MW and MW needed (cycle is cleared between
1256
                      // previous and next access)
1257 359 olof
        8'b01_1?_10_?0,// MW and MW or MR or MRB needed (cycle is
1258 354 olof
                    // cleared between previous and next access)
1259
        8'b10_10_10_00,// MR and MR needed (cycle is cleared between
1260
                       // previous and next access)
1261 359 olof
        8'b10_?1_10_0? :// MR and MR or MW or MWB (cycle is cleared
1262 354 olof
                       // between previous and next access)
1263 39 mohor
          begin
1264 354 olof
            m_wb_cyc_o <= 1'b0;// whatever and master read or write is
1265
                               // needed. We need to clear m_wb_cyc_o
1266
                               // before next access is started
1267 352 olof
            cyc_cleared<= 1'b1;
1268
            IncrTxPointer<= 1'b0;
1269
            tx_burst_cnt<= 0;
1270
            tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1271
            rx_burst_cnt<= 0;
1272
            rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1273
              m_wb_cti_o <= 3'b0;
1274 110 mohor
          end
1275 359 olof
        8'b??_00_10_00,// whatever and no master read or write is needed
1276 354 olof
                       // (ack or err comes finishing previous access)
1277 359 olof
        8'b??_00_01_00 : // Between cyc_cleared request was cleared
1278 110 mohor
          begin
1279 352 olof
            MasterWbTX <= 1'b0;
1280
            MasterWbRX <= 1'b0;
1281
            m_wb_cyc_o <= 1'b0;
1282
            cyc_cleared<= 1'b0;
1283
            IncrTxPointer<= 1'b0;
1284
            rx_burst_cnt<= 0;
1285 354 olof
            // Counter is not decremented, yet, so plus1 is used.
1286
            rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 :
1287
                                       enough_data_in_rxfifo_for_burst;
1288
            m_wb_cti_o <= 3'b0;
1289 39 mohor
          end
1290 354 olof
        8'b00_00_00_00:  // whatever and no master read or write is needed
1291
                         // (ack or err comes finishing previous access)
1292 127 mohor
          begin
1293 352 olof
            tx_burst_cnt<= 0;
1294
            tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1295 127 mohor
          end
1296 226 tadejm
        default:                    // Don't touch
1297 82 mohor
          begin
1298 352 olof
            MasterWbTX <= MasterWbTX;
1299
            MasterWbRX <= MasterWbRX;
1300
            m_wb_cyc_o <= m_wb_cyc_o;
1301
            m_wb_sel_o <= m_wb_sel_o;
1302
            IncrTxPointer<= IncrTxPointer;
1303 82 mohor
          end
1304 39 mohor
      endcase
1305
    end
1306 38 mohor
end
1307
 
1308 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1309 38 mohor
 
1310 354 olof
eth_fifo
1311
     #(
1312
       .DATA_WIDTH(TX_FIFO_DATA_WIDTH),
1313
       .DEPTH(TX_FIFO_DEPTH),
1314
       .CNT_WIDTH(TX_FIFO_CNT_WIDTH))
1315
tx_fifo (
1316
       .data_in(m_wb_dat_i),
1317
       .data_out(TxData_wb),
1318
       .clk(WB_CLK_I),
1319
       .reset(Reset),
1320
       .write(MasterWbTX & m_wb_ack_i),
1321
       .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1322
       .clear(TxFifoClear),
1323
       .full(TxBufferFull),
1324
       .almost_full(TxBufferAlmostFull),
1325
       .almost_empty(TxBufferAlmostEmpty),
1326
       .empty(TxBufferEmpty),
1327
       .cnt(txfifo_cnt)
1328
       );
1329 39 mohor
 
1330 354 olof
// Start: Generation of the TxStartFrm_wb which is then synchronized to the
1331
// MTxClk
1332 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1333 38 mohor
begin
1334 40 mohor
  if(Reset)
1335 352 olof
    TxStartFrm_wb <= 1'b0;
1336 38 mohor
  else
1337 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1338 352 olof
    TxStartFrm_wb <= 1'b1;
1339 38 mohor
  else
1340 39 mohor
  if(TxStartFrm_syncb2)
1341 352 olof
    TxStartFrm_wb <= 1'b0;
1342 38 mohor
end
1343
 
1344 354 olof
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's
1345
// blocked.
1346 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1347 38 mohor
begin
1348 40 mohor
  if(Reset)
1349 352 olof
    StartOccured <= 1'b0;
1350 38 mohor
  else
1351 39 mohor
  if(TxStartFrm_wb)
1352 352 olof
    StartOccured <= 1'b1;
1353 38 mohor
  else
1354 39 mohor
  if(ResetTxBDReady)
1355 352 olof
    StartOccured <= 1'b0;
1356 38 mohor
end
1357
 
1358 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1359 40 mohor
always @ (posedge MTxClk or posedge Reset)
1360 39 mohor
begin
1361 40 mohor
  if(Reset)
1362 352 olof
    TxStartFrm_sync1 <= 1'b0;
1363 39 mohor
  else
1364 352 olof
    TxStartFrm_sync1 <= TxStartFrm_wb;
1365 39 mohor
end
1366 38 mohor
 
1367 40 mohor
always @ (posedge MTxClk or posedge Reset)
1368 39 mohor
begin
1369 40 mohor
  if(Reset)
1370 352 olof
    TxStartFrm_sync2 <= 1'b0;
1371 39 mohor
  else
1372 352 olof
    TxStartFrm_sync2 <= TxStartFrm_sync1;
1373 39 mohor
end
1374
 
1375 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1376 38 mohor
begin
1377 40 mohor
  if(Reset)
1378 352 olof
    TxStartFrm_syncb1 <= 1'b0;
1379 38 mohor
  else
1380 352 olof
    TxStartFrm_syncb1 <= TxStartFrm_sync2;
1381 38 mohor
end
1382
 
1383 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1384 38 mohor
begin
1385 40 mohor
  if(Reset)
1386 352 olof
    TxStartFrm_syncb2 <= 1'b0;
1387 38 mohor
  else
1388 352 olof
    TxStartFrm_syncb2 <= TxStartFrm_syncb1;
1389 39 mohor
end
1390
 
1391 40 mohor
always @ (posedge MTxClk or posedge Reset)
1392 39 mohor
begin
1393 40 mohor
  if(Reset)
1394 352 olof
    TxStartFrm <= 1'b0;
1395 38 mohor
  else
1396 39 mohor
  if(TxStartFrm_sync2)
1397 352 olof
    TxStartFrm <= 1'b1;
1398 39 mohor
  else
1399 354 olof
  if(TxUsedData_q | ~TxStartFrm_sync2 &
1400
     (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
1401 352 olof
    TxStartFrm <= 1'b0;
1402 38 mohor
end
1403 354 olof
// End: Generation of the TxStartFrm_wb which is then synchronized to the
1404
// MTxClk
1405 38 mohor
 
1406
 
1407 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1408 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1409 38 mohor
begin
1410 40 mohor
  if(Reset)
1411 352 olof
    TxEndFrm_wb <= 1'b0;
1412 38 mohor
  else
1413 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1414 352 olof
    TxEndFrm_wb <= 1'b1;
1415 38 mohor
  else
1416 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1417 352 olof
    TxEndFrm_wb <= 1'b0;
1418 38 mohor
end
1419
 
1420
// Marks which bytes are valid within the word.
1421 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1422 38 mohor
 
1423
 
1424 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1425 38 mohor
begin
1426 40 mohor
  if(Reset)
1427 352 olof
    LatchValidBytes <= 1'b0;
1428 38 mohor
  else
1429 39 mohor
  if(TxLengthLt4 & TxBDReady)
1430 352 olof
    LatchValidBytes <= 1'b1;
1431 38 mohor
  else
1432 352 olof
    LatchValidBytes <= 1'b0;
1433 38 mohor
end
1434
 
1435 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1436 38 mohor
begin
1437 40 mohor
  if(Reset)
1438 352 olof
    LatchValidBytes_q <= 1'b0;
1439 38 mohor
  else
1440 352 olof
    LatchValidBytes_q <= LatchValidBytes;
1441 38 mohor
end
1442
 
1443
 
1444 39 mohor
// Latching valid bytes
1445 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1446 38 mohor
begin
1447 40 mohor
  if(Reset)
1448 352 olof
    TxValidBytesLatched <= 2'h0;
1449 38 mohor
  else
1450 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1451 352 olof
    TxValidBytesLatched <= TxValidBytes;
1452 39 mohor
  else
1453
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1454 352 olof
    TxValidBytesLatched <= 2'h0;
1455 38 mohor
end
1456
 
1457
 
1458
assign TxIRQEn          = TxStatus[14];
1459 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1460
assign PerPacketPad     = TxStatus[12];
1461
assign PerPacketCrcEn   = TxStatus[11];
1462 38 mohor
 
1463
 
1464 77 mohor
assign RxIRQEn         = RxStatus[14];
1465 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1466 38 mohor
 
1467
 
1468 354 olof
// Temporary Tx and Rx buffer descriptor address
1469
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite  & ~WrapTxStatusBit}} &
1470
                              (TxBDAddress + 1'b1); // Tx BD increment or wrap
1471
                                                    // (last BD)
1472 38 mohor
 
1473 354 olof
assign TempRxBDAddress[7:1] =
1474
  {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
1475
  {7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1); // Using next Rx BD
1476
                                                // (increment address)
1477 38 mohor
 
1478
// Latching Tx buffer descriptor address
1479 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1480 38 mohor
begin
1481 40 mohor
  if(Reset)
1482 352 olof
    TxBDAddress <= 7'h0;
1483 321 igorm
  else if (r_TxEn & (~r_TxEn_q))
1484 352 olof
    TxBDAddress <= 7'h0;
1485 321 igorm
  else if (TxStatusWrite)
1486 352 olof
    TxBDAddress <= TempTxBDAddress;
1487 38 mohor
end
1488
 
1489
// Latching Rx buffer descriptor address
1490 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1491 38 mohor
begin
1492 40 mohor
  if(Reset)
1493 352 olof
    RxBDAddress <= 7'h0;
1494 321 igorm
  else if(r_RxEn & (~r_RxEn_q))
1495 352 olof
    RxBDAddress <= r_TxBDNum[6:0];
1496 321 igorm
  else if(RxStatusWrite)
1497 352 olof
    RxBDAddress <= TempRxBDAddress;
1498 38 mohor
end
1499
 
1500 354 olof
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0],
1501
                                RetryLimit, LateCollLatched, DeferLatched,
1502
                                CarrierSenseLost};
1503 38 mohor
 
1504 261 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
1505 60 mohor
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1506 38 mohor
 
1507 60 mohor
 
1508 38 mohor
// Signals used for various purposes
1509 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1510 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1511
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1512
 
1513
 
1514 39 mohor
// Generating delayed signals
1515 40 mohor
always @ (posedge MTxClk or posedge Reset)
1516 38 mohor
begin
1517 40 mohor
  if(Reset)
1518 39 mohor
    begin
1519 352 olof
      TxAbort_q      <= 1'b0;
1520
      TxRetry_q      <= 1'b0;
1521
      TxUsedData_q   <= 1'b0;
1522 39 mohor
    end
1523 38 mohor
  else
1524 39 mohor
    begin
1525 352 olof
      TxAbort_q      <= TxAbort;
1526
      TxRetry_q      <= TxRetry;
1527
      TxUsedData_q   <= TxUsedData;
1528 39 mohor
    end
1529 38 mohor
end
1530
 
1531
// Generating delayed signals
1532 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1533 38 mohor
begin
1534 40 mohor
  if(Reset)
1535 38 mohor
    begin
1536 352 olof
      TxDone_wb_q   <= 1'b0;
1537
      TxAbort_wb_q  <= 1'b0;
1538
      TxRetry_wb_q  <= 1'b0;
1539 38 mohor
    end
1540
  else
1541
    begin
1542 352 olof
      TxDone_wb_q   <= TxDone_wb;
1543
      TxAbort_wb_q  <= TxAbort_wb;
1544
      TxRetry_wb_q  <= TxRetry_wb;
1545 38 mohor
    end
1546
end
1547
 
1548
 
1549 219 mohor
reg TxAbortPacketBlocked;
1550
always @ (posedge WB_CLK_I or posedge Reset)
1551
begin
1552
  if(Reset)
1553 352 olof
    TxAbortPacket <= 1'b0;
1554 219 mohor
  else
1555 354 olof
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
1556
    (~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
1557
    (~TxAbortPacketBlocked))
1558 352 olof
    TxAbortPacket <= 1'b1;
1559 219 mohor
  else
1560 352 olof
    TxAbortPacket <= 1'b0;
1561 219 mohor
end
1562
 
1563
 
1564
always @ (posedge WB_CLK_I or posedge Reset)
1565
begin
1566
  if(Reset)
1567 352 olof
    TxAbortPacket_NotCleared <= 1'b0;
1568 221 mohor
  else
1569 272 tadejm
  if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
1570 352 olof
    TxAbortPacket_NotCleared <= 1'b0;
1571 272 tadejm
  else
1572 354 olof
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
1573
     (~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
1574
     (~TxAbortPacketBlocked))
1575 352 olof
    TxAbortPacket_NotCleared <= 1'b1;
1576 221 mohor
end
1577
 
1578
 
1579
always @ (posedge WB_CLK_I or posedge Reset)
1580
begin
1581
  if(Reset)
1582 352 olof
    TxAbortPacketBlocked <= 1'b0;
1583 219 mohor
  else
1584 280 mohor
  if(!TxAbort_wb & TxAbort_wb_q)
1585 352 olof
    TxAbortPacketBlocked <= 1'b0;
1586 280 mohor
  else
1587 219 mohor
  if(TxAbortPacket)
1588 352 olof
    TxAbortPacketBlocked <= 1'b1;
1589 219 mohor
end
1590
 
1591
 
1592
reg TxRetryPacketBlocked;
1593
always @ (posedge WB_CLK_I or posedge Reset)
1594
begin
1595
  if(Reset)
1596 352 olof
    TxRetryPacket <= 1'b0;
1597 219 mohor
  else
1598 354 olof
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1599
     !TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1600 352 olof
    TxRetryPacket <= 1'b1;
1601 219 mohor
  else
1602 352 olof
    TxRetryPacket <= 1'b0;
1603 219 mohor
end
1604
 
1605
 
1606
always @ (posedge WB_CLK_I or posedge Reset)
1607
begin
1608
  if(Reset)
1609 352 olof
    TxRetryPacket_NotCleared <= 1'b0;
1610 221 mohor
  else
1611 272 tadejm
  if(StartTxBDRead)
1612 352 olof
    TxRetryPacket_NotCleared <= 1'b0;
1613 272 tadejm
  else
1614 354 olof
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1615
     !TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1616 352 olof
    TxRetryPacket_NotCleared <= 1'b1;
1617 221 mohor
end
1618
 
1619
 
1620
always @ (posedge WB_CLK_I or posedge Reset)
1621
begin
1622
  if(Reset)
1623 352 olof
    TxRetryPacketBlocked <= 1'b0;
1624 219 mohor
  else
1625 280 mohor
  if(!TxRetry_wb & TxRetry_wb_q)
1626 352 olof
    TxRetryPacketBlocked <= 1'b0;
1627 280 mohor
  else
1628 219 mohor
  if(TxRetryPacket)
1629 352 olof
    TxRetryPacketBlocked <= 1'b1;
1630 219 mohor
end
1631
 
1632
 
1633 221 mohor
reg TxDonePacketBlocked;
1634
always @ (posedge WB_CLK_I or posedge Reset)
1635
begin
1636
  if(Reset)
1637 352 olof
    TxDonePacket <= 1'b0;
1638 221 mohor
  else
1639 354 olof
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1640
     !TxDonePacketBlocked | TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1641 352 olof
    TxDonePacket <= 1'b1;
1642 221 mohor
  else
1643 352 olof
    TxDonePacket <= 1'b0;
1644 221 mohor
end
1645
 
1646
 
1647
always @ (posedge WB_CLK_I or posedge Reset)
1648
begin
1649
  if(Reset)
1650 352 olof
    TxDonePacket_NotCleared <= 1'b0;
1651 221 mohor
  else
1652 272 tadejm
  if(TxEn & TxEn_q & TxDonePacket_NotCleared)
1653 352 olof
    TxDonePacket_NotCleared <= 1'b0;
1654 272 tadejm
  else
1655 354 olof
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1656
     (~TxDonePacketBlocked) | TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
1657 352 olof
    TxDonePacket_NotCleared <= 1'b1;
1658 221 mohor
end
1659
 
1660
 
1661
always @ (posedge WB_CLK_I or posedge Reset)
1662
begin
1663
  if(Reset)
1664 352 olof
    TxDonePacketBlocked <= 1'b0;
1665 221 mohor
  else
1666 280 mohor
  if(!TxDone_wb & TxDone_wb_q)
1667 352 olof
    TxDonePacketBlocked <= 1'b0;
1668 280 mohor
  else
1669 221 mohor
  if(TxDonePacket)
1670 352 olof
    TxDonePacketBlocked <= 1'b1;
1671 221 mohor
end
1672
 
1673
 
1674 38 mohor
// Indication of the last word
1675 40 mohor
always @ (posedge MTxClk or posedge Reset)
1676 38 mohor
begin
1677 40 mohor
  if(Reset)
1678 352 olof
    LastWord <= 1'b0;
1679 38 mohor
  else
1680
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1681 352 olof
    LastWord <= 1'b0;
1682 38 mohor
  else
1683
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1684 352 olof
    LastWord <= TxEndFrm_wb;
1685 38 mohor
end
1686
 
1687
 
1688
// Tx end frame generation
1689 40 mohor
always @ (posedge MTxClk or posedge Reset)
1690 38 mohor
begin
1691 40 mohor
  if(Reset)
1692 352 olof
    TxEndFrm <= 1'b0;
1693 38 mohor
  else
1694 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1695 352 olof
    TxEndFrm <= 1'b0;
1696 38 mohor
  else
1697
  if(Flop & LastWord)
1698
    begin
1699 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1700 352 olof
        1 : TxEndFrm <= TxByteCnt == 2'h0;
1701
        2 : TxEndFrm <= TxByteCnt == 2'h1;
1702
        3 : TxEndFrm <= TxByteCnt == 2'h2;
1703
 
1704
        default : TxEndFrm <= 1'b0;
1705 38 mohor
      endcase
1706
    end
1707
end
1708
 
1709
 
1710
// Tx data selection (latching)
1711 40 mohor
always @ (posedge MTxClk or posedge Reset)
1712 38 mohor
begin
1713 40 mohor
  if(Reset)
1714 352 olof
    TxData <= 0;
1715 38 mohor
  else
1716 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1717 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1718 354 olof
      2'h0 : TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
1719
      2'h1 : TxData <= TxData_wb[23:16];// Big Endian Byte Ordering
1720
      2'h2 : TxData <= TxData_wb[15:08];// Big Endian Byte Ordering
1721
      2'h3 : TxData <= TxData_wb[07:00];// Big Endian Byte Ordering
1722 96 mohor
    endcase
1723 38 mohor
  else
1724 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1725 354 olof
    TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
1726 96 mohor
  else
1727 38 mohor
  if(TxUsedData & Flop)
1728
    begin
1729 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1730 354 olof
 
1731 352 olof
        1 : TxData <= TxDataLatched[23:16];
1732
        2 : TxData <= TxDataLatched[15:8];
1733
        3 : TxData <= TxDataLatched[7:0];
1734 38 mohor
      endcase
1735
    end
1736
end
1737
 
1738
 
1739
// Latching tx data
1740 40 mohor
always @ (posedge MTxClk or posedge Reset)
1741 38 mohor
begin
1742 40 mohor
  if(Reset)
1743 352 olof
    TxDataLatched[31:0] <= 32'h0;
1744 38 mohor
  else
1745 354 olof
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 |
1746
     TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1747 352 olof
    TxDataLatched[31:0] <= TxData_wb[31:0];
1748 38 mohor
end
1749
 
1750
 
1751
// Tx under run
1752 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1753 38 mohor
begin
1754 40 mohor
  if(Reset)
1755 352 olof
    TxUnderRun_wb <= 1'b0;
1756 38 mohor
  else
1757 39 mohor
  if(TxAbortPulse)
1758 352 olof
    TxUnderRun_wb <= 1'b0;
1759 60 mohor
  else
1760
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1761 352 olof
    TxUnderRun_wb <= 1'b1;
1762 60 mohor
end
1763
 
1764
 
1765 159 mohor
reg TxUnderRun_sync1;
1766
 
1767 60 mohor
// Tx under run
1768
always @ (posedge MTxClk or posedge Reset)
1769
begin
1770
  if(Reset)
1771 352 olof
    TxUnderRun_sync1 <= 1'b0;
1772 43 mohor
  else
1773 60 mohor
  if(TxUnderRun_wb)
1774 352 olof
    TxUnderRun_sync1 <= 1'b1;
1775 60 mohor
  else
1776 159 mohor
  if(BlockingTxStatusWrite_sync2)
1777 352 olof
    TxUnderRun_sync1 <= 1'b0;
1778 159 mohor
end
1779
 
1780
// Tx under run
1781
always @ (posedge MTxClk or posedge Reset)
1782
begin
1783
  if(Reset)
1784 352 olof
    TxUnderRun <= 1'b0;
1785 159 mohor
  else
1786
  if(BlockingTxStatusWrite_sync2)
1787 352 olof
    TxUnderRun <= 1'b0;
1788 159 mohor
  else
1789
  if(TxUnderRun_sync1)
1790 352 olof
    TxUnderRun <= 1'b1;
1791 38 mohor
end
1792
 
1793
 
1794
// Tx Byte counter
1795 40 mohor
always @ (posedge MTxClk or posedge Reset)
1796 38 mohor
begin
1797 40 mohor
  if(Reset)
1798 352 olof
    TxByteCnt <= 2'h0;
1799 38 mohor
  else
1800
  if(TxAbort_q | TxRetry_q)
1801 352 olof
    TxByteCnt <= 2'h0;
1802 38 mohor
  else
1803
  if(TxStartFrm & ~TxUsedData)
1804 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1805 352 olof
      2'h0 : TxByteCnt <= 2'h1;
1806
      2'h1 : TxByteCnt <= 2'h2;
1807
      2'h2 : TxByteCnt <= 2'h3;
1808
      2'h3 : TxByteCnt <= 2'h0;
1809 96 mohor
    endcase
1810 38 mohor
  else
1811
  if(TxUsedData & Flop)
1812 352 olof
    TxByteCnt <= TxByteCnt + 1'b1;
1813 38 mohor
end
1814
 
1815 39 mohor
 
1816 150 mohor
always @ (posedge MTxClk or posedge Reset)
1817
begin
1818
  if(Reset)
1819 352 olof
    ReadTxDataFromFifo_tck <= 1'b0;
1820 150 mohor
  else
1821 354 olof
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 &
1822
     ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1823 352 olof
     ReadTxDataFromFifo_tck <= 1'b1;
1824 150 mohor
  else
1825
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1826 352 olof
    ReadTxDataFromFifo_tck <= 1'b0;
1827 38 mohor
end
1828
 
1829 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1830 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1831 38 mohor
begin
1832 40 mohor
  if(Reset)
1833 352 olof
    ReadTxDataFromFifo_sync1 <= 1'b0;
1834 38 mohor
  else
1835 352 olof
    ReadTxDataFromFifo_sync1 <= ReadTxDataFromFifo_tck;
1836 39 mohor
end
1837 38 mohor
 
1838 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1839 38 mohor
begin
1840 40 mohor
  if(Reset)
1841 352 olof
    ReadTxDataFromFifo_sync2 <= 1'b0;
1842 38 mohor
  else
1843 352 olof
    ReadTxDataFromFifo_sync2 <= ReadTxDataFromFifo_sync1;
1844 38 mohor
end
1845
 
1846 40 mohor
always @ (posedge MTxClk or posedge Reset)
1847 38 mohor
begin
1848 40 mohor
  if(Reset)
1849 352 olof
    ReadTxDataFromFifo_syncb1 <= 1'b0;
1850 38 mohor
  else
1851 352 olof
    ReadTxDataFromFifo_syncb1 <= ReadTxDataFromFifo_sync2;
1852 38 mohor
end
1853
 
1854 40 mohor
always @ (posedge MTxClk or posedge Reset)
1855 38 mohor
begin
1856 40 mohor
  if(Reset)
1857 352 olof
    ReadTxDataFromFifo_syncb2 <= 1'b0;
1858 38 mohor
  else
1859 352 olof
    ReadTxDataFromFifo_syncb2 <= ReadTxDataFromFifo_syncb1;
1860 38 mohor
end
1861
 
1862 150 mohor
always @ (posedge MTxClk or posedge Reset)
1863
begin
1864
  if(Reset)
1865 352 olof
    ReadTxDataFromFifo_syncb3 <= 1'b0;
1866 150 mohor
  else
1867 352 olof
    ReadTxDataFromFifo_syncb3 <= ReadTxDataFromFifo_syncb2;
1868 150 mohor
end
1869
 
1870 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1871 38 mohor
begin
1872 40 mohor
  if(Reset)
1873 352 olof
    ReadTxDataFromFifo_sync3 <= 1'b0;
1874 38 mohor
  else
1875 352 olof
    ReadTxDataFromFifo_sync3 <= ReadTxDataFromFifo_sync2;
1876 38 mohor
end
1877
 
1878 354 olof
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 &
1879
                               ~ReadTxDataFromFifo_sync3;
1880
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization
1881
// to the WB_CLK_I
1882 38 mohor
 
1883
 
1884 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1885 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1886 38 mohor
begin
1887 40 mohor
  if(Reset)
1888 352 olof
    TxRetrySync1 <= 1'b0;
1889 38 mohor
  else
1890 352 olof
    TxRetrySync1 <= TxRetry;
1891 38 mohor
end
1892
 
1893 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1894 38 mohor
begin
1895 40 mohor
  if(Reset)
1896 352 olof
    TxRetry_wb <= 1'b0;
1897 38 mohor
  else
1898 352 olof
    TxRetry_wb <= TxRetrySync1;
1899 38 mohor
end
1900
 
1901
 
1902 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1903 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1904 38 mohor
begin
1905 40 mohor
  if(Reset)
1906 352 olof
    TxDoneSync1 <= 1'b0;
1907 38 mohor
  else
1908 352 olof
    TxDoneSync1 <= TxDone;
1909 38 mohor
end
1910
 
1911 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1912 38 mohor
begin
1913 40 mohor
  if(Reset)
1914 352 olof
    TxDone_wb <= 1'b0;
1915 38 mohor
  else
1916 352 olof
    TxDone_wb <= TxDoneSync1;
1917 38 mohor
end
1918
 
1919 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1920 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1921 38 mohor
begin
1922 40 mohor
  if(Reset)
1923 352 olof
    TxAbortSync1 <= 1'b0;
1924 38 mohor
  else
1925 352 olof
    TxAbortSync1 <= TxAbort;
1926 38 mohor
end
1927
 
1928 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1929 38 mohor
begin
1930 40 mohor
  if(Reset)
1931 352 olof
    TxAbort_wb <= 1'b0;
1932 38 mohor
  else
1933 352 olof
    TxAbort_wb <= TxAbortSync1;
1934 38 mohor
end
1935
 
1936
 
1937 354 olof
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 |
1938
                       r_RxEn & ~r_RxEn_q;
1939 39 mohor
 
1940 40 mohor
// Reading the Rx buffer descriptor
1941
always @ (posedge WB_CLK_I or posedge Reset)
1942
begin
1943
  if(Reset)
1944 352 olof
    RxBDRead <= 1'b0;
1945 40 mohor
  else
1946 166 mohor
  if(StartRxBDRead & ~RxReady)
1947 352 olof
    RxBDRead <= 1'b1;
1948 40 mohor
  else
1949
  if(RxBDReady)
1950 352 olof
    RxBDRead <= 1'b0;
1951 40 mohor
end
1952 39 mohor
 
1953
 
1954 354 olof
// Reading of the next receive buffer descriptor starts after reception status
1955
// is written to the previous one.
1956 38 mohor
 
1957
// Latching READY status of the Rx buffer descriptor
1958 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1959 38 mohor
begin
1960 40 mohor
  if(Reset)
1961 352 olof
    RxBDReady <= 1'b0;
1962 38 mohor
  else
1963 166 mohor
  if(RxPointerRead)
1964 352 olof
    RxBDReady <= 1'b0;
1965 150 mohor
  else
1966 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1967 354 olof
    RxBDReady <= ram_do[15];// RxBDReady is sampled only once at the beginning
1968 38 mohor
end
1969
 
1970 40 mohor
// Latching Rx buffer descriptor status
1971 354 olof
// Data is avaliable one cycle after the access is started (at that time
1972
// signal RxEn is not active)
1973 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1974 38 mohor
begin
1975 40 mohor
  if(Reset)
1976 352 olof
    RxStatus <= 2'h0;
1977 38 mohor
  else
1978 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1979 352 olof
    RxStatus <= ram_do[14:13];
1980 38 mohor
end
1981
 
1982
 
1983 166 mohor
// RxReady generation
1984
always @ (posedge WB_CLK_I or posedge Reset)
1985
begin
1986
  if(Reset)
1987 352 olof
    RxReady <= 1'b0;
1988 354 olof
  else if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)
1989 352 olof
    RxReady <= 1'b0;
1990 354 olof
  else if(RxEn & RxEn_q & RxPointerRead)
1991 352 olof
    RxReady <= 1'b1;
1992 166 mohor
end
1993 38 mohor
 
1994
 
1995 40 mohor
// Reading Rx BD pointer
1996
assign StartRxPointerRead = RxBDRead & RxBDReady;
1997
 
1998
// Reading Tx BD Pointer
1999
always @ (posedge WB_CLK_I or posedge Reset)
2000 38 mohor
begin
2001 40 mohor
  if(Reset)
2002 352 olof
    RxPointerRead <= 1'b0;
2003 38 mohor
  else
2004 40 mohor
  if(StartRxPointerRead)
2005 352 olof
    RxPointerRead <= 1'b1;
2006 38 mohor
  else
2007 166 mohor
  if(RxEn & RxEn_q)
2008 352 olof
    RxPointerRead <= 1'b0;
2009 38 mohor
end
2010
 
2011 113 mohor
 
2012 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
2013
always @ (posedge WB_CLK_I or posedge Reset)
2014
begin
2015
  if(Reset)
2016 352 olof
    RxPointerMSB <= 30'h0;
2017 40 mohor
  else
2018
  if(RxEn & RxEn_q & RxPointerRead)
2019 352 olof
    RxPointerMSB <= ram_do[31:2];
2020 40 mohor
  else
2021 113 mohor
  if(MasterWbRX & m_wb_ack_i)
2022 354 olof
      RxPointerMSB <= RxPointerMSB + 1'b1; // Word access (always word access.
2023
                                           // m_wb_sel_o are used for
2024
                                           // selecting bytes)
2025 40 mohor
end
2026 38 mohor
 
2027
 
2028 354 olof
//Latching last addresses from buffer descriptor (used as byte-half-word
2029
//indicator);
2030 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2031
begin
2032
  if(Reset)
2033 352 olof
    RxPointerLSB_rst[1:0] <= 0;
2034 96 mohor
  else
2035 354 olof
  if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active
2036 352 olof
    RxPointerLSB_rst[1:0] <= 0;
2037 96 mohor
  else
2038
  if(RxEn & RxEn_q & RxPointerRead)
2039 352 olof
    RxPointerLSB_rst[1:0] <= ram_do[1:0];
2040 96 mohor
end
2041
 
2042
 
2043 159 mohor
always @ (RxPointerLSB_rst)
2044 96 mohor
begin
2045 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
2046
    2'h0 : RxByteSel[3:0] = 4'hf;
2047
    2'h1 : RxByteSel[3:0] = 4'h7;
2048
    2'h2 : RxByteSel[3:0] = 4'h3;
2049
    2'h3 : RxByteSel[3:0] = 4'h1;
2050 96 mohor
  endcase
2051
end
2052
 
2053
 
2054
always @ (posedge WB_CLK_I or posedge Reset)
2055
begin
2056
  if(Reset)
2057 352 olof
    RxEn_needed <= 1'b0;
2058 354 olof
  else if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
2059 352 olof
    RxEn_needed <= 1'b1;
2060 354 olof
  else if(RxPointerRead & RxEn & RxEn_q)
2061 352 olof
    RxEn_needed <= 1'b0;
2062 38 mohor
end
2063
 
2064
 
2065 354 olof
// Reception status is written back to the buffer descriptor after the end
2066
// of frame is detected.
2067 40 mohor
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
2068 38 mohor
 
2069
 
2070
// Indicating that last byte is being reveived
2071 40 mohor
always @ (posedge MRxClk or posedge Reset)
2072 38 mohor
begin
2073 40 mohor
  if(Reset)
2074 352 olof
    LastByteIn <= 1'b0;
2075 38 mohor
  else
2076 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
2077 352 olof
    LastByteIn <= 1'b0;
2078 38 mohor
  else
2079 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
2080 352 olof
    LastByteIn <= 1'b1;
2081 38 mohor
end
2082
 
2083 354 olof
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) &
2084
                           RxEnableWindow;
2085 118 mohor
 
2086 38 mohor
// Indicating that data reception will end
2087 40 mohor
always @ (posedge MRxClk or posedge Reset)
2088 38 mohor
begin
2089 40 mohor
  if(Reset)
2090 352 olof
    ShiftWillEnd <= 1'b0;
2091 38 mohor
  else
2092 159 mohor
  if(ShiftEnded_rck | RxAbort)
2093 352 olof
    ShiftWillEnd <= 1'b0;
2094 38 mohor
  else
2095 40 mohor
  if(StartShiftWillEnd)
2096 352 olof
    ShiftWillEnd <= 1'b1;
2097 38 mohor
end
2098
 
2099
 
2100
// Receive byte counter
2101 40 mohor
always @ (posedge MRxClk or posedge Reset)
2102 38 mohor
begin
2103 40 mohor
  if(Reset)
2104 352 olof
    RxByteCnt <= 2'h0;
2105 38 mohor
  else
2106 159 mohor
  if(ShiftEnded_rck | RxAbort)
2107 352 olof
    RxByteCnt <= 2'h0;
2108 97 lampret
  else
2109 166 mohor
  if(RxValid & RxStartFrm & RxReady)
2110 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2111 352 olof
      2'h0 : RxByteCnt <= 2'h1;
2112
      2'h1 : RxByteCnt <= 2'h2;
2113
      2'h2 : RxByteCnt <= 2'h3;
2114
      2'h3 : RxByteCnt <= 2'h0;
2115 96 mohor
    endcase
2116 38 mohor
  else
2117 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
2118 352 olof
    RxByteCnt <= RxByteCnt + 1'b1;
2119 38 mohor
end
2120
 
2121
 
2122
// Indicates how many bytes are valid within the last word
2123 40 mohor
always @ (posedge MRxClk or posedge Reset)
2124 38 mohor
begin
2125 40 mohor
  if(Reset)
2126 352 olof
    RxValidBytes <= 2'h1;
2127 38 mohor
  else
2128 96 mohor
  if(RxValid & RxStartFrm)
2129 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2130 352 olof
      2'h0 : RxValidBytes <= 2'h1;
2131
      2'h1 : RxValidBytes <= 2'h2;
2132
      2'h2 : RxValidBytes <= 2'h3;
2133
      2'h3 : RxValidBytes <= 2'h0;
2134 96 mohor
    endcase
2135 38 mohor
  else
2136 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2137 352 olof
    RxValidBytes <= RxValidBytes + 1'b1;
2138 38 mohor
end
2139
 
2140
 
2141 40 mohor
always @ (posedge MRxClk or posedge Reset)
2142 38 mohor
begin
2143 40 mohor
  if(Reset)
2144 352 olof
    RxDataLatched1       <= 24'h0;
2145 38 mohor
  else
2146 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2147 96 mohor
    if(RxStartFrm)
2148 40 mohor
    begin
2149 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2150 354 olof
        // Big Endian Byte Ordering
2151
        2'h0:        RxDataLatched1[31:24] <= RxData;
2152 352 olof
        2'h1:        RxDataLatched1[23:16] <= RxData;
2153
        2'h2:        RxDataLatched1[15:8]  <= RxData;
2154
        2'h3:        RxDataLatched1        <= RxDataLatched1;
2155 96 mohor
      endcase
2156
    end
2157
    else if (RxEnableWindow)
2158
    begin
2159 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2160 354 olof
        // Big Endian Byte Ordering
2161
        2'h0:        RxDataLatched1[31:24] <= RxData;
2162 352 olof
        2'h1:        RxDataLatched1[23:16] <= RxData;
2163
        2'h2:        RxDataLatched1[15:8]  <= RxData;
2164
        2'h3:        RxDataLatched1        <= RxDataLatched1;
2165 40 mohor
      endcase
2166
    end
2167 38 mohor
end
2168
 
2169 40 mohor
// Assembling data that will be written to the rx_fifo
2170
always @ (posedge MRxClk or posedge Reset)
2171 38 mohor
begin
2172 40 mohor
  if(Reset)
2173 352 olof
    RxDataLatched2 <= 32'h0;
2174 38 mohor
  else
2175 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2176 354 olof
    // Big Endian Byte Ordering
2177
    RxDataLatched2 <= {RxDataLatched1[31:8], RxData};
2178 38 mohor
  else
2179 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2180 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2181 354 olof
      // Big Endian Byte Ordering
2182
 
2183 352 olof
      1 : RxDataLatched2 <= {RxDataLatched1[31:24], 24'h0};
2184
      2 : RxDataLatched2 <= {RxDataLatched1[31:16], 16'h0};
2185
      3 : RxDataLatched2 <= {RxDataLatched1[31:8],   8'h0};
2186 40 mohor
    endcase
2187 38 mohor
end
2188
 
2189
 
2190 40 mohor
// Indicating start of the reception process
2191 354 olof
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm &
2192
                              RxEnableWindow & (&RxByteCnt))
2193
                              |(RxValid & RxReady &  RxStartFrm &
2194
                              (&RxPointerLSB_rst))
2195
                              |(ShiftWillEnd & LastByteIn & (&RxByteCnt));
2196 38 mohor
 
2197 150 mohor
always @ (posedge MRxClk or posedge Reset)
2198
begin
2199
  if(Reset)
2200 352 olof
    WriteRxDataToFifo <= 1'b0;
2201 150 mohor
  else
2202
  if(SetWriteRxDataToFifo & ~RxAbort)
2203 352 olof
    WriteRxDataToFifo <= 1'b1;
2204 150 mohor
  else
2205
  if(WriteRxDataToFifoSync2 | RxAbort)
2206 352 olof
    WriteRxDataToFifo <= 1'b0;
2207 150 mohor
end
2208 40 mohor
 
2209 150 mohor
 
2210
always @ (posedge WB_CLK_I or posedge Reset)
2211
begin
2212
  if(Reset)
2213 352 olof
    WriteRxDataToFifoSync1 <= 1'b0;
2214 150 mohor
  else
2215
  if(WriteRxDataToFifo)
2216 352 olof
    WriteRxDataToFifoSync1 <= 1'b1;
2217 150 mohor
  else
2218 352 olof
    WriteRxDataToFifoSync1 <= 1'b0;
2219 150 mohor
end
2220
 
2221
always @ (posedge WB_CLK_I or posedge Reset)
2222
begin
2223
  if(Reset)
2224 352 olof
    WriteRxDataToFifoSync2 <= 1'b0;
2225 150 mohor
  else
2226 352 olof
    WriteRxDataToFifoSync2 <= WriteRxDataToFifoSync1;
2227 150 mohor
end
2228
 
2229
always @ (posedge WB_CLK_I or posedge Reset)
2230
begin
2231
  if(Reset)
2232 352 olof
    WriteRxDataToFifoSync3 <= 1'b0;
2233 150 mohor
  else
2234 352 olof
    WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2;
2235 150 mohor
end
2236
 
2237
 
2238 354 olof
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 &
2239
                              ~WriteRxDataToFifoSync3;
2240 150 mohor
 
2241 40 mohor
 
2242 90 mohor
always @ (posedge MRxClk or posedge Reset)
2243
begin
2244
  if(Reset)
2245 352 olof
    LatchedRxStartFrm <= 0;
2246 90 mohor
  else
2247 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2248 352 olof
    LatchedRxStartFrm <= 1;
2249 90 mohor
  else
2250 150 mohor
  if(SyncRxStartFrm_q)
2251 352 olof
    LatchedRxStartFrm <= 0;
2252 90 mohor
end
2253
 
2254
 
2255
always @ (posedge WB_CLK_I or posedge Reset)
2256
begin
2257
  if(Reset)
2258 352 olof
    SyncRxStartFrm <= 0;
2259 90 mohor
  else
2260
  if(LatchedRxStartFrm)
2261 352 olof
    SyncRxStartFrm <= 1;
2262 90 mohor
  else
2263 352 olof
    SyncRxStartFrm <= 0;
2264 90 mohor
end
2265
 
2266
 
2267
always @ (posedge WB_CLK_I or posedge Reset)
2268
begin
2269
  if(Reset)
2270 352 olof
    SyncRxStartFrm_q <= 0;
2271 90 mohor
  else
2272 352 olof
    SyncRxStartFrm_q <= SyncRxStartFrm;
2273 90 mohor
end
2274
 
2275 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2276
begin
2277
  if(Reset)
2278 352 olof
    SyncRxStartFrm_q2 <= 0;
2279 150 mohor
  else
2280 352 olof
    SyncRxStartFrm_q2 <= SyncRxStartFrm_q;
2281 150 mohor
end
2282 90 mohor
 
2283
 
2284 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2285 90 mohor
 
2286 354 olof
eth_fifo #(
2287
           .DATA_WIDTH(RX_FIFO_DATA_WIDTH),
2288
           .DEPTH(RX_FIFO_DEPTH),
2289
           .CNT_WIDTH(RX_FIFO_CNT_WIDTH))
2290
rx_fifo (
2291
         .clk            (WB_CLK_I),
2292
         .reset          (Reset),
2293
         // Inputs
2294
         .data_in        (RxDataLatched2),
2295
         .write          (WriteRxDataToFifo_wb & ~RxBufferFull),
2296
         .read           (MasterWbRX & m_wb_ack_i),
2297
         .clear          (RxFifoReset),
2298
         // Outputs
2299
         .data_out       (m_wb_dat_o),
2300
         .full           (RxBufferFull),
2301
         .almost_full    (),
2302
         .almost_empty   (RxBufferAlmostEmpty),
2303
         .empty          (RxBufferEmpty),
2304
         .cnt            (rxfifo_cnt)
2305 88 mohor
        );
2306 40 mohor
 
2307 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2308
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2309 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2310 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2311 40 mohor
 
2312
 
2313
// Generation of the end-of-frame signal
2314
always @ (posedge MRxClk or posedge Reset)
2315 38 mohor
begin
2316 40 mohor
  if(Reset)
2317 352 olof
    ShiftEnded_rck <= 1'b0;
2318 38 mohor
  else
2319 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2320 352 olof
    ShiftEnded_rck <= 1'b1;
2321 38 mohor
  else
2322 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2323 352 olof
    ShiftEnded_rck <= 1'b0;
2324 38 mohor
end
2325
 
2326 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2327
begin
2328
  if(Reset)
2329 352 olof
    ShiftEndedSync1 <= 1'b0;
2330 40 mohor
  else
2331 352 olof
    ShiftEndedSync1 <= ShiftEnded_rck;
2332 40 mohor
end
2333 38 mohor
 
2334 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2335 38 mohor
begin
2336 40 mohor
  if(Reset)
2337 352 olof
    ShiftEndedSync2 <= 1'b0;
2338 38 mohor
  else
2339 352 olof
    ShiftEndedSync2 <= ShiftEndedSync1;
2340 40 mohor
end
2341 38 mohor
 
2342 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2343
begin
2344
  if(Reset)
2345 352 olof
    ShiftEndedSync3 <= 1'b0;
2346 118 mohor
  else
2347
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2348 352 olof
    ShiftEndedSync3 <= 1'b1;
2349 118 mohor
  else
2350
  if(ShiftEnded)
2351 352 olof
    ShiftEndedSync3 <= 1'b0;
2352 118 mohor
end
2353 38 mohor
 
2354 40 mohor
// Generation of the end-of-frame signal
2355
always @ (posedge WB_CLK_I or posedge Reset)
2356 38 mohor
begin
2357 40 mohor
  if(Reset)
2358 352 olof
    ShiftEnded <= 1'b0;
2359 38 mohor
  else
2360 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2361 352 olof
    ShiftEnded <= 1'b1;
2362 38 mohor
  else
2363 40 mohor
  if(RxStatusWrite)
2364 352 olof
    ShiftEnded <= 1'b0;
2365 38 mohor
end
2366
 
2367 118 mohor
always @ (posedge MRxClk or posedge Reset)
2368
begin
2369
  if(Reset)
2370 352 olof
    ShiftEndedSync_c1 <= 1'b0;
2371 118 mohor
  else
2372 352 olof
    ShiftEndedSync_c1 <= ShiftEndedSync2;
2373 118 mohor
end
2374 38 mohor
 
2375 118 mohor
always @ (posedge MRxClk or posedge Reset)
2376
begin
2377
  if(Reset)
2378 352 olof
    ShiftEndedSync_c2 <= 1'b0;
2379 118 mohor
  else
2380 352 olof
    ShiftEndedSync_c2 <= ShiftEndedSync_c1;
2381 118 mohor
end
2382
 
2383 40 mohor
// Generation of the end-of-frame signal
2384
always @ (posedge MRxClk or posedge Reset)
2385 38 mohor
begin
2386 40 mohor
  if(Reset)
2387 352 olof
    RxEnableWindow <= 1'b0;
2388 354 olof
  else if(RxStartFrm)
2389 352 olof
    RxEnableWindow <= 1'b1;
2390 354 olof
  else if(RxEndFrm | RxAbort)
2391 352 olof
    RxEnableWindow <= 1'b0;
2392 38 mohor
end
2393
 
2394
 
2395 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2396 38 mohor
begin
2397 40 mohor
  if(Reset)
2398 352 olof
    RxAbortSync1 <= 1'b0;
2399 38 mohor
  else
2400 352 olof
    RxAbortSync1 <= RxAbortLatched;
2401 40 mohor
end
2402
 
2403
always @ (posedge WB_CLK_I or posedge Reset)
2404
begin
2405
  if(Reset)
2406 352 olof
    RxAbortSync2 <= 1'b0;
2407 38 mohor
  else
2408 352 olof
    RxAbortSync2 <= RxAbortSync1;
2409 38 mohor
end
2410
 
2411 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2412
begin
2413
  if(Reset)
2414 352 olof
    RxAbortSync3 <= 1'b0;
2415 150 mohor
  else
2416 352 olof
    RxAbortSync3 <= RxAbortSync2;
2417 150 mohor
end
2418
 
2419
always @ (posedge WB_CLK_I or posedge Reset)
2420
begin
2421
  if(Reset)
2422 352 olof
    RxAbortSync4 <= 1'b0;
2423 150 mohor
  else
2424 352 olof
    RxAbortSync4 <= RxAbortSync3;
2425 150 mohor
end
2426
 
2427 40 mohor
always @ (posedge MRxClk or posedge Reset)
2428
begin
2429
  if(Reset)
2430 352 olof
    RxAbortSyncb1 <= 1'b0;
2431 40 mohor
  else
2432 352 olof
    RxAbortSyncb1 <= RxAbortSync2;
2433 40 mohor
end
2434 38 mohor
 
2435 40 mohor
always @ (posedge MRxClk or posedge Reset)
2436 38 mohor
begin
2437 40 mohor
  if(Reset)
2438 352 olof
    RxAbortSyncb2 <= 1'b0;
2439 38 mohor
  else
2440 352 olof
    RxAbortSyncb2 <= RxAbortSyncb1;
2441 38 mohor
end
2442
 
2443
 
2444 64 mohor
always @ (posedge MRxClk or posedge Reset)
2445
begin
2446
  if(Reset)
2447 352 olof
    RxAbortLatched <= 1'b0;
2448 64 mohor
  else
2449 150 mohor
  if(RxAbortSyncb2)
2450 352 olof
    RxAbortLatched <= 1'b0;
2451 150 mohor
  else
2452 64 mohor
  if(RxAbort)
2453 352 olof
    RxAbortLatched <= 1'b1;
2454 64 mohor
end
2455 40 mohor
 
2456 64 mohor
 
2457 42 mohor
always @ (posedge MRxClk or posedge Reset)
2458
begin
2459
  if(Reset)
2460 352 olof
    LatchedRxLength[15:0] <= 16'h0;
2461 42 mohor
  else
2462 150 mohor
  if(LoadRxStatus)
2463 352 olof
    LatchedRxLength[15:0] <= RxLength[15:0];
2464 42 mohor
end
2465
 
2466
 
2467 354 olof
assign RxStatusIn = {ReceivedPauseFrm,
2468
                     AddressMiss,
2469
                     RxOverrun,
2470
                     InvalidSymbol,
2471
                     DribbleNibble,
2472
                     ReceivedPacketTooBig,
2473
                     ShortFrame,
2474
                     LatchedCrcError,
2475
                     RxLateCollision};
2476 42 mohor
 
2477
always @ (posedge MRxClk or posedge Reset)
2478
begin
2479
  if(Reset)
2480 352 olof
    RxStatusInLatched <= 'h0;
2481 42 mohor
  else
2482 150 mohor
  if(LoadRxStatus)
2483 352 olof
    RxStatusInLatched <= RxStatusIn;
2484 42 mohor
end
2485
 
2486
 
2487 60 mohor
// Rx overrun
2488
always @ (posedge WB_CLK_I or posedge Reset)
2489
begin
2490
  if(Reset)
2491 352 olof
    RxOverrun <= 1'b0;
2492 354 olof
  else if(RxStatusWrite)
2493 352 olof
    RxOverrun <= 1'b0;
2494 354 olof
  else if(RxBufferFull & WriteRxDataToFifo_wb)
2495 352 olof
    RxOverrun <= 1'b1;
2496 60 mohor
end
2497 48 mohor
 
2498 77 mohor
 
2499
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2500
 
2501
 
2502 239 tadejm
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
2503 250 mohor
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
2504 354 olof
// AddressMiss is identifying that a frame was received because of the
2505
// promiscous mode and is not an error
2506 239 tadejm
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
2507
 
2508 272 tadejm
 
2509 354 olof
// Latching and synchronizing RxStatusWrite signal. This signal is used for
2510
// clearing the ReceivedPauseFrm signal
2511 272 tadejm
always @ (posedge WB_CLK_I or posedge Reset)
2512
begin
2513
  if(Reset)
2514 352 olof
    RxStatusWriteLatched <= 1'b0;
2515 272 tadejm
  else
2516
  if(RxStatusWriteLatched_syncb2)
2517 352 olof
    RxStatusWriteLatched <= 1'b0;
2518 272 tadejm
  else
2519
  if(RxStatusWrite)
2520 352 olof
    RxStatusWriteLatched <= 1'b1;
2521 272 tadejm
end
2522
 
2523
 
2524
always @ (posedge MRxClk or posedge Reset)
2525
begin
2526
  if(Reset)
2527
    begin
2528 352 olof
      RxStatusWriteLatched_sync1 <= 1'b0;
2529
      RxStatusWriteLatched_sync2 <= 1'b0;
2530 272 tadejm
    end
2531
  else
2532
    begin
2533 352 olof
      RxStatusWriteLatched_sync1 <= RxStatusWriteLatched;
2534
      RxStatusWriteLatched_sync2 <= RxStatusWriteLatched_sync1;
2535 272 tadejm
    end
2536
end
2537
 
2538
 
2539
always @ (posedge WB_CLK_I or posedge Reset)
2540
begin
2541
  if(Reset)
2542
    begin
2543 352 olof
      RxStatusWriteLatched_syncb1 <= 1'b0;
2544
      RxStatusWriteLatched_syncb2 <= 1'b0;
2545 272 tadejm
    end
2546
  else
2547
    begin
2548 352 olof
      RxStatusWriteLatched_syncb1 <= RxStatusWriteLatched_sync2;
2549
      RxStatusWriteLatched_syncb2 <= RxStatusWriteLatched_syncb1;
2550 272 tadejm
    end
2551
end
2552
 
2553
 
2554 77 mohor
// Tx Done Interrupt
2555
always @ (posedge WB_CLK_I or posedge Reset)
2556
begin
2557