OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac.v] - Blame information for rev 367

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3 364 olof
////  ethmac.v                                                    ////
4 15 mohor
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 202 mohor
////  All additional information is available in the Readme.txt   ////
12 15 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 202 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41 364 olof
// 2011-08-09 olof@opencores.org
42
// Renamed from eth_top.v to ethmac.v to better fit into the OpenCores
43
// Structure
44
//
45 15 mohor
// CVS Revision History
46
//
47
// $Log: not supported by cvs2svn $
48 333 igorm
// Revision 1.51  2005/02/21 11:13:17  igorm
49
// Defer indication fixed.
50
//
51 327 igorm
// Revision 1.50  2004/04/26 15:26:23  igorm
52
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
53
//   previous update of the core.
54
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
55
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
56
//   register. (thanks to Mathias and Torbjorn)
57
// - Multicast reception was fixed. Thanks to Ulrich Gries
58
//
59 321 igorm
// Revision 1.49  2003/11/12 18:24:59  tadejm
60
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
61
//
62 304 tadejm
// Revision 1.48  2003/10/17 07:46:16  markom
63
// mbist signals updated according to newest convention
64
//
65 302 markom
// Revision 1.47  2003/10/06 15:43:45  knguyen
66
// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
67
//
68 301 knguyen
// Revision 1.46  2003/01/30 13:30:22  tadejm
69
// Defer indication changed.
70
//
71 276 tadejm
// Revision 1.45  2003/01/22 13:49:26  tadejm
72
// When control packets were received, they were ignored in some cases.
73
//
74 272 tadejm
// Revision 1.44  2003/01/21 12:09:40  mohor
75
// When receiving normal data frame and RxFlow control was switched on, RXB
76
// interrupt was not set.
77
//
78 270 mohor
// Revision 1.43  2002/11/22 01:57:06  mohor
79
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
80
// synchronized.
81
//
82 261 mohor
// Revision 1.42  2002/11/21 00:09:19  mohor
83
// TPauseRq synchronized to tx_clk.
84
//
85 255 mohor
// Revision 1.41  2002/11/19 18:13:49  mohor
86
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
87
//
88 253 mohor
// Revision 1.40  2002/11/19 17:34:25  mohor
89
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
90
// that a frame was received because of the promiscous mode.
91
//
92 250 mohor
// Revision 1.39  2002/11/18 17:31:55  mohor
93
// wb_rst_i is used for MIIM reset.
94
//
95 248 mohor
// Revision 1.38  2002/11/14 18:37:20  mohor
96
// r_Rst signal does not reset any module any more and is removed from the design.
97
//
98 244 mohor
// Revision 1.37  2002/11/13 22:25:36  tadejm
99
// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
100
//
101 240 tadejm
// Revision 1.36  2002/10/18 17:04:20  tadejm
102
// Changed BIST scan signals.
103
//
104 227 tadejm
// Revision 1.35  2002/10/11 13:36:58  mohor
105
// Typo error fixed. (When using Bist)
106
//
107 218 mohor
// Revision 1.34  2002/10/10 16:49:50  mohor
108
// Signals for WISHBONE B3 compliant interface added.
109
//
110 214 mohor
// Revision 1.33  2002/10/10 16:29:30  mohor
111
// BIST added.
112
//
113 210 mohor
// Revision 1.32  2002/09/20 17:12:58  mohor
114
// CsMiss added. When address between 0x800 and 0xfff is accessed within
115
// Ethernet Core, error acknowledge is generated.
116
//
117 202 mohor
// Revision 1.31  2002/09/12 14:50:17  mohor
118
// CarrierSenseLost bug fixed when operating in full duplex mode.
119
//
120 168 mohor
// Revision 1.30  2002/09/10 10:35:23  mohor
121
// Ethernet debug registers removed.
122
//
123 164 mohor
// Revision 1.29  2002/09/09 13:03:13  mohor
124
// Error acknowledge is generated when accessing BDs and RST bit in the
125
// MODER register (r_Rst) is set.
126
//
127 161 mohor
// Revision 1.28  2002/09/04 18:44:10  mohor
128
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
129
// connected.
130
//
131 149 mohor
// Revision 1.27  2002/07/25 18:15:37  mohor
132
// RxAbort changed. Packets received with MRxErr (from PHY) are also
133
// aborted.
134
//
135 125 mohor
// Revision 1.26  2002/07/17 18:51:50  mohor
136
// EXTERNAL_DMA removed. External DMA not supported.
137
//
138 114 mohor
// Revision 1.25  2002/05/03 10:15:50  mohor
139
// Outputs registered. Reset changed for eth_wishbone module.
140
//
141 106 mohor
// Revision 1.24  2002/04/22 14:15:42  mohor
142
// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
143
// selected in eth_defines.v
144
//
145 103 mohor
// Revision 1.23  2002/03/25 13:33:53  mohor
146
// md_padoen_o changed to md_padoe_o. Signal was always active high, just
147
// name was incorrect.
148
//
149 95 mohor
// Revision 1.22  2002/02/26 16:59:54  mohor
150
// Small fixes for external/internal DMA missmatches.
151
//
152 80 mohor
// Revision 1.21  2002/02/26 16:21:00  mohor
153
// Interrupts changed in the top file
154
//
155 76 mohor
// Revision 1.20  2002/02/18 10:40:17  mohor
156
// Small fixes.
157
//
158 70 mohor
// Revision 1.19  2002/02/16 14:03:44  mohor
159
// Registered trimmed. Unused registers removed.
160
//
161 68 mohor
// Revision 1.18  2002/02/16 13:06:33  mohor
162
// EXTERNAL_DMA used instead of WISHBONE_DMA.
163
//
164 67 mohor
// Revision 1.17  2002/02/16 07:15:27  mohor
165
// Testbench fixed, code simplified, unused signals removed.
166
//
167 65 mohor
// Revision 1.16  2002/02/15 13:49:39  mohor
168
// RxAbort is connected differently.
169
//
170 63 mohor
// Revision 1.15  2002/02/15 11:38:26  mohor
171
// Changes that were lost when updating from 1.11 to 1.14 fixed.
172
//
173 59 mohor
// Revision 1.14  2002/02/14 20:19:11  billditt
174
// Modified for Address Checking,
175
// addition of eth_addrcheck.v
176
//
177
// Revision 1.13  2002/02/12 17:03:03  mohor
178
// HASH0 and HASH1 registers added. Registers address width was
179
// changed to 8 bits.
180
//
181
// Revision 1.12  2002/02/11 09:18:22  mohor
182
// Tx status is written back to the BD.
183
//
184 43 mohor
// Revision 1.11  2002/02/08 16:21:54  mohor
185
// Rx status is written back to the BD.
186
//
187 42 mohor
// Revision 1.10  2002/02/06 14:10:21  mohor
188
// non-DMA host interface added. Select the right configutation in eth_defines.
189
//
190 41 mohor
// Revision 1.9  2002/01/23 10:28:16  mohor
191
// Link in the header changed.
192
//
193 37 mohor
// Revision 1.8  2001/12/05 15:00:16  mohor
194
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
195
// instead of the number of RX descriptors).
196
//
197 34 mohor
// Revision 1.7  2001/12/05 10:45:59  mohor
198
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
199
//
200 33 mohor
// Revision 1.6  2001/10/19 11:24:29  mohor
201
// Number of addresses (wb_adr_i) minimized.
202
//
203 23 mohor
// Revision 1.5  2001/10/19 08:43:51  mohor
204
// eth_timescale.v changed to timescale.v This is done because of the
205
// simulation of the few cores in a one joined project.
206
//
207 22 mohor
// Revision 1.4  2001/10/18 12:07:11  mohor
208
// Status signals changed, Adress decoding changed, interrupt controller
209
// added.
210
//
211 21 mohor
// Revision 1.3  2001/09/24 15:02:56  mohor
212
// Defines changed (All precede with ETH_). Small changes because some
213
// tools generate warnings when two operands are together. Synchronization
214
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
215
// demands).
216
//
217 20 mohor
// Revision 1.2  2001/08/15 14:03:59  mohor
218
// Signal names changed on the top level for easier pad insertion (ASIC).
219
//
220 17 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
221
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
222
// Include files fixed to contain no path.
223
// File names and module names changed ta have a eth_ prologue in the name.
224
// File eth_timescale.v is used to define timescale
225
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
226
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
227
// and Mdo_OE. The bidirectional signal must be created on the top level. This
228
// is done due to the ASIC tools.
229
//
230 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
231
// Unconnected signals are now connected.
232
//
233
// Revision 1.1  2001/07/30 21:23:42  mohor
234
// Directory structure changed. Files checked and joind together.
235
//
236
//
237
//
238 20 mohor
// 
239 15 mohor
 
240
 
241 356 olof
`include "ethmac_defines.v"
242 22 mohor
`include "timescale.v"
243 15 mohor
 
244
 
245 364 olof
module ethmac
246 15 mohor
(
247
  // WISHBONE common
248 17 mohor
  wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
249 15 mohor
 
250
  // WISHBONE slave
251 17 mohor
  wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
252 15 mohor
 
253 41 mohor
  // WISHBONE master
254
  m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
255
  m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
256
  m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
257
 
258 214 mohor
  m_wb_cti_o, m_wb_bte_o,
259
 
260 15 mohor
  //TX
261 20 mohor
  mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
262 15 mohor
 
263
  //RX
264 365 olof
  mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
265 15 mohor
 
266
  // MIIM
267 95 mohor
  mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
268 17 mohor
 
269 21 mohor
  int_o
270 17 mohor
 
271 210 mohor
  // Bist
272
`ifdef ETH_BIST
273 227 tadejm
  ,
274
  // debug chain signals
275 302 markom
  mbist_si_i,       // bist scan serial in
276
  mbist_so_o,       // bist scan serial out
277
  mbist_ctrl_i        // bist chain shift control
278 210 mohor
`endif
279 21 mohor
 
280 15 mohor
);
281
 
282
 
283 349 olof
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
284
parameter TX_FIFO_DEPTH      = `ETH_TX_FIFO_DEPTH;
285
parameter TX_FIFO_CNT_WIDTH  = `ETH_TX_FIFO_CNT_WIDTH;
286
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
287
parameter RX_FIFO_DEPTH      = `ETH_RX_FIFO_DEPTH;
288
parameter RX_FIFO_CNT_WIDTH  = `ETH_RX_FIFO_CNT_WIDTH;
289 15 mohor
 
290
 
291
// WISHBONE common
292 17 mohor
input           wb_clk_i;     // WISHBONE clock
293
input           wb_rst_i;     // WISHBONE reset
294
input   [31:0]  wb_dat_i;     // WISHBONE data input
295
output  [31:0]  wb_dat_o;     // WISHBONE data output
296
output          wb_err_o;     // WISHBONE error output
297 15 mohor
 
298
// WISHBONE slave
299 23 mohor
input   [11:2]  wb_adr_i;     // WISHBONE address input
300 17 mohor
input    [3:0]  wb_sel_i;     // WISHBONE byte select input
301
input           wb_we_i;      // WISHBONE write enable input
302
input           wb_cyc_i;     // WISHBONE cycle input
303
input           wb_stb_i;     // WISHBONE strobe input
304
output          wb_ack_o;     // WISHBONE acknowledge output
305 15 mohor
 
306 41 mohor
// WISHBONE master
307
output  [31:0]  m_wb_adr_o;
308
output   [3:0]  m_wb_sel_o;
309
output          m_wb_we_o;
310
input   [31:0]  m_wb_dat_i;
311
output  [31:0]  m_wb_dat_o;
312
output          m_wb_cyc_o;
313
output          m_wb_stb_o;
314
input           m_wb_ack_i;
315
input           m_wb_err_i;
316 15 mohor
 
317 327 igorm
wire    [29:0]  m_wb_adr_tmp;
318
 
319 214 mohor
output   [2:0]  m_wb_cti_o;   // Cycle Type Identifier
320
output   [1:0]  m_wb_bte_o;   // Burst Type Extension
321 41 mohor
 
322 15 mohor
// Tx
323 20 mohor
input           mtx_clk_pad_i; // Transmit clock (from PHY)
324 21 mohor
output   [3:0]  mtxd_pad_o;    // Transmit nibble (to PHY)
325
output          mtxen_pad_o;   // Transmit enable (to PHY)
326
output          mtxerr_pad_o;  // Transmit error (to PHY)
327 15 mohor
 
328
// Rx
329 20 mohor
input           mrx_clk_pad_i; // Receive clock (from PHY)
330 21 mohor
input    [3:0]  mrxd_pad_i;    // Receive nibble (from PHY)
331
input           mrxdv_pad_i;   // Receive data valid (from PHY)
332
input           mrxerr_pad_i;  // Receive data error (from PHY)
333 15 mohor
 
334
// Common Tx and Rx
335 21 mohor
input           mcoll_pad_i;   // Collision (from PHY)
336
input           mcrs_pad_i;    // Carrier sense (from PHY)
337 15 mohor
 
338
// MII Management interface
339 21 mohor
input           md_pad_i;      // MII data input (from I/O cell)
340
output          mdc_pad_o;     // MII Management data clock (to PHY)
341
output          md_pad_o;      // MII data output (to I/O cell)
342 95 mohor
output          md_padoe_o;    // MII data output enable (to I/O cell)
343 15 mohor
 
344 21 mohor
output          int_o;         // Interrupt output
345 15 mohor
 
346 210 mohor
// Bist
347
`ifdef ETH_BIST
348 302 markom
input   mbist_si_i;       // bist scan serial in
349
output  mbist_so_o;       // bist scan serial out
350
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
351 210 mohor
`endif
352
 
353 360 olof
wire    [31:0]  wb_dbg_dat0;
354
 
355 15 mohor
wire     [7:0]  r_ClkDiv;
356
wire            r_MiiNoPre;
357
wire    [15:0]  r_CtrlData;
358
wire     [4:0]  r_FIAD;
359
wire     [4:0]  r_RGAD;
360
wire            r_WCtrlData;
361
wire            r_RStat;
362
wire            r_ScanStat;
363
wire            NValid_stat;
364
wire            Busy_stat;
365
wire            LinkFail;
366
wire    [15:0]  Prsd;             // Read Status Data (data read from the PHY)
367
wire            WCtrlDataStart;
368
wire            RStatStart;
369
wire            UpdateMIIRX_DATAReg;
370
 
371
wire            TxStartFrm;
372
wire            TxEndFrm;
373
wire            TxUsedData;
374
wire     [7:0]  TxData;
375
wire            TxRetry;
376
wire            TxAbort;
377
wire            TxUnderRun;
378
wire            TxDone;
379
 
380
 
381 149 mohor
reg             WillSendControlFrame_sync1;
382
reg             WillSendControlFrame_sync2;
383
reg             WillSendControlFrame_sync3;
384
reg             RstTxPauseRq;
385 15 mohor
 
386 255 mohor
reg             TxPauseRq_sync1;
387
reg             TxPauseRq_sync2;
388
reg             TxPauseRq_sync3;
389
reg             TPauseRq;
390 15 mohor
 
391 255 mohor
 
392 15 mohor
// Connecting Miim module
393 352 olof
eth_miim miim1
394 15 mohor
(
395 365 olof
  .Clk(wb_clk_i),
396
  .Reset(wb_rst_i),
397
  .Divider(r_ClkDiv),
398
  .NoPre(r_MiiNoPre),
399
  .CtrlData(r_CtrlData),
400
  .Rgad(r_RGAD),
401
  .Fiad(r_FIAD),
402
  .WCtrlData(r_WCtrlData),
403
  .RStat(r_RStat),
404
  .ScanStat(r_ScanStat),
405
  .Mdi(md_pad_i),
406
  .Mdo(md_pad_o),
407
  .MdoEn(md_padoe_o),
408
  .Mdc(mdc_pad_o),
409
  .Busy(Busy_stat),
410
  .Prsd(Prsd),
411
  .LinkFail(LinkFail),
412
  .Nvalid(NValid_stat),
413
  .WCtrlDataStart(WCtrlDataStart),
414
  .RStatStart(RStatStart),
415
  .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
416 15 mohor
);
417
 
418
 
419
 
420
 
421 304 tadejm
wire  [3:0] RegCs;          // Connected to registers
422 17 mohor
wire [31:0] RegDataOut;     // Multiplexed to wb_dat_o
423 42 mohor
wire        r_RecSmall;     // Receive small frames
424 15 mohor
wire        r_LoopBck;      // Loopback
425
wire        r_TxEn;         // Tx Enable
426
wire        r_RxEn;         // Rx Enable
427
 
428
wire        MRxDV_Lb;       // Muxed MII receive data valid
429
wire        MRxErr_Lb;      // Muxed MII Receive Error
430
wire  [3:0] MRxD_Lb;        // Muxed MII Receive Data
431
wire        Transmitting;   // Indication that TxEthMAC is transmitting
432
wire        r_HugEn;        // Huge packet enable
433
wire        r_DlyCrcEn;     // Delayed CRC enabled
434
wire [15:0] r_MaxFL;        // Maximum frame length
435
 
436
wire [15:0] r_MinFL;        // Minimum frame length
437 42 mohor
wire        ShortFrame;
438
wire        DribbleNibble;  // Extra nibble received
439
wire        ReceivedPacketTooBig; // Received packet is too big
440 15 mohor
wire [47:0] r_MAC;          // MAC address
441 42 mohor
wire        LoadRxStatus;   // Rx status was loaded
442 52 billditt
wire [31:0] r_HASH0;        // HASH table, lower 4 bytes
443
wire [31:0] r_HASH1;        // HASH table, upper 4 bytes
444 34 mohor
wire  [7:0] r_TxBDNum;      // Receive buffer descriptor number
445 15 mohor
wire  [6:0] r_IPGT;         // 
446
wire  [6:0] r_IPGR1;        // 
447
wire  [6:0] r_IPGR2;        // 
448
wire  [5:0] r_CollValid;    // 
449 149 mohor
wire [15:0] r_TxPauseTV;    // Transmit PAUSE value
450
wire        r_TxPauseRq;    // Transmit PAUSE request
451 15 mohor
 
452
wire  [3:0] r_MaxRet;       //
453
wire        r_NoBckof;      // 
454
wire        r_ExDfrEn;      // 
455
wire        r_TxFlow;       // Tx flow control enable
456
wire        r_IFG;          // Minimum interframe gap for incoming packets
457
 
458 21 mohor
wire        TxB_IRQ;        // Interrupt Tx Buffer
459
wire        TxE_IRQ;        // Interrupt Tx Error
460
wire        RxB_IRQ;        // Interrupt Rx Buffer
461 76 mohor
wire        RxE_IRQ;        // Interrupt Rx Error
462 21 mohor
wire        Busy_IRQ;       // Interrupt Busy (lack of buffers)
463 15 mohor
 
464 304 tadejm
//wire        DWord;
465
wire        ByteSelected;
466 15 mohor
wire        BDAck;
467 365 olof
wire [31:0] BD_WB_DAT_O;    // wb_dat_o that comes from the Wishbone module
468
                            //(for buffer descriptors read/write)
469 304 tadejm
wire  [3:0] BDCs;           // Buffer descriptor CS
470 365 olof
wire        CsMiss;         // When access to the address between 0x800
471
                            // and 0xfff occurs, acknowledge is set
472 202 mohor
                            // but data is not valid.
473 327 igorm
wire        r_Pad;
474
wire        r_CrcEn;
475
wire        r_FullD;
476
wire        r_Pro;
477
wire        r_Bro;
478
wire        r_NoPre;
479
wire        r_RxFlow;
480
wire        r_PassAll;
481
wire        TxCtrlEndFrm;
482
wire        StartTxDone;
483
wire        SetPauseTimer;
484
wire        TxUsedDataIn;
485
wire        TxDoneIn;
486
wire        TxAbortIn;
487
wire        PerPacketPad;
488
wire        PadOut;
489
wire        PerPacketCrcEn;
490
wire        CrcEnOut;
491
wire        TxStartFrmOut;
492
wire        TxEndFrmOut;
493
wire        ReceivedPauseFrm;
494
wire        ControlFrmAddressOK;
495
wire        RxStatusWriteLatched_sync2;
496
wire        LateCollision;
497
wire        DeferIndication;
498
wire        LateCollLatched;
499
wire        DeferLatched;
500
wire        RstDeferLatched;
501
wire        CarrierSenseLost;
502 15 mohor
 
503 103 mohor
wire        temp_wb_ack_o;
504
wire [31:0] temp_wb_dat_o;
505
wire        temp_wb_err_o;
506 15 mohor
 
507 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
508
  reg         temp_wb_ack_o_reg;
509
  reg [31:0]  temp_wb_dat_o_reg;
510
  reg         temp_wb_err_o_reg;
511
`endif
512
 
513 304 tadejm
//assign DWord = &wb_sel_i;
514
assign ByteSelected = |wb_sel_i;
515
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3];   // 0x0   - 0x3FF
516
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2];   // 0x0   - 0x3FF
517
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1];   // 0x0   - 0x3FF
518
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0];   // 0x0   - 0x3FF
519
assign BDCs[3]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[3];   // 0x400 - 0x7FF
520
assign BDCs[2]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[2];   // 0x400 - 0x7FF
521
assign BDCs[1]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[1];   // 0x400 - 0x7FF
522
assign BDCs[0]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[0];   // 0x400 - 0x7FF
523
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11];                   // 0x800 - 0xfFF
524
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
525
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
526 15 mohor
 
527 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
528
  assign wb_ack_o = temp_wb_ack_o_reg;
529
  assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
530
  assign wb_err_o = temp_wb_err_o_reg;
531
`else
532
  assign wb_ack_o = temp_wb_ack_o;
533
  assign wb_dat_o[31:0] = temp_wb_dat_o;
534
  assign wb_err_o = temp_wb_err_o;
535
`endif
536 15 mohor
 
537 327 igorm
`ifdef ETH_AVALON_BUS
538
  // As Avalon has no corresponding "error" signal, I (erroneously) will
539
  // send an ack to Avalon, even when accessing undefined memory. This
540
  // is a grey area in Avalon vs. Wishbone specs: My understanding
541
  // is that Avalon expects all memory addressable by the addr bus feeding
542
  // a slave to be, at the very minimum, readable.
543
  assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
544
`else // WISHBONE
545
  assign temp_wb_ack_o = (|RegCs) | BDAck;
546
`endif
547 15 mohor
 
548 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
549
  always @ (posedge wb_clk_i or posedge wb_rst_i)
550
  begin
551
    if(wb_rst_i)
552
      begin
553 352 olof
        temp_wb_ack_o_reg <= 1'b0;
554
        temp_wb_dat_o_reg <= 32'h0;
555
        temp_wb_err_o_reg <= 1'b0;
556 103 mohor
      end
557
    else
558
      begin
559 352 olof
        temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg;
560
        temp_wb_dat_o_reg <= temp_wb_dat_o;
561
        temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg;
562 103 mohor
      end
563
  end
564
`endif
565
 
566
 
567 15 mohor
// Connecting Ethernet registers
568 352 olof
eth_registers ethreg1
569 15 mohor
(
570 365 olof
  .DataIn(wb_dat_i),
571
  .Address(wb_adr_i[9:2]),
572
  .Rw(wb_we_i),
573
  .Cs(RegCs),
574
  .Clk(wb_clk_i),
575
  .Reset(wb_rst_i),
576
  .DataOut(RegDataOut),
577
  .r_RecSmall(r_RecSmall),
578
  .r_Pad(r_Pad),
579
  .r_HugEn(r_HugEn),
580
  .r_CrcEn(r_CrcEn),
581
  .r_DlyCrcEn(r_DlyCrcEn),
582
  .r_FullD(r_FullD),
583
  .r_ExDfrEn(r_ExDfrEn),
584
  .r_NoBckof(r_NoBckof),
585
  .r_LoopBck(r_LoopBck),
586
  .r_IFG(r_IFG),
587
  .r_Pro(r_Pro),
588
  .r_Iam(),
589
  .r_Bro(r_Bro),
590
  .r_NoPre(r_NoPre),
591
  .r_TxEn(r_TxEn),
592
  .r_RxEn(r_RxEn),
593
  .Busy_IRQ(Busy_IRQ),
594
  .RxE_IRQ(RxE_IRQ),
595
  .RxB_IRQ(RxB_IRQ),
596
  .TxE_IRQ(TxE_IRQ),
597
  .TxB_IRQ(TxB_IRQ),
598
  .r_IPGT(r_IPGT),
599
  .r_IPGR1(r_IPGR1),
600
  .r_IPGR2(r_IPGR2),
601
  .r_MinFL(r_MinFL),
602
  .r_MaxFL(r_MaxFL),
603
  .r_MaxRet(r_MaxRet),
604
  .r_CollValid(r_CollValid),
605
  .r_TxFlow(r_TxFlow),
606
  .r_RxFlow(r_RxFlow),
607
  .r_PassAll(r_PassAll),
608
  .r_MiiNoPre(r_MiiNoPre),
609
  .r_ClkDiv(r_ClkDiv),
610
  .r_WCtrlData(r_WCtrlData),
611
  .r_RStat(r_RStat),
612
  .r_ScanStat(r_ScanStat),
613
  .r_RGAD(r_RGAD),
614
  .r_FIAD(r_FIAD),
615
  .r_CtrlData(r_CtrlData),
616
  .NValid_stat(NValid_stat),
617
  .Busy_stat(Busy_stat),
618
  .LinkFail(LinkFail),
619
  .r_MAC(r_MAC),
620
  .WCtrlDataStart(WCtrlDataStart),
621
  .RStatStart(RStatStart),
622
  .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),
623
  .Prsd(Prsd),
624
  .r_TxBDNum(r_TxBDNum),
625
  .int_o(int_o),
626
  .r_HASH0(r_HASH0),
627
  .r_HASH1(r_HASH1),
628
  .r_TxPauseRq(r_TxPauseRq),
629
  .r_TxPauseTV(r_TxPauseTV),
630
  .RstTxPauseRq(RstTxPauseRq),
631
  .TxCtrlEndFrm(TxCtrlEndFrm),
632
  .StartTxDone(StartTxDone),
633
  .TxClk(mtx_clk_pad_i),
634
  .RxClk(mrx_clk_pad_i),
635 360 olof
  .dbg_dat(wb_dbg_dat0),
636 261 mohor
  .SetPauseTimer(SetPauseTimer)
637 149 mohor
 
638 15 mohor
);
639
 
640
 
641
 
642
wire  [7:0] RxData;
643
wire        RxValid;
644
wire        RxStartFrm;
645
wire        RxEndFrm;
646 41 mohor
wire        RxAbort;
647 15 mohor
 
648
wire        WillTransmit;            // Will transmit (to RxEthMAC)
649 365 olof
wire        ResetCollision;          // Reset Collision (for synchronizing 
650
                                     // collision)
651 15 mohor
wire  [7:0] TxDataOut;               // Transmit Packet Data (to TxEthMAC)
652
wire        WillSendControlFrame;
653
wire        ReceiveEnd;
654
wire        ReceivedPacketGood;
655
wire        ReceivedLengthOK;
656 42 mohor
wire        InvalidSymbol;
657
wire        LatchedCrcError;
658
wire        RxLateCollision;
659 59 mohor
wire  [3:0] RetryCntLatched;
660
wire  [3:0] RetryCnt;
661
wire        StartTxAbort;
662
wire        MaxCollisionOccured;
663
wire        RetryLimit;
664
wire        StatePreamble;
665
wire  [1:0] StateData;
666 15 mohor
 
667
// Connecting MACControl
668 352 olof
eth_maccontrol maccontrol1
669 15 mohor
(
670 365 olof
  .MTxClk(mtx_clk_pad_i),
671
  .TPauseRq(TPauseRq),
672
  .TxPauseTV(r_TxPauseTV),
673
  .TxDataIn(TxData),
674
  .TxStartFrmIn(TxStartFrm),
675
  .TxEndFrmIn(TxEndFrm),
676
  .TxUsedDataIn(TxUsedDataIn),
677
  .TxDoneIn(TxDoneIn),
678
  .TxAbortIn(TxAbortIn),
679
  .MRxClk(mrx_clk_pad_i),
680
  .RxData(RxData),
681
  .RxValid(RxValid),
682
  .RxStartFrm(RxStartFrm),
683
  .RxEndFrm(RxEndFrm),
684
  .ReceiveEnd(ReceiveEnd),
685
  .ReceivedPacketGood(ReceivedPacketGood),
686
  .TxFlow(r_TxFlow),
687
  .RxFlow(r_RxFlow),
688
  .DlyCrcEn(r_DlyCrcEn),
689
  .MAC(r_MAC),
690
  .PadIn(r_Pad | PerPacketPad),
691
  .PadOut(PadOut),
692
  .CrcEnIn(r_CrcEn | PerPacketCrcEn),
693
  .CrcEnOut(CrcEnOut),
694
  .TxReset(wb_rst_i),
695
  .RxReset(wb_rst_i),
696
  .ReceivedLengthOK(ReceivedLengthOK),
697
  .TxDataOut(TxDataOut),
698
  .TxStartFrmOut(TxStartFrmOut),
699
  .TxEndFrmOut(TxEndFrmOut),
700
  .TxUsedDataOut(TxUsedData),
701
  .TxDoneOut(TxDone),
702
  .TxAbortOut(TxAbort),
703
  .WillSendControlFrame(WillSendControlFrame),
704
  .TxCtrlEndFrm(TxCtrlEndFrm),
705
  .ReceivedPauseFrm(ReceivedPauseFrm),
706
  .ControlFrmAddressOK(ControlFrmAddressOK),
707 272 tadejm
  .SetPauseTimer(SetPauseTimer),
708 365 olof
  .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
709
  .r_PassAll(r_PassAll)
710 15 mohor
);
711
 
712
 
713
 
714
wire TxCarrierSense;          // Synchronized CarrierSense (to Tx clock)
715
wire Collision;               // Synchronized Collision
716
 
717
reg CarrierSense_Tx1;
718
reg CarrierSense_Tx2;
719
reg Collision_Tx1;
720
reg Collision_Tx2;
721
 
722
reg RxEnSync;                 // Synchronized Receive Enable
723
reg WillTransmit_q;
724
reg WillTransmit_q2;
725
 
726
 
727
 
728
// Muxed MII receive data valid
729 17 mohor
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
730 15 mohor
 
731
// Muxed MII Receive Error
732 17 mohor
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
733 15 mohor
 
734
// Muxed MII Receive Data
735 17 mohor
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
736 15 mohor
 
737
 
738
 
739
// Connecting TxEthMAC
740 352 olof
eth_txethmac txethmac1
741 15 mohor
(
742 365 olof
  .MTxClk(mtx_clk_pad_i),
743
  .Reset(wb_rst_i),
744
  .CarrierSense(TxCarrierSense),
745
  .Collision(Collision),
746
  .TxData(TxDataOut),
747
  .TxStartFrm(TxStartFrmOut),
748
  .TxUnderRun(TxUnderRun),
749
  .TxEndFrm(TxEndFrmOut),
750
  .Pad(PadOut),
751
  .MinFL(r_MinFL),
752
  .CrcEn(CrcEnOut),
753
  .FullD(r_FullD),
754
  .HugEn(r_HugEn),
755
  .DlyCrcEn(r_DlyCrcEn),
756
  .IPGT(r_IPGT),
757
  .IPGR1(r_IPGR1),
758
  .IPGR2(r_IPGR2),
759
  .CollValid(r_CollValid),
760
  .MaxRet(r_MaxRet),
761
  .NoBckof(r_NoBckof),
762
  .ExDfrEn(r_ExDfrEn),
763
  .MaxFL(r_MaxFL),
764
  .MTxEn(mtxen_pad_o),
765
  .MTxD(mtxd_pad_o),
766
  .MTxErr(mtxerr_pad_o),
767
  .TxUsedData(TxUsedDataIn),
768
  .TxDone(TxDoneIn),
769
  .TxRetry(TxRetry),
770
  .TxAbort(TxAbortIn),
771
  .WillTransmit(WillTransmit),
772
  .ResetCollision(ResetCollision),
773
  .RetryCnt(RetryCnt),
774
  .StartTxDone(StartTxDone),
775
  .StartTxAbort(StartTxAbort),
776
  .MaxCollisionOccured(MaxCollisionOccured),
777
  .LateCollision(LateCollision),
778
  .DeferIndication(DeferIndication),
779
  .StatePreamble(StatePreamble),
780
  .StateData(StateData)
781 15 mohor
);
782
 
783
 
784
 
785
 
786
wire  [15:0]  RxByteCnt;
787
wire          RxByteCntEq0;
788
wire          RxByteCntGreat2;
789
wire          RxByteCntMaxFrame;
790
wire          RxCrcError;
791
wire          RxStateIdle;
792
wire          RxStatePreamble;
793
wire          RxStateSFD;
794
wire   [1:0]  RxStateData;
795 250 mohor
wire          AddressMiss;
796 15 mohor
 
797
 
798
 
799
// Connecting RxEthMAC
800 352 olof
eth_rxethmac rxethmac1
801 15 mohor
(
802 365 olof
  .MRxClk(mrx_clk_pad_i),
803
  .MRxDV(MRxDV_Lb),
804
  .MRxD(MRxD_Lb),
805
  .Transmitting(Transmitting),
806
  .HugEn(r_HugEn),
807
  .DlyCrcEn(r_DlyCrcEn),
808
  .MaxFL(r_MaxFL),
809
  .r_IFG(r_IFG),
810
  .Reset(wb_rst_i),
811
  .RxData(RxData),
812
  .RxValid(RxValid),
813
  .RxStartFrm(RxStartFrm),
814
  .RxEndFrm(RxEndFrm),
815
  .ByteCnt(RxByteCnt),
816
  .ByteCntEq0(RxByteCntEq0),
817
  .ByteCntGreat2(RxByteCntGreat2),
818
  .ByteCntMaxFrame(RxByteCntMaxFrame),
819
  .CrcError(RxCrcError),
820
  .StateIdle(RxStateIdle),
821
  .StatePreamble(RxStatePreamble),
822
  .StateSFD(RxStateSFD),
823
  .StateData(RxStateData),
824
  .MAC(r_MAC),
825
  .r_Pro(r_Pro),
826
  .r_Bro(r_Bro),
827
  .r_HASH0(r_HASH0),
828
  .r_HASH1(r_HASH1),
829
  .RxAbort(RxAbort),
830
  .AddressMiss(AddressMiss),
831
  .PassAll(r_PassAll),
832
  .ControlFrmAddressOK(ControlFrmAddressOK)
833 15 mohor
);
834
 
835
 
836
// MII Carrier Sense Synchronization
837 240 tadejm
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
838 15 mohor
begin
839 240 tadejm
  if(wb_rst_i)
840 15 mohor
    begin
841 352 olof
      CarrierSense_Tx1 <=  1'b0;
842
      CarrierSense_Tx2 <=  1'b0;
843 15 mohor
    end
844
  else
845
    begin
846 352 olof
      CarrierSense_Tx1 <=  mcrs_pad_i;
847
      CarrierSense_Tx2 <=  CarrierSense_Tx1;
848 15 mohor
    end
849
end
850
 
851
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
852
 
853
 
854
// MII Collision Synchronization
855 240 tadejm
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
856 15 mohor
begin
857 240 tadejm
  if(wb_rst_i)
858 15 mohor
    begin
859 352 olof
      Collision_Tx1 <=  1'b0;
860
      Collision_Tx2 <=  1'b0;
861 15 mohor
    end
862
  else
863
    begin
864 352 olof
      Collision_Tx1 <=  mcoll_pad_i;
865 15 mohor
      if(ResetCollision)
866 352 olof
        Collision_Tx2 <=  1'b0;
867 15 mohor
      else
868
      if(Collision_Tx1)
869 352 olof
        Collision_Tx2 <=  1'b1;
870 15 mohor
    end
871
end
872
 
873
 
874
// Synchronized Collision
875
assign Collision = ~r_FullD & Collision_Tx2;
876
 
877
 
878
 
879
// Delayed WillTransmit
880 20 mohor
always @ (posedge mrx_clk_pad_i)
881 15 mohor
begin
882 352 olof
  WillTransmit_q <=  WillTransmit;
883
  WillTransmit_q2 <=  WillTransmit_q;
884 15 mohor
end
885
 
886
 
887
assign Transmitting = ~r_FullD & WillTransmit_q2;
888
 
889
 
890
 
891
// Synchronized Receive Enable
892 240 tadejm
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
893 15 mohor
begin
894 240 tadejm
  if(wb_rst_i)
895 352 olof
    RxEnSync <=  1'b0;
896 15 mohor
  else
897 301 knguyen
  if(~mrxdv_pad_i)
898 352 olof
    RxEnSync <=  r_RxEn;
899 15 mohor
end
900
 
901
 
902
 
903 149 mohor
// Synchronizing WillSendControlFrame to WB_CLK;
904
always @ (posedge wb_clk_i or posedge wb_rst_i)
905
begin
906
  if(wb_rst_i)
907
    WillSendControlFrame_sync1 <= 1'b0;
908
  else
909 352 olof
    WillSendControlFrame_sync1 <= WillSendControlFrame;
910 149 mohor
end
911 15 mohor
 
912 149 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
913
begin
914
  if(wb_rst_i)
915
    WillSendControlFrame_sync2 <= 1'b0;
916
  else
917 352 olof
    WillSendControlFrame_sync2 <= WillSendControlFrame_sync1;
918 149 mohor
end
919
 
920
always @ (posedge wb_clk_i or posedge wb_rst_i)
921
begin
922
  if(wb_rst_i)
923
    WillSendControlFrame_sync3 <= 1'b0;
924
  else
925 352 olof
    WillSendControlFrame_sync3 <= WillSendControlFrame_sync2;
926 149 mohor
end
927
 
928
always @ (posedge wb_clk_i or posedge wb_rst_i)
929
begin
930
  if(wb_rst_i)
931
    RstTxPauseRq <= 1'b0;
932
  else
933 352 olof
    RstTxPauseRq <= WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
934 149 mohor
end
935
 
936
 
937 255 mohor
 
938
 
939
// TX Pause request Synchronization
940
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
941
begin
942
  if(wb_rst_i)
943
    begin
944 352 olof
      TxPauseRq_sync1 <=  1'b0;
945
      TxPauseRq_sync2 <=  1'b0;
946
      TxPauseRq_sync3 <=  1'b0;
947 255 mohor
    end
948
  else
949
    begin
950 352 olof
      TxPauseRq_sync1 <=  (r_TxPauseRq & r_TxFlow);
951
      TxPauseRq_sync2 <=  TxPauseRq_sync1;
952
      TxPauseRq_sync3 <=  TxPauseRq_sync2;
953 255 mohor
    end
954
end
955
 
956
 
957
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
958
begin
959
  if(wb_rst_i)
960 352 olof
    TPauseRq <=  1'b0;
961 255 mohor
  else
962 352 olof
    TPauseRq <=  TxPauseRq_sync2 & (~TxPauseRq_sync3);
963 255 mohor
end
964
 
965
 
966 261 mohor
wire LatchedMRxErr;
967
reg RxAbort_latch;
968
reg RxAbort_sync1;
969
reg RxAbort_wb;
970
reg RxAbortRst_sync1;
971
reg RxAbortRst;
972 255 mohor
 
973 261 mohor
// Synchronizing RxAbort to the WISHBONE clock
974
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
975
begin
976
  if(wb_rst_i)
977 352 olof
    RxAbort_latch <=  1'b0;
978 365 olof
  else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr &
979
          ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
980 352 olof
    RxAbort_latch <=  1'b1;
981 261 mohor
  else if(RxAbortRst)
982 352 olof
    RxAbort_latch <=  1'b0;
983 261 mohor
end
984 255 mohor
 
985 261 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
986
begin
987
  if(wb_rst_i)
988
    begin
989 352 olof
      RxAbort_sync1 <=  1'b0;
990
      RxAbort_wb    <=  1'b0;
991
      RxAbort_wb    <=  1'b0;
992 261 mohor
    end
993
  else
994
    begin
995 352 olof
      RxAbort_sync1 <=  RxAbort_latch;
996
      RxAbort_wb    <=  RxAbort_sync1;
997 261 mohor
    end
998
end
999
 
1000
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
1001
begin
1002
  if(wb_rst_i)
1003
    begin
1004 352 olof
      RxAbortRst_sync1 <=  1'b0;
1005
      RxAbortRst       <=  1'b0;
1006 261 mohor
    end
1007
  else
1008
    begin
1009 352 olof
      RxAbortRst_sync1 <=  RxAbort_wb;
1010
      RxAbortRst       <=  RxAbortRst_sync1;
1011 261 mohor
    end
1012
end
1013
 
1014
 
1015
 
1016 114 mohor
// Connecting Wishbone module
1017 352 olof
eth_wishbone #(.TX_FIFO_DATA_WIDTH(TX_FIFO_DATA_WIDTH),
1018 349 olof
               .TX_FIFO_DEPTH     (TX_FIFO_DEPTH),
1019
               .TX_FIFO_CNT_WIDTH (TX_FIFO_CNT_WIDTH),
1020
               .RX_FIFO_DATA_WIDTH(RX_FIFO_DATA_WIDTH),
1021
               .RX_FIFO_DEPTH     (RX_FIFO_DEPTH),
1022
               .RX_FIFO_CNT_WIDTH (RX_FIFO_CNT_WIDTH))
1023
wishbone
1024 15 mohor
(
1025 365 olof
  .WB_CLK_I(wb_clk_i),
1026
  .WB_DAT_I(wb_dat_i),
1027
  .WB_DAT_O(BD_WB_DAT_O),
1028 15 mohor
 
1029
  // WISHBONE slave
1030 365 olof
  .WB_ADR_I(wb_adr_i[9:2]),
1031
  .WB_WE_I(wb_we_i),
1032
  .BDCs(BDCs),
1033
  .WB_ACK_O(BDAck),
1034
  .Reset(wb_rst_i),
1035 15 mohor
 
1036 41 mohor
  // WISHBONE master
1037 365 olof
  .m_wb_adr_o(m_wb_adr_tmp),
1038
  .m_wb_sel_o(m_wb_sel_o),
1039
  .m_wb_we_o(m_wb_we_o),
1040
  .m_wb_dat_i(m_wb_dat_i),
1041
  .m_wb_dat_o(m_wb_dat_o),
1042
  .m_wb_cyc_o(m_wb_cyc_o),
1043
  .m_wb_stb_o(m_wb_stb_o),
1044
  .m_wb_ack_i(m_wb_ack_i),
1045
  .m_wb_err_i(m_wb_err_i),
1046 214 mohor
 
1047 365 olof
  .m_wb_cti_o(m_wb_cti_o),
1048
  .m_wb_bte_o(m_wb_bte_o),
1049 41 mohor
 
1050 15 mohor
    //TX
1051 365 olof
  .MTxClk(mtx_clk_pad_i),
1052
  .TxStartFrm(TxStartFrm),
1053
  .TxEndFrm(TxEndFrm),
1054
  .TxUsedData(TxUsedData),
1055
  .TxData(TxData),
1056
  .TxRetry(TxRetry),
1057
  .TxAbort(TxAbort),
1058
  .TxUnderRun(TxUnderRun),
1059
  .TxDone(TxDone),
1060
  .PerPacketCrcEn(PerPacketCrcEn),
1061
  .PerPacketPad(PerPacketPad),
1062 15 mohor
 
1063
  // Register
1064 365 olof
  .r_TxEn(r_TxEn),
1065
  .r_RxEn(r_RxEn),
1066
  .r_TxBDNum(r_TxBDNum),
1067
  .r_RxFlow(r_RxFlow),
1068
  .r_PassAll(r_PassAll),
1069 15 mohor
 
1070
  //RX
1071 365 olof
  .MRxClk(mrx_clk_pad_i),
1072
  .RxData(RxData),
1073
  .RxValid(RxValid),
1074
  .RxStartFrm(RxStartFrm),
1075
  .RxEndFrm(RxEndFrm),
1076
  .Busy_IRQ(Busy_IRQ),
1077
  .RxE_IRQ(RxE_IRQ),
1078
  .RxB_IRQ(RxB_IRQ),
1079
  .TxE_IRQ(TxE_IRQ),
1080
  .TxB_IRQ(TxB_IRQ),
1081 21 mohor
 
1082 365 olof
  .RxAbort(RxAbort_wb),
1083
  .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
1084 41 mohor
 
1085 365 olof
  .InvalidSymbol(InvalidSymbol),
1086
  .LatchedCrcError(LatchedCrcError),
1087
  .RxLength(RxByteCnt),
1088
  .RxLateCollision(RxLateCollision),
1089
  .ShortFrame(ShortFrame),
1090
  .DribbleNibble(DribbleNibble),
1091
  .ReceivedPacketTooBig(ReceivedPacketTooBig),
1092
  .LoadRxStatus(LoadRxStatus),
1093
  .RetryCntLatched(RetryCntLatched),
1094
  .RetryLimit(RetryLimit),
1095
  .LateCollLatched(LateCollLatched),
1096
  .DeferLatched(DeferLatched),
1097
  .RstDeferLatched(RstDeferLatched),
1098
  .CarrierSenseLost(CarrierSenseLost),
1099
  .ReceivedPacketGood(ReceivedPacketGood),
1100
  .AddressMiss(AddressMiss),
1101 261 mohor
  .ReceivedPauseFrm(ReceivedPauseFrm)
1102 59 mohor
 
1103 210 mohor
`ifdef ETH_BIST
1104 218 mohor
  ,
1105 302 markom
  .mbist_si_i       (mbist_si_i),
1106
  .mbist_so_o       (mbist_so_o),
1107
  .mbist_ctrl_i       (mbist_ctrl_i)
1108 210 mohor
`endif
1109 360 olof
`ifdef WISHBONE_DEBUG
1110
  ,
1111
  .dbg_dat0(wb_dbg_dat0)
1112
`endif
1113
 
1114 15 mohor
);
1115
 
1116 327 igorm
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
1117 15 mohor
 
1118
// Connecting MacStatus module
1119 352 olof
eth_macstatus macstatus1
1120 15 mohor
(
1121 365 olof
  .MRxClk(mrx_clk_pad_i),
1122
  .Reset(wb_rst_i),
1123
  .ReceiveEnd(ReceiveEnd),
1124
  .ReceivedPacketGood(ReceivedPacketGood),
1125
     .ReceivedLengthOK(ReceivedLengthOK),
1126
  .RxCrcError(RxCrcError),
1127
  .MRxErr(MRxErr_Lb),
1128
  .MRxDV(MRxDV_Lb),
1129
  .RxStateSFD(RxStateSFD),
1130
  .RxStateData(RxStateData),
1131
  .RxStatePreamble(RxStatePreamble),
1132
  .RxStateIdle(RxStateIdle),
1133
  .Transmitting(Transmitting),
1134
  .RxByteCnt(RxByteCnt),
1135
  .RxByteCntEq0(RxByteCntEq0),
1136
  .RxByteCntGreat2(RxByteCntGreat2),
1137
  .RxByteCntMaxFrame(RxByteCntMaxFrame),
1138 261 mohor
  .InvalidSymbol(InvalidSymbol),
1139 365 olof
  .MRxD(MRxD_Lb),
1140
  .LatchedCrcError(LatchedCrcError),
1141
  .Collision(mcoll_pad_i),
1142
  .CollValid(r_CollValid),
1143
  .RxLateCollision(RxLateCollision),
1144
  .r_RecSmall(r_RecSmall),
1145
  .r_MinFL(r_MinFL),
1146
  .r_MaxFL(r_MaxFL),
1147
  .ShortFrame(ShortFrame),
1148
  .DribbleNibble(DribbleNibble),
1149
  .ReceivedPacketTooBig(ReceivedPacketTooBig),
1150
  .r_HugEn(r_HugEn),
1151
  .LoadRxStatus(LoadRxStatus),
1152
  .RetryCnt(RetryCnt),
1153
  .StartTxDone(StartTxDone),
1154
  .StartTxAbort(StartTxAbort),
1155
  .RetryCntLatched(RetryCntLatched),
1156
  .MTxClk(mtx_clk_pad_i),
1157
  .MaxCollisionOccured(MaxCollisionOccured),
1158
  .RetryLimit(RetryLimit),
1159
  .LateCollision(LateCollision),
1160
  .LateCollLatched(LateCollLatched),
1161
  .DeferIndication(DeferIndication),
1162
  .DeferLatched(DeferLatched),
1163
  .RstDeferLatched(RstDeferLatched),
1164
  .TxStartFrm(TxStartFrmOut),
1165
  .StatePreamble(StatePreamble),
1166
  .StateData(StateData),
1167
  .CarrierSense(CarrierSense_Tx2),
1168
  .CarrierSenseLost(CarrierSenseLost),
1169
  .TxUsedData(TxUsedDataIn),
1170
  .LatchedMRxErr(LatchedMRxErr),
1171
  .Loopback(r_LoopBck),
1172
  .r_FullD(r_FullD)
1173 15 mohor
);
1174
 
1175
 
1176
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.