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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac_defines.v] - Blame information for rev 92

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_defines.v                                               ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.15  2002/02/26 16:11:32  mohor
// Number of interrupts changed
//
// Revision 1.14  2002/02/16 14:03:44  mohor
// Registered trimmed. Unused registers removed.
//
// Revision 1.13  2002/02/16 13:06:33  mohor
// EXTERNAL_DMA used instead of WISHBONE_DMA.
//
// Revision 1.12  2002/02/15 10:58:31  mohor
// Changed that were lost with last update put back to the file.
//
// Revision 1.11  2002/02/14 20:19:41  billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.10  2002/02/12 17:01:19  mohor
// HASH0 and HASH1 registers added. 
 
// Revision 1.9  2002/02/08 16:21:54  mohor
// Rx status is written back to the BD.
//
// Revision 1.8  2002/02/05 16:44:38  mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still  need
// to be fixed.
//
// Revision 1.7  2002/01/23 10:28:16  mohor
// Link in the header changed.
//
// Revision 1.6  2001/12/05 15:00:16  mohor
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
// instead of the number of RX descriptors).
//
// Revision 1.5  2001/12/05 10:21:37  mohor
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
//
// Revision 1.4  2001/11/13 14:23:56  mohor
// Generic memory model is used. Defines are changed for the same reason.
//
// Revision 1.3  2001/10/18 12:07:11  mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.2  2001/09/24 15:02:56  mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
 
 
//`define EXTERNAL_DMA                  // Using DMA
 
 
// Selection of the used memory
//`define XILINX_RAMB4                // Core is going to be implemented in Virtex FPGA and contains Virtex 
                                      // specific elements. 
 
//`define ARTISAN_SDP                 // Core is going to be implemented in ASIC (using Artisan RAM)
 
 
`define ETH_MODER_ADR         8'h0    // 0x0 
`define ETH_INT_SOURCE_ADR    8'h1    // 0x4 
`define ETH_INT_MASK_ADR      8'h2    // 0x8 
`define ETH_IPGT_ADR          8'h3    // 0xC 
`define ETH_IPGR1_ADR         8'h4    // 0x10
`define ETH_IPGR2_ADR         8'h5    // 0x14
`define ETH_PACKETLEN_ADR     8'h6    // 0x18
`define ETH_COLLCONF_ADR      8'h7    // 0x1C
`define ETH_TX_BD_NUM_ADR     8'h8    // 0x20
`define ETH_CTRLMODER_ADR     8'h9    // 0x24
`define ETH_MIIMODER_ADR      8'hA    // 0x28
`define ETH_MIICOMMAND_ADR    8'hB    // 0x2C
`define ETH_MIIADDRESS_ADR    8'hC    // 0x30
`define ETH_MIITX_DATA_ADR    8'hD    // 0x34
`define ETH_MIIRX_DATA_ADR    8'hE    // 0x38
`define ETH_MIISTATUS_ADR     8'hF    // 0x3C
`define ETH_MAC_ADDR0_ADR     8'h10   // 0x40
`define ETH_MAC_ADDR1_ADR     8'h11   // 0x44
`define ETH_HASH0_ADR         8'h12   // 0x48
`define ETH_HASH1_ADR         8'h13   // 0x4C
 
 
`define ETH_MODER_DEF         17'h0A800
`define ETH_INT_SOURCE_DEF    32'h00000000
`define ETH_INT_MASK_DEF      7'h0
`define ETH_IPGT_DEF          7'h12
`define ETH_IPGR1_DEF         7'h0C
`define ETH_IPGR2_DEF         7'h12
`define ETH_PACKETLEN_DEF     32'h003C0600
`define ETH_COLLCONF0_DEF     6'h3f
`define ETH_COLLCONF1_DEF     4'hF
`define ETH_TX_BD_NUM_DEF     8'h80
`define ETH_CTRLMODER_DEF     3'h0
`define ETH_MIIMODER_DEF      11'h064
`define ETH_MIIADDRESS0_DEF   5'h00
`define ETH_MIIADDRESS1_DEF   5'h00
`define ETH_MIITX_DATA_DEF    16'h0000
`define ETH_MIIRX_DATA_DEF    16'h0000
`define ETH_MIISTATUS_DEF     32'h00000000
`define ETH_MAC_ADDR0_DEF     32'h00000000
`define ETH_MAC_ADDR1_DEF     16'h0000
`define ETH_HASH0_DEF         32'h00000000
`define ETH_HASH1_DEF         32'h00000000
 
 
// Outputs are registered (uncomment when needed)
// `define ETH_REGISTERED_OUTPUTS
 
`define TX_FIFO_CNT_WIDTH      4
`define TX_FIFO_DEPTH          8
`define TX_FIFO_DATA_WIDTH    32
 
`define RX_FIFO_CNT_WIDTH      4
`define RX_FIFO_DEPTH          8
`define RX_FIFO_DATA_WIDTH    32

Line No.	Rev	Author	Line
1	15	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_defines.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6	37	mohor	`//// http://www.opencores.org/projects/ethmac/ ////`
7	15	mohor	`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	92	mohor	`// Revision 1.15 2002/02/26 16:11:32 mohor`
45			`// Number of interrupts changed`
46			`//`
47	73	mohor	`// Revision 1.14 2002/02/16 14:03:44 mohor`
48			`// Registered trimmed. Unused registers removed.`
49			`//`
50	68	mohor	`// Revision 1.13 2002/02/16 13:06:33 mohor`
51			`// EXTERNAL_DMA used instead of WISHBONE_DMA.`
52			`//`
53	67	mohor	`// Revision 1.12 2002/02/15 10:58:31 mohor`
54			`// Changed that were lost with last update put back to the file.`
55			`//`
56	55	mohor	`// Revision 1.11 2002/02/14 20:19:41 billditt`
57			`// Modified for Address Checking,`
58			`// addition of eth_addrcheck.v`
59			`//`
60			`// Revision 1.10 2002/02/12 17:01:19 mohor`
61			`// HASH0 and HASH1 registers added.`
62
63	46	mohor	`// Revision 1.9 2002/02/08 16:21:54 mohor`
64			`// Rx status is written back to the BD.`
65			`//`
66	42	mohor	`// Revision 1.8 2002/02/05 16:44:38 mohor`
67			`// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200`
68			`// MHz. Statuses, overrun, control frame transmission and reception still need`
69			`// to be fixed.`
70			`//`
71	40	mohor	`// Revision 1.7 2002/01/23 10:28:16 mohor`
72			`// Link in the header changed.`
73			`//`
74	37	mohor	`// Revision 1.6 2001/12/05 15:00:16 mohor`
75			`// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors`
76			`// instead of the number of RX descriptors).`
77			`//`
78	34	mohor	`// Revision 1.5 2001/12/05 10:21:37 mohor`
79			`// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.`
80			`//`
81	32	mohor	`// Revision 1.4 2001/11/13 14:23:56 mohor`
82			`// Generic memory model is used. Defines are changed for the same reason.`
83			`//`
84	29	mohor	`// Revision 1.3 2001/10/18 12:07:11 mohor`
85			`// Status signals changed, Adress decoding changed, interrupt controller`
86			`// added.`
87			`//`
88	21	mohor	`// Revision 1.2 2001/09/24 15:02:56 mohor`
89			`// Defines changed (All precede with ETH_). Small changes because some`
90			`// tools generate warnings when two operands are together. Synchronization`
91			`// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC`
92			`// demands).`
93			`//`
94	20	mohor	`// Revision 1.1 2001/08/06 14:44:29 mohor`
95			`// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).`
96			`// Include files fixed to contain no path.`
97			`// File names and module names changed ta have a eth_ prologue in the name.`
98			`// File eth_timescale.v is used to define timescale`
99			`// All pin names on the top module are changed to contain _I, _O or _OE at the end.`
100			`// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O`
101			`// and Mdo_OE. The bidirectional signal must be created on the top level. This`
102			`// is done due to the ASIC tools.`
103			`//`
104	15	mohor	`// Revision 1.1 2001/07/30 21:23:42 mohor`
105			`// Directory structure changed. Files checked and joind together.`
106			`//`
107			`//`
108			`//`
109			`//`
110			`//`
111
112	32	mohor
113	67	mohor	//`define EXTERNAL_DMA // Using DMA
114	32	mohor
115
116	29	mohor	`// Selection of the used memory`
117			//`define XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex
118			`// specific elements.`
119	15	mohor
120	29	mohor	//`define ARTISAN_SDP // Core is going to be implemented in ASIC (using Artisan RAM)
121	15	mohor
122
123	55	mohor	`define ETH_MODER_ADR 8'h0 // 0x0
124			`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
125			`define ETH_INT_MASK_ADR 8'h2 // 0x8
126			`define ETH_IPGT_ADR 8'h3 // 0xC
127			`define ETH_IPGR1_ADR 8'h4 // 0x10
128			`define ETH_IPGR2_ADR 8'h5 // 0x14
129			`define ETH_PACKETLEN_ADR 8'h6 // 0x18
130			`define ETH_COLLCONF_ADR 8'h7 // 0x1C
131			`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20
132			`define ETH_CTRLMODER_ADR 8'h9 // 0x24
133			`define ETH_MIIMODER_ADR 8'hA // 0x28
134			`define ETH_MIICOMMAND_ADR 8'hB // 0x2C
135			`define ETH_MIIADDRESS_ADR 8'hC // 0x30
136			`define ETH_MIITX_DATA_ADR 8'hD // 0x34
137			`define ETH_MIIRX_DATA_ADR 8'hE // 0x38
138			`define ETH_MIISTATUS_ADR 8'hF // 0x3C
139			`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40
140			`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44
141			`define ETH_HASH0_ADR 8'h12 // 0x48
142			`define ETH_HASH1_ADR 8'h13 // 0x4C
143	15	mohor
144
145	68	mohor	`define ETH_MODER_DEF 17'h0A800
146	20	mohor	`define ETH_INT_SOURCE_DEF 32'h00000000
147	73	mohor	`define ETH_INT_MASK_DEF 7'h0
148	68	mohor	`define ETH_IPGT_DEF 7'h12
149			`define ETH_IPGR1_DEF 7'h0C
150			`define ETH_IPGR2_DEF 7'h12
151	20	mohor	`define ETH_PACKETLEN_DEF 32'h003C0600
152	68	mohor	`define ETH_COLLCONF0_DEF 6'h3f
153			`define ETH_COLLCONF1_DEF 4'hF
154			`define ETH_TX_BD_NUM_DEF 8'h80
155			`define ETH_CTRLMODER_DEF 3'h0
156			`define ETH_MIIMODER_DEF 11'h064
157			`define ETH_MIIADDRESS0_DEF 5'h00
158			`define ETH_MIIADDRESS1_DEF 5'h00
159			`define ETH_MIITX_DATA_DEF 16'h0000
160			`define ETH_MIIRX_DATA_DEF 16'h0000
161	20	mohor	`define ETH_MIISTATUS_DEF 32'h00000000
162			`define ETH_MAC_ADDR0_DEF 32'h00000000
163	68	mohor	`define ETH_MAC_ADDR1_DEF 16'h0000
164	46	mohor	`define ETH_HASH0_DEF 32'h00000000
165			`define ETH_HASH1_DEF 32'h00000000
166	15	mohor
167	40	mohor
168			`// Outputs are registered (uncomment when needed)`
169			// `define ETH_REGISTERED_OUTPUTS
170
171			`define TX_FIFO_CNT_WIDTH 4
172			`define TX_FIFO_DEPTH 8
173			`define TX_FIFO_DATA_WIDTH 32
174
175			`define RX_FIFO_CNT_WIDTH 4
176			`define RX_FIFO_DEPTH 8
177			`define RX_FIFO_DATA_WIDTH 32

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac_defines.v] - Blame information for rev 92