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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [sim/] [rtl_sim/] [modelsim_sim/] [bin/] [ethernet.mpf] - Blame information for rev 364

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Line No. Rev Author Line
1 183 mohor
[Library]
2
std = $MODEL_TECH/../std
3
ieee = $MODEL_TECH/../ieee
4
verilog = $MODEL_TECH/../verilog
5
vital2000 = $MODEL_TECH/../vital2000
6
std_developerskit = $MODEL_TECH/../std_developerskit
7
synopsys = $MODEL_TECH/../synopsys
8
modelsim_lib = $MODEL_TECH/../modelsim_lib
9
 
10
work = work
11
[vcom]
12
; Turn on VHDL-1993 as the default. Default is off (VHDL-1987).
13
; VHDL93 = 1
14
 
15
; Show source line containing error. Default is off.
16
; Show_source = 1
17
 
18
; Turn off unbound-component warnings. Default is on.
19
; Show_Warning1 = 0
20
 
21
; Turn off process-without-a-wait-statement warnings. Default is on.
22
; Show_Warning2 = 0
23
 
24
; Turn off null-range warnings. Default is on.
25
; Show_Warning3 = 0
26
 
27
; Turn off no-space-in-time-literal warnings. Default is on.
28
; Show_Warning4 = 0
29
 
30
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
31
; Show_Warning5 = 0
32
 
33
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
34
; Optimize_1164 = 0
35
 
36
; Turn on resolving of ambiguous function overloading in favor of the
37
; "explicit" function declaration (not the one automatically created by
38
; the compiler for each type declaration). Default is off.
39
; The .ini file has Explict enabled so that std_logic_signed/unsigned
40
; will match the behavior of synthesis tools.
41
Explicit = 1
42
 
43
; Turn off acceleration of the VITAL packages. Default is to accelerate.
44
; NoVital = 1
45
 
46
; Turn off VITAL compliance checking. Default is checking on.
47
; NoVitalCheck = 1
48
 
49
; Ignore VITAL compliance checking errors. Default is to not ignore.
50
; IgnoreVitalErrors = 1
51
 
52
; Turn off VITAL compliance checking warnings. Default is to show warnings.
53
; Show_VitalChecksWarnings = false
54
 
55
; Keep silent about case statement static warnings.
56
; Default is to give a warning.
57
; NoCaseStaticError = 1
58
 
59
; Keep silent about warnings caused by aggregates that are not locally static.
60
; Default is to give a warning.
61
; NoOthersStaticError = 1
62
 
63
; Treat as errors:
64
;   case statement static warnings
65
;   warnings caused by aggregates that are not locally static
66
; Overrides NoCaseStaticError, NoOthersStaticError settings.
67
; PedanticErrors = 1
68
 
69
; Turn off inclusion of debugging info within design units.
70
; Default is to include debugging info.
71
; NoDebug = 1
72
 
73
; Turn off "loading..." messages. Default is messages on.
74
; Quiet = 1
75
 
76
; Turn on some limited synthesis rule compliance checking. Checks only:
77
;    -- signals used (read) by a process must be in the sensitivity list
78
; CheckSynthesis = 1
79
 
80
; Activate optimizations on expressions that do not involve signals,
81
; waits, or function/procedure/task invocations. Default is off.
82
; ScalarOpts = 1
83
 
84
; Require the user to specify a configuration for all bindings,
85
; and do not generate a compile time default binding for the
86
; component. This will result in an elaboration error of
87
; 'component not bound' if the user fails to do so. Avoids the rare
88
; issue of a false dependency upon the unused default binding.
89
; RequireConfigForAllDefaultBinding = 1
90
 
91
; Inhibit range checking on subscripts of arrays. Range checking on
92
; scalars defined with subtypes is inhibited by default.
93
; NoIndexCheck = 1
94
 
95
; Inhibit range checks on all (implicit and explicit) assignments to
96
; scalar objects defined with subtypes.
97
; NoRangeCheck = 1
98
 
99
VHDL93 = 0
100
NoDebug = 0
101
CheckSynthesis = 0
102
NoVitalCheck = 0
103
Optimize_1164 = 1
104
NoVital = 0
105
Quiet = 0
106
Show_source = 0
107
Show_Warning1 = 1
108
Show_Warning2 = 1
109
Show_Warning3 = 1
110
Show_Warning4 = 1
111
Show_Warning5 = 1
112
[vlog]
113
 
114
; Turn off inclusion of debugging info within design units.
115
; Default is to include debugging info.
116
; NoDebug = 1
117
 
118
; Turn off "loading..." messages. Default is messages on.
119
; Quiet = 1
120
 
121
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
122
; Default is off.
123
; Hazard = 1
124
 
125
; Turn on converting regular Verilog identifiers to uppercase. Allows case
126
; insensitivity for module names. Default is no conversion.
127
; UpCase = 1
128
 
129
; Turn on incremental compilation of modules. Default is off.
130
; Incremental = 1
131
 
132
; Activate optimizations on expressions that do not involve signals,
133
; waits, or function/procedure/task invocations. Default is off.
134
; ScalarOpts = 1
135
 
136
; Turns on lint-style checking.
137
; Show_Lint = 1
138
 
139
; Show source line containing error. Default is off.
140
; Show_source = 1
141
 
142
Quiet = 0
143
Show_source = 0
144
NoDebug = 0
145
Hazard = 0
146
UpCase = 0
147
OptionFile = ../../../../sim/rtl_sim/modelsim_sim/bin/vlog.opt
148
[vsim]
149
; Simulator resolution
150
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
151
resolution = 1ns
152
 
153
; User time unit for run commands
154
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
155
; unit specified for Resolution. For example, if Resolution is 100ps,
156
; then UserTimeUnit defaults to ps.
157
UserTimeUnit = ns
158
 
159
; Default run length
160
RunLength = 100
161
 
162
; Maximum iterations that can be run without advancing simulation time
163
IterationLimit = 5000
164
 
165
; Directives to license manager can be set either as single value or as
166
; space separated multi-values:
167
; vhdl          Immediately reserve a VHDL license
168
; vlog          Immediately reserve a Verilog license
169
; plus          Immediately reserve a VHDL and Verilog license
170
; nomgc         Do not look for Mentor Graphics Licenses
171
; nomti         Do not look for Model Technology Licenses
172
; noqueue       Do not wait in the license queue when a license is not available
173
; viewsim       Try for viewer license but accept simulator license(s) instead
174
;               of queuing for viewer license (PE ONLY)
175
; Single value:
176
; License = plus
177
; Multi-value:
178
; License = noqueue plus
179
 
180
; Stop the simulator after an assertion message
181
; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
182
BreakOnAssertion = 3
183
 
184
; Assertion Message Format
185
; %S - Severity Level
186
; %R - Report Message
187
; %T - Time of assertion
188
; %D - Delta
189
; %I - Instance or Region pathname (if available)
190
; %% - print '%' character
191
; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
192
 
193
; Assertion File - alternate file for storing assertion messages
194
; AssertFile = assert.log
195
 
196
; Default radix for all windows and commands...
197
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
198
DefaultRadix = symbolic
199
 
200
; VSIM Startup command
201
; Startup = do startup.do
202
 
203
; File for saving command transcript
204
TranscriptFile = transcript
205
 
206
; File for saving command history
207
; CommandHistory = cmdhist.log
208
 
209
; Specify whether paths in simulator commands should be described
210
; in VHDL or Verilog format. For VHDL, PathSeparator = /
211
; for Verilog, PathSeparator = .
212
PathSeparator = /
213
 
214
; Specify the dataset separator for fully rooted contexts.
215
; The default is ':'. For example, sim:/top
216
; Must not be the same character as PathSeparator.
217
DatasetSeparator = :
218
 
219
; Disable assertion messages
220
; IgnoreNote = 1
221
; IgnoreWarning = 1
222
; IgnoreError = 1
223
; IgnoreFailure = 1
224
 
225
; Default force kind. May be freeze, drive, or deposit
226
; or in other terms, fixed, wired, or charged.
227
; DefaultForceKind = freeze
228
 
229
; If zero, open files when elaborated; otherwise, open files on
230
; first read or write.  Default is 0.
231
; DelayFileOpen = 1
232
 
233
; Control VHDL files opened for write
234
;   0 = Buffered, 1 = Unbuffered
235
UnbufferedOutput = 0
236
 
237
; Control number of VHDL files open concurrently
238
;   This number should always be less than the
239
;   current ulimit setting for max file descriptors.
240
;   0 = unlimited
241
ConcurrentFileLimit = 40
242
 
243
; Controls the number of hierarchical regions displayed as
244
; part of a signal name shown in the waveform window.  The default
245
; value or a value of zero tells VSIM to display the full name.
246
; WaveSignalNameWidth = 0
247
 
248
; Turn off warnings from the std_logic_arith, std_logic_unsigned
249
; and std_logic_signed packages.
250
; StdArithNoWarnings = 1
251
 
252
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
253
; NumericStdNoWarnings = 1
254
 
255
; Control the format of a generate statement label. Do not quote it.
256
; GenerateFormat = %s__%d
257
 
258
; Specify whether checkpoint files should be compressed.
259
; The default is to be compressed.
260
; CheckpointCompressMode = 0
261
 
262
; List of dynamically loaded objects for Verilog PLI applications
263
; Veriuser = veriuser.sl
264
 
265
; Specify default options for the restart command. Options can be one
266
; or more of: -force -nobreakpoint -nolist -nolog -nowave
267
; DefaultRestartOptions = -force
268
 
269
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
270
; (> 500 megabyte memory footprint). Default is disabled.
271
; Specify number of megabytes to lock.
272
; LockedMemory = 1000
273
 
274
; Turn on (1) or off (0) WLF file compression.
275
; The default is 1; compress WLF file.
276
; WLFCompress = 0
277
 
278
; Specify whether to save all design hierarchy (1) in WLF file
279
; or only regions containing logged signals (0).
280
; The default is 0; log only regions with logged signals.
281
; WLFSaveAllRegions = 1
282
 
283
; WLF file time limit.  Limit WLF file by time, as closely as possible,
284
; to the specified amount of simulation time.  When the limit is exceeded
285
; the earliest times get truncated from the file.
286
; If both time and size limits are specified the most restrictive is used.
287
; UserTimeUnits are used if time units are not specified.
288
; The default is 0; no limit.  Example: WLFTimeLimit = {100 ms}
289
; WLFTimeLimit = 0
290
 
291
; WLF file size limit.  Limit WLF file size, as closely as possible,
292
; to the specified number of megabytes.  If both time and size limits
293
; are specified then the most restrictive is used.
294
; The default is 0; no limit.
295
; WLFSizeLimit = 1000
296
 
297
; Specify whether or not a WLF file should be deleted when the
298
; simulation ends.  A value of 1 will cause the WLF file to be deleted.
299
; The default is 0; do not delete WLF file when simulation ends.
300
; WLFDeleteOnQuit = 1
301
 
302
[lmc]
303
; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
304
libsm = $MODEL_TECH/libsm.sl
305
; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
306
; libsm = $MODEL_TECH/libsm.dll
307
;  Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
308
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
309
;  Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
310
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
311
;  Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
312
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
313
;  Logic Modeling's SmartModel SWIFT software (Windows NT)
314
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
315
;  Logic Modeling's SmartModel SWIFT software (Linux)
316
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
317
 
318
; ModelSim's interface to Logic Modeling's hardware modeler SFI software
319
libhm = $MODEL_TECH/libhm.sl
320
; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
321
; libhm = $MODEL_TECH/libhm.dll
322
;  Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
323
; libsfi = /lib/hp700/libsfi.sl
324
;  Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
325
; libsfi = /lib/rs6000/libsfi.a
326
;  Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
327
; libsfi = /lib/sun4.solaris/libsfi.so
328
;  Logic Modeling's hardware modeler SFI software (Windows NT)
329
; libsfi = /lib/pcnt/lm_sfi.dll
330
;  Logic Modeling's hardware modeler SFI software (Linux)
331
; libsfi = /lib/linux/libsfi.so
332
[Project]
333
Project_Version = 3
334
Project_DefaultLib = work
335
Project_SortMethod = alpha
336
Project_Files_Count = 34
337 184 mohor
Project_File_0 = ../../../../rtl/verilog/eth_registers.v
338
Project_File_P_0 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031654124 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 12 dont_compile 0
339
Project_File_1 = ../../../../rtl/verilog/eth_crc.v
340
Project_File_P_1 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 2 dont_compile 0
341
Project_File_2 = ../../../../rtl/verilog/eth_random.v
342
Project_File_P_2 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 9 dont_compile 0
343
Project_File_3 = ../../../../bench/verilog/wb_bus_mon.v
344
Project_File_P_3 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 30 dont_compile 0
345
Project_File_4 = ../../../../bench/verilog/tb_ethernet.v
346
Project_File_P_4 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1032198830 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 29 dont_compile 0
347
Project_File_5 = ../../../../rtl/verilog/eth_outputcontrol.v
348
Project_File_P_5 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1026245520 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 8 dont_compile 0
349
Project_File_6 = ../../../../rtl/verilog/eth_transmitcontrol.v
350
Project_File_P_6 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 20 dont_compile 0
351 364 olof
Project_File_7 = ../../../../rtl/verilog/ethmac.v
352 184 mohor
Project_File_P_7 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031842218 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 19 dont_compile 0
353
Project_File_8 = ../../../../rtl/verilog/eth_rxaddrcheck.v
354
Project_File_P_8 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031164866 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 13 dont_compile 0
355
Project_File_9 = ../../../../bench/verilog/wb_model_defines.v
356
Project_File_P_9 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 33 dont_compile 0
357
Project_File_10 = ../../../../rtl/verilog/eth_receivecontrol.v
358
Project_File_P_10 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 10 dont_compile 0
359
Project_File_11 = ../../../../rtl/verilog/eth_rxethmac.v
360
Project_File_P_11 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1013843728 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 15 dont_compile 0
361
Project_File_12 = ../../../../bench/verilog/eth_phy_defines.v
362
Project_File_P_12 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 27 dont_compile 0
363
Project_File_13 = ../../../../rtl/verilog/eth_miim.v
364
Project_File_P_13 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1029349930 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 7 dont_compile 0
365
Project_File_14 = ../../../../rtl/verilog/eth_rxcounters.v
366
Project_File_P_14 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1013771610 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 14 dont_compile 0
367
Project_File_15 = ../../../../rtl/verilog/eth_register.v
368
Project_File_P_15 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1029535812 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 11 dont_compile 0
369
Project_File_16 = ../../../../bench/verilog/wb_slave_behavioral.v
370
Project_File_P_16 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 34 dont_compile 0
371
Project_File_17 = ../../../../bench/verilog/wb_master_behavioral.v
372
Project_File_P_17 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 31 dont_compile 0
373
Project_File_18 = ../../../../rtl/verilog/eth_txethmac.v
374
Project_File_P_18 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1014740642 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 22 dont_compile 0
375
Project_File_19 = ../../../../rtl/verilog/eth_wishbone.v
376
Project_File_P_19 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031753926 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 24 dont_compile 0
377
Project_File_20 = ../../../../rtl/verilog/eth_txcounters.v
378
Project_File_P_20 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1019487254 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 21 dont_compile 0
379
Project_File_21 = ../../../../bench/verilog/eth_phy.v
380
Project_File_P_21 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031928616 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 26 dont_compile 0
381
Project_File_22 = ../../../../bench/verilog/wb_master32.v
382
Project_File_P_22 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 32 dont_compile 0
383
Project_File_23 = ../../../../rtl/verilog/eth_rxstatem.v
384
Project_File_P_23 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 16 dont_compile 0
385
Project_File_24 = ../../../../bench/verilog/tb_eth_defines.v
386
Project_File_P_24 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031942506 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 28 dont_compile 0
387
Project_File_25 = ../../../../rtl/verilog/eth_maccontrol.v
388
Project_File_P_25 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 5 dont_compile 0
389
Project_File_26 = ../../../../rtl/verilog/eth_txstatem.v
390
Project_File_P_26 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 23 dont_compile 0
391
Project_File_27 = ../../../../rtl/verilog/eth_shiftreg.v
392
Project_File_P_27 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1029349020 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 17 dont_compile 0
393
Project_File_28 = ../../../../rtl/verilog/eth_spram_256x32.v
394
Project_File_P_28 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1027442170 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 18 dont_compile 0
395
Project_File_29 = ../../../../rtl/verilog/eth_fifo.v
396
Project_File_P_29 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1019483152 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 4 dont_compile 0
397
Project_File_30 = ../../../../rtl/verilog/eth_macstatus.v
398
Project_File_P_30 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031842216 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 6 dont_compile 0
399 356 olof
Project_File_31 = ../../../../rtl/verilog/ethmac_defines.v
400 184 mohor
Project_File_P_31 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031164610 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 3 dont_compile 0
401
Project_File_32 = ../../../../rtl/verilog/eth_clockgen.v
402
Project_File_P_32 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 0 dont_compile 0
403
Project_File_33 = ../../../../rtl/verilog/timescale.v
404
Project_File_P_33 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 25 dont_compile 0
405 183 mohor
Project_Sim_Count = 0
406
Project_Folder_Count = 0

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