OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [sim/] [rtl_sim/] [modelsim_sim/] [run/] [tb_eth.do] - Blame information for rev 215

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 186 mohor
#/////////////////////////////////////////////////////////////////////
2
#///                                                              ////
3
#///  tb_eth.do                                                   ////
4
#///                                                              ////
5
#///  This file is part of the Ethernet IP core project           ////
6
#///  http://www.opencores.org/projects/ethmac/                   ////
7
#///                                                              ////
8
#///  Author(s):                                                  ////
9
#///      - Igor Mohor (igorM@opencores.org)                      ////
10
#///                                                              ////
11
#///  All additional information is avaliable in the Readme.txt   ////
12
#///  file.                                                       ////
13
#///                                                              ////
14
#/////////////////////////////////////////////////////////////////////
15
#///                                                              ////
16
#/// Copyright (C) 2001, 2002 Authors                             ////
17
#///                                                              ////
18
#/// This source file may be used and distributed without         ////
19
#/// restriction provided that this copyright statement is not    ////
20
#/// removed from the file and that any derivative work contains  ////
21
#/// the original copyright notice and the associated disclaimer. ////
22
#///                                                              ////
23
#/// This source file is free software; you can redistribute it   ////
24
#/// and/or modify it under the terms of the GNU Lesser General   ////
25
#/// Public License as published by the Free Software Foundation; ////
26
#/// either version 2.1 of the License, or (at your option) any   ////
27
#/// later version.                                               ////
28
#///                                                              ////
29
#/// This source is distributed in the hope that it will be       ////
30
#/// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
#/// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
#/// PURPOSE.  See the GNU Lesser General Public License for more ////
33
#/// details.                                                     ////
34
#///                                                              ////
35
#/// You should have received a copy of the GNU Lesser General    ////
36
#/// Public License along with this source; if not, download it   ////
37
#/// from http://www.opencores.org/lgpl.shtml                     ////
38
#///                                                              ////
39
#/////////////////////////////////////////////////////////////////////
40
#/
41
#/ CVS Revision History
42
#/
43
#/ $Log: not supported by cvs2svn $
44 215 mohor
#/ Revision 1.2  2002/09/23 18:27:36  mohor
45
#/ ETH_VIRTUAL_SILICON_RAM supported.
46
#/
47 205 mohor
#/ Revision 1.1  2002/09/17 19:10:17  mohor
48
#/ Macro for testbench (DO file).
49 186 mohor
#/
50
#/
51
#/
52 205 mohor
#/
53 186 mohor
 
54
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_clockgen.v}
55
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_crc.v}
56
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_defines.v}
57
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_fifo.v}
58
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_maccontrol.v}
59
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_macstatus.v}
60
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_miim.v}
61
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_outputcontrol.v}
62
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_random.v}
63
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_receivecontrol.v}
64
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_register.v}
65
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_registers.v}
66
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_rxaddrcheck.v}
67
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_rxcounters.v}
68
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_rxethmac.v}
69
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_rxstatem.v}
70
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_shiftreg.v}
71
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_spram_256x32.v}
72
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_top.v}
73
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_transmitcontrol.v}
74
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_txcounters.v}
75
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_txethmac.v}
76
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_txstatem.v}
77
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_wishbone.v}
78
vlog -reportprogress 300 -work work {../../../../rtl/verilog/timescale.v}
79
vlog -reportprogress 300 -work work {../../../../bench/verilog/eth_phy.v}
80
vlog -reportprogress 300 -work work {../../../../bench/verilog/eth_phy_defines.v}
81
vlog -reportprogress 300 -work work {../../../../bench/verilog/tb_eth_defines.v}
82
vlog -reportprogress 300 -work work {../../../../bench/verilog/tb_ethernet.v}
83
vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_bus_mon.v}
84
vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_master_behavioral.v}
85
vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_master32.v}
86
vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_model_defines.v}
87
vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_slave_behavioral.v}
88
 
89
 
90
# If you use define ETH_XILINX_RAMB4 switched on, then uncomment the following lines
91
# vlog -reportprogress 300 -work work {C:/Xilinx/verilog/src/glbl.v}
92
# vlog -reportprogress 300 -work work {C:/Xilinx/verilog/src/unisims/RAMB4_S16.v}
93
 
94 205 mohor
# If you use define ETH_VIRTUAL_SILICON_RAM switched on, then uncomment the following lines
95 215 mohor
# vlog -reportprogress 300 -work work {../../../../../vs_rams/018/vs_hdsp_256x32.v}
96 186 mohor
 
97 215 mohor
# If you use define ETH_VIRTUAL_SILICON_RAM and ETH_BIST switched on, then uncomment
98
# the following lines
99
# vlog -reportprogress 300 -work work {../../../../../vs_rams/018/vs_hdsp_256x32_bist.v}
100
 
101 186 mohor
# If you use define ETH_XILINX_RAMB4 switched on, then uncomment the following lines
102
# !ETH_XILINX_RAMB4
103
  vsim work.tb_ethernet
104
#  ETH_XILINX_RAMB4
105 205 mohor
#  vsim work.glbl work.tb_ethernet
106 186 mohor
 
107
 
108
run -all
109
 
110
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.