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[/] [ethmac/] [trunk/] [sim/] [rtl_sim/] [modelsim_sim/] [run/] [tb_eth.do] - Blame information for rev 364

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1 186 mohor
#/////////////////////////////////////////////////////////////////////
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#///                                                              ////
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#///  tb_eth.do                                                   ////
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#///                                                              ////
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#///  This file is part of the Ethernet IP core project           ////
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#///  http://www.opencores.org/projects/ethmac/                   ////
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#///                                                              ////
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#///  Author(s):                                                  ////
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#///      - Igor Mohor (igorM@opencores.org)                      ////
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#///                                                              ////
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#///  All additional information is avaliable in the Readme.txt   ////
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#///  file.                                                       ////
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#///                                                              ////
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#/////////////////////////////////////////////////////////////////////
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#///                                                              ////
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#/// Copyright (C) 2001, 2002 Authors                             ////
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#///                                                              ////
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#/// This source file may be used and distributed without         ////
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#/// restriction provided that this copyright statement is not    ////
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#/// removed from the file and that any derivative work contains  ////
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#/// the original copyright notice and the associated disclaimer. ////
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#///                                                              ////
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#/// This source file is free software; you can redistribute it   ////
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#/// and/or modify it under the terms of the GNU Lesser General   ////
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#/// Public License as published by the Free Software Foundation; ////
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#/// either version 2.1 of the License, or (at your option) any   ////
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#/// later version.                                               ////
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#///                                                              ////
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#/// This source is distributed in the hope that it will be       ////
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#/// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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#/// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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#/// PURPOSE.  See the GNU Lesser General Public License for more ////
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#/// details.                                                     ////
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#///                                                              ////
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#/// You should have received a copy of the GNU Lesser General    ////
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#/// Public License along with this source; if not, download it   ////
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#/// from http://www.opencores.org/lgpl.shtml                     ////
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#///                                                              ////
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#/////////////////////////////////////////////////////////////////////
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#/
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#/ CVS Revision History
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#/
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#/ $Log: not supported by cvs2svn $
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#/ Revision 1.4  2002/10/11 13:33:56  mohor
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#/ Bist supported.
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#/
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#/ Revision 1.3  2002/10/11 12:42:12  mohor
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#/ Bist supported.
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#/
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#/ Revision 1.2  2002/09/23 18:27:36  mohor
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#/ ETH_VIRTUAL_SILICON_RAM supported.
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#/
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#/ Revision 1.1  2002/09/17 19:10:17  mohor
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#/ Macro for testbench (DO file).
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#/
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#/
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#/
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#/
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#write format wave -window .wave C:/Projects/ethernet/tadejm/ethernet/sim/rtl_sim/modelsim_sim/bin/wave.do
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#.main clear
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_clockgen.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_crc.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/ethmac_defines.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_fifo.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_maccontrol.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_macstatus.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_miim.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_outputcontrol.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_random.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_receivecontrol.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_register.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_registers.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_rxaddrcheck.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_rxcounters.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_rxethmac.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_rxstatem.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_shiftreg.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_spram_256x32.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/ethmac.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_transmitcontrol.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_txcounters.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_txethmac.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_txstatem.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_wishbone.v}
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vlog -reportprogress 300 -work work {../../../../rtl/verilog/timescale.v}
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vlog -reportprogress 300 -work work {../../../../bench/verilog/eth_phy.v}
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vlog -reportprogress 300 -work work {../../../../bench/verilog/eth_phy_defines.v}
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vlog -reportprogress 300 -work work {../../../../bench/verilog/tb_eth_defines.v}
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vlog -reportprogress 300 -work work {../../../../bench/verilog/tb_ethernet.v}
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vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_bus_mon.v}
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vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_master_behavioral.v}
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vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_master32.v}
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vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_model_defines.v}
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vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_slave_behavioral.v}
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# If you use define ETH_XILINX_RAMB4 switched on, then uncomment the following lines
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# vlog -reportprogress 300 -work work {C:/Xilinx/verilog/src/glbl.v}
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# vlog -reportprogress 300 -work work {C:/Xilinx/verilog/src/unisims/RAMB4_S16.v}
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# If you use define ETH_VIRTUAL_SILICON_RAM switched on, then uncomment the following lines
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# vlog -reportprogress 300 -work work {../../../../../vs_rams/018/vs_hdsp_256x32.v}
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# If you use define ETH_VIRTUAL_SILICON_RAM and ETH_BIST switched on, then uncomment
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# the following lines
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# vlog -reportprogress 300 -work work {../../../../../vs_rams/018/vs_hdsp_256x32_bist.v}
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# vlog -reportprogress 300 -work work {../../../../../vs_rams/018/vs_hdsp_256x32_bist_int.v}
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# vlog -reportprogress 300 -work work {../../../../../jtag_marvin/jt_bc1in.v}
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# vlog -reportprogress 300 -work work {../../../../../bist_marvin/bist.v}
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# If you use define ETH_XILINX_RAMB4 switched on, then uncomment the following lines
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# !ETH_XILINX_RAMB4
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  vsim work.tb_ethernet
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#  ETH_XILINX_RAMB4
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  #vsim work.glbl work.tb_ethernet
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do ../bin/eth_wave.do
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#do ../bin/wave.do
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run -all
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