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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [sim/] [rtl_sim/] [ncsim_sim/] [run/] [top_groups.do] - Blame information for rev 364

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Line No. Rev Author Line
1 172 mohor
// Signalscan Version 6.7p1
2
 
3
 
4
define noactivityindicator
5
define analog waveform lines
6
define add variable default overlay off
7
define waveform window analogheight 1
8
define terminal automatic
9
define buttons control \
10
  1 opensimmulationfile \
11
  2 executedofile \
12
  3 designbrowser \
13
  4 waveform \
14
  5 source \
15
  6 breakpoints \
16
  7 definesourcessearchpath \
17
  8 exit \
18
  9 createbreakpoint \
19
  10 creategroup \
20
  11 createmarker \
21
  12 closesimmulationfile \
22
  13 renamesimmulationfile \
23
  14 replacesimulationfiledata \
24
  15 listopensimmulationfiles \
25
  16 savedofile
26
define buttons waveform \
27
  1 undo \
28
  2 cut \
29
  3 copy \
30
  4 paste \
31
  5 delete \
32
  6 zoomin \
33
  7 zoomout \
34
  8 zoomoutfull \
35
  9 expand \
36
  10 createmarker \
37
  11 designbrowser:1 \
38
  12 variableradixbinary \
39
  13 variableradixoctal \
40
  14 variableradixdecimal \
41
  15 variableradixhexadecimal \
42
  16 variableradixascii
43
define buttons designbrowser \
44
  1 undo \
45
  2 cut \
46
  3 copy \
47
  4 paste \
48
  5 delete \
49
  6 cdupscope \
50
  7 getallvariables \
51
  8 getdeepallvariables \
52
  9 addvariables \
53
  10 addvarsandclosewindow \
54
  11 closewindow \
55
  12 scopefiltermodule \
56
  13 scopefiltertask \
57
  14 scopefilterfunction \
58
  15 scopefilterblock \
59
  16 scopefilterprimitive
60
define buttons event \
61
  1 undo \
62
  2 cut \
63
  3 copy \
64
  4 paste \
65
  5 delete \
66
  6 move \
67
  7 closewindow \
68
  8 duplicate \
69
  9 defineasrisingedge \
70
  10 defineasfallingedge \
71
  11 defineasanyedge \
72
  12 variableradixbinary \
73
  13 variableradixoctal \
74
  14 variableradixdecimal \
75
  15 variableradixhexadecimal \
76
  16 variableradixascii
77
define buttons source \
78
  1 undo \
79
  2 cut \
80
  3 copy \
81
  4 paste \
82
  5 delete \
83
  6 createbreakpoint \
84
  7 creategroup \
85
  8 createmarker \
86
  9 createevent \
87
  10 createregisterpage \
88
  11 closewindow \
89
  12 opensimmulationfile \
90
  13 closesimmulationfile \
91
  14 renamesimmulationfile \
92
  15 replacesimulationfiledata \
93
  16 listopensimmulationfiles
94
define buttons register \
95
  1 undo \
96
  2 cut \
97
  3 copy \
98
  4 paste \
99
  5 delete \
100
  6 createregisterpage \
101
  7 closewindow \
102
  8 continuefor \
103
  9 continueuntil \
104
  10 continueforever \
105
  11 stop \
106
  12 previous \
107
  13 next \
108
  14 variableradixbinary \
109
  15 variableradixhexadecimal \
110
  16 variableradixascii
111
define show related transactions
112
define exit prompt
113
define event search direction forward
114
define variable nofullhierarchy
115
define variable nofilenames
116
define variable nofullpathfilenames
117
include bookmark with filenames
118
include scope history without filenames
119 319 tadejm
define waveform window listpane 11
120
define waveform window namepane 16
121 172 mohor
define multivalueindication
122
define pattern curpos dot
123
define pattern cursor1 dot
124
define pattern cursor2 dot
125
define pattern marker dot
126
define print designer "Miha Dolenc"
127
define print border
128
define print color blackonwhite
129
define print command "/usr/ucb/lpr -P%P"
130
define print printer  lp
131
define print range visible
132
define print variable visible
133
define rise fall time low threshold percentage 10
134
define rise fall time high threshold percentage 90
135
define rise fall time low value 0
136
define rise fall time high value 3.3
137
define sendmail command "/usr/lib/sendmail"
138
define sequence time width 30.00
139
define snap
140
 
141
define source noprompt
142
define time units default
143
define userdefinedbussymbol
144
define user guide directory "/usr/local/designacc/signalscan-6.7p1/doc/html"
145
define waveform window grid off
146
define waveform window waveheight 14
147
define waveform window wavespace 6
148
define web browser command netscape
149
define zoom outfull on initial add off
150
add group \
151
    A \
152
 
153
add group \
154
    "WISHBONE common" \
155 364 olof
      tb_ethernet.ethmac.wb_clk_i \
156
      tb_ethernet.ethmac.wb_rst_i \
157
      tb_ethernet.ethmac.wb_dat_i[31:0]'h \
158
      tb_ethernet.ethmac.wb_dat_o[31:0]'h \
159
      tb_ethernet.ethmac.wb_err_o \
160 172 mohor
 
161
add group \
162
    "WISHBONE slave signals" \
163 319 tadejm
      tb_ethernet.eth_sl_wb_dat_i[31:0]'h \
164
      tb_ethernet.eth_sl_wb_dat_o[31:0]'h \
165 364 olof
      tb_ethernet.ethmac.wb_adr_i[11:2]'h \
166
      tb_ethernet.ethmac.wb_sel_i[3:0]'h \
167
      tb_ethernet.ethmac.wb_we_i \
168
      tb_ethernet.ethmac.wb_cyc_i \
169
      tb_ethernet.ethmac.wb_stb_i \
170
      tb_ethernet.ethmac.wb_ack_o \
171 172 mohor
 
172
add group \
173
    "WISHBONE master signals" \
174 364 olof
      tb_ethernet.ethmac.m_wb_adr_o[31:0]'h \
175
      tb_ethernet.ethmac.m_wb_sel_o[3:0]'h \
176
      tb_ethernet.ethmac.m_wb_we_o \
177
      tb_ethernet.ethmac.m_wb_dat_i[31:0]'h \
178
      tb_ethernet.ethmac.m_wb_dat_o[31:0]'h \
179
      tb_ethernet.ethmac.m_wb_cyc_o \
180
      tb_ethernet.ethmac.m_wb_stb_o \
181
      tb_ethernet.ethmac.m_wb_ack_i \
182
      tb_ethernet.ethmac.m_wb_err_i \
183 172 mohor
 
184
add group \
185 319 tadejm
    "WISHBONE RX memory" \
186 364 olof
      tb_ethernet.ethmac.wishbone.TxLength[15:0]'h \
187
      tb_ethernet.ethmac.wishbone.TxLengthEq0 \
188
      tb_ethernet.ethmac.wishbone.TxLengthLt4 \
189
      tb_ethernet.ethmac.wishbone.TxPointerLSB[1:0]'h \
190
      tb_ethernet.ethmac.wishbone.TxPointerLSB_rst[1:0]'h \
191
      tb_ethernet.ethmac.wishbone.TxPointerMSB[31:2]'h \
192
      tb_ethernet.ethmac.wishbone.TxPointerRead \
193
      tb_ethernet.ethmac.wishbone.TxBDReady \
194
      tb_ethernet.ethmac.wishbone.TxBufferAlmostEmpty \
195
      tb_ethernet.ethmac.wishbone.TxBufferAlmostFull \
196
      tb_ethernet.ethmac.wishbone.TxBufferEmpty \
197
      tb_ethernet.ethmac.wishbone.TxBufferFull \
198
      tb_ethernet.ethmac.wishbone.TxData_wb[31:0]'h \
199
      tb_ethernet.ethmac.wishbone.TxData[7:0]'h \
200
      tb_ethernet.ethmac.wishbone.TxDataLatched[31:0]'h \
201
      tb_ethernet.ethmac.wishbone.TxByteCnt[1:0]'h \
202
      tb_ethernet.ethmac.wishbone.TxStatus[14:11]'h \
203
      tb_ethernet.ethmac.wishbone.TxStatusInLatched[8:0]'h \
204 319 tadejm
      tb_ethernet.test_mac_full_duplex_transmit.max_tmp[15:0]'h \
205
      tb_ethernet.test_mac_full_duplex_transmit.min_tmp[15:0]'h \
206
      tb_ethernet.test_mac_full_duplex_transmit.i_length'h \
207
      tb_ethernet.eth_phy.tx_len[31:0]'h \
208
      tb_ethernet.eth_phy.tx_len_err[31:0]'h \
209
      tb_ethernet.eth_phy.tx_cnt[31:0]'h \
210
      tb_ethernet.eth_phy.tx_byte_aligned_ok \
211
      tb_ethernet.wb_slave.CYC_I \
212
      tb_ethernet.wb_slave.STB_I \
213
      tb_ethernet.wb_slave.WE_I \
214
      tb_ethernet.wb_slave.ADR_I[31:0]'h \
215
      tb_ethernet.wb_slave.DAT_I[31:0]'h \
216
      tb_ethernet.wb_slave.SEL_I[3:0]'h \
217
      tb_ethernet.wb_slave.ACK_O \
218
      tb_ethernet.wb_slave.ERR_O \
219
      tb_ethernet.wb_slave.RTY_O \
220
      tb_ethernet.wb_slave.mem_wr_data_out[31:0]'h \
221
      tb_ethernet.test_mac_full_duplex_receive.num_of_frames's \
222
      tb_ethernet.test_mac_full_duplex_receive.first_fr_received \
223
      tb_ethernet.test_mac_full_duplex_receive.bit_end_1's \
224
      tb_ethernet.test_mac_full_duplex_receive.bit_end_2's \
225
      tb_ethernet.test_mac_full_duplex_receive.bit_start_1's \
226
      tb_ethernet.test_mac_full_duplex_receive.bit_start_2's \
227
      tb_ethernet.test_mac_full_duplex_receive.burst_data[32767:0]'h \
228
      tb_ethernet.test_mac_full_duplex_receive.burst_tmp_data[32767:0]'h \
229
      tb_ethernet.test_mac_full_duplex_receive.check_frame \
230
      tb_ethernet.test_mac_full_duplex_receive.data[31:0]'h \
231
      tb_ethernet.test_mac_full_duplex_receive.end_task[31:0]'h \
232
      tb_ethernet.test_mac_full_duplex_receive.fail's \
233
      tb_ethernet.test_mac_full_duplex_receive.first_fr_received \
234
      tb_ethernet.test_mac_full_duplex_receive.frame_ended \
235
      tb_ethernet.test_mac_full_duplex_receive.frame_started \
236
      tb_ethernet.test_mac_full_duplex_receive.i's \
237
      tb_ethernet.test_mac_full_duplex_receive.i1's \
238
      tb_ethernet.test_mac_full_duplex_receive.i2's \
239
      tb_ethernet.test_mac_full_duplex_receive.i3's \
240
      tb_ethernet.test_mac_full_duplex_receive.i_addr's \
241
      tb_ethernet.test_mac_full_duplex_receive.i_data's \
242
      tb_ethernet.test_mac_full_duplex_receive.i_length's \
243
      tb_ethernet.test_mac_full_duplex_receive.max_tmp[15:0]'h \
244
      tb_ethernet.test_mac_full_duplex_receive.min_tmp[15:0]'h \
245
      tb_ethernet.test_mac_full_duplex_receive.num_of_bd's \
246
      tb_ethernet.test_mac_full_duplex_receive.num_of_frames's \
247
      tb_ethernet.test_mac_full_duplex_receive.num_of_reg's \
248
      tb_ethernet.test_mac_full_duplex_receive.speed's \
249
      tb_ethernet.test_mac_full_duplex_receive.st_data[7:0]'h \
250
      tb_ethernet.test_mac_full_duplex_receive.start_task[31:0]'h \
251
      tb_ethernet.test_mac_full_duplex_receive.stop_checking_frame \
252
      tb_ethernet.test_mac_full_duplex_receive.test_num's \
253
      tb_ethernet.test_mac_full_duplex_receive.tmp[31:0]'h \
254
      tb_ethernet.test_mac_full_duplex_receive.tmp_bd'h \
255
      tb_ethernet.test_mac_full_duplex_receive.tmp_bd_num's \
256
      tb_ethernet.test_mac_full_duplex_receive.tmp_data's \
257
      tb_ethernet.test_mac_full_duplex_receive.tmp_ipgt's \
258
      tb_ethernet.test_mac_full_duplex_receive.tmp_len's \
259
      tb_ethernet.test_mac_full_duplex_receive.tx_bd_num[31:0]'h \
260
      tb_ethernet.test_mac_full_duplex_receive.wait_for_frame \
261
      tb_ethernet.wbm_working \
262
      tb_ethernet.check_rx_packet.addr_phy[31:0]'h \
263
      tb_ethernet.check_rx_packet.addr_wb[31:0]'h \
264
      tb_ethernet.check_rx_packet.buffer[21:0]'h \
265
      tb_ethernet.check_rx_packet.data_phy'h \
266
      tb_ethernet.check_rx_packet.data_wb'h \
267
      tb_ethernet.check_rx_packet.delta_t \
268
      tb_ethernet.check_rx_packet.failure[31:0]'h \
269
      tb_ethernet.check_rx_packet.i's \
270
      tb_ethernet.check_rx_packet.len[15:0]'h \
271
      tb_ethernet.check_rx_packet.plus_dribble_nibble \
272
      tb_ethernet.check_rx_packet.rxpnt_phy[31:0]'h \
273
      tb_ethernet.check_rx_packet.rxpnt_wb[31:0]'h \
274
      tb_ethernet.check_rx_packet.successful_dribble_nibble \
275
      tb_ethernet.wb_slave.rd_mem.adr_i[31:0]'h \
276
      tb_ethernet.wb_slave.rd_mem.dat_o[31:0]'h \
277
      tb_ethernet.wb_slave.rd_mem.sel_i[3:0]'h \
278
      tb_ethernet.wb_slave.ADR_I[31:0]'h \
279
      tb_ethernet.wb_slave.mem_wr_data_out[31:0]'h \
280
      tb_ethernet.wb_slave.SEL_I[3:0]'h \
281
 
282
add group \
283 310 tadejm
    "MAC FIFO" \
284 364 olof
      tb_ethernet.ethmac.wishbone.rx_fifo.write \
285
      tb_ethernet.ethmac.wishbone.rx_fifo.data_in[31:0]'h \
286
      tb_ethernet.ethmac.wishbone.rx_fifo.write_pointer[3:0]'h \
287
      tb_ethernet.ethmac.wishbone.rx_fifo.almost_full \
288
      tb_ethernet.ethmac.wishbone.rx_fifo.full \
289
      tb_ethernet.ethmac.wishbone.rx_fifo.read \
290
      tb_ethernet.ethmac.wishbone.rx_fifo.data_out[31:0]'h \
291
      tb_ethernet.ethmac.wishbone.rx_fifo.read_pointer[3:0]'h \
292
      tb_ethernet.ethmac.wishbone.rx_fifo.almost_empty \
293
      tb_ethernet.ethmac.wishbone.rx_fifo.empty \
294 310 tadejm
 
295
add group \
296
    "MAC registers" \
297 364 olof
      tb_ethernet.ethmac.ethreg1.MODEROut[31:0]'h \
298
      tb_ethernet.ethmac.ethreg1.INT_SOURCEOut[31:0]'h \
299
      tb_ethernet.ethmac.ethreg1.INT_MASKOut[31:0]'h \
300
      tb_ethernet.ethmac.ethreg1.IPGTOut[31:0]'h \
301
      tb_ethernet.ethmac.ethreg1.IPGR1Out[31:0]'h \
302
      tb_ethernet.ethmac.ethreg1.IPGR2Out[31:0]'h \
303
      tb_ethernet.ethmac.ethreg1.PACKETLENOut[31:0]'h \
304
      tb_ethernet.ethmac.ethreg1.COLLCONFOut[31:0]'h \
305
      tb_ethernet.ethmac.ethreg1.TX_BD_NUMOut[31:0]'h \
306
      tb_ethernet.ethmac.ethreg1.CTRLMODEROut[31:0]'h \
307
      tb_ethernet.ethmac.ethreg1.MIIMODEROut[31:0]'h \
308
      tb_ethernet.ethmac.ethreg1.MIICOMMANDOut[31:0]'h \
309
      tb_ethernet.ethmac.ethreg1.MIIADDRESSOut[31:0]'h \
310
      tb_ethernet.ethmac.ethreg1.MIITX_DATAOut[31:0]'h \
311
      tb_ethernet.ethmac.ethreg1.MIIRX_DATAOut[31:0]'h \
312
      tb_ethernet.ethmac.ethreg1.MIISTATUSOut[31:0]'h \
313
      tb_ethernet.ethmac.ethreg1.MAC_ADDR0Out[31:0]'h \
314
      tb_ethernet.ethmac.ethreg1.MAC_ADDR1Out[31:0]'h \
315
      tb_ethernet.ethmac.ethreg1.HASH0Out[31:0]'h \
316
      tb_ethernet.ethmac.ethreg1.HASH1Out[31:0]'h \
317
      tb_ethernet.ethmac.ethreg1.TXCTRLOut[31:0]'h \
318 310 tadejm
 
319
add group \
320
    testbench_test_signals \
321
      tb_ethernet.test_mac_full_duplex_transmit.i_length's \
322
      tb_ethernet.test_mac_full_duplex_transmit.tmp_len's \
323
 
324
add group \
325 172 mohor
    "MAC common" \
326 364 olof
      tb_ethernet.ethmac.mcoll_pad_i \
327
      tb_ethernet.ethmac.mcrs_pad_i \
328 172 mohor
 
329
add group \
330
    "MAC TX" \
331 364 olof
      tb_ethernet.ethmac.mtx_clk_pad_i \
332
      tb_ethernet.ethmac.mtxd_pad_o[3:0]'h \
333
      tb_ethernet.ethmac.mtxen_pad_o \
334
      tb_ethernet.ethmac.mtxerr_pad_o \
335 172 mohor
 
336
add group \
337
    "MAC RX" \
338 364 olof
      tb_ethernet.ethmac.mrx_clk_pad_i \
339
      tb_ethernet.ethmac.mrxd_pad_i[3:0]'h \
340
      tb_ethernet.ethmac.mrxdv_pad_i \
341
      tb_ethernet.ethmac.mrxerr_pad_i \
342 172 mohor
 
343
add group \
344
    "MAC MIIM interface" \
345 364 olof
      tb_ethernet.ethmac.mdc_pad_o \
346
      tb_ethernet.ethmac.md_padoe_o \
347
      tb_ethernet.ethmac.md_pad_o \
348
      tb_ethernet.ethmac.md_pad_i \
349
      tb_ethernet.ethmac.miim1.Busy \
350
      tb_ethernet.ethmac.miim1.LinkFail \
351
      tb_ethernet.ethmac.miim1.Nvalid \
352
      tb_ethernet.ethmac.miim1.CtrlData[15:0]'h \
353
      tb_ethernet.ethmac.miim1.UpdateMIIRX_DATAReg \
354
      tb_ethernet.ethmac.miim1.Prsd[15:0]'h \
355
      tb_ethernet.ethmac.miim1.Divider[7:0]'h \
356 172 mohor
 
357
add group \
358
    "Test signals" \
359
      tb_ethernet.test_name[799:0]'a \
360 364 olof
      tb_ethernet.ethmac.miim1.Nvalid \
361
      tb_ethernet.ethmac.miim1.Busy \
362
      tb_ethernet.ethmac.miim1.LinkFail \
363
      tb_ethernet.ethmac.miim1.WriteDataOp \
364
      tb_ethernet.ethmac.miim1.ReadStatusOp \
365
      tb_ethernet.ethmac.miim1.ScanStatusOp \
366
      tb_ethernet.ethmac.ethreg1.MIISTATUSOut[31:0]'h \
367
      tb_ethernet.ethmac.ethreg1.MIITX_DATAOut[31:0]'h \
368
      tb_ethernet.ethmac.ethreg1.MIIRX_DATAOut[31:0]'h \
369
      tb_ethernet.ethmac.ethreg1.MIIMODEROut[31:0]'h \
370
      tb_ethernet.ethmac.miim1.InProgress \
371
      tb_ethernet.ethmac.miim1.InProgress_q1 \
372
      tb_ethernet.ethmac.miim1.InProgress_q2 \
373
      tb_ethernet.ethmac.miim1.InProgress_q3 \
374
      tb_ethernet.ethmac.miim1.shftrg.ShiftReg[7:0]'h \
375 172 mohor
      tb_ethernet.eth_phy.status_bit6_0[6:0]'h \
376
      tb_ethernet.eth_phy.control_bit8_0[8:0]'h \
377
      tb_ethernet.eth_phy.control_bit9 \
378
      tb_ethernet.eth_phy.control_bit14_10[14:10]'h \
379
      tb_ethernet.eth_phy.control_bit15 \
380
      tb_ethernet.eth_phy.eth_speed \
381
      tb_ethernet.eth_phy.m_rst_n_i \
382
      tb_ethernet.eth_phy.mcoll_o \
383
      tb_ethernet.eth_phy.mcrs_o \
384
      tb_ethernet.eth_phy.md_get_phy_address \
385
      tb_ethernet.eth_phy.md_get_reg_address \
386
      tb_ethernet.eth_phy.md_get_reg_data_in \
387
      tb_ethernet.eth_phy.md_put_reg_data_in \
388
      tb_ethernet.eth_phy.md_put_reg_data_out \
389
      tb_ethernet.eth_phy.reg_data_in[15:0]'h \
390
      tb_ethernet.eth_phy.reg_data_out[15:0]'h \
391
      tb_ethernet.eth_phy.register_bus_in[15:0]'h \
392
      tb_ethernet.eth_phy.register_bus_out[15:0]'h \
393
      tb_ethernet.eth_phy.reg_address[4:0]'h \
394
      tb_ethernet.eth_phy.md_io_output \
395
      tb_ethernet.eth_phy.md_io_enable \
396
      tb_ethernet.eth_phy.md_io \
397
      tb_ethernet.Mdc_O \
398
      tb_ethernet.Mdi_I \
399
      tb_ethernet.Mdio_IO \
400
      tb_ethernet.Mdo_O \
401
      tb_ethernet.Mdo_OE \
402
      tb_ethernet.eth_phy.md_io_enable \
403
      tb_ethernet.eth_phy.md_io_output \
404
      tb_ethernet.eth_phy.md_io_rd_wr \
405
      tb_ethernet.eth_phy.md_io_reg \
406
      tb_ethernet.eth_phy.m_rst_n_i \
407
      tb_ethernet.eth_phy.md_transfer_cnt'd \
408
      tb_ethernet.eth_phy.md_transfer_cnt_reset \
409
      tb_ethernet.eth_phy.mdc_i \
410
      tb_ethernet.eth_phy.mrx_clk_o \
411
      tb_ethernet.eth_phy.mrxd_o[3:0]'h \
412
      tb_ethernet.eth_phy.mrxdv_o \
413
      tb_ethernet.eth_phy.mrxerr_o \
414
      tb_ethernet.eth_phy.mtx_clk_o \
415
      tb_ethernet.eth_phy.mtxd_i[3:0]'h \
416
      tb_ethernet.eth_phy.mtxen_i \
417
      tb_ethernet.eth_phy.mtxerr_i \
418
      tb_ethernet.eth_phy.phy_address[4:0]'h \
419
      tb_ethernet.eth_phy.phy_id1[15:0]'h \
420
      tb_ethernet.eth_phy.phy_id2[15:0]'h \
421
      tb_ethernet.eth_phy.phy_log[31:0]'h \
422
      tb_ethernet.eth_phy.reg_address[4:0]'h \
423
      tb_ethernet.eth_phy.register_bus_in[15:0]'h \
424
      tb_ethernet.eth_phy.register_bus_out[15:0]'h \
425
      tb_ethernet.eth_phy.registers_addr_data_test_operation \
426
      tb_ethernet.eth_phy.rx_link_down_halfperiod \
427
        ( \
428
          minmax 0 93 \
429
        ) \
430
      tb_ethernet.eth_phy.self_clear_d0 \
431
      tb_ethernet.eth_phy.self_clear_d1 \
432
      tb_ethernet.eth_phy.self_clear_d2 \
433
      tb_ethernet.eth_phy.self_clear_d3 \
434
      tb_ethernet.eth_phy.status_bit6_0[6:0]'h \
435
      tb_ethernet.eth_phy.status_bit7 \
436
      tb_ethernet.eth_phy.status_bit8 \
437
      tb_ethernet.eth_phy.status_bit15_9[15:9]'h \
438
 
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