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[/] [fade_ether_protocol/] [trunk/] [stable_jumbo_frames_version/] [fpga/] [src/] [AFCK/] [AFCK_fade_top_8ch.vhd] - Blame information for rev 42

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Line No. Rev Author Line
1 37 wzab 
library ieee;
2 
use ieee.std_logic_1164.all;
3 
use ieee.numeric_std.all;
4 
use work.pkt_ack_pkg.all;
5 
use work.desc_mgr_pkg.all;
6 
library unisim;
7 
use unisim.vcomponents.all;
8 
 
9 
entity afck_10g_2 is
10 
 
11 
  port (
12 
    gtx10g_txn      : out   std_logic_vector(7 downto 0);
13 
    gtx10g_txp      : out   std_logic_vector(7 downto 0);
14 
    gtx10g_rxn      : in    std_logic_vector(7 downto 0);
15 
    gtx10g_rxp      : in    std_logic_vector(7 downto 0);
16 
    gtx_refclk_n    : in    std_logic_vector(1 downto 0);
17 
    gtx_refclk_p    : in    std_logic_vector(1 downto 0);
18 
    gtx_sfp_disable : out   std_logic_vector(7 downto 0);
19 
    gtx_rate_sel    : out   std_logic_vector(7 downto 0);
20 
    -- Heartbit LED
21 
    hb_led          : out   std_logic_vector(2 downto 0);
22 
    -- Pin needed to enable switch matrix
23 
    clk_updaten     : out   std_logic;
24 
    si570_oe        : out   std_logic;
25 
    -- I2C interface t control FM-S14 board
26 
    scl             : inout std_logic;
27 
    sda             : inout std_logic;
28 
    boot_clk        : in    std_logic
29 
    );
30 
 
31 
end afck_10g_2;
32 
 
33 
architecture beh1 of afck_10g_2 is
34 
 
35 
  constant N_OF_LINKS : integer := 4;
36 
  constant N_OF_QUADS : integer := 2;
37 
 
38 
  type T_HB is array (0 to 2) of integer;
39 
  signal heart_bit : T_HB                         := (0, 0, 0);
40 
  signal s_hb_led  : std_logic_vector(2 downto 0) := "000";
41 
 
42 41 wzab 
  signal refclk_p : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
43 
  signal refclk_n : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
44 37 wzab 
  signal reset    : std_logic                               := '0';
45 
  signal rst_p    : std_logic                               := '1';  -- generated reset
46 
  signal rst_cnt  : integer                                 := 20000000;
47 
 
48 
  type T_FRQ_CNT is array (0 to 1) of std_logic_vector(31 downto 0);
49 42 wzab 
  signal frq_user           : T_FRQ_CNT                     := (others => (others => '0'));
50 
  signal clk0_frq, clk1_frq : std_logic_vector(31 downto 0) := (others => '0');
51 37 wzab 
 
52 41 wzab 
  signal s_resetdone     : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
53 
  signal core_clk156_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
54 37 wzab 
 
55 
 
56 
  type T_MAC_TABLE is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(47 downto 0);
57 
  constant mac_table : T_MAC_TABLE := (
58 
 
59 
    1 => x"de_ad_fa_de_01_e2",
60 
    2 => x"de_ad_fa_de_02_e2",
61 
    3 => x"de_ad_fa_de_03_e2",
62 
    4 => x"de_ad_fa_de_04_e2",
63 
    5 => x"de_ad_fa_de_05_e2",
64 
    6 => x"de_ad_fa_de_06_e2",
65 
    7 => x"de_ad_fa_de_07_e2"
66 
    );
67 
 
68 41 wzab 
  signal s_txusrclk_out         : std_logic_vector(N_OF_QUADS-1 downto 0)            := (others => '0');
69 
  signal s_txusrclk2_out        : std_logic_vector(N_OF_QUADS-1 downto 0)            := (others => '0');
70 
  signal areset_clk156_out      : std_logic_vector(N_OF_QUADS-1 downto 0)            := (others => '0');
71 
  signal gttxreset_out          : std_logic_vector(N_OF_QUADS-1 downto 0)            := (others => '0');
72 
  signal gtrxreset_out          : std_logic_vector(N_OF_QUADS-1 downto 0)            := (others => '0');
73 
  signal txuserrdy_out          : std_logic_vector(N_OF_QUADS-1 downto 0)            := (others => '0');
74 
  signal reset_counter_done_out : std_logic_vector(N_OF_QUADS-1 downto 0)            := (others => '0');
75 
  signal qplllock_out           : std_logic_vector(N_OF_QUADS-1 downto 0)            := (others => '0');
76 
  signal qplloutclk_out         : std_logic_vector(N_OF_QUADS-1 downto 0)            := (others => '0');
77 
  signal qplloutrefclk_out      : std_logic_vector(N_OF_QUADS-1 downto 0)            := (others => '0');
78 37 wzab 
  type T_XGMII_XD is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(63 downto 0);
79 
  signal xgmii_txd              : T_XGMII_XD                                         := (others => (others => '0'));
80 
  type T_XGMII_XC is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(7 downto 0);
81 
  signal xgmii_txc              : T_XGMII_XC                                         := (others => (others => '0'));
82 
  signal xgmii_rxd              : T_XGMII_XD                                         := (others => (others => '0'));
83 
  signal xgmii_rxc              : T_XGMII_XC                                         := (others => (others => '0'));
84 
  signal configuration_vector   : std_logic_vector(535 downto 0)                     := (others => '0');
85 
  type T_STATUS_VEC is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(447 downto 0);
86 
  signal status_vector          : T_STATUS_VEC                                       := (others => (others => '0'));
87 
  type T_CORE_STATUS is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(7 downto 0);
88 
  signal core_status            : T_CORE_STATUS                                      := (others => (others => '0'));
89 
  signal signal_detect          : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
90 
  signal tx_fault               : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
91 
  signal drp_req                : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
92 
  signal drp_gnt                : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
93 
  signal drp_den_o              : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
94 
  signal drp_dwe_o              : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
95 
  type T_DRP_V16 is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(15 downto 0);
96 
  signal drp_daddr_o            : T_DRP_V16                                          := (others => (others => '0'));
97 
  signal drp_di_o               : T_DRP_V16                                          := (others => (others => '0'));
98 
  signal drp_drdy_o             : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
99 
  signal drp_drpdo_o            : T_DRP_V16                                          := (others => (others => '0'));
100 
  signal drp_den_i              : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
101 
  signal drp_dwe_i              : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
102 
 
103 
  signal drp_daddr_i : T_DRP_V16                                          := (others => (others => '0'));
104 
  signal drp_di_i    : T_DRP_V16                                          := (others => (others => '0'));
105 
  signal drp_drdy_i  : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
106 
  signal drp_drpdo_i : T_DRP_V16                                          := (others => (others => '0'));
107 
  signal tx_disable  : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
108 
 
109 
  --signal counter              : integer   := 0;
110 
  --signal probe2               : std_logic_vector(2 downto 0);
111 
  --signal trig_in, trig_in_ack : std_logic := '0';
112 
  signal rst_n      : std_logic := '0';
113 
  signal rst1, clk1 : std_logic := '0';
114 
  signal clk_user   : std_logic_vector(N_OF_QUADS-1 downto 0);
115 
 
116 
  component ten_gig_eth_pcs_pma_0 is
117 
    port (
118 
      dclk                   : in  std_logic;
119 41 wzab 
      rxrecclk_out           : out std_logic;
120 37 wzab 
      refclk_p               : in  std_logic;
121 
      refclk_n               : in  std_logic;
122 
      sim_speedup_control    : in  std_logic;
123 41 wzab 
      coreclk_out            : out std_logic;
124 37 wzab 
      qplloutclk_out         : out std_logic;
125 
      qplloutrefclk_out      : out std_logic;
126 
      qplllock_out           : out std_logic;
127 
      txusrclk_out           : out std_logic;
128 
      txusrclk2_out          : out std_logic;
129 42 wzab 
      areset_datapathclk_out : out std_logic;
130 37 wzab 
      gttxreset_out          : out std_logic;
131 
      gtrxreset_out          : out std_logic;
132 
      txuserrdy_out          : out std_logic;
133 
      reset_counter_done_out : out std_logic;
134 
      reset                  : in  std_logic;
135 
      gt0_eyescanreset       : in  std_logic;
136 
      gt0_eyescantrigger     : in  std_logic;
137 
      gt0_rxcdrhold          : in  std_logic;
138 
      gt0_txprbsforceerr     : in  std_logic;
139 
      gt0_txpolarity         : in  std_logic;
140 
      gt0_rxpolarity         : in  std_logic;
141 
      gt0_rxrate             : in  std_logic_vector (2 downto 0);
142 
      gt0_txpmareset         : in  std_logic;
143 
      gt0_rxpmareset         : in  std_logic;
144 
      gt0_rxdfelpmreset      : in  std_logic;
145 
      gt0_txprecursor        : in  std_logic_vector (4 downto 0);
146 
      gt0_txpostcursor       : in  std_logic_vector (4 downto 0);
147 
      gt0_txdiffctrl         : in  std_logic_vector (3 downto 0);
148 
      gt0_rxlpmen            : in  std_logic;
149 
      gt0_eyescandataerror   : out std_logic;
150 
      gt0_txbufstatus        : out std_logic_vector (1 downto 0);
151 
      gt0_txresetdone        : out std_logic;
152 
      gt0_rxresetdone        : out std_logic;
153 
      gt0_rxbufstatus        : out std_logic_vector (2 downto 0);
154 
      gt0_rxprbserr          : out std_logic;
155 
      gt0_dmonitorout        : out std_logic_vector (7 downto 0);
156 
      xgmii_txd              : in  std_logic_vector (63 downto 0);
157 
      xgmii_txc              : in  std_logic_vector (7 downto 0);
158 
      xgmii_rxd              : out std_logic_vector (63 downto 0);
159 
      xgmii_rxc              : out std_logic_vector (7 downto 0);
160 
      txp                    : out std_logic;
161 
      txn                    : out std_logic;
162 
      rxp                    : in  std_logic;
163 
      rxn                    : in  std_logic;
164 
      configuration_vector   : in  std_logic_vector (535 downto 0);
165 
      status_vector          : out std_logic_vector (447 downto 0);
166 
      core_status            : out std_logic_vector (7 downto 0);
167 41 wzab 
      resetdone_out          : out std_logic;
168 37 wzab 
      signal_detect          : in  std_logic;
169 
      tx_fault               : in  std_logic;
170 
      drp_req                : out std_logic;
171 
      drp_gnt                : in  std_logic;
172 
      drp_den_o              : out std_logic;
173 
      drp_dwe_o              : out std_logic;
174 
      drp_daddr_o            : out std_logic_vector (15 downto 0);
175 
      drp_di_o               : out std_logic_vector (15 downto 0);
176 
      drp_drdy_i             : in  std_logic;
177 
      drp_drpdo_i            : in  std_logic_vector (15 downto 0);
178 
      drp_den_i              : in  std_logic;
179 
      drp_dwe_i              : in  std_logic;
180 
      drp_daddr_i            : in  std_logic_vector (15 downto 0);
181 
      drp_di_i               : in  std_logic_vector (15 downto 0);
182 
      drp_drdy_o             : out std_logic;
183 
      drp_drpdo_o            : out std_logic_vector (15 downto 0);
184 
      pma_pmd_type           : in  std_logic_vector (2 downto 0);
185 
      tx_disable             : out std_logic);
186 
  end component ten_gig_eth_pcs_pma_0;
187 
 
188 
  component ten_gig_eth_pcs_pma_1 is
189 
    port (
190 
      dclk                 : in  std_logic;
191 42 wzab 
      rxrecclk_out         : out std_logic;
192 
      coreclk              : in  std_logic;
193 37 wzab 
      txusrclk             : in  std_logic;
194 
      txusrclk2            : in  std_logic;
195 41 wzab 
      txoutclk             : out std_logic;
196 37 wzab 
      areset               : in  std_logic;
197 42 wzab 
      areset_coreclk       : in  std_logic;
198 37 wzab 
      gttxreset            : in  std_logic;
199 
      gtrxreset            : in  std_logic;
200 
      sim_speedup_control  : in  std_logic;
201 
      txuserrdy            : in  std_logic;
202 
      qplllock             : in  std_logic;
203 
      qplloutclk           : in  std_logic;
204 
      qplloutrefclk        : in  std_logic;
205 
      reset_counter_done   : in  std_logic;
206 
      gt0_eyescanreset     : in  std_logic;
207 
      gt0_eyescantrigger   : in  std_logic;
208 
      gt0_rxcdrhold        : in  std_logic;
209 
      gt0_txprbsforceerr   : in  std_logic;
210 
      gt0_txpolarity       : in  std_logic;
211 
      gt0_rxpolarity       : in  std_logic;
212 
      gt0_rxrate           : in  std_logic_vector (2 downto 0);
213 
      gt0_txpmareset       : in  std_logic;
214 
      gt0_rxpmareset       : in  std_logic;
215 
      gt0_rxdfelpmreset    : in  std_logic;
216 
      gt0_txprecursor      : in  std_logic_vector (4 downto 0);
217 
      gt0_txpostcursor     : in  std_logic_vector (4 downto 0);
218 
      gt0_txdiffctrl       : in  std_logic_vector (3 downto 0);
219 
      gt0_rxlpmen          : in  std_logic;
220 
      gt0_eyescandataerror : out std_logic;
221 
      gt0_txbufstatus      : out std_logic_vector (1 downto 0);
222 
      gt0_txresetdone      : out std_logic;
223 
      gt0_rxresetdone      : out std_logic;
224 
      gt0_rxbufstatus      : out std_logic_vector (2 downto 0);
225 
      gt0_rxprbserr        : out std_logic;
226 
      gt0_dmonitorout      : out std_logic_vector (7 downto 0);
227 
      xgmii_txd            : in  std_logic_vector (63 downto 0);
228 
      xgmii_txc            : in  std_logic_vector (7 downto 0);
229 
      xgmii_rxd            : out std_logic_vector (63 downto 0);
230 
      xgmii_rxc            : out std_logic_vector (7 downto 0);
231 
      txp                  : out std_logic;
232 
      txn                  : out std_logic;
233 
      rxp                  : in  std_logic;
234 
      rxn                  : in  std_logic;
235 
      configuration_vector : in  std_logic_vector (535 downto 0);
236 
      status_vector        : out std_logic_vector (447 downto 0);
237 
      core_status          : out std_logic_vector (7 downto 0);
238 
      tx_resetdone         : out std_logic;
239 
      rx_resetdone         : out std_logic;
240 
      signal_detect        : in  std_logic;
241 
      tx_fault             : in  std_logic;
242 
      drp_req              : out std_logic;
243 
      drp_gnt              : in  std_logic;
244 
      drp_den_o            : out std_logic;
245 
      drp_dwe_o            : out std_logic;
246 
      drp_daddr_o          : out std_logic_vector (15 downto 0);
247 
      drp_di_o             : out std_logic_vector (15 downto 0);
248 
      drp_drdy_i           : in  std_logic;
249 
      drp_drpdo_i          : in  std_logic_vector (15 downto 0);
250 
      drp_den_i            : in  std_logic;
251 
      drp_dwe_i            : in  std_logic;
252 
      drp_daddr_i          : in  std_logic_vector (15 downto 0);
253 
      drp_di_i             : in  std_logic_vector (15 downto 0);
254 
      drp_drdy_o           : out std_logic;
255 
      drp_drpdo_o          : out std_logic_vector (15 downto 0);
256 
      pma_pmd_type         : in  std_logic_vector (2 downto 0);
257 
      tx_disable           : out std_logic);
258 
  end component ten_gig_eth_pcs_pma_1;
259 
 
260 
  component fade_one_channel is
261 
    generic (
262 
      my_mac : std_logic_vector(47 downto 0));
263 
    port (
264 
      xgmii_txd : out std_logic_vector(63 downto 0);
265 
      xgmii_txc : out std_logic_vector(7 downto 0);
266 
      xgmii_rxd : in  std_logic_vector(63 downto 0);
267 
      xgmii_rxc : in  std_logic_vector(7 downto 0);
268 
      rst_n     : in  std_logic;
269 
      clk_user  : in  std_logic);
270 
  end component fade_one_channel;
271 
 
272 
  component frq_counter is
273 
    generic (
274 
      CNT_TIME   : integer;
275 
      CNT_LENGTH : integer);
276 
    port (
277 
      ref_clk : in  std_logic;
278 
      rst_p   : in  std_logic;
279 
      frq_in  : in  std_logic;
280 
      frq_out : out std_logic_vector(CNT_LENGTH-1 downto 0));
281 
  end component frq_counter;
282 42 wzab 
 
283 37 wzab 
  component vio_stat is
284 
    port (
285 
      clk       : in std_logic;
286 
      probe_in0 : in std_logic_vector(7 downto 0);
287 
      probe_in1 : in std_logic_vector(7 downto 0);
288 
      probe_in2 : in std_logic_vector(7 downto 0);
289 
      probe_in3 : in std_logic_vector(7 downto 0);
290 
      probe_in4 : in std_logic_vector(7 downto 0);
291 
      probe_in5 : in std_logic_vector(7 downto 0);
292 
      probe_in6 : in std_logic_vector(7 downto 0);
293 
      probe_in7 : in std_logic_vector(7 downto 0)
294 
      );
295 
  end component;
296 
 
297 
begin  -- beh1
298 42 wzab 
  si570_oe                  <= '1';
299 
  clk_updaten               <= '1';
300 37 wzab 
  -- Initialization vector
301 
  --configuration_vector(0) <= '1';     -- PMA loopback
302 
  --configuration_vector(110) <= '1';     -- PCS loopback
303 
  configuration_vector(33)  <= '1';     -- training
304 
  configuration_vector(284) <= '1';     -- auto negotiation
305 
 
306 
  signal_detect   <= (others => '1');   -- allow transmission!
307 
  gtx_sfp_disable <= (others => '0');
308 42 wzab 
  gtx_rate_sel    <= (others => '1');
309 37 wzab 
 
310 
  -- Reset generator
311 
  process (boot_clk) is
312 
  begin  -- process
313 
    if boot_clk'event and boot_clk = '1' then  -- rising clock edge
314 
      if rst_cnt > 0 then
315 
        rst_cnt <= rst_cnt - 1;
316 
      else
317 
        rst_p <= '0';
318 
      end if;
319 
    end if;
320 
  end process;
321 
 
322 
 
323 
  rst_n    <= not rst_p;
324 
  refclk_n <= gtx_refclk_n;
325 
  refclk_p <= gtx_refclk_p;
326 
  reset    <= not rst_n;
327 
 
328 
  --trig_in <= '1' when xgmii_rxc /= x"ff" else '0';
329 
 
330 
  gl1 : for q in 0 to N_OF_QUADS-1 generate
331 
    gl2 : for n in 0 to N_OF_LINKS-1 generate
332 
 
333 
      il1 : if n = 0 generate
334 41 wzab 
 
335 37 wzab 
        ten_gig_eth_pcs_pma_0_1 : ten_gig_eth_pcs_pma_0
336 
          port map (
337 
            dclk                   => core_clk156_out(q),
338 42 wzab 
            rxrecclk_out           => open,  --??
339 37 wzab 
            refclk_p               => refclk_p(q),
340 
            refclk_n               => refclk_n(q),
341 41 wzab 
            sim_speedup_control    => '0',
342 42 wzab 
            coreclk_out            => core_clk156_out(q),
343 41 wzab 
            qplloutclk_out         => qplloutclk_out(q),
344 
            qplloutrefclk_out      => qplloutrefclk_out(q),
345 
            qplllock_out           => qplllock_out(q),
346 37 wzab 
            txusrclk_out           => s_txusrclk_out(q),
347 
            txusrclk2_out          => s_txusrclk2_out(q),
348 42 wzab 
            areset_datapathclk_out => areset_clk156_out(q),
349 37 wzab 
            gttxreset_out          => gttxreset_out(q),
350 
            gtrxreset_out          => gtrxreset_out(q),
351 
            txuserrdy_out          => txuserrdy_out(q),
352 
            reset_counter_done_out => reset_counter_done_out(q),
353 41 wzab 
            reset                  => reset,
354 
            gt0_eyescanreset       => '0',
355 
            gt0_eyescantrigger     => '0',
356 
            gt0_rxcdrhold          => '0',
357 
            gt0_txprbsforceerr     => '0',
358 
            gt0_txpolarity         => '0',
359 
            gt0_rxpolarity         => '0',
360 
            gt0_rxrate             => (others => '0'),
361 
            gt0_txpmareset         => '0',
362 
            gt0_rxpmareset         => '0',
363 
            gt0_rxdfelpmreset      => '0',
364 
            gt0_txprecursor        => (others => '0'),
365 
            gt0_txpostcursor       => (others => '0'),
366 
            gt0_txdiffctrl         => "1110",
367 
            gt0_rxlpmen            => '0',
368 
            gt0_eyescandataerror   => open,
369 
            gt0_txbufstatus        => open,
370 
            gt0_txresetdone        => open,
371 
            gt0_rxresetdone        => open,
372 
            gt0_rxbufstatus        => open,
373 
            gt0_rxprbserr          => open,
374 
            gt0_dmonitorout        => open,
375 37 wzab 
            xgmii_txd              => xgmii_txd(q*N_OF_LINKS+n),
376 
            xgmii_txc              => xgmii_txc(q*N_OF_LINKS+n),
377 
            xgmii_rxd              => xgmii_rxd(q*N_OF_LINKS+n),
378 
            xgmii_rxc              => xgmii_rxc(q*N_OF_LINKS+n),
379 41 wzab 
            txp                    => gtx10g_txp(q*N_OF_LINKS+n),
380 
            txn                    => gtx10g_txn(q*N_OF_LINKS+n),
381 
            rxp                    => gtx10g_rxp(q*N_OF_LINKS+n),
382 
            rxn                    => gtx10g_rxn(q*N_OF_LINKS+n),
383 37 wzab 
            configuration_vector   => configuration_vector,
384 
            status_vector          => status_vector(q*N_OF_LINKS+n),
385 
            core_status            => core_status(q*N_OF_LINKS+n),
386 41 wzab 
            resetdone_out          => s_resetdone(q),
387 37 wzab 
            signal_detect          => signal_detect(q*N_OF_LINKS+n),
388 
            tx_fault               => tx_fault(q*N_OF_LINKS+n),
389 
            drp_req                => drp_req(q*N_OF_LINKS+n),
390 
            drp_gnt                => drp_gnt(q*N_OF_LINKS+n),
391 
            drp_den_o              => drp_den_o(q*N_OF_LINKS+n),
392 
            drp_dwe_o              => drp_dwe_o(q*N_OF_LINKS+n),
393 
            drp_daddr_o            => drp_daddr_o(q*N_OF_LINKS+n),
394 
            drp_di_o               => drp_di_o(q*N_OF_LINKS+n),
395 41 wzab 
            drp_drdy_i             => drp_drdy_i(q*N_OF_LINKS+n),
396 
            drp_drpdo_i            => drp_drpdo_i(q*N_OF_LINKS+n),
397 37 wzab 
            drp_den_i              => drp_den_i(q*N_OF_LINKS+n),
398 
            drp_dwe_i              => drp_dwe_i(q*N_OF_LINKS+n),
399 
            drp_daddr_i            => drp_daddr_i(q*N_OF_LINKS+n),
400 
            drp_di_i               => drp_di_i(q*N_OF_LINKS+n),
401 41 wzab 
            drp_drdy_o             => drp_drdy_o(q*N_OF_LINKS+n),
402 
            drp_drpdo_o            => drp_drpdo_o(q*N_OF_LINKS+n),
403 37 wzab 
            pma_pmd_type           => "111",
404 41 wzab 
            tx_disable             => tx_disable(q*N_OF_LINKS+n)
405 37 wzab 
            );
406 
 
407 
      end generate il1;
408 
      il2 : if n /= 0 generate
409 
        ten_gig_eth_pcs_pma_1_1 : entity work.ten_gig_eth_pcs_pma_1
410 
          port map (
411 
            dclk                 => core_clk156_out(q),
412 42 wzab 
            rxrecclk_out         => open,  --??
413 
            coreclk              => core_clk156_out(q),
414 37 wzab 
            txusrclk             => s_txusrclk_out(q),
415 
            txusrclk2            => s_txusrclk2_out(q),
416 
            areset               => reset,
417 42 wzab 
            areset_coreclk       => areset_clk156_out(q),
418 37 wzab 
            gttxreset            => gttxreset_out(q),
419 
            gtrxreset            => gtrxreset_out(q),
420 
            sim_speedup_control  => '0',
421 
            txuserrdy            => txuserrdy_out(q),
422 
            qplllock             => qplllock_out(q),
423 
            qplloutclk           => qplloutclk_out(q),
424 
            qplloutrefclk        => qplloutrefclk_out(q),
425 
            reset_counter_done   => reset_counter_done_out(q),
426 
            gt0_eyescanreset     => '0',
427 
            gt0_eyescantrigger   => '0',
428 
            gt0_rxcdrhold        => '0',
429 
            gt0_txprbsforceerr   => '0',
430 
            gt0_txpolarity       => '0',
431 
            gt0_rxpolarity       => '0',
432 
            gt0_rxrate           => (others => '0'),
433 
            gt0_txpmareset       => '0',
434 
            gt0_rxpmareset       => '0',
435 
            gt0_rxdfelpmreset    => '0',
436 
            gt0_txprecursor      => (others => '0'),
437 
            gt0_txpostcursor     => (others => '0'),
438 
            gt0_txdiffctrl       => "1110",
439 
            gt0_rxlpmen          => '0',
440 
            gt0_eyescandataerror => open,
441 
            gt0_txbufstatus      => open,
442 
            gt0_txresetdone      => open,
443 
            gt0_rxresetdone      => open,
444 
            gt0_rxbufstatus      => open,
445 
            gt0_rxprbserr        => open,
446 
            gt0_dmonitorout      => open,
447 
            xgmii_txd            => xgmii_txd(q*N_OF_LINKS+n),
448 
            xgmii_txc            => xgmii_txc(q*N_OF_LINKS+n),
449 
            xgmii_rxd            => xgmii_rxd(q*N_OF_LINKS+n),
450 
            xgmii_rxc            => xgmii_rxc(q*N_OF_LINKS+n),
451 
            txp                  => gtx10g_txp(q*N_OF_LINKS+n),
452 
            txn                  => gtx10g_txn(q*N_OF_LINKS+n),
453 
            rxp                  => gtx10g_rxp(q*N_OF_LINKS+n),
454 
            rxn                  => gtx10g_rxn(q*N_OF_LINKS+n),
455 
            configuration_vector => configuration_vector,
456 
            status_vector        => status_vector(q*N_OF_LINKS+n),
457 
            core_status          => core_status(q*N_OF_LINKS+n),
458 
            tx_resetdone         => open,
459 
            rx_resetdone         => open,
460 
            signal_detect        => signal_detect(q*N_OF_LINKS+n),
461 
            tx_fault             => tx_fault(q*N_OF_LINKS+n),
462 
            drp_req              => drp_req(q*N_OF_LINKS+n),
463 
            drp_gnt              => drp_gnt(q*N_OF_LINKS+n),
464 
            drp_den_o            => drp_den_o(q*N_OF_LINKS+n),
465 
            drp_dwe_o            => drp_dwe_o(q*N_OF_LINKS+n),
466 
            drp_daddr_o          => drp_daddr_o(q*N_OF_LINKS+n),
467 
            drp_di_o             => drp_di_o(q*N_OF_LINKS+n),
468 
            drp_drdy_i           => drp_drdy_i(q*N_OF_LINKS+n),
469 
            drp_drpdo_i          => drp_drpdo_i(q*N_OF_LINKS+n),
470 
            drp_den_i            => drp_den_i(q*N_OF_LINKS+n),
471 
            drp_dwe_i            => drp_dwe_i(q*N_OF_LINKS+n),
472 
            drp_daddr_i          => drp_daddr_i(q*N_OF_LINKS+n),
473 
            drp_di_i             => drp_di_i(q*N_OF_LINKS+n),
474 
            drp_drdy_o           => drp_drdy_o(q*N_OF_LINKS+n),
475 
            drp_drpdo_o          => drp_drpdo_o(q*N_OF_LINKS+n),
476 
            pma_pmd_type         => "111",
477 
            tx_disable           => tx_disable(q*N_OF_LINKS+n));
478 
      end generate il2;
479 
 
480 
      drp_gnt(q*N_OF_LINKS+n)     <= drp_req(q*N_OF_LINKS+n);
481 
      drp_den_i(q*N_OF_LINKS+n)   <= drp_den_o(q*N_OF_LINKS+n);
482 
      drp_dwe_i(q*N_OF_LINKS+n)   <= drp_dwe_o(q*N_OF_LINKS+n);
483 
      drp_daddr_i(q*N_OF_LINKS+n) <= drp_daddr_o(q*N_OF_LINKS+n);
484 
      drp_di_i(q*N_OF_LINKS+n)    <= drp_di_o(q*N_OF_LINKS+n);
485 
      drp_drpdo_i(q*N_OF_LINKS+n) <= drp_drpdo_o(q*N_OF_LINKS+n);
486 
 
487 
      fade_one_channel_1 : entity work.fade_one_channel
488 
        generic map (
489 
          my_mac => mac_table(q*N_OF_LINKS+n))
490 
        port map (
491 
          xgmii_txd => xgmii_txd(q*N_OF_LINKS+n),
492 
          xgmii_txc => xgmii_txc(q*N_OF_LINKS+n),
493 
          xgmii_rxd => xgmii_rxd(q*N_OF_LINKS+n),
494 
          xgmii_rxc => xgmii_rxc(q*N_OF_LINKS+n),
495 
          rst_n     => rst_n,
496 
          clk_user  => clk_user(q));
497 
 
498 42 wzab 
 
499 37 wzab 
    end generate gl2;
500 
 
501 42 wzab 
    frq_counter_1 : entity work.frq_counter
502 
      generic map (
503 
        CNT_TIME   => 20000000,
504 
        CNT_LENGTH => 32)
505 
      port map (
506 
        ref_clk => boot_clk,
507 
        rst_p   => rst_p,
508 
        frq_in  => clk_user(q),
509 
        frq_out => frq_user(q));
510 37 wzab 
 
511 
 
512 
  end generate gl1;
513 
 
514 
  clk0_frq <= frq_user(0);
515 
  clk1_frq <= frq_user(1);
516 42 wzab 
 
517 37 wzab 
  rst1     <= core_status(0)(0);
518 
  --core_ready <= core_status(0);
519 
  clk1     <= boot_clk;
520 
  clk_user <= core_clk156_out;
521 
 
522 
  -- Frequency meters
523 
  vio_frq_1 : entity work.vio_frq
524 
    port map (
525 
      clk       => boot_clk,
526 
      probe_in0 => clk0_frq,
527 
      probe_in1 => clk1_frq);
528 
 
529 
  -- Vio Link statuses
530 
  vio_stat_1 : entity work.vio_stat
531 
    port map (
532 
      clk       => boot_clk,
533 
      probe_in0 => core_status(0),
534 
      probe_in1 => core_status(1),
535 
      probe_in2 => core_status(2),
536 
      probe_in3 => core_status(3),
537 
      probe_in4 => core_status(4),
538 
      probe_in5 => core_status(5),
539 
      probe_in6 => core_status(6),
540 
      probe_in7 => core_status(7));
541 
 
542 
  -- JTAG<->I2C part for clock-crossbar
543 
  i2c_vio_ctrl_1 : entity work.i2c_vio_ctrl
544 
    port map (
545 
      clk => boot_clk,
546 
      scl => scl,
547 
      sda => sda);
548 
 
549 41 wzab 
  gld1 : for i in 0 to N_OF_QUADS-1 generate
550 37 wzab 
    p1 : process (clk_user(i), rst_n)
551 
    begin  -- process p1
552 
      if rst_n = '0' then               -- asynchronous reset (active low)
553 
        heart_bit(i) <= 0;
554 
      elsif clk_user(i)'event and clk_user(i) = '1' then  -- rising clock edge
555 
        if heart_bit(i) < 80000000 then
556 
          heart_bit(i) <= heart_bit(i) + 1;
557 
        else
558 
          heart_bit(i) <= 0;
559 
          s_hb_led(i)  <= not s_hb_led(i);
560 
        end if;
561 
      end if;
562 
    end process p1;
563 
 
564 
  end generate gld1;
565 
 
566 
  p2 : process (boot_clk, rst_n)
567 
  begin  -- process p1
568 
    if rst_n = '0' then                 -- asynchronous reset (active low)
569 
      heart_bit(2) <= 0;
570 
    elsif boot_clk'event and boot_clk = '1' then  -- rising clock edge
571 
      if heart_bit(2) < 10000000 then
572 
        heart_bit(2) <= heart_bit(2) + 1;
573 
      else
574 
        heart_bit(2) <= 0;
575 
        s_hb_led(2)  <= not s_hb_led(2);
576 
      end if;
577 
    end if;
578 
  end process p2;
579 
 
580 
  hb_led <= s_hb_led;
581 
 
582 
end beh1;

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