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wzab |
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.pkt_ack_pkg.all;
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use work.desc_mgr_pkg.all;
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library unisim;
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use unisim.vcomponents.all;
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entity afck_10g_2 is
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port (
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gtx10g_txn : out std_logic_vector(7 downto 0);
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gtx10g_txp : out std_logic_vector(7 downto 0);
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gtx10g_rxn : in std_logic_vector(7 downto 0);
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gtx10g_rxp : in std_logic_vector(7 downto 0);
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gtx_refclk_n : in std_logic_vector(1 downto 0);
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gtx_refclk_p : in std_logic_vector(1 downto 0);
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gtx_sfp_disable : out std_logic_vector(7 downto 0);
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gtx_rate_sel : out std_logic_vector(7 downto 0);
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-- Heartbit LED
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hb_led : out std_logic_vector(2 downto 0);
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-- Pin needed to enable switch matrix
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clk_updaten : out std_logic;
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si570_oe : out std_logic;
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-- I2C interface t control FM-S14 board
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scl : inout std_logic;
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sda : inout std_logic;
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boot_clk : in std_logic
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);
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end afck_10g_2;
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architecture beh1 of afck_10g_2 is
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constant N_OF_LINKS : integer := 4;
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constant N_OF_QUADS : integer := 2;
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type T_HB is array (0 to 2) of integer;
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signal heart_bit : T_HB := (0, 0, 0);
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signal s_hb_led : std_logic_vector(2 downto 0) := "000";
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wzab |
signal refclk_p : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
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signal refclk_n : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
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wzab |
signal reset : std_logic := '0';
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signal rst_p : std_logic := '1'; -- generated reset
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signal rst_cnt : integer := 20000000;
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type T_FRQ_CNT is array (0 to 1) of std_logic_vector(31 downto 0);
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wzab |
signal frq_user : T_FRQ_CNT := (others => (others => '0'));
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signal clk0_frq, clk1_frq : std_logic_vector(31 downto 0) := (others => '0');
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37 |
wzab |
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wzab |
signal s_resetdone : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
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signal core_clk156_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
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37 |
wzab |
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type T_MAC_TABLE is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(47 downto 0);
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constant mac_table : T_MAC_TABLE := (
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1 => x"de_ad_fa_de_01_e2",
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2 => x"de_ad_fa_de_02_e2",
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3 => x"de_ad_fa_de_03_e2",
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4 => x"de_ad_fa_de_04_e2",
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5 => x"de_ad_fa_de_05_e2",
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6 => x"de_ad_fa_de_06_e2",
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7 => x"de_ad_fa_de_07_e2"
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);
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wzab |
signal s_txusrclk_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
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signal s_txusrclk2_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
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signal areset_clk156_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
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signal gttxreset_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
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signal gtrxreset_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
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signal txuserrdy_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
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signal reset_counter_done_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
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signal qplllock_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
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signal qplloutclk_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
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signal qplloutrefclk_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
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wzab |
type T_XGMII_XD is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(63 downto 0);
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signal xgmii_txd : T_XGMII_XD := (others => (others => '0'));
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type T_XGMII_XC is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(7 downto 0);
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signal xgmii_txc : T_XGMII_XC := (others => (others => '0'));
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signal xgmii_rxd : T_XGMII_XD := (others => (others => '0'));
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signal xgmii_rxc : T_XGMII_XC := (others => (others => '0'));
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signal configuration_vector : std_logic_vector(535 downto 0) := (others => '0');
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type T_STATUS_VEC is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(447 downto 0);
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signal status_vector : T_STATUS_VEC := (others => (others => '0'));
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type T_CORE_STATUS is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(7 downto 0);
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signal core_status : T_CORE_STATUS := (others => (others => '0'));
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signal signal_detect : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
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signal tx_fault : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_req : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_gnt : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_den_o : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_dwe_o : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
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type T_DRP_V16 is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(15 downto 0);
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signal drp_daddr_o : T_DRP_V16 := (others => (others => '0'));
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signal drp_di_o : T_DRP_V16 := (others => (others => '0'));
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signal drp_drdy_o : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_drpdo_o : T_DRP_V16 := (others => (others => '0'));
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signal drp_den_i : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_dwe_i : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_daddr_i : T_DRP_V16 := (others => (others => '0'));
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signal drp_di_i : T_DRP_V16 := (others => (others => '0'));
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signal drp_drdy_i : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_drpdo_i : T_DRP_V16 := (others => (others => '0'));
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signal tx_disable : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0');
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--signal counter : integer := 0;
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--signal probe2 : std_logic_vector(2 downto 0);
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--signal trig_in, trig_in_ack : std_logic := '0';
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signal rst_n : std_logic := '0';
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signal rst1, clk1 : std_logic := '0';
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signal clk_user : std_logic_vector(N_OF_QUADS-1 downto 0);
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component ten_gig_eth_pcs_pma_0 is
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port (
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dclk : in std_logic;
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41 |
wzab |
rxrecclk_out : out std_logic;
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37 |
wzab |
refclk_p : in std_logic;
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refclk_n : in std_logic;
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sim_speedup_control : in std_logic;
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41 |
wzab |
coreclk_out : out std_logic;
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37 |
wzab |
qplloutclk_out : out std_logic;
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qplloutrefclk_out : out std_logic;
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qplllock_out : out std_logic;
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txusrclk_out : out std_logic;
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txusrclk2_out : out std_logic;
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wzab |
areset_datapathclk_out : out std_logic;
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wzab |
gttxreset_out : out std_logic;
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gtrxreset_out : out std_logic;
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txuserrdy_out : out std_logic;
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reset_counter_done_out : out std_logic;
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reset : in std_logic;
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gt0_eyescanreset : in std_logic;
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gt0_eyescantrigger : in std_logic;
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gt0_rxcdrhold : in std_logic;
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gt0_txprbsforceerr : in std_logic;
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gt0_txpolarity : in std_logic;
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gt0_rxpolarity : in std_logic;
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gt0_rxrate : in std_logic_vector (2 downto 0);
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gt0_txpmareset : in std_logic;
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gt0_rxpmareset : in std_logic;
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gt0_rxdfelpmreset : in std_logic;
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gt0_txprecursor : in std_logic_vector (4 downto 0);
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gt0_txpostcursor : in std_logic_vector (4 downto 0);
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gt0_txdiffctrl : in std_logic_vector (3 downto 0);
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gt0_rxlpmen : in std_logic;
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gt0_eyescandataerror : out std_logic;
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gt0_txbufstatus : out std_logic_vector (1 downto 0);
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gt0_txresetdone : out std_logic;
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gt0_rxresetdone : out std_logic;
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gt0_rxbufstatus : out std_logic_vector (2 downto 0);
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gt0_rxprbserr : out std_logic;
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gt0_dmonitorout : out std_logic_vector (7 downto 0);
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xgmii_txd : in std_logic_vector (63 downto 0);
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xgmii_txc : in std_logic_vector (7 downto 0);
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xgmii_rxd : out std_logic_vector (63 downto 0);
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xgmii_rxc : out std_logic_vector (7 downto 0);
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txp : out std_logic;
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txn : out std_logic;
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rxp : in std_logic;
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rxn : in std_logic;
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configuration_vector : in std_logic_vector (535 downto 0);
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status_vector : out std_logic_vector (447 downto 0);
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core_status : out std_logic_vector (7 downto 0);
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wzab |
resetdone_out : out std_logic;
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37 |
wzab |
signal_detect : in std_logic;
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tx_fault : in std_logic;
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drp_req : out std_logic;
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drp_gnt : in std_logic;
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drp_den_o : out std_logic;
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drp_dwe_o : out std_logic;
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drp_daddr_o : out std_logic_vector (15 downto 0);
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drp_di_o : out std_logic_vector (15 downto 0);
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drp_drdy_i : in std_logic;
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drp_drpdo_i : in std_logic_vector (15 downto 0);
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drp_den_i : in std_logic;
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drp_dwe_i : in std_logic;
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drp_daddr_i : in std_logic_vector (15 downto 0);
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drp_di_i : in std_logic_vector (15 downto 0);
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drp_drdy_o : out std_logic;
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drp_drpdo_o : out std_logic_vector (15 downto 0);
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pma_pmd_type : in std_logic_vector (2 downto 0);
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tx_disable : out std_logic);
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end component ten_gig_eth_pcs_pma_0;
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component ten_gig_eth_pcs_pma_1 is
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port (
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dclk : in std_logic;
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42 |
wzab |
rxrecclk_out : out std_logic;
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coreclk : in std_logic;
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37 |
wzab |
txusrclk : in std_logic;
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txusrclk2 : in std_logic;
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41 |
wzab |
txoutclk : out std_logic;
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37 |
wzab |
areset : in std_logic;
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42 |
wzab |
areset_coreclk : in std_logic;
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37 |
wzab |
gttxreset : in std_logic;
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gtrxreset : in std_logic;
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sim_speedup_control : in std_logic;
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txuserrdy : in std_logic;
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qplllock : in std_logic;
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qplloutclk : in std_logic;
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qplloutrefclk : in std_logic;
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reset_counter_done : in std_logic;
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gt0_eyescanreset : in std_logic;
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gt0_eyescantrigger : in std_logic;
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gt0_rxcdrhold : in std_logic;
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gt0_txprbsforceerr : in std_logic;
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gt0_txpolarity : in std_logic;
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gt0_rxpolarity : in std_logic;
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gt0_rxrate : in std_logic_vector (2 downto 0);
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gt0_txpmareset : in std_logic;
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gt0_rxpmareset : in std_logic;
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gt0_rxdfelpmreset : in std_logic;
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gt0_txprecursor : in std_logic_vector (4 downto 0);
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gt0_txpostcursor : in std_logic_vector (4 downto 0);
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gt0_txdiffctrl : in std_logic_vector (3 downto 0);
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gt0_rxlpmen : in std_logic;
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220 |
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gt0_eyescandataerror : out std_logic;
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gt0_txbufstatus : out std_logic_vector (1 downto 0);
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222 |
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gt0_txresetdone : out std_logic;
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gt0_rxresetdone : out std_logic;
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gt0_rxbufstatus : out std_logic_vector (2 downto 0);
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gt0_rxprbserr : out std_logic;
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226 |
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gt0_dmonitorout : out std_logic_vector (7 downto 0);
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227 |
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xgmii_txd : in std_logic_vector (63 downto 0);
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xgmii_txc : in std_logic_vector (7 downto 0);
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xgmii_rxd : out std_logic_vector (63 downto 0);
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xgmii_rxc : out std_logic_vector (7 downto 0);
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txp : out std_logic;
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txn : out std_logic;
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rxp : in std_logic;
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rxn : in std_logic;
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configuration_vector : in std_logic_vector (535 downto 0);
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status_vector : out std_logic_vector (447 downto 0);
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core_status : out std_logic_vector (7 downto 0);
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tx_resetdone : out std_logic;
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rx_resetdone : out std_logic;
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signal_detect : in std_logic;
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tx_fault : in std_logic;
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drp_req : out std_logic;
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drp_gnt : in std_logic;
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drp_den_o : out std_logic;
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245 |
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drp_dwe_o : out std_logic;
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drp_daddr_o : out std_logic_vector (15 downto 0);
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247 |
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drp_di_o : out std_logic_vector (15 downto 0);
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248 |
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drp_drdy_i : in std_logic;
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drp_drpdo_i : in std_logic_vector (15 downto 0);
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drp_den_i : in std_logic;
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drp_dwe_i : in std_logic;
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drp_daddr_i : in std_logic_vector (15 downto 0);
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drp_di_i : in std_logic_vector (15 downto 0);
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254 |
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drp_drdy_o : out std_logic;
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255 |
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drp_drpdo_o : out std_logic_vector (15 downto 0);
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256 |
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pma_pmd_type : in std_logic_vector (2 downto 0);
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tx_disable : out std_logic);
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end component ten_gig_eth_pcs_pma_1;
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259 |
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260 |
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component fade_one_channel is
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261 |
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generic (
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262 |
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my_mac : std_logic_vector(47 downto 0));
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263 |
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port (
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264 |
|
|
xgmii_txd : out std_logic_vector(63 downto 0);
|
265 |
|
|
xgmii_txc : out std_logic_vector(7 downto 0);
|
266 |
|
|
xgmii_rxd : in std_logic_vector(63 downto 0);
|
267 |
|
|
xgmii_rxc : in std_logic_vector(7 downto 0);
|
268 |
|
|
rst_n : in std_logic;
|
269 |
|
|
clk_user : in std_logic);
|
270 |
|
|
end component fade_one_channel;
|
271 |
|
|
|
272 |
|
|
component frq_counter is
|
273 |
|
|
generic (
|
274 |
|
|
CNT_TIME : integer;
|
275 |
|
|
CNT_LENGTH : integer);
|
276 |
|
|
port (
|
277 |
|
|
ref_clk : in std_logic;
|
278 |
|
|
rst_p : in std_logic;
|
279 |
|
|
frq_in : in std_logic;
|
280 |
|
|
frq_out : out std_logic_vector(CNT_LENGTH-1 downto 0));
|
281 |
|
|
end component frq_counter;
|
282 |
42 |
wzab |
|
283 |
37 |
wzab |
component vio_stat is
|
284 |
|
|
port (
|
285 |
|
|
clk : in std_logic;
|
286 |
|
|
probe_in0 : in std_logic_vector(7 downto 0);
|
287 |
|
|
probe_in1 : in std_logic_vector(7 downto 0);
|
288 |
|
|
probe_in2 : in std_logic_vector(7 downto 0);
|
289 |
|
|
probe_in3 : in std_logic_vector(7 downto 0);
|
290 |
|
|
probe_in4 : in std_logic_vector(7 downto 0);
|
291 |
|
|
probe_in5 : in std_logic_vector(7 downto 0);
|
292 |
|
|
probe_in6 : in std_logic_vector(7 downto 0);
|
293 |
|
|
probe_in7 : in std_logic_vector(7 downto 0)
|
294 |
|
|
);
|
295 |
|
|
end component;
|
296 |
|
|
|
297 |
44 |
wzab |
component i2c_vio_ctrl is
|
298 |
|
|
port (
|
299 |
|
|
clk : in std_logic;
|
300 |
|
|
scl : inout std_logic;
|
301 |
|
|
sda : inout std_logic);
|
302 |
|
|
end component i2c_vio_ctrl;
|
303 |
|
|
|
304 |
|
|
component vio_frq is
|
305 |
|
|
port (
|
306 |
|
|
clk : in std_logic;
|
307 |
|
|
probe_in0 : in std_logic_vector (31 downto 0);
|
308 |
|
|
probe_in1 : in std_logic_vector (31 downto 0));
|
309 |
|
|
end component vio_frq;
|
310 |
|
|
|
311 |
37 |
wzab |
begin -- beh1
|
312 |
42 |
wzab |
si570_oe <= '1';
|
313 |
|
|
clk_updaten <= '1';
|
314 |
37 |
wzab |
-- Initialization vector
|
315 |
|
|
--configuration_vector(0) <= '1'; -- PMA loopback
|
316 |
|
|
--configuration_vector(110) <= '1'; -- PCS loopback
|
317 |
|
|
configuration_vector(33) <= '1'; -- training
|
318 |
|
|
configuration_vector(284) <= '1'; -- auto negotiation
|
319 |
|
|
|
320 |
|
|
signal_detect <= (others => '1'); -- allow transmission!
|
321 |
|
|
gtx_sfp_disable <= (others => '0');
|
322 |
42 |
wzab |
gtx_rate_sel <= (others => '1');
|
323 |
37 |
wzab |
|
324 |
|
|
-- Reset generator
|
325 |
|
|
process (boot_clk) is
|
326 |
|
|
begin -- process
|
327 |
|
|
if boot_clk'event and boot_clk = '1' then -- rising clock edge
|
328 |
|
|
if rst_cnt > 0 then
|
329 |
|
|
rst_cnt <= rst_cnt - 1;
|
330 |
|
|
else
|
331 |
|
|
rst_p <= '0';
|
332 |
|
|
end if;
|
333 |
|
|
end if;
|
334 |
|
|
end process;
|
335 |
|
|
|
336 |
|
|
|
337 |
|
|
rst_n <= not rst_p;
|
338 |
|
|
refclk_n <= gtx_refclk_n;
|
339 |
|
|
refclk_p <= gtx_refclk_p;
|
340 |
|
|
reset <= not rst_n;
|
341 |
|
|
|
342 |
|
|
--trig_in <= '1' when xgmii_rxc /= x"ff" else '0';
|
343 |
|
|
|
344 |
|
|
gl1 : for q in 0 to N_OF_QUADS-1 generate
|
345 |
|
|
gl2 : for n in 0 to N_OF_LINKS-1 generate
|
346 |
|
|
|
347 |
|
|
il1 : if n = 0 generate
|
348 |
41 |
wzab |
|
349 |
37 |
wzab |
ten_gig_eth_pcs_pma_0_1 : ten_gig_eth_pcs_pma_0
|
350 |
|
|
port map (
|
351 |
|
|
dclk => core_clk156_out(q),
|
352 |
42 |
wzab |
rxrecclk_out => open, --??
|
353 |
37 |
wzab |
refclk_p => refclk_p(q),
|
354 |
|
|
refclk_n => refclk_n(q),
|
355 |
41 |
wzab |
sim_speedup_control => '0',
|
356 |
42 |
wzab |
coreclk_out => core_clk156_out(q),
|
357 |
41 |
wzab |
qplloutclk_out => qplloutclk_out(q),
|
358 |
|
|
qplloutrefclk_out => qplloutrefclk_out(q),
|
359 |
|
|
qplllock_out => qplllock_out(q),
|
360 |
37 |
wzab |
txusrclk_out => s_txusrclk_out(q),
|
361 |
|
|
txusrclk2_out => s_txusrclk2_out(q),
|
362 |
42 |
wzab |
areset_datapathclk_out => areset_clk156_out(q),
|
363 |
37 |
wzab |
gttxreset_out => gttxreset_out(q),
|
364 |
|
|
gtrxreset_out => gtrxreset_out(q),
|
365 |
|
|
txuserrdy_out => txuserrdy_out(q),
|
366 |
|
|
reset_counter_done_out => reset_counter_done_out(q),
|
367 |
41 |
wzab |
reset => reset,
|
368 |
|
|
gt0_eyescanreset => '0',
|
369 |
|
|
gt0_eyescantrigger => '0',
|
370 |
|
|
gt0_rxcdrhold => '0',
|
371 |
|
|
gt0_txprbsforceerr => '0',
|
372 |
|
|
gt0_txpolarity => '0',
|
373 |
|
|
gt0_rxpolarity => '0',
|
374 |
|
|
gt0_rxrate => (others => '0'),
|
375 |
|
|
gt0_txpmareset => '0',
|
376 |
|
|
gt0_rxpmareset => '0',
|
377 |
|
|
gt0_rxdfelpmreset => '0',
|
378 |
|
|
gt0_txprecursor => (others => '0'),
|
379 |
|
|
gt0_txpostcursor => (others => '0'),
|
380 |
|
|
gt0_txdiffctrl => "1110",
|
381 |
|
|
gt0_rxlpmen => '0',
|
382 |
|
|
gt0_eyescandataerror => open,
|
383 |
|
|
gt0_txbufstatus => open,
|
384 |
|
|
gt0_txresetdone => open,
|
385 |
|
|
gt0_rxresetdone => open,
|
386 |
|
|
gt0_rxbufstatus => open,
|
387 |
|
|
gt0_rxprbserr => open,
|
388 |
|
|
gt0_dmonitorout => open,
|
389 |
37 |
wzab |
xgmii_txd => xgmii_txd(q*N_OF_LINKS+n),
|
390 |
|
|
xgmii_txc => xgmii_txc(q*N_OF_LINKS+n),
|
391 |
|
|
xgmii_rxd => xgmii_rxd(q*N_OF_LINKS+n),
|
392 |
|
|
xgmii_rxc => xgmii_rxc(q*N_OF_LINKS+n),
|
393 |
41 |
wzab |
txp => gtx10g_txp(q*N_OF_LINKS+n),
|
394 |
|
|
txn => gtx10g_txn(q*N_OF_LINKS+n),
|
395 |
|
|
rxp => gtx10g_rxp(q*N_OF_LINKS+n),
|
396 |
|
|
rxn => gtx10g_rxn(q*N_OF_LINKS+n),
|
397 |
37 |
wzab |
configuration_vector => configuration_vector,
|
398 |
|
|
status_vector => status_vector(q*N_OF_LINKS+n),
|
399 |
|
|
core_status => core_status(q*N_OF_LINKS+n),
|
400 |
41 |
wzab |
resetdone_out => s_resetdone(q),
|
401 |
37 |
wzab |
signal_detect => signal_detect(q*N_OF_LINKS+n),
|
402 |
|
|
tx_fault => tx_fault(q*N_OF_LINKS+n),
|
403 |
|
|
drp_req => drp_req(q*N_OF_LINKS+n),
|
404 |
|
|
drp_gnt => drp_gnt(q*N_OF_LINKS+n),
|
405 |
|
|
drp_den_o => drp_den_o(q*N_OF_LINKS+n),
|
406 |
|
|
drp_dwe_o => drp_dwe_o(q*N_OF_LINKS+n),
|
407 |
|
|
drp_daddr_o => drp_daddr_o(q*N_OF_LINKS+n),
|
408 |
|
|
drp_di_o => drp_di_o(q*N_OF_LINKS+n),
|
409 |
41 |
wzab |
drp_drdy_i => drp_drdy_i(q*N_OF_LINKS+n),
|
410 |
|
|
drp_drpdo_i => drp_drpdo_i(q*N_OF_LINKS+n),
|
411 |
37 |
wzab |
drp_den_i => drp_den_i(q*N_OF_LINKS+n),
|
412 |
|
|
drp_dwe_i => drp_dwe_i(q*N_OF_LINKS+n),
|
413 |
|
|
drp_daddr_i => drp_daddr_i(q*N_OF_LINKS+n),
|
414 |
|
|
drp_di_i => drp_di_i(q*N_OF_LINKS+n),
|
415 |
41 |
wzab |
drp_drdy_o => drp_drdy_o(q*N_OF_LINKS+n),
|
416 |
|
|
drp_drpdo_o => drp_drpdo_o(q*N_OF_LINKS+n),
|
417 |
37 |
wzab |
pma_pmd_type => "111",
|
418 |
41 |
wzab |
tx_disable => tx_disable(q*N_OF_LINKS+n)
|
419 |
37 |
wzab |
);
|
420 |
|
|
|
421 |
|
|
end generate il1;
|
422 |
|
|
il2 : if n /= 0 generate
|
423 |
44 |
wzab |
ten_gig_eth_pcs_pma_1_1 : ten_gig_eth_pcs_pma_1
|
424 |
37 |
wzab |
port map (
|
425 |
|
|
dclk => core_clk156_out(q),
|
426 |
42 |
wzab |
rxrecclk_out => open, --??
|
427 |
|
|
coreclk => core_clk156_out(q),
|
428 |
37 |
wzab |
txusrclk => s_txusrclk_out(q),
|
429 |
|
|
txusrclk2 => s_txusrclk2_out(q),
|
430 |
|
|
areset => reset,
|
431 |
42 |
wzab |
areset_coreclk => areset_clk156_out(q),
|
432 |
37 |
wzab |
gttxreset => gttxreset_out(q),
|
433 |
|
|
gtrxreset => gtrxreset_out(q),
|
434 |
|
|
sim_speedup_control => '0',
|
435 |
|
|
txuserrdy => txuserrdy_out(q),
|
436 |
|
|
qplllock => qplllock_out(q),
|
437 |
|
|
qplloutclk => qplloutclk_out(q),
|
438 |
|
|
qplloutrefclk => qplloutrefclk_out(q),
|
439 |
|
|
reset_counter_done => reset_counter_done_out(q),
|
440 |
|
|
gt0_eyescanreset => '0',
|
441 |
|
|
gt0_eyescantrigger => '0',
|
442 |
|
|
gt0_rxcdrhold => '0',
|
443 |
|
|
gt0_txprbsforceerr => '0',
|
444 |
|
|
gt0_txpolarity => '0',
|
445 |
|
|
gt0_rxpolarity => '0',
|
446 |
|
|
gt0_rxrate => (others => '0'),
|
447 |
|
|
gt0_txpmareset => '0',
|
448 |
|
|
gt0_rxpmareset => '0',
|
449 |
|
|
gt0_rxdfelpmreset => '0',
|
450 |
|
|
gt0_txprecursor => (others => '0'),
|
451 |
|
|
gt0_txpostcursor => (others => '0'),
|
452 |
|
|
gt0_txdiffctrl => "1110",
|
453 |
|
|
gt0_rxlpmen => '0',
|
454 |
|
|
gt0_eyescandataerror => open,
|
455 |
|
|
gt0_txbufstatus => open,
|
456 |
|
|
gt0_txresetdone => open,
|
457 |
|
|
gt0_rxresetdone => open,
|
458 |
|
|
gt0_rxbufstatus => open,
|
459 |
|
|
gt0_rxprbserr => open,
|
460 |
|
|
gt0_dmonitorout => open,
|
461 |
|
|
xgmii_txd => xgmii_txd(q*N_OF_LINKS+n),
|
462 |
|
|
xgmii_txc => xgmii_txc(q*N_OF_LINKS+n),
|
463 |
|
|
xgmii_rxd => xgmii_rxd(q*N_OF_LINKS+n),
|
464 |
|
|
xgmii_rxc => xgmii_rxc(q*N_OF_LINKS+n),
|
465 |
|
|
txp => gtx10g_txp(q*N_OF_LINKS+n),
|
466 |
|
|
txn => gtx10g_txn(q*N_OF_LINKS+n),
|
467 |
|
|
rxp => gtx10g_rxp(q*N_OF_LINKS+n),
|
468 |
|
|
rxn => gtx10g_rxn(q*N_OF_LINKS+n),
|
469 |
|
|
configuration_vector => configuration_vector,
|
470 |
|
|
status_vector => status_vector(q*N_OF_LINKS+n),
|
471 |
|
|
core_status => core_status(q*N_OF_LINKS+n),
|
472 |
|
|
tx_resetdone => open,
|
473 |
|
|
rx_resetdone => open,
|
474 |
|
|
signal_detect => signal_detect(q*N_OF_LINKS+n),
|
475 |
|
|
tx_fault => tx_fault(q*N_OF_LINKS+n),
|
476 |
|
|
drp_req => drp_req(q*N_OF_LINKS+n),
|
477 |
|
|
drp_gnt => drp_gnt(q*N_OF_LINKS+n),
|
478 |
|
|
drp_den_o => drp_den_o(q*N_OF_LINKS+n),
|
479 |
|
|
drp_dwe_o => drp_dwe_o(q*N_OF_LINKS+n),
|
480 |
|
|
drp_daddr_o => drp_daddr_o(q*N_OF_LINKS+n),
|
481 |
|
|
drp_di_o => drp_di_o(q*N_OF_LINKS+n),
|
482 |
|
|
drp_drdy_i => drp_drdy_i(q*N_OF_LINKS+n),
|
483 |
|
|
drp_drpdo_i => drp_drpdo_i(q*N_OF_LINKS+n),
|
484 |
|
|
drp_den_i => drp_den_i(q*N_OF_LINKS+n),
|
485 |
|
|
drp_dwe_i => drp_dwe_i(q*N_OF_LINKS+n),
|
486 |
|
|
drp_daddr_i => drp_daddr_i(q*N_OF_LINKS+n),
|
487 |
|
|
drp_di_i => drp_di_i(q*N_OF_LINKS+n),
|
488 |
|
|
drp_drdy_o => drp_drdy_o(q*N_OF_LINKS+n),
|
489 |
|
|
drp_drpdo_o => drp_drpdo_o(q*N_OF_LINKS+n),
|
490 |
|
|
pma_pmd_type => "111",
|
491 |
|
|
tx_disable => tx_disable(q*N_OF_LINKS+n));
|
492 |
|
|
end generate il2;
|
493 |
|
|
|
494 |
|
|
drp_gnt(q*N_OF_LINKS+n) <= drp_req(q*N_OF_LINKS+n);
|
495 |
|
|
drp_den_i(q*N_OF_LINKS+n) <= drp_den_o(q*N_OF_LINKS+n);
|
496 |
|
|
drp_dwe_i(q*N_OF_LINKS+n) <= drp_dwe_o(q*N_OF_LINKS+n);
|
497 |
|
|
drp_daddr_i(q*N_OF_LINKS+n) <= drp_daddr_o(q*N_OF_LINKS+n);
|
498 |
|
|
drp_di_i(q*N_OF_LINKS+n) <= drp_di_o(q*N_OF_LINKS+n);
|
499 |
|
|
drp_drpdo_i(q*N_OF_LINKS+n) <= drp_drpdo_o(q*N_OF_LINKS+n);
|
500 |
|
|
|
501 |
|
|
fade_one_channel_1 : entity work.fade_one_channel
|
502 |
|
|
generic map (
|
503 |
|
|
my_mac => mac_table(q*N_OF_LINKS+n))
|
504 |
|
|
port map (
|
505 |
|
|
xgmii_txd => xgmii_txd(q*N_OF_LINKS+n),
|
506 |
|
|
xgmii_txc => xgmii_txc(q*N_OF_LINKS+n),
|
507 |
|
|
xgmii_rxd => xgmii_rxd(q*N_OF_LINKS+n),
|
508 |
|
|
xgmii_rxc => xgmii_rxc(q*N_OF_LINKS+n),
|
509 |
|
|
rst_n => rst_n,
|
510 |
|
|
clk_user => clk_user(q));
|
511 |
|
|
|
512 |
42 |
wzab |
|
513 |
37 |
wzab |
end generate gl2;
|
514 |
|
|
|
515 |
42 |
wzab |
frq_counter_1 : entity work.frq_counter
|
516 |
|
|
generic map (
|
517 |
|
|
CNT_TIME => 20000000,
|
518 |
|
|
CNT_LENGTH => 32)
|
519 |
|
|
port map (
|
520 |
|
|
ref_clk => boot_clk,
|
521 |
|
|
rst_p => rst_p,
|
522 |
|
|
frq_in => clk_user(q),
|
523 |
|
|
frq_out => frq_user(q));
|
524 |
37 |
wzab |
|
525 |
|
|
|
526 |
|
|
end generate gl1;
|
527 |
|
|
|
528 |
|
|
clk0_frq <= frq_user(0);
|
529 |
|
|
clk1_frq <= frq_user(1);
|
530 |
42 |
wzab |
|
531 |
37 |
wzab |
rst1 <= core_status(0)(0);
|
532 |
|
|
--core_ready <= core_status(0);
|
533 |
|
|
clk1 <= boot_clk;
|
534 |
|
|
clk_user <= core_clk156_out;
|
535 |
|
|
|
536 |
|
|
-- Frequency meters
|
537 |
44 |
wzab |
vio_frq_1 : vio_frq
|
538 |
37 |
wzab |
port map (
|
539 |
|
|
clk => boot_clk,
|
540 |
|
|
probe_in0 => clk0_frq,
|
541 |
|
|
probe_in1 => clk1_frq);
|
542 |
|
|
|
543 |
|
|
-- Vio Link statuses
|
544 |
44 |
wzab |
vio_stat_1 : vio_stat
|
545 |
37 |
wzab |
port map (
|
546 |
|
|
clk => boot_clk,
|
547 |
|
|
probe_in0 => core_status(0),
|
548 |
|
|
probe_in1 => core_status(1),
|
549 |
|
|
probe_in2 => core_status(2),
|
550 |
|
|
probe_in3 => core_status(3),
|
551 |
|
|
probe_in4 => core_status(4),
|
552 |
|
|
probe_in5 => core_status(5),
|
553 |
|
|
probe_in6 => core_status(6),
|
554 |
|
|
probe_in7 => core_status(7));
|
555 |
|
|
|
556 |
|
|
-- JTAG<->I2C part for clock-crossbar
|
557 |
44 |
wzab |
i2c_vio_ctrl_1 : i2c_vio_ctrl
|
558 |
37 |
wzab |
port map (
|
559 |
|
|
clk => boot_clk,
|
560 |
|
|
scl => scl,
|
561 |
|
|
sda => sda);
|
562 |
|
|
|
563 |
41 |
wzab |
gld1 : for i in 0 to N_OF_QUADS-1 generate
|
564 |
37 |
wzab |
p1 : process (clk_user(i), rst_n)
|
565 |
|
|
begin -- process p1
|
566 |
|
|
if rst_n = '0' then -- asynchronous reset (active low)
|
567 |
|
|
heart_bit(i) <= 0;
|
568 |
|
|
elsif clk_user(i)'event and clk_user(i) = '1' then -- rising clock edge
|
569 |
|
|
if heart_bit(i) < 80000000 then
|
570 |
|
|
heart_bit(i) <= heart_bit(i) + 1;
|
571 |
|
|
else
|
572 |
|
|
heart_bit(i) <= 0;
|
573 |
|
|
s_hb_led(i) <= not s_hb_led(i);
|
574 |
|
|
end if;
|
575 |
|
|
end if;
|
576 |
|
|
end process p1;
|
577 |
|
|
|
578 |
|
|
end generate gld1;
|
579 |
|
|
|
580 |
|
|
p2 : process (boot_clk, rst_n)
|
581 |
|
|
begin -- process p1
|
582 |
|
|
if rst_n = '0' then -- asynchronous reset (active low)
|
583 |
|
|
heart_bit(2) <= 0;
|
584 |
|
|
elsif boot_clk'event and boot_clk = '1' then -- rising clock edge
|
585 |
|
|
if heart_bit(2) < 10000000 then
|
586 |
|
|
heart_bit(2) <= heart_bit(2) + 1;
|
587 |
|
|
else
|
588 |
|
|
heart_bit(2) <= 0;
|
589 |
|
|
s_hb_led(2) <= not s_hb_led(2);
|
590 |
|
|
end if;
|
591 |
|
|
end if;
|
592 |
|
|
end process p2;
|
593 |
|
|
|
594 |
|
|
hb_led <= s_hb_led;
|
595 |
|
|
|
596 |
|
|
end beh1;
|