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URL https://opencores.org/ocsvn/fade_ether_protocol/fade_ether_protocol/trunk

Subversion Repositories fade_ether_protocol

[/] [fade_ether_protocol/] [trunk/] [stable_jumbo_frames_version/] [fpga/] [src/] [kc705/] [kc705_fade_top.vhd] - Blame information for rev 42

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1 15 wzab 
library ieee;
2 
use ieee.std_logic_1164.all;
3 
use ieee.numeric_std.all;
4 
use work.pkt_ack_pkg.all;
5 
use work.desc_mgr_pkg.all;
6 
 
7 
entity kc705_10g_2 is
8 42 wzab 
 
9 15 wzab 
  port (
10 
    gtx10g_txn    : out std_logic;
11 
    gtx10g_txp    : out std_logic;
12 
    gtx10g_rxn    : in  std_logic;
13 
    gtx10g_rxp    : in  std_logic;
14 
    gtx_refclk_n  : in  std_logic;
15 
    gtx_refclk_p  : in  std_logic;
16 
    --xgmii_txd     : in  std_logic_vector(63 downto 0);
17 
    --xgmii_txc     : in  std_logic_vector(7 downto 0);
18 
    --xgmii_rxd     : out std_logic_vector(63 downto 0);
19 
    --xgmii_rxc     : out std_logic_vector(7 downto 0);
20 
    txusrclk_out  : out std_logic;
21 
    txusrclk2_out : out std_logic;
22 
    resetdone     : out std_logic;
23 
    core_ready    : out std_logic;
24 
    trig_ack      : out std_logic;
25 
    led5          : out std_logic;
26 
    clk_2         : in  std_logic;
27 
    start         : in  std_logic;
28 
    rst_p         : in  std_logic);
29 
 
30 
end kc705_10g_2;
31 
 
32 
architecture beh1 of kc705_10g_2 is
33 
 
34 
  signal heart_bit : integer := 0;
35 
 
36 
  signal refclk_p               : std_logic                      := '0';
37 
  signal refclk_n               : std_logic                      := '0';
38 
  signal reset                  : std_logic                      := '0';
39 
  signal s_resetdone            : std_logic                      := '0';
40 
  signal core_clk156_out        : std_logic                      := '0';
41 
  signal txp                    : std_logic                      := '0';
42 
  signal txn                    : std_logic                      := '0';
43 
  signal rxp                    : std_logic                      := '0';
44 
  signal rxn                    : std_logic                      := '0';
45 
  signal dclk_out               : std_logic                      := '0';
46 
  signal s_txusrclk_out         : std_logic                      := '0';
47 
  signal s_txusrclk2_out        : std_logic                      := '0';
48 
  signal areset_clk156_out      : std_logic                      := '0';
49 
  signal gttxreset_out          : std_logic                      := '0';
50 
  signal gtrxreset_out          : std_logic                      := '0';
51 
  signal txuserrdy_out          : std_logic                      := '0';
52 
  signal reset_counter_done_out : std_logic                      := '0';
53 
  signal qplllock_out           : std_logic                      := '0';
54 
  signal qplloutclk_out         : std_logic                      := '0';
55 
  signal qplloutrefclk_out      : std_logic                      := '0';
56 
  signal xgmii_txd              : std_logic_vector(63 downto 0)  := (others => '0');
57 
  signal xgmii_txc              : std_logic_vector(7 downto 0)   := (others => '0');
58 
  signal xgmii_rxd              : std_logic_vector(63 downto 0)  := (others => '0');
59 
  signal xgmii_rxc              : std_logic_vector(7 downto 0)   := (others => '0');
60 
  signal configuration_vector   : std_logic_vector(535 downto 0) := (others => '0');
61 
  signal status_vector          : std_logic_vector(447 downto 0) := (others => '0');
62 
  signal core_status            : std_logic_vector(7 downto 0)   := (others => '0');
63 
  signal signal_detect          : std_logic                      := '0';
64 
  signal tx_fault               : std_logic                      := '0';
65 
  signal drp_req                : std_logic                      := '0';
66 
  signal drp_gnt                : std_logic                      := '0';
67 
  signal drp_den_o              : std_logic                      := '0';
68 
  signal drp_dwe_o              : std_logic                      := '0';
69 
  signal drp_daddr_o            : std_logic_vector(15 downto 0)  := (others => '0');
70 
  signal drp_di_o               : std_logic_vector(15 downto 0)  := (others => '0');
71 
  signal drp_drdy_o             : std_logic                      := '0';
72 
  signal drp_drpdo_o            : std_logic_vector(15 downto 0)  := (others => '0');
73 
  signal drp_den_i              : std_logic                      := '0';
74 
  signal drp_dwe_i              : std_logic                      := '0';
75 
  signal drp_daddr_i            : std_logic_vector(15 downto 0)  := (others => '0');
76 
  signal drp_di_i               : std_logic_vector(15 downto 0)  := (others => '0');
77 
  signal drp_drdy_i             : std_logic                      := '0';
78 
  signal drp_drpdo_i            : std_logic_vector(15 downto 0)  := (others => '0');
79 
  signal tx_disable             : std_logic                      := '0';
80 
 
81 
  signal counter              : integer   := 0;
82 
  signal probe2               : std_logic_vector(2 downto 0);
83 
  signal trig_in, trig_in_ack : std_logic := '0';
84 
  signal rst_n, rst1, clk1    : std_logic := '0';
85 
  signal hb_led               : std_logic := '0';
86 
  signal s_led5               : std_logic := '0';
87 
 
88 
  -- Signals associated with the FADE core
89 
  signal my_mac                   : std_logic_vector(47 downto 0);
90 
  signal sender                   : std_logic_vector(47 downto 0);
91 
  signal peer_mac                 : std_logic_vector(47 downto 0);
92 
  constant my_ether_type          : std_logic_vector(15 downto 0) := x"fade";
93 
  signal transm_delay             : unsigned(31 downto 0);
94 26 wzab 
  signal retr_count               : std_logic_vector(31 downto 0);
95 15 wzab 
  signal restart                  : std_logic;
96 
  signal fade_rst_n, fade_rst_del : std_logic                     := '0';
97 
  signal fade_rst_p               : std_logic;
98 
 
99 
  signal test_dta                          : unsigned(63 downto 0);
100 
  signal dta                               : std_logic_vector(63 downto 0);
101 
  signal s_dta_we, dta_we                  : std_logic                         := '0';
102 
  signal dta_ready                         : std_logic;
103 
  signal snd_start                         : std_logic;
104 18 wzab 
  signal flushed                           : std_logic                         := '0';
105 
  signal dta_eod                           : std_logic                         := '0';
106 15 wzab 
  signal snd_ready                         : std_logic;
107 
  signal clk_user                          : std_logic;
108 
  signal dmem_we                           : std_logic;
109 
  signal dmem_addr                         : std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0);
110 
  signal dmem_dta                          : std_logic_vector(63 downto 0);
111 
  signal tx_mem_addr                       : std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0);
112 
  signal tx_mem_data                       : std_logic_vector(63 downto 0);
113 
  signal pkt_number                        : unsigned(31 downto 0);
114 
  signal seq_number                        : unsigned(15 downto 0)             := (others => '0');
115 
  signal start_pkt, stop_pkt               : unsigned(7 downto 0)              := (others => '0');
116 
  -- signals related to user commands handling
117 
  signal cmd_response_in, cmd_response_out : std_logic_vector(12*8-1 downto 0) := (others => '0');
118 
  signal cmd_start                         : std_logic                         := '0';
119 
  signal cmd_run                           : std_logic                         := '0';
120 18 wzab 
  signal cmd_retr_s                        : std_logic                         := '0';
121 15 wzab 
  signal cmd_ack                           : std_logic                         := '0';
122 
  signal cmd_code                          : std_logic_vector(15 downto 0)     := (others => '0');
123 
  signal cmd_seq                           : std_logic_vector(15 downto 0)     := (others => '0');
124 
  signal cmd_arg                           : std_logic_vector(31 downto 0)     := (others => '0');
125 
 
126 
 
127 
  -- debug signals
128 
  signal dbg    : std_logic_vector(3 downto 0);
129 
  signal rx_crc : std_logic_vector(31 downto 0);
130 
  signal rx_cmd : std_logic_vector(31 downto 0);
131 
  signal rx_arg : std_logic_vector(31 downto 0);
132 
 
133 
  signal ack_fifo_din, ack_fifo_dout                                   : std_logic_vector(pkt_ack_width-1 downto 0);
134 
  signal ack_fifo_wr_en, ack_fifo_rd_en, ack_fifo_empty, ack_fifo_full : std_logic;
135 
  signal ack_fifo_dbg                                                  : pkt_ack;
136 18 wzab 
  signal transmit_data, td_del0, td_del1                               : std_logic := '0';
137 15 wzab 
 
138 18 wzab 
  attribute mark_debug              : string;
139 
  attribute mark_debug of xgmii_txd : signal is "true";
140 
  attribute mark_debug of xgmii_txc : signal is "true";
141 
 
142 15 wzab 
  component ila_1
143 
    port (
144 
      clk         : in  std_logic;
145 
      trig_in     : in  std_logic;
146 
      trig_in_ack : out std_logic;
147 
      probe0      : in  std_logic_vector(63 downto 0);
148 
      probe1      : in  std_logic_vector(7 downto 0);
149 
      probe2      : in  std_logic_vector(2 downto 0);
150 
      probe3      : in  std_logic_vector(7 downto 0);
151 
      probe4      : in  std_logic_vector(3 downto 0);
152 
      probe5      : in  std_logic_vector(31 downto 0);
153 
      probe6      : in  std_logic_vector(31 downto 0);
154 
      probe7      : in  std_logic_vector(15 downto 0);
155 
      probe8      : in  std_logic_vector(31 downto 0);
156 
      probe9      : in  std_logic_vector(31 downto 0);
157 18 wzab 
      probe10     : in  std_logic_vector(63 downto 0);
158 
      probe11     : in  std_logic_vector(7 downto 0)
159 15 wzab 
      );
160 
  end component;
161 
 
162 26 wzab 
  component ten_gig_eth_pcs_pma_0 is
163 
    port (
164 
      dclk                   : in  std_logic;
165 42 wzab 
      rxrecclk_out           : out std_logic;
166 26 wzab 
      refclk_p               : in  std_logic;
167 
      refclk_n               : in  std_logic;
168 
      sim_speedup_control    : in  std_logic;
169 42 wzab 
      coreclk_out            : out std_logic;
170 26 wzab 
      qplloutclk_out         : out std_logic;
171 
      qplloutrefclk_out      : out std_logic;
172 
      qplllock_out           : out std_logic;
173 
      txusrclk_out           : out std_logic;
174 
      txusrclk2_out          : out std_logic;
175 42 wzab 
      areset_datapathclk_out : out std_logic;
176 26 wzab 
      gttxreset_out          : out std_logic;
177 
      gtrxreset_out          : out std_logic;
178 
      txuserrdy_out          : out std_logic;
179 
      reset_counter_done_out : out std_logic;
180 
      reset                  : in  std_logic;
181 
      gt0_eyescanreset       : in  std_logic;
182 
      gt0_eyescantrigger     : in  std_logic;
183 
      gt0_rxcdrhold          : in  std_logic;
184 
      gt0_txprbsforceerr     : in  std_logic;
185 
      gt0_txpolarity         : in  std_logic;
186 
      gt0_rxpolarity         : in  std_logic;
187 
      gt0_rxrate             : in  std_logic_vector (2 downto 0);
188 
      gt0_txpmareset         : in  std_logic;
189 
      gt0_rxpmareset         : in  std_logic;
190 
      gt0_rxdfelpmreset      : in  std_logic;
191 
      gt0_txprecursor        : in  std_logic_vector (4 downto 0);
192 
      gt0_txpostcursor       : in  std_logic_vector (4 downto 0);
193 
      gt0_txdiffctrl         : in  std_logic_vector (3 downto 0);
194 
      gt0_rxlpmen            : in  std_logic;
195 
      gt0_eyescandataerror   : out std_logic;
196 
      gt0_txbufstatus        : out std_logic_vector (1 downto 0);
197 
      gt0_txresetdone        : out std_logic;
198 
      gt0_rxresetdone        : out std_logic;
199 
      gt0_rxbufstatus        : out std_logic_vector (2 downto 0);
200 
      gt0_rxprbserr          : out std_logic;
201 
      gt0_dmonitorout        : out std_logic_vector (7 downto 0);
202 
      xgmii_txd              : in  std_logic_vector (63 downto 0);
203 
      xgmii_txc              : in  std_logic_vector (7 downto 0);
204 
      xgmii_rxd              : out std_logic_vector (63 downto 0);
205 
      xgmii_rxc              : out std_logic_vector (7 downto 0);
206 
      txp                    : out std_logic;
207 
      txn                    : out std_logic;
208 
      rxp                    : in  std_logic;
209 
      rxn                    : in  std_logic;
210 
      configuration_vector   : in  std_logic_vector (535 downto 0);
211 
      status_vector          : out std_logic_vector (447 downto 0);
212 
      core_status            : out std_logic_vector (7 downto 0);
213 42 wzab 
      resetdone_out          : out std_logic;
214 26 wzab 
      signal_detect          : in  std_logic;
215 
      tx_fault               : in  std_logic;
216 
      drp_req                : out std_logic;
217 
      drp_gnt                : in  std_logic;
218 
      drp_den_o              : out std_logic;
219 
      drp_dwe_o              : out std_logic;
220 
      drp_daddr_o            : out std_logic_vector (15 downto 0);
221 
      drp_di_o               : out std_logic_vector (15 downto 0);
222 
      drp_drdy_i             : in  std_logic;
223 
      drp_drpdo_i            : in  std_logic_vector (15 downto 0);
224 
      drp_den_i              : in  std_logic;
225 
      drp_dwe_i              : in  std_logic;
226 
      drp_daddr_i            : in  std_logic_vector (15 downto 0);
227 
      drp_di_i               : in  std_logic_vector (15 downto 0);
228 
      drp_drdy_o             : out std_logic;
229 
      drp_drpdo_o            : out std_logic_vector (15 downto 0);
230 
      pma_pmd_type           : in  std_logic_vector (2 downto 0);
231 
      tx_disable             : out std_logic);
232 
  end component ten_gig_eth_pcs_pma_0;
233 15 wzab 
 
234 
  component eth_receiver is
235 
    port (
236 
      peer_mac       : out std_logic_vector(47 downto 0);
237 
      my_mac         : in  std_logic_vector(47 downto 0);
238 
      my_ether_type  : in  std_logic_vector(15 downto 0);
239 
      transmit_data  : out std_logic;
240 
      restart        : out std_logic;
241 
      ack_fifo_full  : in  std_logic;
242 
      ack_fifo_wr_en : out std_logic;
243 
      ack_fifo_din   : out std_logic_vector(pkt_ack_width-1 downto 0);
244 
      clk            : in  std_logic;
245 
      rst_n          : in  std_logic;
246 
      dbg            : out std_logic_vector(3 downto 0);
247 
      crc            : out std_logic_vector(31 downto 0);
248 
      cmd            : out std_logic_vector(31 downto 0);
249 
      arg            : out std_logic_vector(31 downto 0);
250 
      Rx_Clk         : in  std_logic;
251 
      RxC            : in  std_logic_vector(7 downto 0);
252 
      RxD            : in  std_logic_vector(63 downto 0));
253 
  end component eth_receiver;
254 
 
255 
  component eth_sender is
256 
    port (
257 
      peer_mac      : in  std_logic_vector(47 downto 0);
258 
      my_mac        : in  std_logic_vector(47 downto 0);
259 
      my_ether_type : in  std_logic_vector(15 downto 0);
260 
      pkt_number    : in  unsigned(31 downto 0);
261 
      seq_number    : in  unsigned(15 downto 0);
262 
      transm_delay  : in  unsigned(31 downto 0);
263 
      clk           : in  std_logic;
264 
      rst_n         : in  std_logic;
265 
      ready         : out std_logic;
266 18 wzab 
      flushed       : in  std_logic;
267 15 wzab 
      start         : in  std_logic;
268 
      cmd_start     : in  std_logic;
269 
      tx_mem_addr   : out std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0);
270 
      tx_mem_data   : in  std_logic_vector(63 downto 0);
271 
      cmd_response  : in  std_logic_vector(12*8-1 downto 0);
272 
      Tx_Clk        : in  std_logic;
273 
      TxC           : out std_logic_vector(7 downto 0);
274 
      TxD           : out std_logic_vector(63 downto 0));
275 
  end component eth_sender;
276 
 
277 
  component dp_ram_scl
278 
    generic (
279 
      DATA_WIDTH : integer;
280 
      ADDR_WIDTH : integer);
281 
    port (
282 
      clk_a  : in  std_logic;
283 
      we_a   : in  std_logic;
284 
      addr_a : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
285 
      data_a : in  std_logic_vector(DATA_WIDTH-1 downto 0);
286 
      q_a    : out std_logic_vector(DATA_WIDTH-1 downto 0);
287 
      clk_b  : in  std_logic;
288 
      we_b   : in  std_logic;
289 
      addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
290 
      data_b : in  std_logic_vector(DATA_WIDTH-1 downto 0);
291 
      q_b    : out std_logic_vector(DATA_WIDTH-1 downto 0));
292 
  end component;
293 
 
294 
  component ack_fifo
295 
    port (
296 
      rst    : in  std_logic;
297 
      wr_clk : in  std_logic;
298 
      rd_clk : in  std_logic;
299 
      din    : in  std_logic_vector(pkt_ack_width-1 downto 0);
300 
      wr_en  : in  std_logic;
301 
      rd_en  : in  std_logic;
302 
      dout   : out std_logic_vector(pkt_ack_width-1 downto 0);
303 
      full   : out std_logic;
304 
      empty  : out std_logic);
305 
  end component;
306 
 
307 
  component cmd_proc is
308 
    port (
309 
      cmd_code     : in  std_logic_vector(15 downto 0);
310 
      cmd_seq      : in  std_logic_vector(15 downto 0);
311 
      cmd_arg      : in  std_logic_vector(31 downto 0);
312 
      cmd_run      : in  std_logic;
313 
      cmd_ack      : out std_logic;
314 
      cmd_response : out std_logic_vector(8*12-1 downto 0);
315 
      clk          : in  std_logic;
316 26 wzab 
      rst_p        : in  std_logic;
317 
      retr_count   : in  std_logic_vector(31 downto 0)
318 
      );
319 15 wzab 
  end component cmd_proc;
320 
 
321 
  component desc_manager is
322 
    generic (
323 
      LOG2_N_OF_PKTS : integer;
324 
      N_OF_PKTS      : integer);
325 
    port (
326 
      dta              : in  std_logic_vector(63 downto 0);
327 
      dta_we           : in  std_logic;
328 
      dta_ready        : out std_logic;
329 18 wzab 
      dta_eod          : in  std_logic;
330 15 wzab 
      pkt_number       : out unsigned(31 downto 0);
331 
      seq_number       : out unsigned(15 downto 0);
332 
      cmd_response_out : out std_logic_vector(12*8-1 downto 0);
333 
      snd_cmd_start    : out std_logic;
334 
      snd_start        : out std_logic;
335 
      snd_ready        : in  std_logic;
336 18 wzab 
      flushed          : out std_logic;
337 15 wzab 
      dmem_addr        : out std_logic_vector(LOG2_NWRDS_IN_PKT+LOG2_N_OF_PKTS-1 downto 0);
338 
      dmem_dta         : out std_logic_vector(63 downto 0);
339 
      dmem_we          : out std_logic;
340 
      ack_fifo_empty   : in  std_logic;
341 
      ack_fifo_rd_en   : out std_logic;
342 
      ack_fifo_dout    : in  std_logic_vector(pkt_ack_width-1 downto 0);
343 
      cmd_code         : out std_logic_vector(15 downto 0);
344 
      cmd_seq          : out std_logic_vector(15 downto 0);
345 
      cmd_arg          : out std_logic_vector(31 downto 0);
346 
      cmd_run          : out std_logic;
347 18 wzab 
      cmd_retr_s       : out std_logic;
348 15 wzab 
      cmd_ack          : in  std_logic;
349 
      cmd_response_in  : in  std_logic_vector(8*12-1 downto 0);
350 
      transmit_data    : in  std_logic;
351 
      transm_delay     : out unsigned(31 downto 0);
352 26 wzab 
      retr_count       : out std_logic_vector(31 downto 0);
353 15 wzab 
      dbg              : out std_logic_vector(3 downto 0);
354 
      clk              : in  std_logic;
355 
      rst_n            : in  std_logic);
356 
  end component desc_manager;
357 42 wzab 
 
358 15 wzab 
begin  -- beh1
359 
  my_mac                    <= x"de_ad_ba_be_be_ef";
360 
  -- Initialization vector
361 
  configuration_vector(33)  <= '1';     -- training
362 
  configuration_vector(284) <= '1';     -- auto negotiation
363 
 
364 
  signal_detect <= '1';                 -- allow transmission!
365 
 
366 
  rst_n    <= not rst_p;
367 
  refclk_n <= gtx_refclk_n;
368 
  refclk_p <= gtx_refclk_p;
369 
  reset    <= not rst_n;
370 
 
371 
  rx_crc <= std_logic_vector(pkt_number);  -- To be removed!
372 
 
373 18 wzab 
  trig_in <= '1' when xgmii_rxc /= x"ff" else '0';
374 15 wzab 
 
375 
 
376 
  ila_0_1 : ila_1
377 
    port map (
378 
      clk         => clk1,
379 
      trig_in     => trig_in,
380 
      trig_in_ack => trig_ack,
381 
      probe0      => xgmii_rxd,
382 
      probe1      => xgmii_rxc,
383 
      probe2      => probe2,
384 
      probe3      => core_status,
385 
      probe4      => dbg,
386 
      probe5      => rx_crc,
387 
      probe6      => std_logic_vector(ack_fifo_dbg.pkt),
388 
      probe7      => std_logic_vector(ack_fifo_dbg.cmd),
389 
      probe8      => rx_cmd,
390 
      probe9      => rx_arg,
391 18 wzab 
      probe10     => xgmii_txd,
392 
      probe11     => xgmii_txc
393 15 wzab 
      );
394 
 
395 
  probe2(0)    <= cmd_run;
396 
  probe2(1)    <= cmd_ack;
397 
  probe2(2)    <= cmd_retr_s;
398 
  ack_fifo_dbg <= stlv_to_pkt_ack(ack_fifo_din);
399 
 
400 
  ten_gig_eth_pcs_pma_0_1 : ten_gig_eth_pcs_pma_0
401 42 wzab 
 
402 15 wzab 
    port map (
403 26 wzab 
      dclk                   => clk_user,
404 42 wzab 
      rxrecclk_out           => open,   --??
405 15 wzab 
      refclk_p               => refclk_p,
406 
      refclk_n               => refclk_n,
407 42 wzab 
      sim_speedup_control    => '0',
408 
      coreclk_out            => core_clk156_out,
409 
      qplloutclk_out         => qplloutclk_out,
410 
      qplloutrefclk_out      => qplloutrefclk_out,
411 
      qplllock_out           => qplllock_out,
412 15 wzab 
      txusrclk_out           => s_txusrclk_out,
413 
      txusrclk2_out          => s_txusrclk2_out,
414 42 wzab 
      areset_datapathclk_out => areset_clk156_out,
415 15 wzab 
      gttxreset_out          => gttxreset_out,
416 
      gtrxreset_out          => gtrxreset_out,
417 
      txuserrdy_out          => txuserrdy_out,
418 
      reset_counter_done_out => reset_counter_done_out,
419 42 wzab 
      reset                  => reset,
420 
      gt0_eyescanreset       => '0',
421 
      gt0_eyescantrigger     => '0',
422 
      gt0_rxcdrhold          => '0',
423 
      gt0_txprbsforceerr     => '0',
424 
      gt0_txpolarity         => '1',
425 
      gt0_rxpolarity         => '1',
426 
      gt0_rxrate             => (others => '0'),
427 
      gt0_txpmareset         => '0',
428 
      gt0_rxpmareset         => '0',
429 
      gt0_rxdfelpmreset      => '0',
430 
      gt0_txprecursor        => (others => '0'),
431 
      gt0_txpostcursor       => (others => '0'),
432 
      gt0_txdiffctrl         => "1110",
433 
      gt0_rxlpmen            => '0',
434 
      gt0_eyescandataerror   => open,
435 
      gt0_txbufstatus        => open,
436 
      gt0_txresetdone        => open,
437 
      gt0_rxresetdone        => open,
438 
      gt0_rxbufstatus        => open,
439 
      gt0_rxprbserr          => open,
440 
      gt0_dmonitorout        => open,
441 15 wzab 
      xgmii_txd              => xgmii_txd,
442 
      xgmii_txc              => xgmii_txc,
443 
      xgmii_rxd              => xgmii_rxd,
444 
      xgmii_rxc              => xgmii_rxc,
445 42 wzab 
      txp                    => gtx10g_txp,
446 
      txn                    => gtx10g_txn,
447 
      rxp                    => gtx10g_rxp,
448 
      rxn                    => gtx10g_rxn,
449 15 wzab 
      configuration_vector   => configuration_vector,
450 
      status_vector          => status_vector,
451 
      core_status            => core_status,
452 42 wzab 
      resetdone_out          => s_resetdone,
453 15 wzab 
      signal_detect          => signal_detect,
454 
      tx_fault               => tx_fault,
455 
      drp_req                => drp_req,
456 
      drp_gnt                => drp_gnt,
457 
      drp_den_o              => drp_den_o,
458 
      drp_dwe_o              => drp_dwe_o,
459 
      drp_daddr_o            => drp_daddr_o,
460 
      drp_di_o               => drp_di_o,
461 42 wzab 
      drp_drdy_i             => drp_drdy_i,
462 
      drp_drpdo_i            => drp_drpdo_i,
463 15 wzab 
      drp_den_i              => drp_den_i,
464 
      drp_dwe_i              => drp_dwe_i,
465 
      drp_daddr_i            => drp_daddr_i,
466 
      drp_di_i               => drp_di_i,
467 42 wzab 
      drp_drdy_o             => drp_drdy_o,
468 
      drp_drpdo_o            => drp_drpdo_o,
469 26 wzab 
      pma_pmd_type           => "111",
470 42 wzab 
      tx_disable             => tx_disable
471 15 wzab 
      );
472 
 
473 
  drp_gnt     <= drp_req;
474 
  drp_den_i   <= drp_den_o;
475 
  drp_dwe_i   <= drp_dwe_o;
476 
  drp_daddr_i <= drp_daddr_o;
477 
  drp_di_i    <= drp_di_o;
478 
  drp_drpdo_i <= drp_drpdo_o;
479 
 
480 
  txusrclk_out <= rst_n;                --s_txusrclk_out;
481 
  resetdone    <= hb_led;               --s_resetdone;
482 
 
483 
  rst1       <= core_status(0);
484 
  core_ready <= core_status(0);
485 
  clk1       <= core_clk156_out;
486 
  clk_user   <= core_clk156_out;
487 
 
488 
 
489 
 
490 
  p1 : process (clk1, rst_n)
491 
  begin  -- process p1
492 
    if rst_n = '0' then                   -- asynchronous reset (active low)
493 
      heart_bit <= 0;
494 
    elsif clk1'event and clk1 = '1' then  -- rising clock edge
495 
      if heart_bit < 80000000 then
496 
        heart_bit <= heart_bit + 1;
497 
      else
498 
        heart_bit <= 0;
499 
        hb_led    <= not hb_led;
500 
      end if;
501 
    end if;
502 
  end process p1;
503 
 
504 
  --addr_a <= to_integer(unsigned(dmem_addr));
505 
  --addr_b <= to_integer(unsigned(tx_mem_addr));
506 
 
507 
  dp_ram_scl_1 : dp_ram_scl
508 
    generic map (
509 
      DATA_WIDTH => 64,
510 
      ADDR_WIDTH => LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT)
511 
    port map (
512 
      clk_a  => clk_user,
513 
      we_a   => dmem_we,
514 
      addr_a => dmem_addr,
515 
      data_a => dmem_dta,
516 
      q_a    => open,
517 
      clk_b  => clk1,
518 
      we_b   => '0',
519 
      addr_b => tx_mem_addr,
520 
      data_b => (others => '0'),
521 
      q_b    => tx_mem_data);
522 
 
523 
  desc_manager_1 : desc_manager
524 
    generic map (
525 
      LOG2_N_OF_PKTS => LOG2_N_OF_PKTS,
526 
      N_OF_PKTS      => N_OF_PKTS)
527 
    port map (
528 
      dta              => dta,
529 
      dta_we           => dta_we,
530 18 wzab 
      dta_eod          => dta_eod,
531 15 wzab 
      dta_ready        => dta_ready,
532 
      pkt_number       => pkt_number,
533 
      seq_number       => seq_number,
534 
      cmd_response_out => cmd_response_out,
535 
      snd_cmd_start    => cmd_start,
536 
      snd_start        => snd_start,
537 18 wzab 
      flushed          => flushed,
538 15 wzab 
      snd_ready        => snd_ready,
539 
      dmem_addr        => dmem_addr,
540 
      dmem_dta         => dmem_dta,
541 
      dmem_we          => dmem_we,
542 
      ack_fifo_empty   => ack_fifo_empty,
543 
      ack_fifo_rd_en   => ack_fifo_rd_en,
544 
      ack_fifo_dout    => ack_fifo_dout,
545 
      cmd_code         => cmd_code,
546 
      cmd_seq          => cmd_seq,
547 
      cmd_arg          => cmd_arg,
548 
      cmd_run          => cmd_run,
549 18 wzab 
      cmd_retr_s       => cmd_retr_s,
550 15 wzab 
      cmd_ack          => cmd_ack,
551 
      cmd_response_in  => cmd_response_in,
552 
      transmit_data    => transmit_data,
553 
      transm_delay     => transm_delay,
554 26 wzab 
      retr_count       => retr_count,
555 15 wzab 
      dbg              => dbg,
556 
      clk              => clk_user,
557 
      rst_n            => fade_rst_n);
558 
 
559 
  cmd_proc_1 : cmd_proc
560 
    port map (
561 
      cmd_code     => cmd_code,
562 
      cmd_seq      => cmd_seq,
563 
      cmd_arg      => cmd_arg,
564 
      cmd_run      => cmd_run,
565 
      cmd_ack      => cmd_ack,
566 
      cmd_response => cmd_response_in,
567 
      clk          => clk_user,
568 26 wzab 
      rst_p        => fade_rst_p,
569 
      retr_count   => retr_count
570 
      );
571 15 wzab 
 
572 
  eth_sender_1 : eth_sender
573 
    port map (
574 
      peer_mac      => peer_mac,
575 
      my_mac        => my_mac,
576 
      my_ether_type => my_ether_type,
577 
      pkt_number    => pkt_number,
578 
      seq_number    => seq_number,
579 
      transm_delay  => transm_delay,
580 
      clk           => clk_user,
581 
      rst_n         => fade_rst_n,
582 
      ready         => snd_ready,
583 18 wzab 
      flushed       => flushed,
584 15 wzab 
      start         => snd_start,
585 
      cmd_start     => cmd_start,
586 
      tx_mem_addr   => tx_mem_addr,
587 
      tx_mem_data   => tx_mem_data,
588 
      cmd_response  => cmd_response_out,
589 
      Tx_Clk        => clk1,
590 
      TxC           => xgmii_txc,
591 
      TxD           => xgmii_txd);
592 
 
593 
  eth_receiver_2 : eth_receiver
594 
    port map (
595 
      peer_mac       => peer_mac,
596 
      my_mac         => my_mac,
597 
      my_ether_type  => my_ether_type,
598 
      transmit_data  => transmit_data,
599 
      restart        => restart,
600 
      ack_fifo_full  => ack_fifo_full,
601 
      ack_fifo_wr_en => ack_fifo_wr_en,
602 
      ack_fifo_din   => ack_fifo_din,
603 
      clk            => clk_user,
604 
      rst_n          => fade_rst_n,
605 
      dbg            => open,
606 
      cmd            => rx_cmd,
607 
      arg            => rx_arg,
608 
      Rx_Clk         => clk1,
609 
      RxC            => xgmii_rxc,
610 
      RxD            => xgmii_rxd);
611 
 
612 
  ack_fifo_1 : ack_fifo
613 
    port map (
614 
      rst    => fade_rst_p,
615 
      wr_clk => clk1,
616 
      rd_clk => Clk_user,
617 
      din    => ack_fifo_din,
618 
      wr_en  => ack_fifo_wr_en,
619 
      rd_en  => ack_fifo_rd_en,
620 
      dout   => ack_fifo_dout,
621 
      full   => ack_fifo_full,
622 
      empty  => ack_fifo_empty);
623 
 
624 
 
625 
  -- signal generator
626 
 
627 
  s_dta_we <= '1' when dta_ready = '1' and transmit_data = '1' else '0';
628 
 
629 18 wzab 
  dta_we <= s_dta_we;
630 
 
631 15 wzab 
  dta <= std_logic_vector(test_dta);
632 
 
633 
  process (Clk_user, rst_n)
634 
  begin  -- process
635 26 wzab 
    if fade_rst_n = '0' then            -- asynchronous reset (active low)
636 15 wzab 
      test_dta <= (others => '0');
637 18 wzab 
      td_del0  <= '0';
638 
      td_del1  <= '0';
639 15 wzab 
    elsif Clk_user'event and Clk_user = '1' then  -- rising clock edge
640 
      if s_dta_we = '1' then
641 
        test_dta <= test_dta + x"1234567809abcdef";
642 
      end if;
643 18 wzab 
      -- Generate the dta_eod pulse after transmit_data
644 
      -- goes low
645 
      td_del0 <= transmit_data;
646 
      td_del1 <= td_del0;
647 
      if (td_del1 = '1') and (td_del0 = '0') then
648 
        dta_eod <= '1';
649 
      else
650 
        dta_eod <= '0';
651 
      end if;
652 15 wzab 
    end if;
653 
  end process;
654 
 
655 
  process (Clk_user, rst_n)
656 
  begin  -- process
657 
    if rst_n = '0' then                 -- asynchronous reset (active low)
658 
      fade_rst_n   <= '0';
659 
      fade_rst_del <= '0';
660 
    elsif Clk_user'event and Clk_user = '1' then  -- rising clock edge
661 
      if restart = '1' then
662 
        fade_rst_n   <= '0';
663 
        fade_rst_del <= '0';
664 
      else
665 
        fade_rst_del <= '1';
666 
        fade_rst_n   <= fade_rst_del;
667 
      end if;
668 
    end if;
669 
  end process;
670 
 
671 
  fade_rst_p <= not fade_rst_n;
672 42 wzab 
 
673 15 wzab 
end beh1;

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