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craighaywo |
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity sseg is
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Port (
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CLK : in STD_LOGIC;
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VAL_IN : in STD_LOGIC_VECTOR (15 downto 0);
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SSEG_OUT : out STD_LOGIC_VECTOR(7 downto 0);
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AN_OUT : out STD_LOGIC_VECTOR(3 downto 0));
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end sseg;
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architecture Behavioral of sseg is
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constant C_clk_div_400hz : std_logic_vector(19 downto 0) := X"1E847";
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signal clk_div_counter : std_logic_vector(19 downto 0) := (others => '0');
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signal clk_400hz : std_logic := '0';
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signal digit_pattern_array : std_logic_vector(7 downto 0) := "00000000";
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signal current_segment : std_logic_vector(1 downto 0) := "00";
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signal cathode_select : std_logic_vector(3 downto 0) := "0000";
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signal current_digit : std_logic_vector(3 downto 0) := "0000";
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begin
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SSEG_OUT <= digit_pattern_array;
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AN_OUT <= cathode_select;
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-- Slows up CLK from 50MHz to MUX_CLK 400Hz.
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process(CLK)
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begin
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if rising_edge(CLK) then
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if clk_div_counter = C_clk_div_400hz then
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clk_div_counter <= (others => '0');
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clk_400hz <= '1';
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else
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clk_div_counter <= clk_div_counter + 1;
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clk_400hz <= '0';
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end if;
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end if;
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end process;
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process(CLK)
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begin
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if rising_edge(CLK) then
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case current_digit is
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when "0000" => digit_pattern_array <= "00000011";
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when "0001" => digit_pattern_array <= "10011111";
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when "0010" => digit_pattern_array <= "00100101";
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when "0011" => digit_pattern_array <= "00001101";
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when "0100" => digit_pattern_array <= "10011001";
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when "0101" => digit_pattern_array <= "01001001";
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when "0110" => digit_pattern_array <= "01000001";
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when "0111" => digit_pattern_array <= "00011111";
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when "1000" => digit_pattern_array <= "00000001";
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when "1001" => digit_pattern_array <= "00011001";
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when "1010" => digit_pattern_array <= "00010001";
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when "1011" => digit_pattern_array <= "11000001";
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when "1100" => digit_pattern_array <= "01100011";
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when "1101" => digit_pattern_array <= "10000101";
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when "1110" => digit_pattern_array <= "01100001";
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when "1111" => digit_pattern_array <= "01110001";
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when others => null;
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end case;
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end if;
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end process;
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process(CLK)
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begin
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if rising_edge(CLK) then
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if clk_400hz = '1' then
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current_segment <= current_segment + 1;
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case current_segment is
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when "00" =>
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cathode_select <= "1110";
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current_digit <= VAL_IN(3 downto 0);
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when "01" =>
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cathode_select <= "1101";
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current_digit <= VAL_IN(7 downto 4);
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when "10" =>
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cathode_select <= "1011";
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current_digit <= VAL_IN(11 downto 8);
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when "11" =>
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cathode_select <= "0111";
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current_digit <= VAL_IN(15 downto 12);
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when others => null;
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end case;
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end if;
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end if;
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end process;
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end Behavioral;
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