URL https://opencores.org/ocsvn/fft_fir_filter/fft_fir_filter/trunk

Subversion Repositories fft_fir_filter

[/] [fft_fir_filter/] [trunk/] [rtl/] [alfft_core_sli.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log


---------------------------------------------------------------------
----                                                             ----
----  FFT Filter IP core                                         ----
----                                                             ----
----  Authors: Anatoliy Sergienko, Volodya Lepeha                ----
----  Company: Unicore Systems http://unicore.co.ua              ----
----                                                             ----
----  Downloaded from: http://www.opencores.org                  ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2006-2010 Unicore Systems LTD                 ----
---- www.unicore.co.ua                                           ----
---- o.uzenkov@unicore.co.ua                                     ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
---- THIS SOFTWARE IS PROVIDED "AS IS"                           ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT              ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT         ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION)                 ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,              ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING                 ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,                 ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.          ----
----                                                             ----
---------------------------------------------------------------------
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~           
--              DESCRIPTION:
--
--      FUNCTION         Fast Fourier Transform of
--                       N=16, 32, 64, 128, 256, 512, 1024, 2048 points,
--                       N= 2**n,
--                       ifft=0 forward FFT, =1 inverse FFT
--                       rams=1 - single data RAM, =2 dual data RAM
--                       input data width: iwidth = 8,...,16 bit   signed 
--                                             output   data width: owidth = 8,...,16 bit   signed     
--                       coefficient width : wwidth = 8,...,16 bit
--                                  Synthesable for Virtex, SpartanII FPGAs. 
--             
--      FILES:           ALFFT_Core_sli.vhd -this file
--               FFTDPATHi.vhd   - data path of the FFT butterfly                        
--               CONTROL_i.vhd   - control unit       
--                                    ROM_COSi.vhd   -  coefficient ROM
--                                   RAMX_2.vhd   - data RAM block                  
--                  When redesign data RAM blocks
--                     the Core will fit another FPGA families
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
entity ALFFT_Corei is
        generic (width: INTEGER:=8      ;       -- output data width =8...16
                wwidth: INTEGER:=8;                     --  coefficient width =8...16  
                n:INTEGER:=7 ;
                v2:INTEGER:=1 ; -- 1 - Virtex2
                reall:INTEGER:= 0  --wch. mass: 0 -complex 1 - 2 realnych
                );  --4,5, 6,7,8,9,10,11   - transform length factor
        port (
                CLK: in STD_LOGIC;
                RST: in STD_LOGIC;
                CE: in STD_LOGIC;
                START: in STD_LOGIC;
                FILTER: in STD_LOGIC_VECTOR (1 downto 0);                --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff
                L1:in STD_LOGIC_VECTOR (n-1 downto 0);            -- tsastoty filtrow
                H1:in STD_LOGIC_VECTOR (n-1 downto 0);            -- tsastoty filtrow
                L2:in STD_LOGIC_VECTOR (n-1 downto 0);
                H2:in STD_LOGIC_VECTOR (n-1 downto 0);
                DATAE: in STD_LOGIC;
                DATAIRE: in STD_LOGIC_VECTOR (width-1 downto 0);
                DATAIIM: in STD_LOGIC_VECTOR (width-1 downto 0);
                FFTRDY: out STD_LOGIC;
                READY: out STD_LOGIC;
                WERES: out STD_LOGIC;
                ADDRRES: inout STD_LOGIC_VECTOR (n-1 downto 0);
                DATAORE: out STD_LOGIC_VECTOR (width-1 downto 0);
                DATAOIM: out STD_LOGIC_VECTOR (width-1 downto 0);
                EXP: out STD_LOGIC_VECTOR (3 downto 0)
                );
end ALFFT_Corei;
 
architecture ALFFT_CoreS of ALFFT_Corei is
 
        component  FFTDPATHI is
                generic (width: integer :=8     ;               --  word width =8...16
                        wwdth: integer:=7;                      --  coefficient width =7...15  
                        reall:integer;
                        V2:integer
                        );
                port (
                        CLK: in STD_LOGIC;
                        RST: in STD_LOGIC;
                        CE: in STD_LOGIC;
                        ODDC:     in STD_LOGIC;      --Odd cycle
                        DIV2: in STD_LOGIC;             --Scaling factor
                        ZWR: in STD_LOGIC;
                        ZWI: in STD_LOGIC;
                        SIGNRE:  in STD_LOGIC;
                        MODE: in STD_LOGIC_VECTOR (1 downto 0);
                        REDI: in STD_LOGIC_VECTOR (width downto 0);
                        IMDI: in STD_LOGIC_VECTOR (width downto 0);
                        WF: in STD_LOGIC_VECTOR (wwdth-1 downto 0);
                        REDO: out STD_LOGIC_VECTOR (width downto 0);
                        IMDO: out STD_LOGIC_VECTOR (width downto 0)
                        );
        end  component;
 
        component  ROM_COSi is
                generic(n: integer; --- FFT factor= 6,7,8,9,10,11
                        wwdth: integer:=15;-- output word width =8...15  , cos>0
                        wnd: integer);
                port  ( SELW:in STD_LOGIC_vector(1 downto 0);
                        ADDRROM :in std_logic_vector(n-2 downto 0);
                        COS : out std_logic_vector(wwdth-1 downto 0)
                        );
        end component ;
 
 
 
 
 
        component CONTROLi is
                generic (n:INTEGER;  -- 6,7,8,9,10,11
                        reall:INTEGER:= 0  --wch. mass: 0 -complex 1 - 2 realnych
                        );
                port (
                        CLK: in STD_LOGIC;
                        RST: in STD_LOGIC;
                        CE: in STD_LOGIC;
                        START: in STD_LOGIC;
                        DATAE: in STD_LOGIC;
                        OVERF: in STD_LOGIC;
                        FILTER: in STD_LOGIC_VECTOR (1 downto 0);                --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff
                        L1:in STD_LOGIC_VECTOR (n-1 downto 0);            -- tsastoty filtrow
                        H1:in STD_LOGIC_VECTOR (n-1 downto 0);            -- tsastoty filtrow
                        L2:in STD_LOGIC_VECTOR (n-1 downto 0);
                        H2:in STD_LOGIC_VECTOR (n-1 downto 0);
                        FFTRDY: out STD_LOGIC;
                        READY: out STD_LOGIC;
                        WEI: out STD_LOGIC;
                        WEM: out STD_LOGIC;
                        WERES: out STD_LOGIC;
                        ODDC:     out STD_LOGIC;
                        EVEN: out STD_LOGIC;                     --0- 0th bank 1- 1st bank -for DIRE,DIIM
                        DIV2: out STD_LOGIC;
                        ZWR: out STD_LOGIC;
                        ZWI: out STD_LOGIC;
                        RESRAM:   out STD_LOGIC;
                        SIGNRE:  out STD_LOGIC;
                        INITOVERF:   out STD_LOGIC;
                        SEL: out STD_LOGIC;       -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM 
                        SELW: out STD_LOGIC_vector(1 downto 0);    --0 -twiddle 1 - window  
                        MODE: out STD_LOGIC_VECTOR (1 downto 0);
                        EXP: out STD_LOGIC_VECTOR (3 downto 0);
                        ADDRR: out STD_LOGIC_VECTOR (n  downto 0);
                        ADDRWM: out STD_LOGIC_VECTOR (n downto 0) ;
                        ADDRRES: out STD_LOGIC_VECTOR (n - 1 downto 0);
                        ADDRROM :out STD_LOGIC_VECTOR(n- 2 downto 0)
                        );
        end component ;
        component  RAM1X_2 is
                generic(width : INTEGER;
                        n:INTEGER;        -- 6,7,8,9,10,11
                        v2:INTEGER:=1);
                port (
                        CLK: in STD_LOGIC;
                        RST: in STD_LOGIC;
                        CE: in STD_LOGIC;
                        WE: in STD_LOGIC;
                        INITOVERF:    in STD_LOGIC;
                        ADDRW: in STD_LOGIC_VECTOR (n downto 0);
                        ADDRR: in STD_LOGIC_VECTOR (n downto 0);
                        SEL: in STD_LOGIC;                              -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM
                        RESRAM:  in STD_LOGIC;
                        DIRE: in STD_LOGIC_VECTOR (width-1 downto 0);
                        DIIM: in STD_LOGIC_VECTOR (width-1 downto 0);
                        DMRE: in STD_LOGIC_VECTOR (width-1 downto 0);
                        DMIM: in STD_LOGIC_VECTOR (width-1 downto 0);
                        OVERF:out  STD_LOGIC;
                        DORE: out STD_LOGIC_VECTOR (width-1 downto 0);
                        DOIM: out STD_LOGIC_VECTOR (width-1 downto 0)
                        );
        end      component;
 
        --constant zeros: STD_LOGIC_VECTOR (owidth-iwidth-1 downto 0):=(others=>'0');
        signal  ODDC:   STD_LOGIC;      --Odd cycle
        signal  DIV2:  STD_LOGIC;             --Scaling factor
        signal          ZWR: STD_LOGIC;
        signal          ZWI:  STD_LOGIC;
        signal          SIGNRE:  STD_LOGIC;
        signal          REDI:  STD_LOGIC_VECTOR (width-1 downto 0);
        signal          IMDI:  STD_LOGIC_VECTOR (width-1 downto 0);
        signal          WF:  STD_LOGIC_VECTOR (wwidth-2 downto 0);
        signal          REDO: STD_LOGIC_VECTOR (width-1 downto 0);
        signal          IMDO:  STD_LOGIC_VECTOR (width-1 downto 0);
        signal      OVERF: STD_LOGIC;
        signal          INITOVERF:     STD_LOGIC;
        signal          WEI: STD_LOGIC;
        signal          WEM: STD_LOGIC;
        signal          SEL:  STD_LOGIC;          -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM 
        signal     SELW:STD_LOGIC_vector(1 downto 0);
        signal          EVEN:  STD_LOGIC;                        --0- 0th bank 1- 1st bank -for DIRE,DIIM
        signal          ADDRW: STD_LOGIC_VECTOR (n - 1 downto 0);
        signal          ADDRR:  STD_LOGIC_VECTOR (n  downto 0);
        signal          ADDRWM: STD_LOGIC_VECTOR (n  downto 0) ;
        signal          ADDRROM : STD_LOGIC_VECTOR(n- 2 downto 0);
        signal      MODE: STD_LOGIC_VECTOR (1 downto 0);
        signal    sn11,sn12:integer;
        signal                  RESRAM:  STD_LOGIC;
 
 
        signal DIRE,DIIM:    STD_LOGIC_VECTOR (width-1 downto 0);
begin
 
        DIRE<=DATAIRE;-- & zeros;
        DIIM<=DATAIIM;-- & zeros;
 
 
        U_PATH:  FFTDPATHI
        generic map(width=>width-1,             --  word width =7...15
                wwdth=>wwidth-1,                        --  coefficient width =7...15  
                reall=>reall,
                V2=>v2
                )
        port map(
                CLK=>  CLK,
                RST=> RST,
                CE=>  CE,
                MODE=>mode,
                ODDC=>ODDC,         --Odd cycle
                DIV2=>    DIV2,           --Scaling factor
                ZWR=>  ZWR,
                ZWI=>    ZWI,
                SIGNRE=>SIGNRE,
                REDI=>REDI,
                IMDI=> IMDI,
                WF=> WF,
                REDO=>REDO,
                IMDO=>IMDO
                );
 
        U_ROM:ROM_COSi
        generic map(n=>n, --- FFT factor= 6,7,8,9,10,11
                wwdth=>wwidth-1, -- output word width =8...15  , cos>0
                wnd=>1 --okno blackmana
                )
        port map (
                SELW=>selw,
                ADDRROM =>ADDRROM,
                COS =>WF);
 
 
        --      CNTR_SLIP2: if slip=2 generate  
        U_CNTRL: CONTROLi
        generic map(n=>n ,                   -- 6,7,8,9,10,11
                reall=>reall
                )
        port map(
                CLK=>CLK ,
                RST=> RST,
                CE=>CE ,
                filter=>filter,         --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff
                L1=>L1,          -- tsastoty filtrow
                H1=>H1,
                L2=>L2,
                H2=>H2,
                START=>START ,
                DATAE=> DATAE,
                OVERF=> OVERF,
                FFTRDY=>        FFTRDY,
                READY=> READY,
                --      WEI=> WEI,
                WEM=> WEM,
                RESRAM=>RESRAM,
                INITOVERF=>INITOVERF,
                WERES=>WERES,
                SEL=>SEL ,      -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM 
                ODDC=>ODDC,
                MODE=>mode,
                EVEN=> EVEN,                     --0- 0th bank 1- 1st bank -for DIRE,DIIM
                DIV2=> DIV2,
                ZWR=> ZWR,
                ZWI=> ZWI,
                SELW=>selw,
                SIGNRE=>SIGNRE ,
                EXP=>EXP,
                ADDRR=> ADDRR,
                ADDRWM=> ADDRWM,
                ADDRRES=>ADDRRES,
                ADDRROM =>ADDRROM
                );
 
        U_RAM:   RAM1X_2
        generic map(
                width =>width,
                n=>n              -- 6,7,8,9,10,11
                ,v2=>v2
                )
        port map(
                CLK=>CLK ,
                RST=> RST,
                CE=> CE,
                WE=> WEM,          -- for input data
                ADDRW=> ADDRWM,
                ADDRR=> ADDRR,
                SEL=>SEL,
                DIRE=>DIRE,
                RESRAM=>RESRAM,
                DIIM=> DIIM,
                DMRE=> REDO,
                DMIM=> IMDO,
                OVERF=> OVERF ,
                INITOVERF=>INITOVERF,
                DORE=>REDI,
                DOIM=> IMDI
                );
 
 
 
        DATAORE<=REDO ;
        DATAOIM<=IMDO ;
 
        sn11<=conv_integer(signed(redo));--when addrres(n-1)='0' else 0;        
        sn12<=conv_integer(signed(imdo));
 
 
end ALFFT_CoreS;

Browse

Tools

Subversion Repositories fft_fir_filter

[/] [fft_fir_filter/] [trunk/] [rtl/] [alfft_core_sli.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	unicore	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- FFT Filter IP core ----`
4			`---- ----`
5			`---- Authors: Anatoliy Sergienko, Volodya Lepeha ----`
6			`---- Company: Unicore Systems http://unicore.co.ua ----`
7			`---- ----`
8			`---- Downloaded from: http://www.opencores.org ----`
9			`---- ----`
10			`---------------------------------------------------------------------`
11			`---- ----`
12			`---- Copyright (C) 2006-2010 Unicore Systems LTD ----`
13			`---- www.unicore.co.ua ----`
14			`---- o.uzenkov@unicore.co.ua ----`
15			`---- ----`
16			`---- This source file may be used and distributed without ----`
17			`---- restriction provided that this copyright statement is not ----`
18			`---- removed from the file and that any derivative work contains ----`
19			`---- the original copyright notice and the associated disclaimer.----`
20			`---- ----`
21			`---- THIS SOFTWARE IS PROVIDED "AS IS" ----`
22			`---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----`
23			`---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----`
24			`---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----`
25			`---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----`
26			`---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----`
27			`---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
28			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----`
29			`---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----`
30			`---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----`
31			`---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----`
32			`---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----`
33			`---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
34			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----`
35			`---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----`
36			`---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----`
37			`---- ----`
38			`---------------------------------------------------------------------`
39			`--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~`
40			`-- DESCRIPTION:`
41			`--`
42			`-- FUNCTION Fast Fourier Transform of`
43			`-- N=16, 32, 64, 128, 256, 512, 1024, 2048 points,`
44			`-- N= 2**n,`
45			`-- ifft=0 forward FFT, =1 inverse FFT`
46			`-- rams=1 - single data RAM, =2 dual data RAM`
47			`-- input data width: iwidth = 8,...,16 bit signed`
48			`-- output data width: owidth = 8,...,16 bit signed`
49			`-- coefficient width : wwidth = 8,...,16 bit`
50			`-- Synthesable for Virtex, SpartanII FPGAs.`
51			`--`
52			`-- FILES: ALFFT_Core_sli.vhd -this file`
53			`-- FFTDPATHi.vhd - data path of the FFT butterfly`
54			`-- CONTROL_i.vhd - control unit`
55			`-- ROM_COSi.vhd - coefficient ROM`
56			`-- RAMX_2.vhd - data RAM block`
57			`-- When redesign data RAM blocks`
58			`-- the Core will fit another FPGA families`
59			`--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--`
60
61			`library IEEE;`
62			`use IEEE.std_logic_1164.all;`
63			`use IEEE.std_logic_arith.all;`
64
65			`entity ALFFT_Corei is`
66			`generic (width: INTEGER:=8 ; -- output data width =8...16`
67			`wwidth: INTEGER:=8; -- coefficient width =8...16`
68			`n:INTEGER:=7 ;`
69			`v2:INTEGER:=1 ; -- 1 - Virtex2`
70			`reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych`
71			`); --4,5, 6,7,8,9,10,11 - transform length factor`
72			`port (`
73			`CLK: in STD_LOGIC;`
74			`RST: in STD_LOGIC;`
75			`CE: in STD_LOGIC;`
76			`START: in STD_LOGIC;`
77			`FILTER: in STD_LOGIC_VECTOR (1 downto 0); --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff`
78			`L1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow`
79			`H1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow`
80			`L2:in STD_LOGIC_VECTOR (n-1 downto 0);`
81			`H2:in STD_LOGIC_VECTOR (n-1 downto 0);`
82			`DATAE: in STD_LOGIC;`
83			`DATAIRE: in STD_LOGIC_VECTOR (width-1 downto 0);`
84			`DATAIIM: in STD_LOGIC_VECTOR (width-1 downto 0);`
85			`FFTRDY: out STD_LOGIC;`
86			`READY: out STD_LOGIC;`
87			`WERES: out STD_LOGIC;`
88			`ADDRRES: inout STD_LOGIC_VECTOR (n-1 downto 0);`
89			`DATAORE: out STD_LOGIC_VECTOR (width-1 downto 0);`
90			`DATAOIM: out STD_LOGIC_VECTOR (width-1 downto 0);`
91			`EXP: out STD_LOGIC_VECTOR (3 downto 0)`
92			`);`
93			`end ALFFT_Corei;`
94
95			`architecture ALFFT_CoreS of ALFFT_Corei is`
96
97			`component FFTDPATHI is`
98			`generic (width: integer :=8 ; -- word width =8...16`
99			`wwdth: integer:=7; -- coefficient width =7...15`
100			`reall:integer;`
101			`V2:integer`
102			`);`
103			`port (`
104			`CLK: in STD_LOGIC;`
105			`RST: in STD_LOGIC;`
106			`CE: in STD_LOGIC;`
107			`ODDC: in STD_LOGIC; --Odd cycle`
108			`DIV2: in STD_LOGIC; --Scaling factor`
109			`ZWR: in STD_LOGIC;`
110			`ZWI: in STD_LOGIC;`
111			`SIGNRE: in STD_LOGIC;`
112			`MODE: in STD_LOGIC_VECTOR (1 downto 0);`
113			`REDI: in STD_LOGIC_VECTOR (width downto 0);`
114			`IMDI: in STD_LOGIC_VECTOR (width downto 0);`
115			`WF: in STD_LOGIC_VECTOR (wwdth-1 downto 0);`
116			`REDO: out STD_LOGIC_VECTOR (width downto 0);`
117			`IMDO: out STD_LOGIC_VECTOR (width downto 0)`
118			`);`
119			`end component;`
120
121			`component ROM_COSi is`
122			`generic(n: integer; --- FFT factor= 6,7,8,9,10,11`
123			`wwdth: integer:=15;-- output word width =8...15 , cos>0`
124			`wnd: integer);`
125			`port ( SELW:in STD_LOGIC_vector(1 downto 0);`
126			`ADDRROM :in std_logic_vector(n-2 downto 0);`
127			`COS : out std_logic_vector(wwdth-1 downto 0)`
128			`);`
129			`end component ;`
130
131
132
133
134
135			`component CONTROLi is`
136			`generic (n:INTEGER; -- 6,7,8,9,10,11`
137			`reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych`
138			`);`
139			`port (`
140			`CLK: in STD_LOGIC;`
141			`RST: in STD_LOGIC;`
142			`CE: in STD_LOGIC;`
143			`START: in STD_LOGIC;`
144			`DATAE: in STD_LOGIC;`
145			`OVERF: in STD_LOGIC;`
146			`FILTER: in STD_LOGIC_VECTOR (1 downto 0); --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff`
147			`L1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow`
148			`H1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow`
149			`L2:in STD_LOGIC_VECTOR (n-1 downto 0);`
150			`H2:in STD_LOGIC_VECTOR (n-1 downto 0);`
151			`FFTRDY: out STD_LOGIC;`
152			`READY: out STD_LOGIC;`
153			`WEI: out STD_LOGIC;`
154			`WEM: out STD_LOGIC;`
155			`WERES: out STD_LOGIC;`
156			`ODDC: out STD_LOGIC;`
157			`EVEN: out STD_LOGIC; --0- 0th bank 1- 1st bank -for DIRE,DIIM`
158			`DIV2: out STD_LOGIC;`
159			`ZWR: out STD_LOGIC;`
160			`ZWI: out STD_LOGIC;`
161			`RESRAM: out STD_LOGIC;`
162			`SIGNRE: out STD_LOGIC;`
163			`INITOVERF: out STD_LOGIC;`
164			`SEL: out STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM`
165			`SELW: out STD_LOGIC_vector(1 downto 0); --0 -twiddle 1 - window`
166			`MODE: out STD_LOGIC_VECTOR (1 downto 0);`
167			`EXP: out STD_LOGIC_VECTOR (3 downto 0);`
168			`ADDRR: out STD_LOGIC_VECTOR (n downto 0);`
169			`ADDRWM: out STD_LOGIC_VECTOR (n downto 0) ;`
170			`ADDRRES: out STD_LOGIC_VECTOR (n - 1 downto 0);`
171			`ADDRROM :out STD_LOGIC_VECTOR(n- 2 downto 0)`
172			`);`
173			`end component ;`
174			`component RAM1X_2 is`
175			`generic(width : INTEGER;`
176			`n:INTEGER; -- 6,7,8,9,10,11`
177			`v2:INTEGER:=1);`
178			`port (`
179			`CLK: in STD_LOGIC;`
180			`RST: in STD_LOGIC;`
181			`CE: in STD_LOGIC;`
182			`WE: in STD_LOGIC;`
183			`INITOVERF: in STD_LOGIC;`
184			`ADDRW: in STD_LOGIC_VECTOR (n downto 0);`
185			`ADDRR: in STD_LOGIC_VECTOR (n downto 0);`
186			`SEL: in STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM`
187			`RESRAM: in STD_LOGIC;`
188			`DIRE: in STD_LOGIC_VECTOR (width-1 downto 0);`
189			`DIIM: in STD_LOGIC_VECTOR (width-1 downto 0);`
190			`DMRE: in STD_LOGIC_VECTOR (width-1 downto 0);`
191			`DMIM: in STD_LOGIC_VECTOR (width-1 downto 0);`
192			`OVERF:out STD_LOGIC;`
193			`DORE: out STD_LOGIC_VECTOR (width-1 downto 0);`
194			`DOIM: out STD_LOGIC_VECTOR (width-1 downto 0)`
195			`);`
196			`end component;`
197
198			`--constant zeros: STD_LOGIC_VECTOR (owidth-iwidth-1 downto 0):=(others=>'0');`
199			`signal ODDC: STD_LOGIC; --Odd cycle`
200			`signal DIV2: STD_LOGIC; --Scaling factor`
201			`signal ZWR: STD_LOGIC;`
202			`signal ZWI: STD_LOGIC;`
203			`signal SIGNRE: STD_LOGIC;`
204			`signal REDI: STD_LOGIC_VECTOR (width-1 downto 0);`
205			`signal IMDI: STD_LOGIC_VECTOR (width-1 downto 0);`
206			`signal WF: STD_LOGIC_VECTOR (wwidth-2 downto 0);`
207			`signal REDO: STD_LOGIC_VECTOR (width-1 downto 0);`
208			`signal IMDO: STD_LOGIC_VECTOR (width-1 downto 0);`
209			`signal OVERF: STD_LOGIC;`
210			`signal INITOVERF: STD_LOGIC;`
211			`signal WEI: STD_LOGIC;`
212			`signal WEM: STD_LOGIC;`
213			`signal SEL: STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM`
214			`signal SELW:STD_LOGIC_vector(1 downto 0);`
215			`signal EVEN: STD_LOGIC; --0- 0th bank 1- 1st bank -for DIRE,DIIM`
216			`signal ADDRW: STD_LOGIC_VECTOR (n - 1 downto 0);`
217			`signal ADDRR: STD_LOGIC_VECTOR (n downto 0);`
218			`signal ADDRWM: STD_LOGIC_VECTOR (n downto 0) ;`
219			`signal ADDRROM : STD_LOGIC_VECTOR(n- 2 downto 0);`
220			`signal MODE: STD_LOGIC_VECTOR (1 downto 0);`
221			`signal sn11,sn12:integer;`
222			`signal RESRAM: STD_LOGIC;`
223
224
225			`signal DIRE,DIIM: STD_LOGIC_VECTOR (width-1 downto 0);`
226			`begin`
227
228			`DIRE<=DATAIRE;-- & zeros;`
229			`DIIM<=DATAIIM;-- & zeros;`
230
231
232			`U_PATH: FFTDPATHI`
233			`generic map(width=>width-1, -- word width =7...15`
234			`wwdth=>wwidth-1, -- coefficient width =7...15`
235			`reall=>reall,`
236			`V2=>v2`
237			`)`
238			`port map(`
239			`CLK=> CLK,`
240			`RST=> RST,`
241			`CE=> CE,`
242			`MODE=>mode,`
243			`ODDC=>ODDC, --Odd cycle`
244			`DIV2=> DIV2, --Scaling factor`
245			`ZWR=> ZWR,`
246			`ZWI=> ZWI,`
247			`SIGNRE=>SIGNRE,`
248			`REDI=>REDI,`
249			`IMDI=> IMDI,`
250			`WF=> WF,`
251			`REDO=>REDO,`
252			`IMDO=>IMDO`
253			`);`
254
255			`U_ROM:ROM_COSi`
256			`generic map(n=>n, --- FFT factor= 6,7,8,9,10,11`
257			`wwdth=>wwidth-1, -- output word width =8...15 , cos>0`
258			`wnd=>1 --okno blackmana`
259			`)`
260			`port map (`
261			`SELW=>selw,`
262			`ADDRROM =>ADDRROM,`
263			`COS =>WF);`
264
265
266			`-- CNTR_SLIP2: if slip=2 generate`
267			`U_CNTRL: CONTROLi`
268			`generic map(n=>n , -- 6,7,8,9,10,11`
269			`reall=>reall`
270			`)`
271			`port map(`
272			`CLK=>CLK ,`
273			`RST=> RST,`
274			`CE=>CE ,`
275			`filter=>filter, --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff`
276			`L1=>L1, -- tsastoty filtrow`
277			`H1=>H1,`
278			`L2=>L2,`
279			`H2=>H2,`
280			`START=>START ,`
281			`DATAE=> DATAE,`
282			`OVERF=> OVERF,`
283			`FFTRDY=> FFTRDY,`
284			`READY=> READY,`
285			`-- WEI=> WEI,`
286			`WEM=> WEM,`
287			`RESRAM=>RESRAM,`
288			`INITOVERF=>INITOVERF,`
289			`WERES=>WERES,`
290			`SEL=>SEL , -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM`
291			`ODDC=>ODDC,`
292			`MODE=>mode,`
293			`EVEN=> EVEN, --0- 0th bank 1- 1st bank -for DIRE,DIIM`
294			`DIV2=> DIV2,`
295			`ZWR=> ZWR,`
296			`ZWI=> ZWI,`
297			`SELW=>selw,`
298			`SIGNRE=>SIGNRE ,`
299			`EXP=>EXP,`
300			`ADDRR=> ADDRR,`
301			`ADDRWM=> ADDRWM,`
302			`ADDRRES=>ADDRRES,`
303			`ADDRROM =>ADDRROM`
304			`);`
305
306			`U_RAM: RAM1X_2`
307			`generic map(`
308			`width =>width,`
309			`n=>n -- 6,7,8,9,10,11`
310			`,v2=>v2`
311			`)`
312			`port map(`
313			`CLK=>CLK ,`
314			`RST=> RST,`
315			`CE=> CE,`
316			`WE=> WEM, -- for input data`
317			`ADDRW=> ADDRWM,`
318			`ADDRR=> ADDRR,`
319			`SEL=>SEL,`
320			`DIRE=>DIRE,`
321			`RESRAM=>RESRAM,`
322			`DIIM=> DIIM,`
323			`DMRE=> REDO,`
324			`DMIM=> IMDO,`
325			`OVERF=> OVERF ,`
326			`INITOVERF=>INITOVERF,`
327			`DORE=>REDI,`
328			`DOIM=> IMDI`
329			`);`
330
331
332
333			`DATAORE<=REDO ;`
334			`DATAOIM<=IMDO ;`
335
336			`sn11<=conv_integer(signed(redo));--when addrres(n-1)='0' else 0;`
337			`sn12<=conv_integer(signed(imdo));`
338
339
340			`end ALFFT_CoreS;`