URL https://opencores.org/ocsvn/fft_fir_filter/fft_fir_filter/trunk

Subversion Repositories fft_fir_filter

[/] [fft_fir_filter/] [trunk/] [rtl/] [control_i.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log


---------------------------------------------------------------------
----                                                             ----
----  FFT Filter IP core                                         ----
----                                                             ----
----  Authors: Anatoliy Sergienko, Volodya Lepeha                ----
----  Company: Unicore Systems http://unicore.co.ua              ----
----                                                             ----
----  Downloaded from: http://www.opencores.org                  ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2006-2010 Unicore Systems LTD                 ----
---- www.unicore.co.ua                                           ----
---- o.uzenkov@unicore.co.ua                                     ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
---- THIS SOFTWARE IS PROVIDED "AS IS"                           ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT              ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT         ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION)                 ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,              ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING                 ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,                 ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.          ----
----                                                             ----
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
 
entity  CONTROLi is
        generic (n:INTEGER;  -- 6,7,8,9,10,11
                reall:INTEGER:= 0  --wch. mass: 0 -complex 1 - 2 realnych
                );
        port (
                CLK: in STD_LOGIC;
                RST: in STD_LOGIC;
                CE: in STD_LOGIC;
                START: in STD_LOGIC;
                DATAE: in STD_LOGIC;
                OVERF: in STD_LOGIC;
                FILTER: in STD_LOGIC_VECTOR (1 downto 0);                --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff
                L1:in STD_LOGIC_VECTOR (n-1 downto 0);            -- tsastoty filtrow
                H1:in STD_LOGIC_VECTOR (n-1 downto 0);            -- tsastoty filtrow
                L2:in STD_LOGIC_VECTOR (n-1 downto 0);
                H2:in STD_LOGIC_VECTOR (n-1 downto 0);
                FFTRDY: out STD_LOGIC;
                READY: out STD_LOGIC;
                WEI: out STD_LOGIC;
                WEM: out STD_LOGIC;
                WERES: out STD_LOGIC;
                ODDC:     out STD_LOGIC;
                EVEN: out STD_LOGIC;                     --0- 0th bank 1- 1st bank -for DIRE,DIIM
                DIV2: out STD_LOGIC;
                ZWR: out STD_LOGIC;
                ZWI: out STD_LOGIC;
                SIGNRE:  out STD_LOGIC;
                INITOVERF:   out STD_LOGIC;
                RESRAM:   out STD_LOGIC;
                SEL: out STD_LOGIC;       -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM 
                SELW: out STD_LOGIC_vector(1 downto 0);    --0 -twiddle 1 - window  
                MODE: out STD_LOGIC_VECTOR (1 downto 0);
                EXP: out STD_LOGIC_VECTOR (3 downto 0);
                ADDRR: out STD_LOGIC_VECTOR (n  downto 0);
                ADDRWM: out STD_LOGIC_VECTOR (n downto 0) ;
                ADDRRES: out STD_LOGIC_VECTOR (n - 1 downto 0);
                ADDRROM :out STD_LOGIC_VECTOR(n- 2 downto 0)
                );
end CONTROLi;
 
 
 
architecture CONTROL_slip of CONTROLi is
 
        constant NN: INTEGER:=2**n;
        constant lat: INTEGER:=6;--7; --latency
        constant lat2: INTEGER:=7; --latency in butterflies       
        constant one:INTEGER:=2**(n-1);
        constant onehalf:INTEGER:=2**(n-2);
        signal   startd,strt,iarrdy,iarrdy1,go,god,god2,DATAED: STD_LOGIC;
        signal fftfly,filt1fly,filt2fly,filt3fly,resfly:   STD_LOGIC; --FFT run flag,input flag,result fag
        signal resrdy, idatardy:   STD_LOGIC; --FFT result ready flag
        signal fftend,FFTRDYi:   STD_LOGIC; --FFT end flag
        signal enditera:STD_LOGIC; --end of iteration 
        signal incbfly:         STD_LOGIC; -- +1 to reading data address     
        signal incbflyw:         STD_LOGIC; -- +1 to writing data address     
        signal startitera: STD_LOGIC; -- iteration start
        signal startiterad1: STD_LOGIC; -- iteration start  
        signal startiterad0: STD_LOGIC; -- iteration start
        signal ODDCi:   STD_LOGIC; -- 1 when odd clock cycle         
        signal startiterad2: STD_LOGIC;     --delayed iteration start
        signal wefft: STD_LOGIC;     --we fft data
        signal addrwid, addrwidi        :STD_LOGIC_VECTOR(n-1 downto 0);  --I. data writing address
        signal invaddr:STD_LOGIC_VECTOR(n-1 downto 0);--inverse writing address
        signal itera:STD_LOGIC_VECTOR(n-1 downto 0); --iteration number           
        signal  ADDRRi:  STD_LOGIC_VECTOR (n-1 downto 0); --data reading address
        signal  ADDRwosstw:  STD_LOGIC_VECTOR (n-1 downto 0); --data reading address
        signal  ADDRWi:  STD_LOGIC_VECTOR (n-1 downto 0); --data writimg address
        signal  addres0,addres1:        STD_LOGIC_VECTOR (n-1 downto 0);
        signal  resnum:STD_LOGIC_VECTOR (n-1 downto 0);
        signal  resnumi:STD_LOGIC_VECTOR (n downto 0);
        signal  ADDRwf,addrwfi,addrrf,addrrfi,ctt,addrfilt:  STD_LOGIC_VECTOR (n-1 downto 0); --data writimg address
        signal addrfilt1,addrfilt2: STD_LOGIC_VECTOR (4 downto 0);
        signal  ADDRF:  STD_LOGIC_VECTOR (n-2 downto 0); --data writing address
        signal  bflies:  STD_LOGIC_VECTOR (n downto 0); --butterfly counter
        signal startiterad:       STD_LOGIC_VECTOR (15 downto 0);
        signal incaddrf:STD_LOGIC_VECTOR(n-2 downto 0);    -- increment to the factor address
        signal  EXPi:  STD_LOGIC_VECTOR (3 downto 0);
        signal ADDRROMi,addrROMF :STD_LOGIC_VECTOR (n-2 downto 0);
        signal  WERESULTi,wed,filtd:  STD_LOGIC;
        signal irdy:STD_LOGIC_VECTOR (1 downto 0);
        signal ird,winend,wefilt,outp:  STD_LOGIC;
        signal filt1flyd,filt2flyd,filt3flyd,resflyd:STD_LOGIC_VECTOR (15 downto 0);
        signal fwd,fwdd,resend,wereswosst:STD_LOGIC;
        signal filt1end,filt2end,filt3end:std_logic;
        constant nulls:STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'0');
        constant ones:STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'1');
        constant oneh:STD_LOGIC_VECTOR (n downto 0):=
        conv_std_logic_vector((nn),n+1);
        constant nullsaf:STD_LOGIC_VECTOR (n-6 downto 0):=(others=>'0');
begin
 
 
 
 
        CTRFILT1:process(CLK,RST,addrwfi,oddci)    -- data counter for reading/writing to multiply by window
                variable addrwfii:  STD_LOGIC_VECTOR (n-1 downto 0);
        begin
                if RST='1' then
                        addrwfi<=(others=>'0');
                        ctt<=(others=>'0');
                        addrfilt1<=(others=>'0');
                        addrfilt2<=(others=>'0');
                        addrrfi<=(others=>'0');
                        wefilt<='0';
                        filt1end<='0'; -- koniec umnozenia na okno
                        EVEN<='0';
                        startd<='0';
                        filtd<='0';
                        addrROMF<=(others=>'0');
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                filtd<=filt2fly or  filt3fly;
                                EVEN<=filt1fly;
                                filt1flyd<=filt1flyd(14 downto 0)& filt1fly ;
                                filt2flyd<=filt2flyd(14 downto 0)& filt2fly;
                                filt3flyd<=filt3flyd(14 downto 0)& filt3fly;
                                filt1end<='0';
                                filt2end<='0';
                                filt3end<='0';
                                startd<=START;
                                if (START='0' and startd='1')
                                        or (filt1end='1' and FILTER="10")
                                        or (filt2end='1' and FILTER="11")  then         -- or FFTRDYi='1' 
                                        addrwfi<=(others=>'0');
                                        ctt<=(others=>'0');
                                        if L1=nulls then
                                                addrfilt1<="01000";
                                        else
                                                addrfilt1<="00000";
                                        end if;
                                        if L2=nulls then
                                                addrfilt2<="01000";
                                        else
                                                addrfilt2<="00000";
                                        end if;
                                        addrrfi<=(others=>'0');
                                        wefilt<='0';
                                elsif filt1fly='1' then
                                        if ODDCi='1' then
                                                ctt<=ctt+1;
                                                if ctt>=L1-5 and addrfilt1<8 then
                                                        addrfilt1<=addrfilt1+1;
                                                end if;
                                                if ctt>=H1-3 and addrfilt1<16 then
                                                        addrfilt1<=addrfilt1+1;
                                                end if;
 
 
                                                if ctt>=L2-5 and addrfilt2<8 then
                                                        addrfilt2<=addrfilt2+1;
                                                end if;
                                                if ctt>=H2-3 and addrfilt2<16 then
                                                        addrfilt2<=addrfilt2+1;
                                                end if;
                                        end if;
                                        if wefilt='1' then
                                                addrwfi<=addrwfi+1;--address zapisi 
                                        end if;
                                        if filt1flyd(2)='1' then
                                                wefilt<='1';
                                        end if;
                                        if      addrwf= nn-1  then
                                                filt1end<='1';    --konec umnozenia na okno
                                        end if;
                                        if      addrwf= nn-1 or filt1end='1' then
                                                wefilt<='0';
                                        end if;
 
                                elsif (filt2fly or  filt3fly)='1'   then           --filtd='1'---------differenciator
                                        addrrfi<=addrrfi+1;
                                        if wefilt='1' then
                                                addrwfi<=addrwfi+1;--address zapisi 
                                        end if;
                                        if (filt2flyd(3)='1')--and filt2fly='1') 
                                                or (filt3flyd(3)='1')--and filt3fly='1') 
                                                then
                                                wefilt<='1';
                                        end if;
                                        if      addrwfi= nn-1 then
                                                if filt2fly='1' then
                                                        filt2end<='1';    --konec umnozenia na okno
                                                        wefilt<='0';
                                                elsif filt3fly='1' then
                                                        filt3end<='1';
                                                        wefilt<='0';
                                                end if;
 
                                        end if;
                                end if;
                                addrROMF<=addrrfi(n-1 downto 1);
                        end if;
                end if;
 
                   addrwfii:= addrwfi(0)&addrwfi(n-1 downto 1);
 
                if     (filt1fly='1' and reall=0)
                        or (filt2fly='1' and reall=0)
                        or (filt3fly='1' and reall=0 ) then
                        for i in 0 to n-1 loop
                                addrwf(i)<=addrwfii(n-i-1);   --2-th inverse writing address
                        end loop;
                else
                        addrwf<=addrwfi;
                end if;
        end process;
        addrrf<=addrrfi ;--when oddci='0'
        --      else not addrrfi; 
 
        addrfilt<=nullsaf & addrfilt1 when oddci='0'  --'1'
        else nullsaf & addrfilt2 ;
 
 
 
 
 
        CTLAT:process(RST,CLK)      --delay on 1 LUT
        begin
                if RST='1' then
                        startiterad1<='0';
                        startiterad2<='0';
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                startiterad1<=startitera;
                                startiterad2<=startiterad0;
                        end if;
                end if;
        end process;
 
        CTLATS:process(RST,CLK)      --delay on 1 LUT     
        begin
                if CLK='1' and CLK'event then
                        if CE='1' then
                                startiterad<=startiterad(14 downto 0)&startitera;
                        end if;
                end if;
        end process;
        startiterad0<=   startiterad(lat);
 
 
        TODDC:process(CLK,RST)      --odd cycle for FFT
        begin
                if RST='1' then
                        ODDCi<='0';
                elsif CLK='1' and CLK'event    then
                        if CE='1' then
                                if (START='0' and startd='1') or filt1end='1' or filt2end='1'or filt3end='1'
                                        or startitera='1' or FFTend='1' or resend='1' then
                                        ODDCi<='0';
                                else -- fftfly='1' or resfly='1' then
                                        ODDCi<= not ODDCi;
                                end if;
                        end if;
                end if;
        end process;
 
        ODDC<= ODDCi;
 
        CTRADDR:process(CLK,RST,addrri)  --FFT read counter        
                variable sum:STD_LOGIC_VECTOR (n downto 0);
                variable inc:STD_LOGIC;
        begin
                if RST='1' then
                        incbfly<='0';
                        ADDRRi<=( others=>'0');
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                if startitera='1' then
                                        ADDRRi<=( others=>'0');
                                elsif fftfly='1' then
                                        sum:='0'&ADDRRi+itera;
                                        inc:= sum(n);
                                        ADDRRi<=sum(n-1 downto 0)+inc;
                                        incbfly<=inc;
                                end if;
                        end if;
                end if;
        end process;
 
 
        CTWADDR:process(CLK,RST,ADDRWi)  --FFT write counter       
                variable sum:STD_LOGIC_VECTOR (n downto 0);
                variable inc:STD_LOGIC;
        begin
                if RST='1' then
                        ADDRWi<=( others=>'0');
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                if startiterad2='1' then
                                        ADDRWi<=( others=>'0');
                                elsif fftfly='1' then
                                        sum:='0'&ADDRWi+itera;
                                        inc:= sum(n);
                                        ADDRWi<=sum(n-1 downto 0)+inc;
                                end if;
                        end if;
                end if;
        end process;
 
        LINCADDRF:process(itera)
        begin
                for i in 0 to n-2 loop
                        incaddrf(i)<=itera(n-1-i);
                end loop;
        end process;
 
        CTADDRF: process(CLK,RST)  --iteration counter               
        begin
                if RST='1' then
                        ADDRF<=( others=>'0');
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                if startiterad1='1' then
                                        ADDRF<=( others=>'0');
                                elsif fftfly='1' and incbfly = '1' then
                                        ADDRF<=ADDRF+incaddrf;
                                end if;
                        end if;
                end if;
        end process;
 
 
 
        FADDRROM:process(CLK,RST)
        begin
                if RST='1' then
                        SIGNRE<='0';
                        ZWR<='0';
                        ZWI<='0';
                        ADDRROMi<=( others=>'0');
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                if ADDRF=onehalf then
                                        ZWR<='1';
                                else
                                        ZWR<='0';
                                end if;
 
                                if ADDRF=0 or resfly='1' then
                                        ZWI<='1';
                                else
                                        ZWI<='0';
                                end if;
 
                                if ODDCi='1' then      --cosine address
                                        if ADDRF(n-2)='0' then
                                                ADDRROMi<='0'&ADDRF(n-3 downto 0);
                                                SIGNRE<='0';
                                        else
                                                ADDRROMi<=onehalf-('0'&ADDRF(n-3 downto 0));
                                                SIGNRE<='1';
                                        end if;
 
                                else                                 -- sine address
                                        if ADDRF(n-2)='0' then
                                                ADDRROMi<=onehalf -('0'&ADDRF(n-3 downto 0));
                                        else
                                                ADDRROMi<='0'&ADDRF(n-3 downto 0);
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
 
        CTBFLIES:process(CLK,RST,bflies)  --butterfly counter               
        begin
                if RST='1' then
                        wefft<='0';
                        enditera<='0';
                        bflies<=( others=>'0');
                        WERESULTi<='0';
                        FFTRDYi<='0';
                        resrdy<='0';
 
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                resrdy<=  startitera and        itera(n-2);
                                if startiterad2='1' then
                                        wefft<='1';
                                        if  itera(n-1)='1'then
                                                WERESULTi<='1';
                                        end if;
                                end if;
 
                                if startitera='1' then
                                        bflies<=( others=>'0');
                                elsif  fftfly='1'
                                        then
                                        bflies<=bflies+1;
                                end if;
 
                                if idatardy ='1' and go ='0'   then
                                        FFTRDYi<='1';
                                elsif bflies=nn + lat2 and enditera='0' then
                                        enditera<='1';
                                        wefft<='0';
                                        WERESULTi<='0';
                                        if itera(n-1)='1' then
                                                FFTRDYi<='1';
                                        end if;
                                else
                                        enditera<='0';
                                        FFTRDYi<='0';
                                end if;
                        end if;
                end if;
        end process;
 
        TIARRDY:process(CLK,RST)    --1st input data ready
        begin
                if RST='1' then
                        iarrdy<='0';
                        iarrdy1<='0';
                        go<='0';
                        god<='0';
                        god2<='0';
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                if START='1' then
                                        iarrdy<='0';
                                        iarrdy1<='0';
                                        go<='0';
                                elsif idatardy='1' then
                                        iarrdy<='1';
                                        go<='1';
                                        god<='0';
                                        if go='0'
                                                then
                                                iarrdy1<='1';
                                        end if;
 
                                else
                                        god2<=god;
                                        iarrdy<='0';
                                        iarrdy1<='0';
                                        if   FFTRDYi='1' then
                                                god<='1'    ;
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
        CTITERA:process(CLK,RST)  --iteration counter               
        begin
                if RST='1' then
                        itera<=CONV_STD_LOGIC_VECTOR(1,n);
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                if  FFTRDYi='1' then
                                        itera<=CONV_STD_LOGIC_VECTOR(1,n);
                                elsif enditera='1' then
                                        itera<=itera(n-2 downto 0)&'0';
                                end if;
                        end if;
                end if;
        end process;
 
 
        CTWOSST:process(CLK,RST,addres0,addres1,oddci)  -- data counters for wosstanowlenija
                variable addrw:STD_LOGIC_VECTOR(n-1 downto 0);
        begin
                if RST='1' then
                        addres0<=(others=>'0');
                        addres1<=(others=>'0');
                        resnumi<=(others=>'0');
                        resend<='0';
                        --      WERESwosst<='0';        
                        RESRAM<='0';
                elsif CLK='1' and CLK'event then
 
                        if CE='1' then
                                resend<='0';
                                resflyd<=resflyd(14 downto 0)& resfly;
                                if (FILTER=0 and reall=1 and START='0' and startd = '1')
                                        or (FILTER=1 and filt1end='1'and reall=1)
                                        or (FILTER=2 and filt2end='1'and reall=1)
                                        or (FILTER=3 and filt3end='1'and reall=1)
                                        then
                                        RESRAM<='0';
                                        addres0<=  (others=>'0');
                                        addres1<= (others=>'0');
                                        resnumi<=(others=>'0');
                                elsif resfly='1' then
                                        if oddci='1' and resflyd(7)='1' then   --'1'
                                                addres0<=UNSIGNED(addres0)+1;
                                                addres1<=UNSIGNED(addres1)-1;
                                        end if;
                                        resnumi<=UNSIGNED(resnumi)+1;
                                        if resnumi=oneh then
                                                RESRAM<='1';
                                        end if;
                                end if;
                                if UNSIGNED(addres0)=nn/2 then
                                        resend<='1';
                                end if;
                                if (resflyd(7) and resfly)='0' then
                                        RESRAM<='0';
                                end if;
                        end if;
                end if;
                if      oddci='0' then
                        addrw:= addres0;
                else
                        addrw:= addres1;
                end if;
                --2-ja inversija        
                if reall=1 then
                        for i in 0 to n-1 loop
                                addrwosstw(i)<=addrw(n-i-1);   --2-th inverse writing address
                        end loop;
                else
                        addrwosstw<=addrw;
                end if;
 
        end process;
        WERESwosst<=resflyd(7) and resfly;
 
        resnum<=resnumi(n-1 downto 0);
 
 
        TTFFTFLY:process(CLK,RST,enditera) --triggers of the FFT running
        begin
                if RST='1' then
                        filt1fly<='0';
                        filt2fly<='0';
                        filt3fly<='0';
                        resfly<='0';
                        fftfly<='0';
                        fftend<='0';
                        MODE<="00";
                elsif CLK='1' and CLK'event    then
                        if CE='1' then
                                if START='0' and startd = '1'then-- 
                                        if FILTER=0 then
                                                if reall=0 then
                                                        MODE<="01";
                                                        fftfly<='1';
                                                else
                                                        resfly<='1';
                                                        MODE<="10";
                                                end if;
                                        else
                                                filt1fly<='1';
                                                MODE<="00";
                                        end if;
                                elsif filt1end='1' then
                                        filt1fly<='0';
                                        if FILTER=1 then
                                                if reall=0 then
                                                        MODE<="01";
                                                        fftfly<='1';
                                                else
                                                        resfly<='1';
                                                        MODE<="10";
                                                end if;
                                        else
                                                filt2fly<='1';
                                                MODE<="11";
                                        end if;
                                elsif filt2end='1' then
                                        filt2fly<='0';
                                        if FILTER=2 then
                                                if reall=0 then
                                                        MODE<="01";
                                                        fftfly<='1';
                                                else
                                                        MODE<="10";
                                                        resfly<='1';
                                                end if;
                                        else
                                                filt3fly<='1';
                                                MODE<="11";
                                        end if;
                                elsif filt3end='1' then
                                        filt3fly<='0';
                                        if reall=0 then
                                                MODE<="01";
                                                fftfly<='1';
                                        else
                                                MODE<="10";
                                                resfly<='1';
                                        end if;
                                elsif resend='1' then
                                        resfly<='0';
                                        fftfly<='1';
                                        MODE<="01";
                                elsif FFTend='1' then
                                        fftfly<='0';
                                end if;
                        end if;
                end if;
                fftend<=  (enditera and itera(n-1)) ;
        end process;
 
        REXP:  process(CLK,RST)  --exponent counter               
        begin
                if RST='1' then
                        EXPi<=( others=>'0');
                        DIV2<='0';
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                if ((FILTER=0 and start='0' and startd='1')
                                        or (FILTER=1 and filt1end='1')
                                        or (FILTER=2 and filt2end='1')
                                        or (FILTER=3 and filt3end='1'))  then
                                        EXPi<=( 0 =>OVERF, others=>'0');
                                        DIV2<= overf;
                                elsif startitera='1' and (fftfly='1' or resfly='1')then
                                        if OVERF = '1' then
                                                EXPi<=UNSIGNED(EXPi)+1;
                                                DIV2<='1';
                                        else
                                                DIV2<='0';
                                        end if;
                                elsif   FFTRDYi='1' then
                                        DIV2<='0';
                                end if;
                        end if;
                end if;
        end process;
 
 
        --WEI<=DATAE; 
        WEd<=DATAE;
 
 
 
 
        FFTRDY<=        FFTRDYi  after 3 ns;
        startitera<=  '1' when (enditera='1' and FFTRDYi='0')
        or (filt1end='1' and FILTER=1 and reall=0)
        or (filt2end='1' and FILTER=2 and reall=0 )
        or (filt3end='1' and FILTER=3 and reall=0)
        or (resend='1' and reall=1)
        else '0';
 
        WEM<=wefilt when filt1fly='1' or filt2fly='1'or filt3fly='1'
        else wefft  when fftfly='1'
        else WERESwosst ;
 
 
 
        WERES<= WERESULTi after 1 ns;
        ADDRRES<= ADDRWi when fftfly='1' and itera(n-1)='1' else (others=>'0');
 
        ADDRR<='1'& resnum  when resfly='1'
        else '1'& addrrf when filt2fly='1' or filt3fly='1'
        else '0'& ADDRRi ;
 
        ADDRWM<= '0'&addrwf  when filt1fly='1'and FILTER=1  and reall=0
        else '1'&addrwf  when filt3fly='1' or filt2fly='1'      or filt1fly='1'
        else '0'&addrwosstw when resfly='1'
        else '0'& ADDRWi;
 
        SEL<='1' when (FILTER="00" and reall=0 and fftfly ='1' and itera(0)='1')
        or(FILTER="00" and reall=1 and resfly ='1')
        or(FILTER/="00" and filt1fly='1')
        else '0';
 
        SELW<= "01" when filt1fly='1' else
        "10" when (Filt2fly or filt3fly)='1' else
        "00";
 
        INITOVERF<=startitera;-- and START;   
 
        ADDRROM<= addrfilt(n-2 downto 0) when filt1fly='1'
        else addrROMF when filt2fly='1' or filt3fly='1'
        else ADDRROMi(n-2 downto 0) when fftfly='1'
        else (others=>'0');-- when oddci='1'     else '1'&nulls(n-3 downto 0);
 
        READY<=resrdy  after 3 ns;
 
        EXP<=EXPi;
 
end CONTROL_slip;

Browse

Tools

Subversion Repositories fft_fir_filter

[/] [fft_fir_filter/] [trunk/] [rtl/] [control_i.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	unicore	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- FFT Filter IP core ----`
4			`---- ----`
5			`---- Authors: Anatoliy Sergienko, Volodya Lepeha ----`
6			`---- Company: Unicore Systems http://unicore.co.ua ----`
7			`---- ----`
8			`---- Downloaded from: http://www.opencores.org ----`
9			`---- ----`
10			`---------------------------------------------------------------------`
11			`---- ----`
12			`---- Copyright (C) 2006-2010 Unicore Systems LTD ----`
13			`---- www.unicore.co.ua ----`
14			`---- o.uzenkov@unicore.co.ua ----`
15			`---- ----`
16			`---- This source file may be used and distributed without ----`
17			`---- restriction provided that this copyright statement is not ----`
18			`---- removed from the file and that any derivative work contains ----`
19			`---- the original copyright notice and the associated disclaimer.----`
20			`---- ----`
21			`---- THIS SOFTWARE IS PROVIDED "AS IS" ----`
22			`---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----`
23			`---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----`
24			`---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----`
25			`---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----`
26			`---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----`
27			`---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
28			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----`
29			`---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----`
30			`---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----`
31			`---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----`
32			`---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----`
33			`---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
34			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----`
35			`---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----`
36			`---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----`
37			`---- ----`
38			`---------------------------------------------------------------------`
39			`library IEEE;`
40			`use IEEE.std_logic_1164.all;`
41			`use IEEE.std_logic_unsigned.all;`
42			`use IEEE.std_logic_arith.all;`
43
44			`entity CONTROLi is`
45			`generic (n:INTEGER; -- 6,7,8,9,10,11`
46			`reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych`
47			`);`
48			`port (`
49			`CLK: in STD_LOGIC;`
50			`RST: in STD_LOGIC;`
51			`CE: in STD_LOGIC;`
52			`START: in STD_LOGIC;`
53			`DATAE: in STD_LOGIC;`
54			`OVERF: in STD_LOGIC;`
55			`FILTER: in STD_LOGIC_VECTOR (1 downto 0); --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff`
56			`L1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow`
57			`H1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow`
58			`L2:in STD_LOGIC_VECTOR (n-1 downto 0);`
59			`H2:in STD_LOGIC_VECTOR (n-1 downto 0);`
60			`FFTRDY: out STD_LOGIC;`
61			`READY: out STD_LOGIC;`
62			`WEI: out STD_LOGIC;`
63			`WEM: out STD_LOGIC;`
64			`WERES: out STD_LOGIC;`
65			`ODDC: out STD_LOGIC;`
66			`EVEN: out STD_LOGIC; --0- 0th bank 1- 1st bank -for DIRE,DIIM`
67			`DIV2: out STD_LOGIC;`
68			`ZWR: out STD_LOGIC;`
69			`ZWI: out STD_LOGIC;`
70			`SIGNRE: out STD_LOGIC;`
71			`INITOVERF: out STD_LOGIC;`
72			`RESRAM: out STD_LOGIC;`
73			`SEL: out STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM`
74			`SELW: out STD_LOGIC_vector(1 downto 0); --0 -twiddle 1 - window`
75			`MODE: out STD_LOGIC_VECTOR (1 downto 0);`
76			`EXP: out STD_LOGIC_VECTOR (3 downto 0);`
77			`ADDRR: out STD_LOGIC_VECTOR (n downto 0);`
78			`ADDRWM: out STD_LOGIC_VECTOR (n downto 0) ;`
79			`ADDRRES: out STD_LOGIC_VECTOR (n - 1 downto 0);`
80			`ADDRROM :out STD_LOGIC_VECTOR(n- 2 downto 0)`
81			`);`
82			`end CONTROLi;`
83
84
85
86			`architecture CONTROL_slip of CONTROLi is`
87
88			`constant NN: INTEGER:=2**n;`
89			`constant lat: INTEGER:=6;--7; --latency`
90			`constant lat2: INTEGER:=7; --latency in butterflies`
91			`constant one:INTEGER:=2**(n-1);`
92			`constant onehalf:INTEGER:=2**(n-2);`
93			`signal startd,strt,iarrdy,iarrdy1,go,god,god2,DATAED: STD_LOGIC;`
94			`signal fftfly,filt1fly,filt2fly,filt3fly,resfly: STD_LOGIC; --FFT run flag,input flag,result fag`
95			`signal resrdy, idatardy: STD_LOGIC; --FFT result ready flag`
96			`signal fftend,FFTRDYi: STD_LOGIC; --FFT end flag`
97			`signal enditera:STD_LOGIC; --end of iteration`
98			`signal incbfly: STD_LOGIC; -- +1 to reading data address`
99			`signal incbflyw: STD_LOGIC; -- +1 to writing data address`
100			`signal startitera: STD_LOGIC; -- iteration start`
101			`signal startiterad1: STD_LOGIC; -- iteration start`
102			`signal startiterad0: STD_LOGIC; -- iteration start`
103			`signal ODDCi: STD_LOGIC; -- 1 when odd clock cycle`
104			`signal startiterad2: STD_LOGIC; --delayed iteration start`
105			`signal wefft: STD_LOGIC; --we fft data`
106			`signal addrwid, addrwidi :STD_LOGIC_VECTOR(n-1 downto 0); --I. data writing address`
107			`signal invaddr:STD_LOGIC_VECTOR(n-1 downto 0);--inverse writing address`
108			`signal itera:STD_LOGIC_VECTOR(n-1 downto 0); --iteration number`
109			`signal ADDRRi: STD_LOGIC_VECTOR (n-1 downto 0); --data reading address`
110			`signal ADDRwosstw: STD_LOGIC_VECTOR (n-1 downto 0); --data reading address`
111			`signal ADDRWi: STD_LOGIC_VECTOR (n-1 downto 0); --data writimg address`
112			`signal addres0,addres1: STD_LOGIC_VECTOR (n-1 downto 0);`
113			`signal resnum:STD_LOGIC_VECTOR (n-1 downto 0);`
114			`signal resnumi:STD_LOGIC_VECTOR (n downto 0);`
115			`signal ADDRwf,addrwfi,addrrf,addrrfi,ctt,addrfilt: STD_LOGIC_VECTOR (n-1 downto 0); --data writimg address`
116			`signal addrfilt1,addrfilt2: STD_LOGIC_VECTOR (4 downto 0);`
117			`signal ADDRF: STD_LOGIC_VECTOR (n-2 downto 0); --data writing address`
118			`signal bflies: STD_LOGIC_VECTOR (n downto 0); --butterfly counter`
119			`signal startiterad: STD_LOGIC_VECTOR (15 downto 0);`
120			`signal incaddrf:STD_LOGIC_VECTOR(n-2 downto 0); -- increment to the factor address`
121			`signal EXPi: STD_LOGIC_VECTOR (3 downto 0);`
122			`signal ADDRROMi,addrROMF :STD_LOGIC_VECTOR (n-2 downto 0);`
123			`signal WERESULTi,wed,filtd: STD_LOGIC;`
124			`signal irdy:STD_LOGIC_VECTOR (1 downto 0);`
125			`signal ird,winend,wefilt,outp: STD_LOGIC;`
126			`signal filt1flyd,filt2flyd,filt3flyd,resflyd:STD_LOGIC_VECTOR (15 downto 0);`
127			`signal fwd,fwdd,resend,wereswosst:STD_LOGIC;`
128			`signal filt1end,filt2end,filt3end:std_logic;`
129			`constant nulls:STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'0');`
130			`constant ones:STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'1');`
131			`constant oneh:STD_LOGIC_VECTOR (n downto 0):=`
132			`conv_std_logic_vector((nn),n+1);`
133			`constant nullsaf:STD_LOGIC_VECTOR (n-6 downto 0):=(others=>'0');`
134			`begin`
135
136
137
138
139			`CTRFILT1:process(CLK,RST,addrwfi,oddci) -- data counter for reading/writing to multiply by window`
140			`variable addrwfii: STD_LOGIC_VECTOR (n-1 downto 0);`
141			`begin`
142			`if RST='1' then`
143			`addrwfi<=(others=>'0');`
144			`ctt<=(others=>'0');`
145			`addrfilt1<=(others=>'0');`
146			`addrfilt2<=(others=>'0');`
147			`addrrfi<=(others=>'0');`
148			`wefilt<='0';`
149			`filt1end<='0'; -- koniec umnozenia na okno`
150			`EVEN<='0';`
151			`startd<='0';`
152			`filtd<='0';`
153			`addrROMF<=(others=>'0');`
154			`elsif CLK='1' and CLK'event then`
155			`if CE='1' then`
156			`filtd<=filt2fly or filt3fly;`
157			`EVEN<=filt1fly;`
158			`filt1flyd<=filt1flyd(14 downto 0)& filt1fly ;`
159			`filt2flyd<=filt2flyd(14 downto 0)& filt2fly;`
160			`filt3flyd<=filt3flyd(14 downto 0)& filt3fly;`
161			`filt1end<='0';`
162			`filt2end<='0';`
163			`filt3end<='0';`
164			`startd<=START;`
165			`if (START='0' and startd='1')`
166			`or (filt1end='1' and FILTER="10")`
167			`or (filt2end='1' and FILTER="11") then -- or FFTRDYi='1'`
168			`addrwfi<=(others=>'0');`
169			`ctt<=(others=>'0');`
170			`if L1=nulls then`
171			`addrfilt1<="01000";`
172			`else`
173			`addrfilt1<="00000";`
174			`end if;`
175			`if L2=nulls then`
176			`addrfilt2<="01000";`
177			`else`
178			`addrfilt2<="00000";`
179			`end if;`
180			`addrrfi<=(others=>'0');`
181			`wefilt<='0';`
182			`elsif filt1fly='1' then`
183			`if ODDCi='1' then`
184			`ctt<=ctt+1;`
185			`if ctt>=L1-5 and addrfilt1<8 then`
186			`addrfilt1<=addrfilt1+1;`
187			`end if;`
188			`if ctt>=H1-3 and addrfilt1<16 then`
189			`addrfilt1<=addrfilt1+1;`
190			`end if;`
191
192
193			`if ctt>=L2-5 and addrfilt2<8 then`
194			`addrfilt2<=addrfilt2+1;`
195			`end if;`
196			`if ctt>=H2-3 and addrfilt2<16 then`
197			`addrfilt2<=addrfilt2+1;`
198			`end if;`
199			`end if;`
200			`if wefilt='1' then`
201			`addrwfi<=addrwfi+1;--address zapisi`
202			`end if;`
203			`if filt1flyd(2)='1' then`
204			`wefilt<='1';`
205			`end if;`
206			`if addrwf= nn-1 then`
207			`filt1end<='1'; --konec umnozenia na okno`
208			`end if;`
209			`if addrwf= nn-1 or filt1end='1' then`
210			`wefilt<='0';`
211			`end if;`
212
213			`elsif (filt2fly or filt3fly)='1' then --filtd='1'---------differenciator`
214			`addrrfi<=addrrfi+1;`
215			`if wefilt='1' then`
216			`addrwfi<=addrwfi+1;--address zapisi`
217			`end if;`
218			`if (filt2flyd(3)='1')--and filt2fly='1')`
219			`or (filt3flyd(3)='1')--and filt3fly='1')`
220			`then`
221			`wefilt<='1';`
222			`end if;`
223			`if addrwfi= nn-1 then`
224			`if filt2fly='1' then`
225			`filt2end<='1'; --konec umnozenia na okno`
226			`wefilt<='0';`
227			`elsif filt3fly='1' then`
228			`filt3end<='1';`
229			`wefilt<='0';`
230			`end if;`
231
232			`end if;`
233			`end if;`
234			`addrROMF<=addrrfi(n-1 downto 1);`
235			`end if;`
236			`end if;`
237
238			`addrwfii:= addrwfi(0)&addrwfi(n-1 downto 1);`
239
240			`if (filt1fly='1' and reall=0)`
241			`or (filt2fly='1' and reall=0)`
242			`or (filt3fly='1' and reall=0 ) then`
243			`for i in 0 to n-1 loop`
244			`addrwf(i)<=addrwfii(n-i-1); --2-th inverse writing address`
245			`end loop;`
246			`else`
247			`addrwf<=addrwfi;`
248			`end if;`
249			`end process;`
250			`addrrf<=addrrfi ;--when oddci='0'`
251			`-- else not addrrfi;`
252
253			`addrfilt<=nullsaf & addrfilt1 when oddci='0' --'1'`
254			`else nullsaf & addrfilt2 ;`
255
256
257
258
259
260			`CTLAT:process(RST,CLK) --delay on 1 LUT`
261			`begin`
262			`if RST='1' then`
263			`startiterad1<='0';`
264			`startiterad2<='0';`
265			`elsif CLK='1' and CLK'event then`
266			`if CE='1' then`
267			`startiterad1<=startitera;`
268			`startiterad2<=startiterad0;`
269			`end if;`
270			`end if;`
271			`end process;`
272
273			`CTLATS:process(RST,CLK) --delay on 1 LUT`
274			`begin`
275			`if CLK='1' and CLK'event then`
276			`if CE='1' then`
277			`startiterad<=startiterad(14 downto 0)&startitera;`
278			`end if;`
279			`end if;`
280			`end process;`
281			`startiterad0<= startiterad(lat);`
282
283
284			`TODDC:process(CLK,RST) --odd cycle for FFT`
285			`begin`
286			`if RST='1' then`
287			`ODDCi<='0';`
288			`elsif CLK='1' and CLK'event then`
289			`if CE='1' then`
290			`if (START='0' and startd='1') or filt1end='1' or filt2end='1'or filt3end='1'`
291			`or startitera='1' or FFTend='1' or resend='1' then`
292			`ODDCi<='0';`
293			`else -- fftfly='1' or resfly='1' then`
294			`ODDCi<= not ODDCi;`
295			`end if;`
296			`end if;`
297			`end if;`
298			`end process;`
299
300			`ODDC<= ODDCi;`
301
302			`CTRADDR:process(CLK,RST,addrri) --FFT read counter`
303			`variable sum:STD_LOGIC_VECTOR (n downto 0);`
304			`variable inc:STD_LOGIC;`
305			`begin`
306			`if RST='1' then`
307			`incbfly<='0';`
308			`ADDRRi<=( others=>'0');`
309			`elsif CLK='1' and CLK'event then`
310			`if CE='1' then`
311			`if startitera='1' then`
312			`ADDRRi<=( others=>'0');`
313			`elsif fftfly='1' then`
314			`sum:='0'&ADDRRi+itera;`
315			`inc:= sum(n);`
316			`ADDRRi<=sum(n-1 downto 0)+inc;`
317			`incbfly<=inc;`
318			`end if;`
319			`end if;`
320			`end if;`
321			`end process;`
322
323
324			`CTWADDR:process(CLK,RST,ADDRWi) --FFT write counter`
325			`variable sum:STD_LOGIC_VECTOR (n downto 0);`
326			`variable inc:STD_LOGIC;`
327			`begin`
328			`if RST='1' then`
329			`ADDRWi<=( others=>'0');`
330			`elsif CLK='1' and CLK'event then`
331			`if CE='1' then`
332			`if startiterad2='1' then`
333			`ADDRWi<=( others=>'0');`
334			`elsif fftfly='1' then`
335			`sum:='0'&ADDRWi+itera;`
336			`inc:= sum(n);`
337			`ADDRWi<=sum(n-1 downto 0)+inc;`
338			`end if;`
339			`end if;`
340			`end if;`
341			`end process;`
342
343			`LINCADDRF:process(itera)`
344			`begin`
345			`for i in 0 to n-2 loop`
346			`incaddrf(i)<=itera(n-1-i);`
347			`end loop;`
348			`end process;`
349
350			`CTADDRF: process(CLK,RST) --iteration counter`
351			`begin`
352			`if RST='1' then`
353			`ADDRF<=( others=>'0');`
354			`elsif CLK='1' and CLK'event then`
355			`if CE='1' then`
356			`if startiterad1='1' then`
357			`ADDRF<=( others=>'0');`
358			`elsif fftfly='1' and incbfly = '1' then`
359			`ADDRF<=ADDRF+incaddrf;`
360			`end if;`
361			`end if;`
362			`end if;`
363			`end process;`
364
365
366
367			`FADDRROM:process(CLK,RST)`
368			`begin`
369			`if RST='1' then`
370			`SIGNRE<='0';`
371			`ZWR<='0';`
372			`ZWI<='0';`
373			`ADDRROMi<=( others=>'0');`
374			`elsif CLK='1' and CLK'event then`
375			`if CE='1' then`
376			`if ADDRF=onehalf then`
377			`ZWR<='1';`
378			`else`
379			`ZWR<='0';`
380			`end if;`
381
382			`if ADDRF=0 or resfly='1' then`
383			`ZWI<='1';`
384			`else`
385			`ZWI<='0';`
386			`end if;`
387
388			`if ODDCi='1' then --cosine address`
389			`if ADDRF(n-2)='0' then`
390			`ADDRROMi<='0'&ADDRF(n-3 downto 0);`
391			`SIGNRE<='0';`
392			`else`
393			`ADDRROMi<=onehalf-('0'&ADDRF(n-3 downto 0));`
394			`SIGNRE<='1';`
395			`end if;`
396
397			`else -- sine address`
398			`if ADDRF(n-2)='0' then`
399			`ADDRROMi<=onehalf -('0'&ADDRF(n-3 downto 0));`
400			`else`
401			`ADDRROMi<='0'&ADDRF(n-3 downto 0);`
402			`end if;`
403			`end if;`
404			`end if;`
405			`end if;`
406			`end process;`
407
408
409			`CTBFLIES:process(CLK,RST,bflies) --butterfly counter`
410			`begin`
411			`if RST='1' then`
412			`wefft<='0';`
413			`enditera<='0';`
414			`bflies<=( others=>'0');`
415			`WERESULTi<='0';`
416			`FFTRDYi<='0';`
417			`resrdy<='0';`
418
419			`elsif CLK='1' and CLK'event then`
420			`if CE='1' then`
421			`resrdy<= startitera and itera(n-2);`
422			`if startiterad2='1' then`
423			`wefft<='1';`
424			`if itera(n-1)='1'then`
425			`WERESULTi<='1';`
426			`end if;`
427			`end if;`
428
429			`if startitera='1' then`
430			`bflies<=( others=>'0');`
431			`elsif fftfly='1'`
432			`then`
433			`bflies<=bflies+1;`
434			`end if;`
435
436			`if idatardy ='1' and go ='0' then`
437			`FFTRDYi<='1';`
438			`elsif bflies=nn + lat2 and enditera='0' then`
439			`enditera<='1';`
440			`wefft<='0';`
441			`WERESULTi<='0';`
442			`if itera(n-1)='1' then`
443			`FFTRDYi<='1';`
444			`end if;`
445			`else`
446			`enditera<='0';`
447			`FFTRDYi<='0';`
448			`end if;`
449			`end if;`
450			`end if;`
451			`end process;`
452
453			`TIARRDY:process(CLK,RST) --1st input data ready`
454			`begin`
455			`if RST='1' then`
456			`iarrdy<='0';`
457			`iarrdy1<='0';`
458			`go<='0';`
459			`god<='0';`
460			`god2<='0';`
461			`elsif CLK='1' and CLK'event then`
462			`if CE='1' then`
463			`if START='1' then`
464			`iarrdy<='0';`
465			`iarrdy1<='0';`
466			`go<='0';`
467			`elsif idatardy='1' then`
468			`iarrdy<='1';`
469			`go<='1';`
470			`god<='0';`
471			`if go='0'`
472			`then`
473			`iarrdy1<='1';`
474			`end if;`
475
476			`else`
477			`god2<=god;`
478			`iarrdy<='0';`
479			`iarrdy1<='0';`
480			`if FFTRDYi='1' then`
481			`god<='1' ;`
482			`end if;`
483			`end if;`
484			`end if;`
485			`end if;`
486			`end process;`
487
488			`CTITERA:process(CLK,RST) --iteration counter`
489			`begin`
490			`if RST='1' then`
491			`itera<=CONV_STD_LOGIC_VECTOR(1,n);`
492			`elsif CLK='1' and CLK'event then`
493			`if CE='1' then`
494			`if FFTRDYi='1' then`
495			`itera<=CONV_STD_LOGIC_VECTOR(1,n);`
496			`elsif enditera='1' then`
497			`itera<=itera(n-2 downto 0)&'0';`
498			`end if;`
499			`end if;`
500			`end if;`
501			`end process;`
502
503
504			`CTWOSST:process(CLK,RST,addres0,addres1,oddci) -- data counters for wosstanowlenija`
505			`variable addrw:STD_LOGIC_VECTOR(n-1 downto 0);`
506			`begin`
507			`if RST='1' then`
508			`addres0<=(others=>'0');`
509			`addres1<=(others=>'0');`
510			`resnumi<=(others=>'0');`
511			`resend<='0';`
512			`-- WERESwosst<='0';`
513			`RESRAM<='0';`
514			`elsif CLK='1' and CLK'event then`
515
516			`if CE='1' then`
517			`resend<='0';`
518			`resflyd<=resflyd(14 downto 0)& resfly;`
519			`if (FILTER=0 and reall=1 and START='0' and startd = '1')`
520			`or (FILTER=1 and filt1end='1'and reall=1)`
521			`or (FILTER=2 and filt2end='1'and reall=1)`
522			`or (FILTER=3 and filt3end='1'and reall=1)`
523			`then`
524			`RESRAM<='0';`
525			`addres0<= (others=>'0');`
526			`addres1<= (others=>'0');`
527			`resnumi<=(others=>'0');`
528			`elsif resfly='1' then`
529			`if oddci='1' and resflyd(7)='1' then --'1'`
530			`addres0<=UNSIGNED(addres0)+1;`
531			`addres1<=UNSIGNED(addres1)-1;`
532			`end if;`
533			`resnumi<=UNSIGNED(resnumi)+1;`
534			`if resnumi=oneh then`
535			`RESRAM<='1';`
536			`end if;`
537			`end if;`
538			`if UNSIGNED(addres0)=nn/2 then`
539			`resend<='1';`
540			`end if;`
541			`if (resflyd(7) and resfly)='0' then`
542			`RESRAM<='0';`
543			`end if;`
544			`end if;`
545			`end if;`
546			`if oddci='0' then`
547			`addrw:= addres0;`
548			`else`
549			`addrw:= addres1;`
550			`end if;`
551			`--2-ja inversija`
552			`if reall=1 then`
553			`for i in 0 to n-1 loop`
554			`addrwosstw(i)<=addrw(n-i-1); --2-th inverse writing address`
555			`end loop;`
556			`else`
557			`addrwosstw<=addrw;`
558			`end if;`
559
560			`end process;`
561			`WERESwosst<=resflyd(7) and resfly;`
562
563			`resnum<=resnumi(n-1 downto 0);`
564
565
566			`TTFFTFLY:process(CLK,RST,enditera) --triggers of the FFT running`
567			`begin`
568			`if RST='1' then`
569			`filt1fly<='0';`
570			`filt2fly<='0';`
571			`filt3fly<='0';`
572			`resfly<='0';`
573			`fftfly<='0';`
574			`fftend<='0';`
575			`MODE<="00";`
576			`elsif CLK='1' and CLK'event then`
577			`if CE='1' then`
578			`if START='0' and startd = '1'then--`
579			`if FILTER=0 then`
580			`if reall=0 then`
581			`MODE<="01";`
582			`fftfly<='1';`
583			`else`
584			`resfly<='1';`
585			`MODE<="10";`
586			`end if;`
587			`else`
588			`filt1fly<='1';`
589			`MODE<="00";`
590			`end if;`
591			`elsif filt1end='1' then`
592			`filt1fly<='0';`
593			`if FILTER=1 then`
594			`if reall=0 then`
595			`MODE<="01";`
596			`fftfly<='1';`
597			`else`
598			`resfly<='1';`
599			`MODE<="10";`
600			`end if;`
601			`else`
602			`filt2fly<='1';`
603			`MODE<="11";`
604			`end if;`
605			`elsif filt2end='1' then`
606			`filt2fly<='0';`
607			`if FILTER=2 then`
608			`if reall=0 then`
609			`MODE<="01";`
610			`fftfly<='1';`
611			`else`
612			`MODE<="10";`
613			`resfly<='1';`
614			`end if;`
615			`else`
616			`filt3fly<='1';`
617			`MODE<="11";`
618			`end if;`
619			`elsif filt3end='1' then`
620			`filt3fly<='0';`
621			`if reall=0 then`
622			`MODE<="01";`
623			`fftfly<='1';`
624			`else`
625			`MODE<="10";`
626			`resfly<='1';`
627			`end if;`
628			`elsif resend='1' then`
629			`resfly<='0';`
630			`fftfly<='1';`
631			`MODE<="01";`
632			`elsif FFTend='1' then`
633			`fftfly<='0';`
634			`end if;`
635			`end if;`
636			`end if;`
637			`fftend<= (enditera and itera(n-1)) ;`
638			`end process;`
639
640			`REXP: process(CLK,RST) --exponent counter`
641			`begin`
642			`if RST='1' then`
643			`EXPi<=( others=>'0');`
644			`DIV2<='0';`
645			`elsif CLK='1' and CLK'event then`
646			`if CE='1' then`
647			`if ((FILTER=0 and start='0' and startd='1')`
648			`or (FILTER=1 and filt1end='1')`
649			`or (FILTER=2 and filt2end='1')`
650			`or (FILTER=3 and filt3end='1')) then`
651			`EXPi<=( 0 =>OVERF, others=>'0');`
652			`DIV2<= overf;`
653			`elsif startitera='1' and (fftfly='1' or resfly='1')then`
654			`if OVERF = '1' then`
655			`EXPi<=UNSIGNED(EXPi)+1;`
656			`DIV2<='1';`
657			`else`
658			`DIV2<='0';`
659			`end if;`
660			`elsif FFTRDYi='1' then`
661			`DIV2<='0';`
662			`end if;`
663			`end if;`
664			`end if;`
665			`end process;`
666
667
668			`--WEI<=DATAE;`
669			`WEd<=DATAE;`
670
671
672
673
674			`FFTRDY<= FFTRDYi after 3 ns;`
675			`startitera<= '1' when (enditera='1' and FFTRDYi='0')`
676			`or (filt1end='1' and FILTER=1 and reall=0)`
677			`or (filt2end='1' and FILTER=2 and reall=0 )`
678			`or (filt3end='1' and FILTER=3 and reall=0)`
679			`or (resend='1' and reall=1)`
680			`else '0';`
681
682			`WEM<=wefilt when filt1fly='1' or filt2fly='1'or filt3fly='1'`
683			`else wefft when fftfly='1'`
684			`else WERESwosst ;`
685
686
687
688			`WERES<= WERESULTi after 1 ns;`
689			`ADDRRES<= ADDRWi when fftfly='1' and itera(n-1)='1' else (others=>'0');`
690
691			`ADDRR<='1'& resnum when resfly='1'`
692			`else '1'& addrrf when filt2fly='1' or filt3fly='1'`
693			`else '0'& ADDRRi ;`
694
695			`ADDRWM<= '0'&addrwf when filt1fly='1'and FILTER=1 and reall=0`
696			`else '1'&addrwf when filt3fly='1' or filt2fly='1' or filt1fly='1'`
697			`else '0'&addrwosstw when resfly='1'`
698			`else '0'& ADDRWi;`
699
700			`SEL<='1' when (FILTER="00" and reall=0 and fftfly ='1' and itera(0)='1')`
701			`or(FILTER="00" and reall=1 and resfly ='1')`
702			`or(FILTER/="00" and filt1fly='1')`
703			`else '0';`
704
705			`SELW<= "01" when filt1fly='1' else`
706			`"10" when (Filt2fly or filt3fly)='1' else`
707			`"00";`
708
709			`INITOVERF<=startitera;-- and START;`
710
711			`ADDRROM<= addrfilt(n-2 downto 0) when filt1fly='1'`
712			`else addrROMF when filt2fly='1' or filt3fly='1'`
713			`else ADDRROMi(n-2 downto 0) when fftfly='1'`
714			`else (others=>'0');-- when oddci='1' else '1'&nulls(n-3 downto 0);`
715
716			`READY<=resrdy after 3 ns;`
717
718			`EXP<=EXPi;`
719
720			`end CONTROL_slip;`