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[/] [fft_fir_filter/] [trunk/] [rtl/] [denorm.vhd] - Blame information for rev 2

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---------------------------------------------------------------------
----                                                             ----
----  FFT Filter IP core                                         ----
----                                                             ----
----  Authors: Anatoliy Sergienko, Volodya Lepeha                ----
----  Company: Unicore Systems http://unicore.co.ua              ----
----                                                             ----
----  Downloaded from: http://www.opencores.org                  ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2006-2010 Unicore Systems LTD                 ----
---- www.unicore.co.ua                                           ----
---- o.uzenkov@unicore.co.ua                                     ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
---- THIS SOFTWARE IS PROVIDED "AS IS"                           ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT              ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT         ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION)                 ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,              ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING                 ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,                 ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.          ----
----                                                             ----
---------------------------------------------------------------------
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~           
--     Data is shifted right and then written when is address is
--      betweenn  0100..0 and 1011..1
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
 
entity DENORM is
        generic (width: integer :=8     ;       --  word width =8...24
                n:INTEGER:=7 ;
                satur:INTEGER:=1 ; --1 - usilenie s ogranicheniem 
                reall:INTEGER:= 0 ;
                v2:INTEGER:=1 );-- 1 - Virtex2
        port (
                CLK: in STD_LOGIC;
                RST: in STD_LOGIC;
                CE: in STD_LOGIC;
                DATAE: in STD_LOGIC;
                START: in STD_LOGIC;      -- 
                INIT: in STD_LOGIC;      -- 
                WERES: in STD_LOGIC;
                SPRDY: in STD_LOGIC;
                ADDRRES: in STD_LOGIC_VECTOR (n-1 downto 0);
                EXPI: in STD_LOGIC_VECTOR (3 downto 0);
                EXPF: in STD_LOGIC_VECTOR (3 downto 0);
                REDI: in STD_LOGIC_VECTOR (width-1 downto 0);
                IMDI: in STD_LOGIC_VECTOR (width-1 downto 0);
                RDY: out STD_LOGIC;
                REDO: out STD_LOGIC_VECTOR (width-1 downto 0);
                IMDO: out STD_LOGIC_VECTOR (width-1 downto 0)
                );
end DENORM;
 
 
architecture FFTDPATH_s of DENORM is
        component  RAMB16_S36_S36 is
                port (DIA    : in STD_LOGIC_VECTOR (31 downto 0);
                        DIB    : in STD_LOGIC_VECTOR (31 downto 0);
                        DIPA    : in STD_LOGIC_VECTOR (3 downto 0);
                        DIPB    : in STD_LOGIC_VECTOR (3 downto 0);
                        ENA    : in STD_ULOGIC;
                        ENB    : in STD_ULOGIC;
                        WEA    : in STD_ULOGIC;
                        WEB    : in STD_ULOGIC;
                        SSRA   : in STD_ULOGIC;
                        SSRB   : in STD_ULOGIC;
                        CLKA   : in STD_ULOGIC;
                        CLKB   : in STD_ULOGIC;
                        ADDRA  : in STD_LOGIC_VECTOR (8 downto 0);
                        ADDRB  : in STD_LOGIC_VECTOR (8 downto 0);
                        DOA    : out STD_LOGIC_VECTOR (31 downto 0);
                        DOB    : out STD_LOGIC_VECTOR (31 downto 0);
                        DOPA    : out STD_LOGIC_VECTOR (3 downto 0);
                        DOPB    : out STD_LOGIC_VECTOR (3 downto 0)
                        );
        end     component;
        component   RAMB16_S18_S18 is
                port (DIA    : in STD_LOGIC_VECTOR (15 downto 0);
                        DIB    : in STD_LOGIC_VECTOR (15 downto 0);
                        DIPA    : in STD_LOGIC_VECTOR (1 downto 0);
                        DIPB    : in STD_LOGIC_VECTOR (1 downto 0);
                        ENA    : in STD_ULOGIC;
                        ENB    : in STD_ULOGIC;
                        WEA    : in STD_ULOGIC;
                        WEB    : in STD_ULOGIC;
                        SSRA   : in STD_ULOGIC;
                        SSRB   : in STD_ULOGIC;
                        CLKA   : in STD_ULOGIC;
                        CLKB   : in STD_ULOGIC;
                        ADDRA  : in STD_LOGIC_VECTOR (9 downto 0);
                        ADDRB  : in STD_LOGIC_VECTOR (9 downto 0);
                        DOA    : out STD_LOGIC_VECTOR (15 downto 0);
                        DOB    : out STD_LOGIC_VECTOR (15 downto 0);
                        DOPA    : out STD_LOGIC_VECTOR (1 downto 0);
                        DOPB    : out STD_LOGIC_VECTOR (1 downto 0)
                        );
        end     component;
        constant nulls:std_logic_vector(31 downto 0):=X"00000000";
        constant ones:std_logic_vector(n-1 downto 0):=(others=>'1');
        constant plus1:std_logic_vector(17 downto 0):="011111111111111111";
        constant minus1:std_logic_vector(17 downto 0):="100000000000000000";
        constant gnd:STD_LOGIC:='0';
        constant endaddrr:std_logic_vector(9 downto 0):=nulls(9-n downto 0)&ones;
        constant endaddr:STD_LOGIC_VECTOR (9 downto 0):=
        conv_std_logic_vector((2**n-10),10);
 
        signal exp,expfi:std_logic_vector(3 downto 0);
        signal DRES,DIMS:std_logic_vector(17 downto 0);
        signal DRESS,DIMSS:std_logic_vector(18 downto 0);
        signal DRE0,DIM0,DIMou,REDOi,REDOii,IMDOi,IMDOii:std_logic_vector(17 downto 0);
        signal DRE0i,DIM0i,DRESi,DIMSi:std_logic_vector(31 downto 0);
        signal D32,D32o:std_logic_vector(31 downto 0);
        signal D4,D4o:std_logic_vector(3 downto 0);
        signal ADDR:std_logic_vector(n-1 downto 0);
        signal ADDRW,addrr:std_logic_vector(9 downto 0);
        signal WEM,an:STD_LOGIC;
 
 
begin
 
 
        RC:process(CLK,RST)
                variable        exi:STD_LOGIC_VECTOR(4 downto 0);
        begin
                if RST='1' then
                        exp<="0000";
                        expfi<="0000";
                elsif rising_edge(CLK) then
                        if SPRDY='1' then
                                if reall=1 then
                                        expfi<=EXPF;
                                else
                                        expfi<=EXPF+2;
                                end if;
                        end if;
                        exi:='0'&EXPI+ EXPFi;            --common exponent  
                        --if exi(4)='1' then
                        --                              exi:="00000";
                        --                      end if;
                        if INIT='1' then
 
                                EXP<=exi(3 downto 0);
 
 
                        end if;
                end if;
        end process;
 
        DRE0i<=SXT(REDI,32)     ;
        DIM0i<=SXT(IMDI,32);
 
        DRESi <= SHL(DRE0i,exp);
        DIMSi <= SHL(DIM0i,exp);
        DRESs<=DRESi(20+n downto n+2);
        DIMSs<=DIMSi(20+n downto n+2);
 
        SAT:if satur=1 generate
                DRES<= plus1 when DRESS(18)='0' and  DRESS(17)='1' else
                minus1 when DRESS(18)='1' and  DRESS(17)='0' else
                DRESS(17 downto 0);
                DIMS<= plus1 when DIMSS(18)='0' and  DIMSS(17)='1' else
                minus1 when DIMSS(18)='1' and  DIMSS(17)='0' else
                DIMSS(17 downto 0);
        end generate;
        NSAT:if satur=0 generate
                DRES<= DRESS(17 downto 0);
                DIMS<=DIMSS(17 downto 0);
        end generate;
 
 
        D32<=DIMS(13 downto 0)&DRES;
        D4<=DIMS(17 downto 14);
 
        ADDR<=ADDRRES;
        ADR:process(addr) begin
                ADDRW<=(others=>'0');
                ADDRW(n-1)<=an;
                ADDRW(n-2)<=not ADDR(n-2);--    not ADDR(n-2);  
                ADDRW(n-3 downto 0)<=    ADDR(n-3 downto 0);
        end process;
        WEM<=WERES when (ADDR(n-1) xor ADDR(n-2))='1' else '0';
        --WEM<=WERES when ADDR(n-1)='0' else '0';
 
        CTO:process(CLK,RST)
                variable ea: std_logic_vector(9 downto 0);
 
        begin
                if reall=0 then
                ea:=endaddr;--"0000000000"; 
                else
                ea:=endaddrr;
                end if;
 
                if RST='1' then
                                RDY<='0';
                        an<='0';
                        addrr<=ea;
                elsif rising_edge(CLK) then
                        if start ='1' then
                                an<='1';
                                addrr<=ea;--0000000000";                
                        elsif  DATAE='1' then
                                if addrr(n-1 downto 0)=nulls(n-1 downto 0) then--ones(n-1 downto 0) then
                                        addrr<=endaddrr;
                                        RDY<='1';
                                else
                                                RDY<='0';
                                        addrr<=addrr-1;   --adres tshtenija dla wydachi resultata
                                end if;
 
                        end if;
                        if init='1' then
                                an<=not an;
                        end if;
 
                end if;
        end process;
 
 
 
        RAM_V2_9:        if V2=1 and n<=9 generate
                U_RAM512: RAMB16_S36_S36
                port map (DIA=>D32,
                        DIB  =>nulls,
                        DIPA =>D4,
                        DIPB =>nulls(3 downto 0),
                        ENA  =>CE,
                        ENB  =>CE,
                        WEA  =>WEM,
                        WEB  =>gnd,
                        SSRA =>gnd,
                        SSRB =>gnd,
                        CLKA =>CLK,
                        CLKB =>CLK,
                        ADDRA =>ADDRW(8 downto 0),
                        ADDRB =>ADDRR(8 downto 0),
                        DOA  =>open,
                        DOB   =>D32o,
                        DOPA  =>open,
                        DOPB  =>d4o     );
                REDO<=  D32o(17 downto 18-width) ;
                DIMou<=  D4o  & D32o(31 downto 18);
                IMDO<=  DIMOu(17 downto 18-width) ;
 
        end generate;
 
        RAM_V2_10:       if V2=1 and n=10 generate
                U_RAM1024_0: RAMB16_S18_S18
                port map (DIA=>DRES(15 downto 0),
                        DIB  =>nulls(15 downto 0),
                        DIPA =>DRES(17 downto 16),
                        DIPB =>nulls(1 downto 0),
                        ENA  =>CE,
                        ENB  =>CE,
                        WEA  =>WEM,
                        WEB  =>gnd,
                        SSRA =>gnd,
                        SSRB =>gnd,
                        CLKA =>CLK,
                        CLKB =>CLK,
                        ADDRA =>ADDRW,
                        ADDRB =>ADDRR,
                        DOA  =>open,
                        DOB   =>REDOi(15 downto 0),
                        DOPA  =>open,
                        DOPB  =>REDOi(17 downto 16));
 
                U_RAM1024_1:  RAMB16_S18_S18
                port map (DIA=>DIMS(15 downto 0),
                        DIB  =>nulls(15 downto 0),
                        DIPA =>DIMS(17 downto 16),
                        DIPB =>nulls(1 downto 0),
                        ENA  =>CE,
                        ENB  =>CE,
                        WEA  =>WEM,
                        WEB  =>gnd,
                        SSRA =>gnd,
                        SSRB =>gnd,
                        CLKA =>CLK,
                        CLKB =>CLK,
                        ADDRA =>ADDRW,
                        ADDRB =>ADDRR,
                        DOA  =>open,
                        DOB   =>IMDOi(15 downto 0),
                        DOPA  =>open,
                        DOPB  =>IMDOi(17 downto 16));
 
 
 
                REDO<=  REDOi(17 downto 18-width) ;
                IMDO<=  IMDOi(17 downto 18-width) ;
        end generate;
 
 
 
 
 
end FFTDPATH_s;

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Subversion Repositories fft_fir_filter

[/] [fft_fir_filter/] [trunk/] [rtl/] [denorm.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	unicore
2			`---------------------------------------------------------------------`
3			`---- ----`
4			`---- FFT Filter IP core ----`
5			`---- ----`
6			`---- Authors: Anatoliy Sergienko, Volodya Lepeha ----`
7			`---- Company: Unicore Systems http://unicore.co.ua ----`
8			`---- ----`
9			`---- Downloaded from: http://www.opencores.org ----`
10			`---- ----`
11			`---------------------------------------------------------------------`
12			`---- ----`
13			`---- Copyright (C) 2006-2010 Unicore Systems LTD ----`
14			`---- www.unicore.co.ua ----`
15			`---- o.uzenkov@unicore.co.ua ----`
16			`---- ----`
17			`---- This source file may be used and distributed without ----`
18			`---- restriction provided that this copyright statement is not ----`
19			`---- removed from the file and that any derivative work contains ----`
20			`---- the original copyright notice and the associated disclaimer.----`
21			`---- ----`
22			`---- THIS SOFTWARE IS PROVIDED "AS IS" ----`
23			`---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----`
24			`---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----`
25			`---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----`
26			`---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----`
27			`---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----`
28			`---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
29			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----`
30			`---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----`
31			`---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----`
32			`---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----`
33			`---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----`
34			`---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
35			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----`
36			`---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----`
37			`---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----`
38			`---- ----`
39			`---------------------------------------------------------------------`
40			`--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~`
41			`-- Data is shifted right and then written when is address is`
42			`-- betweenn 0100..0 and 1011..1`
43
44
45			`library IEEE;`
46			`use IEEE.std_logic_1164.all;`
47			`use IEEE.std_logic_arith.all;`
48			`use IEEE.std_logic_signed.all;`
49
50			`entity DENORM is`
51			`generic (width: integer :=8 ; -- word width =8...24`
52			`n:INTEGER:=7 ;`
53			`satur:INTEGER:=1 ; --1 - usilenie s ogranicheniem`
54			`reall:INTEGER:= 0 ;`
55			`v2:INTEGER:=1 );-- 1 - Virtex2`
56			`port (`
57			`CLK: in STD_LOGIC;`
58			`RST: in STD_LOGIC;`
59			`CE: in STD_LOGIC;`
60			`DATAE: in STD_LOGIC;`
61			`START: in STD_LOGIC; --`
62			`INIT: in STD_LOGIC; --`
63			`WERES: in STD_LOGIC;`
64			`SPRDY: in STD_LOGIC;`
65			`ADDRRES: in STD_LOGIC_VECTOR (n-1 downto 0);`
66			`EXPI: in STD_LOGIC_VECTOR (3 downto 0);`
67			`EXPF: in STD_LOGIC_VECTOR (3 downto 0);`
68			`REDI: in STD_LOGIC_VECTOR (width-1 downto 0);`
69			`IMDI: in STD_LOGIC_VECTOR (width-1 downto 0);`
70			`RDY: out STD_LOGIC;`
71			`REDO: out STD_LOGIC_VECTOR (width-1 downto 0);`
72			`IMDO: out STD_LOGIC_VECTOR (width-1 downto 0)`
73			`);`
74			`end DENORM;`
75
76
77			`architecture FFTDPATH_s of DENORM is`
78			`component RAMB16_S36_S36 is`
79			`port (DIA : in STD_LOGIC_VECTOR (31 downto 0);`
80			`DIB : in STD_LOGIC_VECTOR (31 downto 0);`
81			`DIPA : in STD_LOGIC_VECTOR (3 downto 0);`
82			`DIPB : in STD_LOGIC_VECTOR (3 downto 0);`
83			`ENA : in STD_ULOGIC;`
84			`ENB : in STD_ULOGIC;`
85			`WEA : in STD_ULOGIC;`
86			`WEB : in STD_ULOGIC;`
87			`SSRA : in STD_ULOGIC;`
88			`SSRB : in STD_ULOGIC;`
89			`CLKA : in STD_ULOGIC;`
90			`CLKB : in STD_ULOGIC;`
91			`ADDRA : in STD_LOGIC_VECTOR (8 downto 0);`
92			`ADDRB : in STD_LOGIC_VECTOR (8 downto 0);`
93			`DOA : out STD_LOGIC_VECTOR (31 downto 0);`
94			`DOB : out STD_LOGIC_VECTOR (31 downto 0);`
95			`DOPA : out STD_LOGIC_VECTOR (3 downto 0);`
96			`DOPB : out STD_LOGIC_VECTOR (3 downto 0)`
97			`);`
98			`end component;`
99			`component RAMB16_S18_S18 is`
100			`port (DIA : in STD_LOGIC_VECTOR (15 downto 0);`
101			`DIB : in STD_LOGIC_VECTOR (15 downto 0);`
102			`DIPA : in STD_LOGIC_VECTOR (1 downto 0);`
103			`DIPB : in STD_LOGIC_VECTOR (1 downto 0);`
104			`ENA : in STD_ULOGIC;`
105			`ENB : in STD_ULOGIC;`
106			`WEA : in STD_ULOGIC;`
107			`WEB : in STD_ULOGIC;`
108			`SSRA : in STD_ULOGIC;`
109			`SSRB : in STD_ULOGIC;`
110			`CLKA : in STD_ULOGIC;`
111			`CLKB : in STD_ULOGIC;`
112			`ADDRA : in STD_LOGIC_VECTOR (9 downto 0);`
113			`ADDRB : in STD_LOGIC_VECTOR (9 downto 0);`
114			`DOA : out STD_LOGIC_VECTOR (15 downto 0);`
115			`DOB : out STD_LOGIC_VECTOR (15 downto 0);`
116			`DOPA : out STD_LOGIC_VECTOR (1 downto 0);`
117			`DOPB : out STD_LOGIC_VECTOR (1 downto 0)`
118			`);`
119			`end component;`
120			`constant nulls:std_logic_vector(31 downto 0):=X"00000000";`
121			`constant ones:std_logic_vector(n-1 downto 0):=(others=>'1');`
122			`constant plus1:std_logic_vector(17 downto 0):="011111111111111111";`
123			`constant minus1:std_logic_vector(17 downto 0):="100000000000000000";`
124			`constant gnd:STD_LOGIC:='0';`
125			`constant endaddrr:std_logic_vector(9 downto 0):=nulls(9-n downto 0)&ones;`
126			`constant endaddr:STD_LOGIC_VECTOR (9 downto 0):=`
127			`conv_std_logic_vector((2**n-10),10);`
128
129			`signal exp,expfi:std_logic_vector(3 downto 0);`
130			`signal DRES,DIMS:std_logic_vector(17 downto 0);`
131			`signal DRESS,DIMSS:std_logic_vector(18 downto 0);`
132			`signal DRE0,DIM0,DIMou,REDOi,REDOii,IMDOi,IMDOii:std_logic_vector(17 downto 0);`
133			`signal DRE0i,DIM0i,DRESi,DIMSi:std_logic_vector(31 downto 0);`
134			`signal D32,D32o:std_logic_vector(31 downto 0);`
135			`signal D4,D4o:std_logic_vector(3 downto 0);`
136			`signal ADDR:std_logic_vector(n-1 downto 0);`
137			`signal ADDRW,addrr:std_logic_vector(9 downto 0);`
138			`signal WEM,an:STD_LOGIC;`
139
140
141			`begin`
142
143
144			`RC:process(CLK,RST)`
145			`variable exi:STD_LOGIC_VECTOR(4 downto 0);`
146			`begin`
147			`if RST='1' then`
148			`exp<="0000";`
149			`expfi<="0000";`
150			`elsif rising_edge(CLK) then`
151			`if SPRDY='1' then`
152			`if reall=1 then`
153			`expfi<=EXPF;`
154			`else`
155			`expfi<=EXPF+2;`
156			`end if;`
157			`end if;`
158			`exi:='0'&EXPI+ EXPFi; --common exponent`
159			`--if exi(4)='1' then`
160			`-- exi:="00000";`
161			`-- end if;`
162			`if INIT='1' then`
163
164			`EXP<=exi(3 downto 0);`
165
166
167			`end if;`
168			`end if;`
169			`end process;`
170
171			`DRE0i<=SXT(REDI,32) ;`
172			`DIM0i<=SXT(IMDI,32);`
173
174			`DRESi <= SHL(DRE0i,exp);`
175			`DIMSi <= SHL(DIM0i,exp);`
176			`DRESs<=DRESi(20+n downto n+2);`
177			`DIMSs<=DIMSi(20+n downto n+2);`
178
179			`SAT:if satur=1 generate`
180			`DRES<= plus1 when DRESS(18)='0' and DRESS(17)='1' else`
181			`minus1 when DRESS(18)='1' and DRESS(17)='0' else`
182			`DRESS(17 downto 0);`
183			`DIMS<= plus1 when DIMSS(18)='0' and DIMSS(17)='1' else`
184			`minus1 when DIMSS(18)='1' and DIMSS(17)='0' else`
185			`DIMSS(17 downto 0);`
186			`end generate;`
187			`NSAT:if satur=0 generate`
188			`DRES<= DRESS(17 downto 0);`
189			`DIMS<=DIMSS(17 downto 0);`
190			`end generate;`
191
192
193			`D32<=DIMS(13 downto 0)&DRES;`
194			`D4<=DIMS(17 downto 14);`
195
196			`ADDR<=ADDRRES;`
197			`ADR:process(addr) begin`
198			`ADDRW<=(others=>'0');`
199			`ADDRW(n-1)<=an;`
200			`ADDRW(n-2)<=not ADDR(n-2);-- not ADDR(n-2);`
201			`ADDRW(n-3 downto 0)<= ADDR(n-3 downto 0);`
202			`end process;`
203			`WEM<=WERES when (ADDR(n-1) xor ADDR(n-2))='1' else '0';`
204			`--WEM<=WERES when ADDR(n-1)='0' else '0';`
205
206			`CTO:process(CLK,RST)`
207			`variable ea: std_logic_vector(9 downto 0);`
208
209			`begin`
210			`if reall=0 then`
211			`ea:=endaddr;--"0000000000";`
212			`else`
213			`ea:=endaddrr;`
214			`end if;`
215
216			`if RST='1' then`
217			`RDY<='0';`
218			`an<='0';`
219			`addrr<=ea;`
220			`elsif rising_edge(CLK) then`
221			`if start ='1' then`
222			`an<='1';`
223			`addrr<=ea;--0000000000";`
224			`elsif DATAE='1' then`
225			`if addrr(n-1 downto 0)=nulls(n-1 downto 0) then--ones(n-1 downto 0) then`
226			`addrr<=endaddrr;`
227			`RDY<='1';`
228			`else`
229			`RDY<='0';`
230			`addrr<=addrr-1; --adres tshtenija dla wydachi resultata`
231			`end if;`
232
233			`end if;`
234			`if init='1' then`
235			`an<=not an;`
236			`end if;`
237
238			`end if;`
239			`end process;`
240
241
242
243			`RAM_V2_9: if V2=1 and n<=9 generate`
244			`U_RAM512: RAMB16_S36_S36`
245			`port map (DIA=>D32,`
246			`DIB =>nulls,`
247			`DIPA =>D4,`
248			`DIPB =>nulls(3 downto 0),`
249			`ENA =>CE,`
250			`ENB =>CE,`
251			`WEA =>WEM,`
252			`WEB =>gnd,`
253			`SSRA =>gnd,`
254			`SSRB =>gnd,`
255			`CLKA =>CLK,`
256			`CLKB =>CLK,`
257			`ADDRA =>ADDRW(8 downto 0),`
258			`ADDRB =>ADDRR(8 downto 0),`
259			`DOA =>open,`
260			`DOB =>D32o,`
261			`DOPA =>open,`
262			`DOPB =>d4o );`
263			`REDO<= D32o(17 downto 18-width) ;`
264			`DIMou<= D4o & D32o(31 downto 18);`
265			`IMDO<= DIMOu(17 downto 18-width) ;`
266
267			`end generate;`
268
269			`RAM_V2_10: if V2=1 and n=10 generate`
270			`U_RAM1024_0: RAMB16_S18_S18`
271			`port map (DIA=>DRES(15 downto 0),`
272			`DIB =>nulls(15 downto 0),`
273			`DIPA =>DRES(17 downto 16),`
274			`DIPB =>nulls(1 downto 0),`
275			`ENA =>CE,`
276			`ENB =>CE,`
277			`WEA =>WEM,`
278			`WEB =>gnd,`
279			`SSRA =>gnd,`
280			`SSRB =>gnd,`
281			`CLKA =>CLK,`
282			`CLKB =>CLK,`
283			`ADDRA =>ADDRW,`
284			`ADDRB =>ADDRR,`
285			`DOA =>open,`
286			`DOB =>REDOi(15 downto 0),`
287			`DOPA =>open,`
288			`DOPB =>REDOi(17 downto 16));`
289
290			`U_RAM1024_1: RAMB16_S18_S18`
291			`port map (DIA=>DIMS(15 downto 0),`
292			`DIB =>nulls(15 downto 0),`
293			`DIPA =>DIMS(17 downto 16),`
294			`DIPB =>nulls(1 downto 0),`
295			`ENA =>CE,`
296			`ENB =>CE,`
297			`WEA =>WEM,`
298			`WEB =>gnd,`
299			`SSRA =>gnd,`
300			`SSRB =>gnd,`
301			`CLKA =>CLK,`
302			`CLKB =>CLK,`
303			`ADDRA =>ADDRW,`
304			`ADDRB =>ADDRR,`
305			`DOA =>open,`
306			`DOB =>IMDOi(15 downto 0),`
307			`DOPA =>open,`
308			`DOPB =>IMDOi(17 downto 16));`
309
310
311
312			`REDO<= REDOi(17 downto 18-width) ;`
313			`IMDO<= IMDOi(17 downto 18-width) ;`
314			`end generate;`
315
316
317
318
319
320			`end FFTDPATH_s;`