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---------------------------------------------------------------------
----                                                             ----
----  FFT Filter IP core                                         ----
----                                                             ----
----  Authors: Anatoliy Sergienko, Volodya Lepeha                ----
----  Company: Unicore Systems http://unicore.co.ua              ----
----                                                             ----
----  Downloaded from: http://www.opencores.org                  ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2006-2010 Unicore Systems LTD                 ----
---- www.unicore.co.ua                                           ----
---- o.uzenkov@unicore.co.ua                                     ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
---- THIS SOFTWARE IS PROVIDED "AS IS"                           ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT              ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT         ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION)                 ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,              ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING                 ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,                 ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.          ----
----                                                             ----
---------------------------------------------------------------------
-- AUTHORS      Volodymir Lepekha,              
--              Anatoli Sergyienko.
--HISTORY       :07.2005 mode added:
--           00 - multiply by window
--           01 - butterfly
--           10 - restore for real FFT     
-- only for Virtex2 and later   
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~           
 
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
entity FFTDPATH is
        generic (       ifft: integer:=0;
                width: integer :=8      ;               --  word width =8...24
                Wwdth: integer:=7;                      --  coefficient width =7...15  
                V2:integer
                );
        port (
                CLK: in STD_LOGIC;
                RST: in STD_LOGIC;
                CE: in STD_LOGIC;
                ODDC: in STD_LOGIC;      --
                DIV2: in STD_LOGIC;             --Scaling factor
                ZWR: in STD_LOGIC;
                ZWI: in STD_LOGIC;
                SIGNRE:  in STD_LOGIC;
                MODE: in STD_LOGIC_VECTOR (1 downto 0);
                REDI: in STD_LOGIC_VECTOR (width downto 0);
                IMDI: in STD_LOGIC_VECTOR (width downto 0);
                WF: in STD_LOGIC_VECTOR (wwdth-1 downto 0);
                REDO: out STD_LOGIC_VECTOR (width downto 0);
                IMDO: out STD_LOGIC_VECTOR (width downto 0)
                );
end FFTDPATH;
 
 
architecture FFTDPATH_s of FFTDPATH is
 
        constant zeros: STD_LOGIC_VECTOR (width-wwdth downto 0):=
        CONV_STD_LOGIC_VECTOR(0,width-wwdth+1);
        signal  ar,ai,ar3,ai3:    STD_LOGIC_VECTOR (width-1 downto 0);
        signal  br1,bi1,br,bi,br2,bi2:    STD_LOGIC_VECTOR (width-1 downto 0);
        signal renorm,imnorm,br4,bi4:     STD_LOGIC_VECTOR (width-1 downto 0);
        signal ard,aid:   STD_LOGIC_VECTOR (3 downto 0);
        signal wr,wr1:    STD_LOGIC_VECTOR (wwdth-1 downto 0);
        signal prodrb,prodib: STD_LOGIC_VECTOR (width+wwdth downto 0);
        signal prodr1,prodi1: STD_LOGIC_VECTOR (width+wwdth-2 downto wwdth-2);
        signal prodr2,prodi2: STD_LOGIC_VECTOR (width+wwdth-1 downto wwdth-2);
        signal prodr,prodi,prodrd,prodid: STD_LOGIC_VECTOR (width downto 0);
        signal cr,ci:     STD_LOGIC_VECTOR (width downto 0);
        signal dr,di:     STD_LOGIC_VECTOR (width+2 downto 0);
        signal zwri,zwii,zwr1,zwi1,zwr2,zwi2,signrei,signre1,signre2: STD_LOGIC;
 
 
begin
 
        SHIFT:process(REDI,IMDI,DIV2)
        begin
                if DIV2='1' then
                        renorm <=  REDI (width downto 1);
                        imnorm <= IMDI (width downto 1);
                else
                        renorm <= REDI(width-1 downto 0);
                        imnorm <= IMDI(width-1 downto 0);
                end if;
        end process;
 
        RDELAY:process(CLK,RST)
        begin
                if RST = '1' then
                        wr <= (others =>'0');
                        wr1 <= (others =>'0');
                        ar <= (others =>'0');
                        br <= (others =>'0');
                        br1<= (others =>'0');
                        br2 <= (others =>'0');
                        ar3 <= (others =>'0');
                        br4 <= (others =>'0');
                        ai <= (others =>'0');
                        bi <= (others =>'0');
                        bi1<= (others =>'0');
                        bi2 <= (others =>'0');
                        ai3 <= (others =>'0');
                        bi4 <= (others =>'0');
                elsif CLK = '1' and CLK'event then
                        if CE = '1' then
                                wr<=WF;
                                wr1<=wr;
                                br2<=br1;
                                bi2<=bi1;
                                if ODDC='0' then
                                        ar<= renorm;
                                        ar3<=ar;
                                        br4<=br2;
                                        ai<= imnorm;
                                        ai3<=ai;
                                        bi4<=bi2;
                                else
                                        br<= renorm;
                                        br1<=br;
                                        bi<= imnorm;
                                        bi1<=bi;
                                end if;
                        end if;
                end if;
        end process;
 
        TTDELAY:process(CLK,RST)
        begin
                if RST='1' then
                        zwri<='0';
                        zwii<='0';
                        zwr1<='0';
                        zwi1<='0';
                        zwr2<='0';
                        zwi2<='0';
                        signrei<='0';
                        signre1<='0';
                        signre2<='0';
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                zwri<=ZWR;
                                zwii<=ZWI;
                                zwr1<=zwri;
                                zwi1<=zwii;
                                zwr2<=zwr1;
                                zwi2<=zwi1;
                                signrei<=SIGNRE;
                                signre1<=signrei;
                                signre2<=signre1;
                        end if;
                end if;
        end process;
 
 
 
 
 
        BLCK:if v2=1 generate
                MPU_U:  process(CLK,RST)
                        variable prodr,prodi:STD_LOGIC_VECTOR(width+wwdth-2 downto 0);
                        variable minusre,minusim:STD_LOGIC;
                begin
                        if RST = '1' then
                                prodrb <= (others =>'0');
                                prodr2 <= (others =>'0');
                                prodib <= (others =>'0');
                                prodi2 <= (others =>'0');
 
                        elsif CLK = '1' and CLK'event then
                                if CE = '1' then
                                        prodrb <= signed('0'& wr) * signed(ar);
                                        prodib <= signed('0'& wr) * signed(ai);
 
                                        prodr2<=prodrb(width+wwdth-1 downto wwdth-2);
                                        prodi2<=prodib(width+wwdth-1 downto wwdth-2);
                                end if;
                        end if;
                end process;
        end generate;
 
        prodr<=prodr2( width+wwdth-1 downto wwdth-1);
        prodi<=prodi2( width+wwdth-1 downto wwdth-1);
 
        RPRODD: process(CLK,RST)
        begin
 
                if RST='1' then
                        prodrd<=(others=>'0');
                        prodid<=(others=>'0');
                elsif CLK='1' and CLK'event then
                        if CE ='1' then
                                if signre1='1' then
                                        prodrd<= - signed(prodr);
                                        prodid<= - signed(prodi);
                                else
                                        prodrd<=prodr;
                                        prodid<=prodi;
                                end if;
                        end if;
                end if;
        end process;
 
        FFTINST:if IFFT=0  generate
                ACPROD:process(RST,CLK)
                begin
                        if RST='1' then
                                cr<=(others=>'0');
                                ci<=(others=>'0');
                        elsif CLK='1' and CLK'event then
                                if CE ='1' and ODDC='0' then
                                        if zwi2='1' then
                                                cr <= ar3&'0';
                                                ci <= ai3&'0';
                                        elsif zwr2='1' then
                                                cr <= ai3&'0';
                                                ci <= - signed(ar3&'0');
                                        else
                                                cr<=  signed(prodrd)+signed(prodi);
                                                ci<=  signed(prodid)-signed(prodr);
                                        end if;
                                end if;
                        end if;
                end process;
        end generate;
 
        IFFTINST:if IFFT=1  generate
                ACPROD:process(RST,CLK)
                begin
                        if RST='1' then
                                cr<=(others=>'0');
                                ci<=(others=>'0');
                        elsif CLK='1' and CLK'event then
                                if CE ='1' and ODDC='0' then
                                        if zwi2='1' then
                                                cr <= ar3&'0';
                                                ci <= ai3&'0';
                                        elsif zwr2='1' then
                                                cr <= 0- signed(ai3&'0');
                                                ci <= ar3&'0';
                                        else-- if signre2='1' then
                                                --                                                      cr<= 0- signed(prodrd)-signed(prodi);
                                                --                                                      ci<= 0- signed(prodid)+signed(prodr);
                                                --                                              else
                                                cr<=  signed(prodrd)-signed(prodi);
                                                ci<=  signed(prodid)+signed(prodr);
                                                --      end if;
                                        end if;
                                end if;
                        end if;
                end process;
 
        end generate;
 
        ABUTTERF:process(CLK,RST)
        begin
                if RST='1' then
                        dr<=(others=>'0');
                        di<=(others=>'0');
                elsif CLK='1' and CLK'event then
                        if CE ='1' then
                                case MODE is
                                        when "00" => dr<=prodr&"01";
                                        di<=prodI&"01" ;
                                        when "01" => --butterfly
                                        if ODDC='1' then                              --addition with rounding
                                                dr<=signed(br4&"01")+signed( cr(width)&cr&'1');
                                                di<=signed(bi4&"01")+signed( ci(width)&ci&'1');
                                        else
                                                dr<=signed(br4&"01")-signed( cr(width)&cr&'1');
                                                di<=signed(bi4&"01")-signed( ci(width)&ci&'1');
                                        end if;
                                        when others=>   -- Wosstanowlenie
                                        if ODDC='1' then                              --addition with rounding
                                                dr<=signed(br4&"01")+signed( cr(width)&cr&'1');
                                                di<=signed(bi4&"01")-signed( ci(width)&ci&'1');
                                        else
                                                dr<=signed(bi4&"01")+signed( ci(width)&ci&'1');
                                                di<=signed( cr(width)&cr&'1')- signed(br4&"01");
                                        end if;
                                end case ;
                        end if;
                end if;
        end process;
 
        REDO<=  dr(width+2 downto 2) ;
        IMDO<=  di(width+2 downto 2);
 
 
end FFTDPATH_s;

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Subversion Repositories fft_fir_filter

[/] [fft_fir_filter/] [trunk/] [rtl/] [fftdpath.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	unicore	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- FFT Filter IP core ----`
4			`---- ----`
5			`---- Authors: Anatoliy Sergienko, Volodya Lepeha ----`
6			`---- Company: Unicore Systems http://unicore.co.ua ----`
7			`---- ----`
8			`---- Downloaded from: http://www.opencores.org ----`
9			`---- ----`
10			`---------------------------------------------------------------------`
11			`---- ----`
12			`---- Copyright (C) 2006-2010 Unicore Systems LTD ----`
13			`---- www.unicore.co.ua ----`
14			`---- o.uzenkov@unicore.co.ua ----`
15			`---- ----`
16			`---- This source file may be used and distributed without ----`
17			`---- restriction provided that this copyright statement is not ----`
18			`---- removed from the file and that any derivative work contains ----`
19			`---- the original copyright notice and the associated disclaimer.----`
20			`---- ----`
21			`---- THIS SOFTWARE IS PROVIDED "AS IS" ----`
22			`---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----`
23			`---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----`
24			`---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----`
25			`---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----`
26			`---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----`
27			`---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
28			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----`
29			`---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----`
30			`---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----`
31			`---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----`
32			`---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----`
33			`---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
34			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----`
35			`---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----`
36			`---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----`
37			`---- ----`
38			`---------------------------------------------------------------------`
39			`-- AUTHORS Volodymir Lepekha,`
40			`-- Anatoli Sergyienko.`
41			`--HISTORY :07.2005 mode added:`
42			`-- 00 - multiply by window`
43			`-- 01 - butterfly`
44			`-- 10 - restore for real FFT`
45			`-- only for Virtex2 and later`
46			`--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~`
47
48
49
50			`library IEEE;`
51			`use IEEE.std_logic_1164.all;`
52			`use IEEE.std_logic_arith.all;`
53
54			`entity FFTDPATH is`
55			`generic ( ifft: integer:=0;`
56			`width: integer :=8 ; -- word width =8...24`
57			`Wwdth: integer:=7; -- coefficient width =7...15`
58			`V2:integer`
59			`);`
60			`port (`
61			`CLK: in STD_LOGIC;`
62			`RST: in STD_LOGIC;`
63			`CE: in STD_LOGIC;`
64			`ODDC: in STD_LOGIC; --`
65			`DIV2: in STD_LOGIC; --Scaling factor`
66			`ZWR: in STD_LOGIC;`
67			`ZWI: in STD_LOGIC;`
68			`SIGNRE: in STD_LOGIC;`
69			`MODE: in STD_LOGIC_VECTOR (1 downto 0);`
70			`REDI: in STD_LOGIC_VECTOR (width downto 0);`
71			`IMDI: in STD_LOGIC_VECTOR (width downto 0);`
72			`WF: in STD_LOGIC_VECTOR (wwdth-1 downto 0);`
73			`REDO: out STD_LOGIC_VECTOR (width downto 0);`
74			`IMDO: out STD_LOGIC_VECTOR (width downto 0)`
75			`);`
76			`end FFTDPATH;`
77
78
79			`architecture FFTDPATH_s of FFTDPATH is`
80
81			`constant zeros: STD_LOGIC_VECTOR (width-wwdth downto 0):=`
82			`CONV_STD_LOGIC_VECTOR(0,width-wwdth+1);`
83			`signal ar,ai,ar3,ai3: STD_LOGIC_VECTOR (width-1 downto 0);`
84			`signal br1,bi1,br,bi,br2,bi2: STD_LOGIC_VECTOR (width-1 downto 0);`
85			`signal renorm,imnorm,br4,bi4: STD_LOGIC_VECTOR (width-1 downto 0);`
86			`signal ard,aid: STD_LOGIC_VECTOR (3 downto 0);`
87			`signal wr,wr1: STD_LOGIC_VECTOR (wwdth-1 downto 0);`
88			`signal prodrb,prodib: STD_LOGIC_VECTOR (width+wwdth downto 0);`
89			`signal prodr1,prodi1: STD_LOGIC_VECTOR (width+wwdth-2 downto wwdth-2);`
90			`signal prodr2,prodi2: STD_LOGIC_VECTOR (width+wwdth-1 downto wwdth-2);`
91			`signal prodr,prodi,prodrd,prodid: STD_LOGIC_VECTOR (width downto 0);`
92			`signal cr,ci: STD_LOGIC_VECTOR (width downto 0);`
93			`signal dr,di: STD_LOGIC_VECTOR (width+2 downto 0);`
94			`signal zwri,zwii,zwr1,zwi1,zwr2,zwi2,signrei,signre1,signre2: STD_LOGIC;`
95
96
97			`begin`
98
99			`SHIFT:process(REDI,IMDI,DIV2)`
100			`begin`
101			`if DIV2='1' then`
102			`renorm <= REDI (width downto 1);`
103			`imnorm <= IMDI (width downto 1);`
104			`else`
105			`renorm <= REDI(width-1 downto 0);`
106			`imnorm <= IMDI(width-1 downto 0);`
107			`end if;`
108			`end process;`
109
110			`RDELAY:process(CLK,RST)`
111			`begin`
112			`if RST = '1' then`
113			`wr <= (others =>'0');`
114			`wr1 <= (others =>'0');`
115			`ar <= (others =>'0');`
116			`br <= (others =>'0');`
117			`br1<= (others =>'0');`
118			`br2 <= (others =>'0');`
119			`ar3 <= (others =>'0');`
120			`br4 <= (others =>'0');`
121			`ai <= (others =>'0');`
122			`bi <= (others =>'0');`
123			`bi1<= (others =>'0');`
124			`bi2 <= (others =>'0');`
125			`ai3 <= (others =>'0');`
126			`bi4 <= (others =>'0');`
127			`elsif CLK = '1' and CLK'event then`
128			`if CE = '1' then`
129			`wr<=WF;`
130			`wr1<=wr;`
131			`br2<=br1;`
132			`bi2<=bi1;`
133			`if ODDC='0' then`
134			`ar<= renorm;`
135			`ar3<=ar;`
136			`br4<=br2;`
137			`ai<= imnorm;`
138			`ai3<=ai;`
139			`bi4<=bi2;`
140			`else`
141			`br<= renorm;`
142			`br1<=br;`
143			`bi<= imnorm;`
144			`bi1<=bi;`
145			`end if;`
146			`end if;`
147			`end if;`
148			`end process;`
149
150			`TTDELAY:process(CLK,RST)`
151			`begin`
152			`if RST='1' then`
153			`zwri<='0';`
154			`zwii<='0';`
155			`zwr1<='0';`
156			`zwi1<='0';`
157			`zwr2<='0';`
158			`zwi2<='0';`
159			`signrei<='0';`
160			`signre1<='0';`
161			`signre2<='0';`
162			`elsif CLK='1' and CLK'event then`
163			`if CE='1' then`
164			`zwri<=ZWR;`
165			`zwii<=ZWI;`
166			`zwr1<=zwri;`
167			`zwi1<=zwii;`
168			`zwr2<=zwr1;`
169			`zwi2<=zwi1;`
170			`signrei<=SIGNRE;`
171			`signre1<=signrei;`
172			`signre2<=signre1;`
173			`end if;`
174			`end if;`
175			`end process;`
176
177
178
179
180
181			`BLCK:if v2=1 generate`
182			`MPU_U: process(CLK,RST)`
183			`variable prodr,prodi:STD_LOGIC_VECTOR(width+wwdth-2 downto 0);`
184			`variable minusre,minusim:STD_LOGIC;`
185			`begin`
186			`if RST = '1' then`
187			`prodrb <= (others =>'0');`
188			`prodr2 <= (others =>'0');`
189			`prodib <= (others =>'0');`
190			`prodi2 <= (others =>'0');`
191
192			`elsif CLK = '1' and CLK'event then`
193			`if CE = '1' then`
194			`prodrb <= signed('0'& wr) * signed(ar);`
195			`prodib <= signed('0'& wr) * signed(ai);`
196
197			`prodr2<=prodrb(width+wwdth-1 downto wwdth-2);`
198			`prodi2<=prodib(width+wwdth-1 downto wwdth-2);`
199			`end if;`
200			`end if;`
201			`end process;`
202			`end generate;`
203
204			`prodr<=prodr2( width+wwdth-1 downto wwdth-1);`
205			`prodi<=prodi2( width+wwdth-1 downto wwdth-1);`
206
207			`RPRODD: process(CLK,RST)`
208			`begin`
209
210			`if RST='1' then`
211			`prodrd<=(others=>'0');`
212			`prodid<=(others=>'0');`
213			`elsif CLK='1' and CLK'event then`
214			`if CE ='1' then`
215			`if signre1='1' then`
216			`prodrd<= - signed(prodr);`
217			`prodid<= - signed(prodi);`
218			`else`
219			`prodrd<=prodr;`
220			`prodid<=prodi;`
221			`end if;`
222			`end if;`
223			`end if;`
224			`end process;`
225
226			`FFTINST:if IFFT=0 generate`
227			`ACPROD:process(RST,CLK)`
228			`begin`
229			`if RST='1' then`
230			`cr<=(others=>'0');`
231			`ci<=(others=>'0');`
232			`elsif CLK='1' and CLK'event then`
233			`if CE ='1' and ODDC='0' then`
234			`if zwi2='1' then`
235			`cr <= ar3&'0';`
236			`ci <= ai3&'0';`
237			`elsif zwr2='1' then`
238			`cr <= ai3&'0';`
239			`ci <= - signed(ar3&'0');`
240			`else`
241			`cr<= signed(prodrd)+signed(prodi);`
242			`ci<= signed(prodid)-signed(prodr);`
243			`end if;`
244			`end if;`
245			`end if;`
246			`end process;`
247			`end generate;`
248
249			`IFFTINST:if IFFT=1 generate`
250			`ACPROD:process(RST,CLK)`
251			`begin`
252			`if RST='1' then`
253			`cr<=(others=>'0');`
254			`ci<=(others=>'0');`
255			`elsif CLK='1' and CLK'event then`
256			`if CE ='1' and ODDC='0' then`
257			`if zwi2='1' then`
258			`cr <= ar3&'0';`
259			`ci <= ai3&'0';`
260			`elsif zwr2='1' then`
261			`cr <= 0- signed(ai3&'0');`
262			`ci <= ar3&'0';`
263			`else-- if signre2='1' then`
264			`-- cr<= 0- signed(prodrd)-signed(prodi);`
265			`-- ci<= 0- signed(prodid)+signed(prodr);`
266			`-- else`
267			`cr<= signed(prodrd)-signed(prodi);`
268			`ci<= signed(prodid)+signed(prodr);`
269			`-- end if;`
270			`end if;`
271			`end if;`
272			`end if;`
273			`end process;`
274
275			`end generate;`
276
277			`ABUTTERF:process(CLK,RST)`
278			`begin`
279			`if RST='1' then`
280			`dr<=(others=>'0');`
281			`di<=(others=>'0');`
282			`elsif CLK='1' and CLK'event then`
283			`if CE ='1' then`
284			`case MODE is`
285			`when "00" => dr<=prodr&"01";`
286			`di<=prodI&"01" ;`
287			`when "01" => --butterfly`
288			`if ODDC='1' then --addition with rounding`
289			`dr<=signed(br4&"01")+signed( cr(width)&cr&'1');`
290			`di<=signed(bi4&"01")+signed( ci(width)&ci&'1');`
291			`else`
292			`dr<=signed(br4&"01")-signed( cr(width)&cr&'1');`
293			`di<=signed(bi4&"01")-signed( ci(width)&ci&'1');`
294			`end if;`
295			`when others=> -- Wosstanowlenie`
296			`if ODDC='1' then --addition with rounding`
297			`dr<=signed(br4&"01")+signed( cr(width)&cr&'1');`
298			`di<=signed(bi4&"01")-signed( ci(width)&ci&'1');`
299			`else`
300			`dr<=signed(bi4&"01")+signed( ci(width)&ci&'1');`
301			`di<=signed( cr(width)&cr&'1')- signed(br4&"01");`
302			`end if;`
303			`end case ;`
304			`end if;`
305			`end if;`
306			`end process;`
307
308			`REDO<= dr(width+2 downto 2) ;`
309			`IMDO<= di(width+2 downto 2);`
310
311
312			`end FFTDPATH_s;`