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[/] [fft_fir_filter/] [trunk/] [rtl/] [ram2x_2.vhd] - Blame information for rev 2

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---------------------------------------------------------------------
----                                                             ----
----  FFT Filter IP core                                         ----
----                                                             ----
----  Authors: Anatoliy Sergienko, Volodya Lepeha                ----
----  Company: Unicore Systems http://unicore.co.ua              ----
----                                                             ----
----  Downloaded from: http://www.opencores.org                  ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2006-2010 Unicore Systems LTD                 ----
---- www.unicore.co.ua                                           ----
---- o.uzenkov@unicore.co.ua                                     ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
---- THIS SOFTWARE IS PROVIDED "AS IS"                           ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT              ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT         ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION)                 ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,              ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING                 ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,                 ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.          ----
----                                                             ----
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
entity RAM2X2 is
        generic(  iwidth : INTEGER:=16;
                width : INTEGER:=16;
                n:INTEGER:=8;     -- 6,7,8,9,10,11
                v2:INTEGER);
        port (
                CLK: in STD_LOGIC;
                RST: in STD_LOGIC;
                CE: in STD_LOGIC;
                WEI: in STD_LOGIC;          -- for input data
                WEM: in STD_LOGIC;        -- for intermediate data    
                INITOVERF:in STD_LOGIC;
                ADDRWIN: in STD_LOGIC_VECTOR (n - 1 downto 0);
                ADDRWM: in STD_LOGIC_VECTOR (n - 1 downto 0);
                ADDRR: in STD_LOGIC_VECTOR (n - 1 downto 0);
                EVEN: in STD_LOGIC;                      --0- 1th bank is read 1- 0tht bank -is read
                DIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
                DIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
                DMRE: in STD_LOGIC_VECTOR (width-1 downto 0);
                DMIM: in STD_LOGIC_VECTOR (width-1 downto 0);
                OVERF:out  STD_LOGIC;
                DORE: out STD_LOGIC_VECTOR (width-1 downto 0);
                DOIM: out STD_LOGIC_VECTOR (width-1 downto 0)
                );
end RAM2X2   ;
 
 
architecture RAM2X_2 of RAM2X2 is
 
        component RAMB16_S18_S18 is
                port (DIA    : in STD_LOGIC_VECTOR (15 downto 0);
                        DIB    : in STD_LOGIC_VECTOR (15 downto 0);
                        DIPA    : in STD_LOGIC_VECTOR (1 downto 0);
                        DIPB    : in STD_LOGIC_VECTOR (1 downto 0);
                        ENA    : in STD_ULOGIC;
                        ENB    : in STD_ULOGIC;
                        WEA    : in STD_ULOGIC;
                        WEB    : in STD_ULOGIC;
                        SSRA   : in STD_ULOGIC;
                        SSRB   : in STD_ULOGIC;
                        CLKA   : in STD_ULOGIC;
                        CLKB   : in STD_ULOGIC;
                        ADDRA  : in STD_LOGIC_VECTOR (9 downto 0);
                        ADDRB  : in STD_LOGIC_VECTOR (9 downto 0);
                        DOA    : out STD_LOGIC_VECTOR (15 downto 0);
                        DOB    : out STD_LOGIC_VECTOR (15 downto 0);
                        DOPA    : out STD_LOGIC_VECTOR (1 downto 0);
                        DOPB    : out STD_LOGIC_VECTOR (1 downto 0)
                        );
        end component ;
        signal EN : STD_LOGIC;
        signal ADDRA100,ADDRA101,ADDRB10:  STD_LOGIC_VECTOR (9 downto 0);
        signal DIREi,DIIMi:    STD_LOGIC_VECTOR (width-1 downto 0);
        Signal DIAR,DIAMR,DIB,DOA,DOBR0,DOBR1:  STD_LOGIC_VECTOR (17 downto 0);
        Signal DIAI,DIAMI,DOBI0,DOBI1:  STD_LOGIC_VECTOR (17 downto 0);
        signal  WEA0,WEA1,WEB, WEIi,OVER:STD_LOGIC;
        constant nulls:STD_LOGIC_VECTOR (17 downto 0):=(others=>'0');
 
begin
        --Writing at ADDRW address
        --      Reading at ADDRR address
 
        EN <= '1';
 
        RDI:process(CLK,RST) --wchodnoj registr
        begin
                if RST='1' then
                        WEIi<='0';
                        DIREi<=(others=>'0');
                        DIIMi<=(others=>'0');
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                WEIi<=WEI;
                                DIREi<=SXT(DIRE,width);--&nulls(width-iwidth-1 downto 0);
                                DIIMi<=SXT(DIIM,width);--&nulls(width-iwidth-1 downto 0);
                        end if;
                end if;
        end process;
 
        DIAR( width-1 downto 0)<= DIREi;
        DIAI( width-1 downto 0)<=DIIMi;
        DIAMR( width-1 downto 0)<= DMRE;
        DIAMI( width-1 downto 0)<=DMIM;
        ZEROD:    for i in  width to 17 generate
                DIAR(i)<='0';
                DIAI(i)<='0';
                DIAMR(i)<='0';
                DIAMI(i)<='0';
        end generate;
 
 
 
 
        DIB<=(others=>'0');
        WEB<='0';
 
 
 
        ADDRA100(n-1 downto 0)<=ADDRWIN(n-1 downto 0);
        ADDRA100(9 downto n)<=(others=>'0');
 
        ADDRA101(n-1 downto 0)<=ADDRWM(n-1 downto 0);
        ADDRA101(9 downto n)<=(others=>'0');
        ADDRB10(n-1 downto 0)<=ADDRR(n-1 downto 0);
        ADDRB10(9 downto n)<=(others=>'0');
 
 
        RAMD1024v2:     if        n<=10 and v2=1 generate
                ADDRB10(n-1 downto 0)<=ADDRR(n-1 downto 0);
                -- input RAM    
                RAM1024I_R:   RAMB16_S18_S18 --RE- part  
                port map (
                        CLKA => CLK,  CLKB => CLK,SSRA => RST,SSRB => RST,
                        WEA  => WEI, WEB  => WEB,ENA  => EN,ENB  => EN,
                        DIPA => DIAR(17 downto 16),
                        DIPB => DIB(17 downto 16),
                        DIA  => DIAR(15 downto 0),
                        DIB  => DIB(15 downto 0),
                        ADDRA => ADDRA100, ADDRB => ADDRB10,
                        DOPA => open,--DOA2(17 downto 16),
                        DOPB => DOBR0(17 downto 16),
                        DOA  => open,--DOA2(15 downto 0),
                        DOB  => DOBR0(15 downto 0));
 
                RAM1024I_I:   RAMB16_S18_S18
                port map (
                        CLKA => CLK,  CLKB => CLK,SSRA => RST,SSRB => RST,
                        WEA  => WEI, WEB  => WEB,ENA  => EN,ENB  => EN,
                        DIPA => DIAI(17 downto 16),
                        DIPB => DIB(17 downto 16),
                        DIA  => DIAI(15 downto 0),
                        DIB  => DIB(15 downto 0),
                        ADDRA => ADDRA100, ADDRB => ADDRB10,
                        DOPA => open,--DOA2(17 downto 16),
                        DOPB => DOBI0(17 downto 16),
                        DOA  => open,--DOA2(15 downto 0),
                        DOB  => DOBI0(15 downto 0));
 
                -- Working RAMs         
                RAM1024_R:   RAMB16_S18_S18      --Re -part
                port map (
                        CLKA => CLK,  CLKB => CLK,SSRA => RST,SSRB => RST,
                        WEA  => WEM, WEB  => WEB,ENA  => EN,ENB  => EN,
                        DIPA => DIAMR(17 downto 16),
                        DIPB => DIB(17 downto 16),
                        DIA  => DIAMR(15 downto 0),
                        DIB  => DIB(15 downto 0),
                        ADDRA => ADDRA101, ADDRB => ADDRB10,
                        DOPA => open,--DOA2(17 downto 16),
                        DOPB => DOBR1(17 downto 16),
                        DOA  => open,--DOA2(15 downto 0),
                        DOB  => DOBR1(15 downto 0));
 
                RAM1024_I:   RAMB16_S18_S18
                port map (
                        CLKA => CLK,  CLKB => CLK,SSRA => RST,SSRB => RST,
                        WEA  => WEM, WEB  => WEB,ENA  => EN,ENB  => EN,
                        DIPA => DIAMI(17 downto 16),
                        DIPB => DIB(17 downto 16),
                        DIA  => DIAMI(15 downto 0),
                        DIB  => DIB(15 downto 0),
                        ADDRA => ADDRA101, ADDRB => ADDRB10,
                        DOPA => open,--DOA2(17 downto 16),
                        DOPB => DOBI1(17 downto 16),
                        DOA  => open,--DOA2(15 downto 0),
                        DOB  => DOBI1(15 downto 0));
        end generate;
 
        TOVERFR:process(CLK,RST,DMRE,DMIM)
        begin
                OVER<=  (DIAMR( width-1) xor  DIAMR( width-2)) or (DIAMR( width-1) xor  DIAMR( width-3))
                or (DIAMI( width-1) xor  DIAMI( width-2)) or (DIAMI( width-1) xor  DIAMI( width-3));
                if RST='1' then
                        OVERF<='0';
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                if  INITOVERF='1' then
                                        OVERF<='0';
                                elsif over='1' and WEM='1' then
                                        OVERF<='1';
                                end if;
                        end if;
                end if;
        end process;
 
        DORE<=DOBR0(width-1 downto 0) when EVEN='0' else DOBR1(width-1 downto 0);
        DOIM<=DOBI0(width-1 downto 0) when EVEN='0' else DOBI1(width-1 downto 0);
 
 
end RAM2X_2;

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Subversion Repositories fft_fir_filter

[/] [fft_fir_filter/] [trunk/] [rtl/] [ram2x_2.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	unicore	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- FFT Filter IP core ----`
4			`---- ----`
5			`---- Authors: Anatoliy Sergienko, Volodya Lepeha ----`
6			`---- Company: Unicore Systems http://unicore.co.ua ----`
7			`---- ----`
8			`---- Downloaded from: http://www.opencores.org ----`
9			`---- ----`
10			`---------------------------------------------------------------------`
11			`---- ----`
12			`---- Copyright (C) 2006-2010 Unicore Systems LTD ----`
13			`---- www.unicore.co.ua ----`
14			`---- o.uzenkov@unicore.co.ua ----`
15			`---- ----`
16			`---- This source file may be used and distributed without ----`
17			`---- restriction provided that this copyright statement is not ----`
18			`---- removed from the file and that any derivative work contains ----`
19			`---- the original copyright notice and the associated disclaimer.----`
20			`---- ----`
21			`---- THIS SOFTWARE IS PROVIDED "AS IS" ----`
22			`---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----`
23			`---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----`
24			`---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----`
25			`---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----`
26			`---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----`
27			`---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
28			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----`
29			`---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----`
30			`---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----`
31			`---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----`
32			`---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----`
33			`---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
34			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----`
35			`---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----`
36			`---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----`
37			`---- ----`
38			`---------------------------------------------------------------------`
39			`library IEEE;`
40			`use IEEE.std_logic_1164.all;`
41			`use IEEE.std_logic_arith.all;`
42			`use IEEE.std_logic_unsigned.all;`
43
44			`entity RAM2X2 is`
45			`generic( iwidth : INTEGER:=16;`
46			`width : INTEGER:=16;`
47			`n:INTEGER:=8; -- 6,7,8,9,10,11`
48			`v2:INTEGER);`
49			`port (`
50			`CLK: in STD_LOGIC;`
51			`RST: in STD_LOGIC;`
52			`CE: in STD_LOGIC;`
53			`WEI: in STD_LOGIC; -- for input data`
54			`WEM: in STD_LOGIC; -- for intermediate data`
55			`INITOVERF:in STD_LOGIC;`
56			`ADDRWIN: in STD_LOGIC_VECTOR (n - 1 downto 0);`
57			`ADDRWM: in STD_LOGIC_VECTOR (n - 1 downto 0);`
58			`ADDRR: in STD_LOGIC_VECTOR (n - 1 downto 0);`
59			`EVEN: in STD_LOGIC; --0- 1th bank is read 1- 0tht bank -is read`
60			`DIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);`
61			`DIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);`
62			`DMRE: in STD_LOGIC_VECTOR (width-1 downto 0);`
63			`DMIM: in STD_LOGIC_VECTOR (width-1 downto 0);`
64			`OVERF:out STD_LOGIC;`
65			`DORE: out STD_LOGIC_VECTOR (width-1 downto 0);`
66			`DOIM: out STD_LOGIC_VECTOR (width-1 downto 0)`
67			`);`
68			`end RAM2X2 ;`
69
70
71			`architecture RAM2X_2 of RAM2X2 is`
72
73			`component RAMB16_S18_S18 is`
74			`port (DIA : in STD_LOGIC_VECTOR (15 downto 0);`
75			`DIB : in STD_LOGIC_VECTOR (15 downto 0);`
76			`DIPA : in STD_LOGIC_VECTOR (1 downto 0);`
77			`DIPB : in STD_LOGIC_VECTOR (1 downto 0);`
78			`ENA : in STD_ULOGIC;`
79			`ENB : in STD_ULOGIC;`
80			`WEA : in STD_ULOGIC;`
81			`WEB : in STD_ULOGIC;`
82			`SSRA : in STD_ULOGIC;`
83			`SSRB : in STD_ULOGIC;`
84			`CLKA : in STD_ULOGIC;`
85			`CLKB : in STD_ULOGIC;`
86			`ADDRA : in STD_LOGIC_VECTOR (9 downto 0);`
87			`ADDRB : in STD_LOGIC_VECTOR (9 downto 0);`
88			`DOA : out STD_LOGIC_VECTOR (15 downto 0);`
89			`DOB : out STD_LOGIC_VECTOR (15 downto 0);`
90			`DOPA : out STD_LOGIC_VECTOR (1 downto 0);`
91			`DOPB : out STD_LOGIC_VECTOR (1 downto 0)`
92			`);`
93			`end component ;`
94			`signal EN : STD_LOGIC;`
95			`signal ADDRA100,ADDRA101,ADDRB10: STD_LOGIC_VECTOR (9 downto 0);`
96			`signal DIREi,DIIMi: STD_LOGIC_VECTOR (width-1 downto 0);`
97			`Signal DIAR,DIAMR,DIB,DOA,DOBR0,DOBR1: STD_LOGIC_VECTOR (17 downto 0);`
98			`Signal DIAI,DIAMI,DOBI0,DOBI1: STD_LOGIC_VECTOR (17 downto 0);`
99			`signal WEA0,WEA1,WEB, WEIi,OVER:STD_LOGIC;`
100			`constant nulls:STD_LOGIC_VECTOR (17 downto 0):=(others=>'0');`
101
102			`begin`
103			`--Writing at ADDRW address`
104			`-- Reading at ADDRR address`
105
106			`EN <= '1';`
107
108			`RDI:process(CLK,RST) --wchodnoj registr`
109			`begin`
110			`if RST='1' then`
111			`WEIi<='0';`
112			`DIREi<=(others=>'0');`
113			`DIIMi<=(others=>'0');`
114			`elsif CLK='1' and CLK'event then`
115			`if CE='1' then`
116			`WEIi<=WEI;`
117			`DIREi<=SXT(DIRE,width);--&nulls(width-iwidth-1 downto 0);`
118			`DIIMi<=SXT(DIIM,width);--&nulls(width-iwidth-1 downto 0);`
119			`end if;`
120			`end if;`
121			`end process;`
122
123			`DIAR( width-1 downto 0)<= DIREi;`
124			`DIAI( width-1 downto 0)<=DIIMi;`
125			`DIAMR( width-1 downto 0)<= DMRE;`
126			`DIAMI( width-1 downto 0)<=DMIM;`
127			`ZEROD: for i in width to 17 generate`
128			`DIAR(i)<='0';`
129			`DIAI(i)<='0';`
130			`DIAMR(i)<='0';`
131			`DIAMI(i)<='0';`
132			`end generate;`
133
134
135
136
137			`DIB<=(others=>'0');`
138			`WEB<='0';`
139
140
141
142			`ADDRA100(n-1 downto 0)<=ADDRWIN(n-1 downto 0);`
143			`ADDRA100(9 downto n)<=(others=>'0');`
144
145			`ADDRA101(n-1 downto 0)<=ADDRWM(n-1 downto 0);`
146			`ADDRA101(9 downto n)<=(others=>'0');`
147			`ADDRB10(n-1 downto 0)<=ADDRR(n-1 downto 0);`
148			`ADDRB10(9 downto n)<=(others=>'0');`
149
150
151			`RAMD1024v2: if n<=10 and v2=1 generate`
152			`ADDRB10(n-1 downto 0)<=ADDRR(n-1 downto 0);`
153			`-- input RAM`
154			`RAM1024I_R: RAMB16_S18_S18 --RE- part`
155			`port map (`
156			`CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RST,`
157			`WEA => WEI, WEB => WEB,ENA => EN,ENB => EN,`
158			`DIPA => DIAR(17 downto 16),`
159			`DIPB => DIB(17 downto 16),`
160			`DIA => DIAR(15 downto 0),`
161			`DIB => DIB(15 downto 0),`
162			`ADDRA => ADDRA100, ADDRB => ADDRB10,`
163			`DOPA => open,--DOA2(17 downto 16),`
164			`DOPB => DOBR0(17 downto 16),`
165			`DOA => open,--DOA2(15 downto 0),`
166			`DOB => DOBR0(15 downto 0));`
167
168			`RAM1024I_I: RAMB16_S18_S18`
169			`port map (`
170			`CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RST,`
171			`WEA => WEI, WEB => WEB,ENA => EN,ENB => EN,`
172			`DIPA => DIAI(17 downto 16),`
173			`DIPB => DIB(17 downto 16),`
174			`DIA => DIAI(15 downto 0),`
175			`DIB => DIB(15 downto 0),`
176			`ADDRA => ADDRA100, ADDRB => ADDRB10,`
177			`DOPA => open,--DOA2(17 downto 16),`
178			`DOPB => DOBI0(17 downto 16),`
179			`DOA => open,--DOA2(15 downto 0),`
180			`DOB => DOBI0(15 downto 0));`
181
182			`-- Working RAMs`
183			`RAM1024_R: RAMB16_S18_S18 --Re -part`
184			`port map (`
185			`CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RST,`
186			`WEA => WEM, WEB => WEB,ENA => EN,ENB => EN,`
187			`DIPA => DIAMR(17 downto 16),`
188			`DIPB => DIB(17 downto 16),`
189			`DIA => DIAMR(15 downto 0),`
190			`DIB => DIB(15 downto 0),`
191			`ADDRA => ADDRA101, ADDRB => ADDRB10,`
192			`DOPA => open,--DOA2(17 downto 16),`
193			`DOPB => DOBR1(17 downto 16),`
194			`DOA => open,--DOA2(15 downto 0),`
195			`DOB => DOBR1(15 downto 0));`
196
197			`RAM1024_I: RAMB16_S18_S18`
198			`port map (`
199			`CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RST,`
200			`WEA => WEM, WEB => WEB,ENA => EN,ENB => EN,`
201			`DIPA => DIAMI(17 downto 16),`
202			`DIPB => DIB(17 downto 16),`
203			`DIA => DIAMI(15 downto 0),`
204			`DIB => DIB(15 downto 0),`
205			`ADDRA => ADDRA101, ADDRB => ADDRB10,`
206			`DOPA => open,--DOA2(17 downto 16),`
207			`DOPB => DOBI1(17 downto 16),`
208			`DOA => open,--DOA2(15 downto 0),`
209			`DOB => DOBI1(15 downto 0));`
210			`end generate;`
211
212			`TOVERFR:process(CLK,RST,DMRE,DMIM)`
213			`begin`
214			`OVER<= (DIAMR( width-1) xor DIAMR( width-2)) or (DIAMR( width-1) xor DIAMR( width-3))`
215			`or (DIAMI( width-1) xor DIAMI( width-2)) or (DIAMI( width-1) xor DIAMI( width-3));`
216			`if RST='1' then`
217			`OVERF<='0';`
218			`elsif CLK='1' and CLK'event then`
219			`if CE='1' then`
220			`if INITOVERF='1' then`
221			`OVERF<='0';`
222			`elsif over='1' and WEM='1' then`
223			`OVERF<='1';`
224			`end if;`
225			`end if;`
226			`end if;`
227			`end process;`
228
229			`DORE<=DOBR0(width-1 downto 0) when EVEN='0' else DOBR1(width-1 downto 0);`
230			`DOIM<=DOBI0(width-1 downto 0) when EVEN='0' else DOBI1(width-1 downto 0);`
231
232
233			`end RAM2X_2;`