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Subversion Repositories fixed_point_arithmetic_parameterized

[/] [fixed_point_arithmetic_parameterized/] [trunk/] [testfixtures/] [qdiv_tf.v] - Blame information for rev 3

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`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   19:41:28 08/24/2011
// Design Name:   divider
// Module Name:   C:/Documents and Settings/samskalicky/Desktop/PLE/divider_tf.v
// Project Name:  PLE
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: divider
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
 
module qdiv_tf;
//Parameterized values
        parameter Q = 15;
        parameter N = 32;
 
        // Inputs
        reg [N-1:0] dividend;
        reg [N-1:0] divisor;
        reg start;
        reg clk;
        real top;
        real bottom;
 
        // Outputs
        wire [N-1:0] quotient;
        wire done;
        real result;
 
 
        // Instantiate the Unit Under Test (UUT)
        //module  Params  Name  Signals
        qdiv #(Q,N)     uut (dividend, divisor, start, clk, quotient,done);
 
        initial begin
                // Initialize Inputs
                top = -32.5;
                bottom = 2.25;
 
                conv_rational(top,dividend);
                conv_rational(bottom,divisor);
 
                start = 1;
                clk = 0;
 
                // Wait 100 ns for global reset to finish
                #100;
 
                // Add stimulus here
                start = 0;
 
                #366;
                conv_fixed(quotient,result);
                $display("%f / %f = %f",top,bottom,result);
        end
 
        always
        begin
                #5 clk = ~clk;
        end
 
        /*
         *      Task to convert from rational to fixed point
         */
         task conv_rational;
         input real num;
         output [N-1:0] fixed;
 
         integer i;
         real tmp;
 
         begin
                 tmp = num;
 
                 //set sign
                 if(tmp < 0) begin
                 //if its negative, set the sign bit and make the temporary number position by multiplying by -1
                        fixed[N-1] = 1;
                        tmp = tmp * -1;
                 end
                 else begin
                 //if its positive, the sign bit is zero
                        fixed[N-1] = 0;
                 end
 
                 //check that the number isnt too large
                 if(tmp > (1 << N-Q-1)) begin
                        $display("Error!!! rational number %f is larger than %d whole bits can represent!",num,N-Q-1);
                 end
 
                 //set whole part
                 for(i=0; i<N-Q-1; i=i+1) begin
                        if(tmp >= (1 << N-Q-2-i)) begin
                        //if its greater or equal, subtract out this power of 2 and put a one at this position
                                fixed[N-2-i] = 1;
                                tmp = tmp - (1 << N-Q-2-i);
                        end
                        else begin
                        //if its less, put a zero at this position
                                fixed[N-2-i] = 0;
                        end
                 end
 
                 //set fractional part
                 for(i=1; i<=Q; i=i+1) begin
                        if(tmp >= 1.0/(1 << i)) begin
                        //if its greater or equal, subtract out this power of 2 and put a one at this position
                                fixed[Q-i] = 1;
                                tmp = tmp - 1.0/(1 << i);
                        end
                        else begin
                        //if its less, put a zero at this position
                                fixed[Q-i] = 0;
                        end
                 end
 
                 //check that the number isnt too small (loss of precision)
                 if(tmp > 0) begin
                        $display("Error!!! LOSS OF PRECISION converting rational number %f's fractional part using %d bits!",num,Q);
                 end
         end
         endtask;
 
         /*
         *      Task to convert from fixed point to rational
         */
         task conv_fixed;
         input [N-1:0] fixed;
         output real num;
 
         integer i;
 
         begin
                 num = 0;
 
                 //set whole part
                 for(i=0; i<N-Q-1; i=i+1) begin
                        if(fixed[N-2-i] == 1) begin
                        //if theres a one at this position, add the power of 2 to the rational number
                                num = num + (1 << N-Q-2-i);
                        end
                 end
 
                 //set fractional part
                 for(i=1; i<=Q; i=i+1) begin
                        if(fixed[Q-i] == 1) begin
                        //if theres a one at this position, add the power of 2 to the rational number
                                num = num + 1.0/(1 << i);
                        end
                 end
 
                 //set sign
                 if(fixed[N-1] == 1) begin
                 //if the sign bit is set, negate the rational number
                        num = num * -1;
                 end
         end
         endtask;
 
endmodule

Line No.	Rev	Author	Line
1	3	samis13	`timescale 1ns / 1ps
2
3			`////////////////////////////////////////////////////////////////////////////////`
4			`// Company:`
5			`// Engineer:`
6			`//`
7			`// Create Date: 19:41:28 08/24/2011`
8			`// Design Name: divider`
9			`// Module Name: C:/Documents and Settings/samskalicky/Desktop/PLE/divider_tf.v`
10			`// Project Name: PLE`
11			`// Target Device:`
12			`// Tool versions:`
13			`// Description:`
14			`//`
15			`// Verilog Test Fixture created by ISE for module: divider`
16			`//`
17			`// Dependencies:`
18			`//`
19			`// Revision:`
20			`// Revision 0.01 - File Created`
21			`// Additional Comments:`
22			`//`
23			`////////////////////////////////////////////////////////////////////////////////`
24
25	2	samis13	`module qdiv_tf;`
26	3	samis13	`//Parameterized values`
27			`parameter Q = 15;`
28			`parameter N = 32;`
29
30			`// Inputs`
31			`reg [N-1:0] dividend;`
32			`reg [N-1:0] divisor;`
33			`reg start;`
34	2	samis13	`reg clk;`
35	3	samis13	`real top;`
36			`real bottom;`
37
38			`// Outputs`
39			`wire [N-1:0] quotient;`
40			`wire done;`
41			`real result;`
42
43
44			`// Instantiate the Unit Under Test (UUT)`
45			`//module Params Name Signals`
46			`qdiv #(Q,N) uut (dividend, divisor, start, clk, quotient,done);`
47
48			`initial begin`
49	2	samis13	`// Initialize Inputs`
50	3	samis13	`top = -32.5;`
51			`bottom = 2.25;`
52	2	samis13
53	3	samis13	`conv_rational(top,dividend);`
54			`conv_rational(bottom,divisor);`
55
56			`start = 1;`
57			`clk = 0;`
58
59			`// Wait 100 ns for global reset to finish`
60			`#100;`
61
62			`// Add stimulus here`
63	2	samis13	`start = 0;`
64	3	samis13
65			`#366;`
66			`conv_fixed(quotient,result);`
67			`$display("%f / %f = %f",top,bottom,result);`
68			`end`
69
70			`always`
71			`begin`
72			`#5 clk = ~clk;`
73	2	samis13	`end`
74	3	samis13
75			`/*`
76			`* Task to convert from rational to fixed point`
77			`*/`
78			`task conv_rational;`
79			`input real num;`
80			`output [N-1:0] fixed;`
81
82			`integer i;`
83			`real tmp;`
84
85			`begin`
86			`tmp = num;`
87
88			`//set sign`
89			`if(tmp < 0) begin`
90			`//if its negative, set the sign bit and make the temporary number position by multiplying by -1`
91			`fixed[N-1] = 1;`
92			`tmp = tmp * -1;`
93			`end`
94			`else begin`
95			`//if its positive, the sign bit is zero`
96			`fixed[N-1] = 0;`
97			`end`
98
99			`//check that the number isnt too large`
100			`if(tmp > (1 << N-Q-1)) begin`
101			`$display("Error!!! rational number %f is larger than %d whole bits can represent!",num,N-Q-1);`
102			`end`
103
104			`//set whole part`
105			`for(i=0; i<N-Q-1; i=i+1) begin`
106			`if(tmp >= (1 << N-Q-2-i)) begin`
107			`//if its greater or equal, subtract out this power of 2 and put a one at this position`
108			`fixed[N-2-i] = 1;`
109			`tmp = tmp - (1 << N-Q-2-i);`
110			`end`
111			`else begin`
112			`//if its less, put a zero at this position`
113			`fixed[N-2-i] = 0;`
114			`end`
115			`end`
116
117			`//set fractional part`
118			`for(i=1; i<=Q; i=i+1) begin`
119			`if(tmp >= 1.0/(1 << i)) begin`
120			`//if its greater or equal, subtract out this power of 2 and put a one at this position`
121			`fixed[Q-i] = 1;`
122			`tmp = tmp - 1.0/(1 << i);`
123			`end`
124			`else begin`
125			`//if its less, put a zero at this position`
126			`fixed[Q-i] = 0;`
127			`end`
128			`end`
129
130			`//check that the number isnt too small (loss of precision)`
131			`if(tmp > 0) begin`
132			`$display("Error!!! LOSS OF PRECISION converting rational number %f's fractional part using %d bits!",num,Q);`
133			`end`
134			`end`
135			`endtask;`
136
137			`/*`
138			`* Task to convert from fixed point to rational`
139			`*/`
140			`task conv_fixed;`
141			`input [N-1:0] fixed;`
142			`output real num;`
143
144			`integer i;`
145
146			`begin`
147			`num = 0;`
148
149			`//set whole part`
150			`for(i=0; i<N-Q-1; i=i+1) begin`
151			`if(fixed[N-2-i] == 1) begin`
152			`//if theres a one at this position, add the power of 2 to the rational number`
153			`num = num + (1 << N-Q-2-i);`
154			`end`
155			`end`
156
157			`//set fractional part`
158			`for(i=1; i<=Q; i=i+1) begin`
159			`if(fixed[Q-i] == 1) begin`
160			`//if theres a one at this position, add the power of 2 to the rational number`
161			`num = num + 1.0/(1 << i);`
162			`end`
163			`end`
164
165			`//set sign`
166			`if(fixed[N-1] == 1) begin`
167			`//if the sign bit is set, negate the rational number`
168			`num = num * -1;`
169			`end`
170			`end`
171			`endtask;`
172
173			`endmodule`

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Subversion Repositories fixed_point_arithmetic_parameterized

[/] [fixed_point_arithmetic_parameterized/] [trunk/] [testfixtures/] [qdiv_tf.v] - Blame information for rev 3