OpenCores
URL https://opencores.org/ocsvn/floating_point_adder_subtractor/floating_point_adder_subtractor/trunk

Subversion Repositories floating_point_adder_subtractor

[/] [floating_point_adder_subtractor/] [web_uploads/] [addsub.vhd] - Blame information for rev 6

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 root
library ieee;
2
use ieee.std_logic_1164.all;
3
use ieee.std_logic_arith.all;
4
use ieee.std_logic_unsigned.all;
5
 
6
entity addsub is
7
port
8
        ( input_a,input_b : in std_logic_vector(32 downto 0);
9
          msb_ab : in std_logic_vector(1 downto 0);
10
          clk,reset,finish_shift,add_sub : in std_logic;
11
          finish_addsub : out std_logic;
12
      output_result : out std_logic_vector(33 downto 0)
13
        );      -- input_a larger after swap, inpu_b shifted according to 
14
end addsub;
15
 
16
architecture addsub of addsub is
17
begin
18
process(clk,input_a,input_b,clk,reset,finish_shift,add_sub,msb_ab)
19
variable man_a,man_b,temp : std_logic_vector(24 downto 0);
20
variable exp_a : std_logic_vector(7 downto 0);
21
variable msb_a,msb_b : std_logic;
22
begin
23
 
24
if (reset='1' or finish_shift='0') then
25
        output_result<="0000000000000000000000000000000000";
26
        finish_addsub<='0';
27
 
28
elsif( reset='0' and finish_shift='1' and input_a="0000000000000000000000000000000000" and
29
     input_b="0000000000000000000000000000000000" ) then
30
 
31
        output_result<="0000000000000000000000000000000000";
32
        finish_addsub<='1';
33
elsif( reset='0' and finish_shift='1') then
34
 
35
        exp_a:=input_a(31 downto 24);
36
        man_a:='0' & input_a(23 downto 0);
37
        man_b:='0' & input_b(23 downto 0);
38
        msb_a:=input_a(32);
39
        msb_b:=input_b(32);
40
 
41
        if (add_sub='0') then  -- subtraction
42
          if( msb_ab="00" or msb_ab="11")then       --if both same sign then subtract
43
          temp:= man_a - man_b;                                     --mantissa
44
          elsif( msb_ab="01" or msb_ab="10") then   --if un equal sign, add mantissa
45
          temp:= man_a + man_b;
46
          end if;
47
        end if;
48
 
49
        if (add_sub='1') then
50
          if( msb_ab="00" or msb_ab="11")then
51
          temp:= man_a + man_b;
52
          elsif( msb_ab="01" or msb_ab="10") then
53
          temp:= man_a - man_b;
54
          end if;
55
        end if;
56
 
57
output_result <= msb_a & exp_a & temp;
58
finish_addsub <= '1';
59
end if;
60
end process;
61
end addsub;
62
 
63
 
64
 
65
 
66
 
67
 
68
 
69
 
70
 
71
 
72
 
73
 
74
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.