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[/] [floating_point_adder_subtractor/] [web_uploads/] [shift.vhd] - Blame information for rev 6

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1 6 root
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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-- shift input_b 
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entity shift is
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port (
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                input : in std_logic_vector (32 downto 0);
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                diff_exp : in std_logic_vector (7 downto 0);
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                clk,finish_swap : in std_logic;
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                output_b : out std_logic_vector (32 downto 0);
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                finish_shift : out std_logic :='0'
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          );
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end shift;
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architecture shift of shift is
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begin
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process(input,clk,diff_exp,finish_swap)
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variable diff_exp_var : std_logic_vector(7 downto 0);
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variable mantissa : std_logic_vector (23 downto 0);
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begin
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  if (finish_swap='0') then
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        output_b <= "000000000000000000000000000000000";
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        finish_shift <= '0';
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  else
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        diff_exp_var := diff_exp ;
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        mantissa := input(23 downto 0);
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          if (diff_exp > "00000000") then
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             for i in 1 to 10 loop
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                if (diff_exp_var > "00000000") then
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                mantissa(22 downto 0):=mantissa(23 downto 1);
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                mantissa(23):='0';
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                diff_exp_var:=diff_exp_var - 1;
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                end if;
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             end loop;
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        end if;
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  finish_shift <= '1';
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  output_b <= input(32 downto 24) & mantissa(23 downto 0);
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  end if;
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end process;
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end shift;
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