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-------------------------------------------------------------------------------

--| @file vga.vhd

--| @brief      Text Mode Video Controller VHDL Module and VT100

--|             Terminal Emulator

--| @author     Javier Valcarce García

--| @author     Richard James Howe (vt100, vt100_tb, atoi, color attributes)

--| @copyright  Copyright 2007 Javier Valcarce García, 2017, 2019 Richard James Howe

--| @license    LGPL version 3

--| @email      javier.valcarce@gmail.com

--| @note       (Modifications and repackaging by Richard James Howe)

--|

--| This is a modified version of the text terminal available at

--| <https://opencores.org/project,interface_vga80x40>. Additions include per

--| character attribute information (color, bold, reverse video, blink text)

--| and a VT100 terminal interface.

--|

--| See also <http://www.javiervalcarce.eu/html/vhdl-vga80x40-en.html>.

--|

-------------------------------------------------------------------------------

----- VGA Package -------------------------------------------------------------

library ieee, work;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.util.common_generics;

package vga_pkg is

        type vga_physical_interface is record

                red:   std_ulogic_vector(2 downto 0);

                green: std_ulogic_vector(2 downto 0);

                blue:  std_ulogic_vector(1 downto 0);

                hsync: std_ulogic;

                vsync: std_ulogic;

        end record;

        type vga_control_registers_we_interface is record

                crx: std_ulogic; -- Write enable for cursor X position register

                cry: std_ulogic; -- Write enable for VGA control register

                ctl: std_ulogic; -- Write enable for cursor Y position register

        end record;

        type vga_control_registers_interface is record

                crx:    std_ulogic_vector(6 downto 0); -- Cursor position X

                cry:    std_ulogic_vector(5 downto 0); -- Cursor position Y

                ctl:    std_ulogic_vector(4 downto 0); -- Control register

        end record;

        constant vga_control_registers_initialize: vga_control_registers_interface := (

                        cry => (others => '0'),

                        crx => (others => '0'),

                        ctl => (others => '0'));

        constant vga_control_registers_we_initialize: vga_control_registers_we_interface := (

                        cry => '0',

                        crx => '0',

                        ctl => '0');

        component vga_top is

        generic(g: common_generics);

        port(

                clk:         in  std_ulogic;

                clk25MHz:    in  std_ulogic;

                rst:         in  std_ulogic;

                -- VGA Text buffer interface

                vga_we_ram:  in  std_ulogic; -- Write enable RAM

                vga_din:     in  std_ulogic_vector(15 downto 0);

                vga_addr:    in  std_ulogic_vector(12 downto 0);

                base:        in  std_ulogic_vector(12 downto 0);

                -- VGA control registers

                i_font_sel:       in std_ulogic_vector(0 downto 0);

                i_vga_control_we: in vga_control_registers_we_interface;

                i_vga_control:    in vga_control_registers_interface;

                o_vga:    out vga_physical_interface);

        end component;

        component vga_core is

        generic(g: common_generics);

        port (

                rst:       in  std_ulogic;

                clk25MHz:  in  std_ulogic;

                text_a:    out std_ulogic_vector(11 downto 0); -- text buffer

                text_d:    in  std_ulogic_vector(15 downto 0);

                font_a:    out std_ulogic_vector(12 downto 0); -- font buffer

                font_d:    in  std_ulogic_vector( 7 downto 0);

                font_sel:  in  std_ulogic_vector(0 downto 0);

                 --

                ocrx:      in  std_ulogic_vector(6 downto 0);

                ocry:      in  std_ulogic_vector(5 downto 0);

                octl:      in  std_ulogic_vector(4 downto 0);

                --

                o_vga: out vga_physical_interface);

        end component;

        component losr is

        generic (g: common_generics; N: positive := 4);

        port

        (

                rst:  in  std_ulogic;

                clk:  in  std_ulogic;

                load: in  std_ulogic;

                ce:   in  std_ulogic;

                do:   out std_ulogic := '0';

                di:   in  std_ulogic_vector(N - 1 downto 0));

        end component;

        component ctrm is

        generic (g: common_generics; M: positive := 8);

        port (

                rst: in  std_ulogic; -- asynchronous rst

                clk: in  std_ulogic;

                ce:  in  std_ulogic; -- enable counting

                rs:  in  std_ulogic; -- synchronous rst

                do:  out integer range (M-1) downto 0 := 0);

        end component;

        component vt100 is

        generic (g: common_generics);

        port(

                clk:        in  std_ulogic;

                clk25MHz:   in  std_ulogic;

                rst:        in  std_ulogic;

                we:         in  std_ulogic;

                char:       in  std_ulogic_vector(7 downto 0);

                busy:       out std_ulogic;

                o_vga:      out vga_physical_interface);

        end component;

        -- VGA test bench, not-synthesizeable

        component vt100_tb is

                generic(g: common_generics);

        end component;

        component atoi is

                generic(g: common_generics; N: positive := 16);

                port(

                        clk:    in  std_ulogic;

                        rst:    in  std_ulogic;

                        we:     in  std_ulogic;

                        init:   in  std_ulogic;

                        char:   in  std_ulogic_vector(7 downto 0);

                        char_o: out std_ulogic_vector(7 downto 0);

                        done_o: out std_ulogic;

                        -- ready:  out std_ulogic;

                        n_o:    out unsigned(N - 1 downto 0));

        end component;

end package;

----- VGA Package -------------------------------------------------------------

----- VGA Test Bench ----------------------------------------------------------

library ieee, work;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.math_real.all;

use work.vga_pkg.all;

use work.util.all;

entity vt100_tb is

        generic(g: common_generics);

end entity;

architecture behav of vt100_tb is

        constant clock_period: time := 1000 ms / g.clock_frequency;

        signal clk, rst: std_ulogic := '0';

        signal stop:     std_ulogic := '0';

        signal clk25MHz, rst25MHz: std_ulogic := '0';

        signal char:     std_ulogic_vector(7 downto 0);

        signal we:       std_ulogic := '0';

        signal busy:     std_ulogic := '0';

        signal physical: vga_physical_interface;

        -- NB. 'string' range is (1 to X), not (X-1 downto 0)

        -- HT = Horizontal Tab

        -- LF = Line Feed

        -- CR = Carriage Return

        -- ESC = Escape

        constant CSI:   string := ESC & "[";

        constant RESET: string := CSI & "0m";

        constant RED:   string := CSI & "31m";

        constant GREEN: string := CSI & "32m";

        constant NL:    string := CR & LF;

        constant test_string: string := "Hello!" & HT & "World!" & RED & NL & "How are you?" & RESET & NL ;

        shared variable test_vector: ulogic_string(test_string'range) := to_std_ulogic_vector(test_string);

        shared variable index: integer := 1; -- starts at '1' due to string range

        constant g_cs25MHz: common_generics := (clock_frequency => 25_000_000, asynchronous_reset => g.asynchronous_reset, delay => g.delay);

begin

        cs: entity work.clock_source_tb

                generic map(g => g, hold_rst => 2)

                port map(stop => stop, clk => clk, rst => rst);

        cs25MHz: entity work.clock_source_tb

                generic map(g => g_cs25MHz, hold_rst => 2)

                port map(stop => stop, clk => clk25MHz, rst => rst25MHz);

        uut: work.vga_pkg.vt100

        generic map(g => g)

        port map(

                clk      => clk,

                clk25MHz => clk25MHz,

                rst      => rst,

                we       => we,

                char     => char,

                busy     => busy,

                o_vga    => physical);

        stimulus_process: process

        begin

                char <= test_vector(index);

                we <= '0';

                wait for clock_period * 20;

                for i in test_vector'range loop

                        we <= '1';

                        char <= test_vector(index);

                        wait for clock_period;

                        we <= '0';

                        wait for clock_period;

                        while busy = '1' loop

                                wait until busy = '0';

                                wait for clock_period;

                        end loop;

                        -- wait for clock_period * 20;

                        -- wait until busy = '0';

                        -- report integer'image(index);

                        if index < (test_vector'high - 1) then

                                index := index + 1;

                        else

                                index := 1;

                        end if;

                end loop;

                stop <= '1';

                wait;

        end process;

end architecture;

----- VGA Test Bench ----------------------------------------------------------

----- ATOI --------------------------------------------------------------------

-- The purpose of this module is to read in numeric characters ('0' through

-- '9') and convert the string into a binary number ('n_o'). On the first non-

-- numeric character the module stops and outputs that non-numeric character

-- as well as the converted number string. The module waits in the FINISHED

-- state until the module is reset by an external signal ('init').

--

-- The module is named after the C function, 'atoi', for converting a string

-- into an integer.

--

library ieee,work;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.vga_pkg.all;

use work.util.common_generics;

entity atoi is

        generic(g: common_generics; N: positive := 16);

        port(

                clk:    in  std_ulogic;

                rst:    in  std_ulogic;

                we:     in  std_ulogic;

                init:   in  std_ulogic;

                char:   in  std_ulogic_vector(7 downto 0);

                char_o: out std_ulogic_vector(7 downto 0);

                done_o: out std_ulogic;

                -- ready:  out std_ulogic;

                n_o:    out unsigned(N - 1 downto 0));

end entity;

architecture rlt of atoi is

        type state_type is (RESET, WAITING, COMMAND, ACCUMULATE, WRITE, FINISHED);

        signal state_c, state_n: state_type   := RESET;

        signal c_c, c_n: unsigned(char'range) := (others => '0');

        signal n_c, n_n: unsigned(n_o'range)  := (others => '0');

        signal f_c, f_n: boolean              := true;

begin

        char_o <= std_ulogic_vector(c_c);

        n_o    <= n_c;

        -- ready  <= '1' when state_c = WAITING else '0';

        process(clk, rst)

                variable akk: unsigned((2 * N) - 1 downto 0) := (others => '0');

        begin

                if rst = '1' and g.asynchronous_reset then

                        state_n   <= RESET;

                elsif rising_edge(clk) then

                        if rst = '1' and not g.asynchronous_reset then

                                state_n <= RESET;

                        else

                                state_c <= state_n;

                                c_c     <= c_n;

                                n_c     <= n_n;

                                f_c     <= f_n;

                                done_o  <= '0';

                                if state_c = RESET then

                                        c_n     <= (others => '0');

                                        n_n     <= (others => '0');

                                        f_n     <= true;

                                        state_n <= WAITING;

                                elsif state_c = WAITING then

                                        if we = '1' then

                                                c_n     <= unsigned(char);

                                                state_n <= COMMAND;

                                        end if;

                                elsif state_c = COMMAND then

                                        state_n <= ACCUMULATE;

                                        case c_c is

                                        when x"30"  =>

                                        when x"31"  =>

                                        when x"32"  =>

                                        when x"33"  =>

                                        when x"34"  =>

                                        when x"35"  =>

                                        when x"36"  =>

                                        when x"37"  =>

                                        when x"38"  =>

                                        when x"39"  =>

                                        when others =>

                                                state_n <= WRITE;

                                        end case;

                                elsif state_c = ACCUMULATE then

                                        if f_c then

                                                f_n <= false;

                                                n_n <= n_c + (c_c - x"30");

                                        else

                                                akk := n_c * to_unsigned(10, N);

                                                n_n <= akk(N - 1 downto 0) + (c_c - x"30");

                                        end if;

                                        state_n <= WAITING;

                                elsif state_c = WRITE then

                                        done_o  <= '1';

                                        state_n <= FINISHED;

                                elsif state_c = FINISHED then

                                        null; -- wait for a reset

                                else

                                        state_n <= RESET;

                                        report "Invalid State" severity failure;

                                end if;

                                if init = '1' then

                                        assert state_c = FINISHED report "Lost Conversion" severity error;

                                        state_n <= RESET;

                                end if;

                        end if;

                end if;

        end process;

end architecture;

----- ATOI --------------------------------------------------------------------

----- VT100 Terminal Emulator -------------------------------------------------

-- This module contains the VGA module and wraps it in a terminal emulator,

-- based on the VT100 <https://en.wikipedia.org/wiki/VT100>, it only implements

-- a subset of the commands supplied by the VT100. This simplifies the usage

-- of the VGA text mode display, other VHDL components only have to write bytes

-- and do not have to worry about cursor position or implementing new lines,

-- tabs, and other very basic features.

--

-- The interface is designed to act like a UART, simply write a byte to it

-- and so long as the interface is not busy, it will be written to the screen

-- (or interpreter as part of a command sequence).

library ieee, work;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.vga_pkg.all;

use work.util.common_generics;

entity vt100 is

        generic(g: common_generics);

        port(

                clk:        in  std_ulogic;

                clk25MHz:   in  std_ulogic;

                rst:        in  std_ulogic;

                we:         in  std_ulogic;

                char:       in  std_ulogic_vector(7 downto 0);

                busy:       out std_ulogic;

                o_vga:      out vga_physical_interface);

end entity;

-- A better way of structuring this would be to process numbers in parallel

-- with different components, one processing potential attributes, one holding

-- one to two numbers - the results are then used. This would deal with runs

-- of attributes, which is allowed.

architecture rtl of vt100 is

        constant width:  positive := 80;

        constant height: positive := 40;

        constant number: positive := 8;

        type state_type is (RESET, ACCEPT, NORMAL, WRAP, LIMIT, CSI, COMMAND,

        NUMBER1, NUMBER2, COMMAND1, COMMAND2, WRITE, ERASING, ATTRIB, ADVANCE);

        signal state_c, state_n: state_type := RESET;

        constant tab:          unsigned(char'range) := x"09";

        constant backspace:    unsigned(char'range) := x"08";

        constant ascii_bell:   unsigned(char'range) := x"07";

        constant lf:           unsigned(char'range) := x"0a";

        constant cr:           unsigned(char'range) := x"0d";

        constant esc:          unsigned(char'range) := x"1b";

        constant blank:        unsigned(char'range) := x"20";

        constant asterisk:     unsigned(char'range) := x"2A";

        constant ascii_7:      unsigned(char'range) := x"37"; -- '7'

        constant ascii_8:      unsigned(char'range) := x"38"; -- '8'

        constant lsqb:         unsigned(char'range) := x"5b"; -- '['

        constant ascii_c:      unsigned(char'range) := x"63"; -- 'c'

        constant attr_default: unsigned(7 downto 0) := "00111000";

        constant ctl_default:  unsigned(4 downto 0) := "01111";

        signal addr:           std_ulogic_vector(12 downto 0) := (others => '0');

        signal data_we:        std_ulogic                     := '0';

        signal x:              std_ulogic_vector(6 downto 0)  := (others => '0');

        signal y:              std_ulogic_vector(5 downto 0)  := (others => '0');

        signal cursor_we:      std_ulogic                     := '0';

        signal x_n, x_c:       unsigned(x'range)    := (others => '0');

        signal y_n, y_c:       unsigned(y'range)    := (others => '0');

        signal c_n, c_c:       unsigned(char'range) := (others => '0');

        signal attr_c, attr_n: unsigned(attr_default'range) := attr_default;

        signal ctl_c, ctl_n:   unsigned(ctl_default'range)  := ctl_default;

        signal n1_n, n1_c:     unsigned(7 downto 0) := (others => '0');

        signal n2_n, n2_c:     unsigned(6 downto 0) := (others => '0');

        signal conceal_n, conceal_c: boolean := false;

        signal x_minus_one:         unsigned(x'range) := (others => '0');

        signal x_minus_one_limited: unsigned(x'range) := (others => '0');

        signal x_underflow:         boolean           := false;

        signal x_plus_one:          unsigned(x'range) := (others => '0');

        signal x_plus_one_limited:  unsigned(x'range) := (others => '0');

        signal x_overflow:          boolean           := false;

        signal y_minus_one:         unsigned(y'range) := (others => '0');

        signal y_minus_one_limited: unsigned(y'range) := (others => '0');

        signal y_underflow:         boolean           := false;

        signal y_plus_one:          unsigned(y'range) := (others => '0');

        signal y_plus_one_limited:  unsigned(y'range) := (others => '0');

        signal y_overflow:          boolean           := false;

        signal count_c, count_n:    unsigned(addr'range) := (others => '0');

        signal limit_c, limit_n:    unsigned(addr'high - 3 downto 0) := (others => '0');

        signal akk_done_o:  std_ulogic := '0';

        -- signal akk_ready_o: std_ulogic := '0';

        signal akk_init:    std_ulogic := '0';

        signal n_o:         unsigned(number - 1 downto 0) := (others => '0');

        signal akk_char_o:  std_ulogic_vector(char'range) := (others => '0');

        signal font_sel_c, font_sel_n: std_ulogic_vector(0 downto 0) := (others => '0');

        signal saved_x_n, saved_x_c:       unsigned(x'range)    := (others => '0');

        signal saved_y_n, saved_y_c:       unsigned(y'range)    := (others => '0');

        signal saved_attr_n, saved_attr_c: unsigned(attr_default'range) := (others => '0');

        signal reverse_video_c, reverse_video_n: boolean := false;

        signal base_n, base_c: unsigned(addr'high downto 4) := (others => '0');

        signal addr_sel:       unsigned(addr'range) := (others => '0');

        signal saved_base_n, saved_base_c: unsigned(base_c'range) := (others => '0');

        signal is_base_saved_n, is_base_saved_c: boolean := false;

begin

        accumulator_0: work.vga_pkg.atoi

                generic map(g => g, N => number)

                port map(

                        clk    => clk,

                        rst    => rst,

                        we     => we,

                        init   => akk_init,

                        char   => char,

                        char_o => akk_char_o,

                        done_o => akk_done_o,

                        -- ready  => akk_ready_o,

                        n_o    => n_o);

        address: block

                signal mul: unsigned(15 downto 0)     := (others => '0');

                signal addr_int: unsigned(addr'range) := (others => '0');

        begin

                mul      <= to_unsigned(to_integer(y_c) * width, mul'length);

                addr_int <= mul(addr_int'range) + ("000000" & x_c);

                addr_sel <= addr_int when state_c /= ERASING else count_c;

                addr     <= std_ulogic_vector(addr_sel + (base_c & "0000"));

        end block;

        x_minus_one         <= x_c - 1;

        x_plus_one          <= x_c + 1;

        x_overflow          <= x_c         >  (width  - 1);

        x_underflow         <= x_minus_one >= (width  - 1);

        x_minus_one_limited <= (others => '0') when x_underflow else x_minus_one;

        x_plus_one_limited  <= to_unsigned(width - 1, x_c'length) when x_overflow else x_plus_one;

        y_plus_one          <= y_c + 1;

        y_minus_one         <= y_c - 1;

        y_overflow          <= y_c         >= (height - 1); -- NB. > for 1 more row, slightly off edge of screen

        y_underflow         <= y_minus_one >  (height - 1);

        y_minus_one_limited <= (others => '0') when y_underflow else y_minus_one;

        y_plus_one_limited  <= to_unsigned(height - 1, y_c'length) when y_overflow else y_plus_one;

        busy <= '1' when state_c = ERASING

                        or state_c = WRITE

                        or state_c = RESET

                        or state_c = WRAP

                        or state_c = ATTRIB

                        or state_c = ADVANCE

                        else '0';

        vga_blk: block

                signal vga_din:    std_ulogic_vector(15 downto 0)     := (others => '0');

                signal vga_ctr_we: vga_control_registers_we_interface := vga_control_registers_we_initialize;

                signal vga_ctr:    vga_control_registers_interface    := vga_control_registers_initialize;

                signal attr:       unsigned(attr_c'range)             := attr_default;

                signal ch:         std_ulogic_vector(c_c'range)       := (others => '0');

        begin

                ch             <= std_ulogic_vector(asterisk) when conceal_c else std_ulogic_vector(c_c);

                attr           <= attr_c when state_c /= ERASING else attr_default;

                vga_din        <= std_ulogic_vector(attr) & ch;

                vga_ctr.crx    <= std_ulogic_vector(x_plus_one); -- not limited, goes off screen edge

                vga_ctr.cry    <= std_ulogic_vector(y_c);

                vga_ctr.ctl    <= std_ulogic_vector(ctl_c);

                vga_ctr_we.crx <= cursor_we;

                vga_ctr_we.cry <= cursor_we;

                vga_ctr_we.ctl <= cursor_we;

                vga_0: work.vga_pkg.vga_top

                generic map(g => g)

                port map(

                        clk               =>  clk,

                        clk25MHz          =>  clk25MHz,

                        rst               =>  rst,

                        vga_we_ram        =>  data_we,

                        vga_din           =>  vga_din,

                        vga_addr          =>  addr,

                        base(base_c'range)=>  std_ulogic_vector(base_c),

                        base(3 downto 0)  =>  "0000",

                        i_font_sel        =>  font_sel_c,

                        i_vga_control_we  =>  vga_ctr_we,

                        i_vga_control     =>  vga_ctr,

                        o_vga             =>  o_vga);

        end block;

        -- Subset of commands implemented:

        -- ED  - Erase Display, CSI n 'J'

        -- RIS - Erase Display, ESC 'c'

        -- SGR - Select Graphic Rendition - for colors, CSI n 'm'

        -- HVP - Horizontal and Vertical Position - CSI n ; m 'f'

        -- The cursor commands are also supported: CUU, CUD, CUF,

        -- CUB, CNL, CPL and CHA

        fsm: process(clk, rst)

                variable limit_value: unsigned(addr'range) := (others => '0');

                variable repeat:      boolean    := false;

                variable exit_repeat: state_type := RESET;

                procedure reverse_video(a: unsigned(2 downto 0); foreground: boolean) is

                begin

                        if foreground then

                                if reverse_video_c then

                                        attr_n(2 downto 0) <= a;

                                else

                                        attr_n(5 downto 3) <= a;

                                end if;

                        else

                                if reverse_video_c then

                                        attr_n(5 downto 3) <= a;

                                else

                                        attr_n(2 downto 0) <= a;

                                end if;

                        end if;

                end procedure;

        begin

                if rst = '1' and g.asynchronous_reset then

                        state_c <= RESET;

                elsif rising_edge(clk) then

                        if rst = '1' and not g.asynchronous_reset then

                                state_c <= RESET;