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[/] [forwardcom/] [trunk/] [bitstream_settings_a.xdc] - Blame information for rev 27

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Line No. Rev Author Line
1 27 Agner
# ForwardCom soft core
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# Constraints for Nexys Artix-7 100T board
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# Agner Fog 2021-07-31
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property CFGBVS VCCO [current_design]
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# Board input clock 100 MHz (this affects simulation only)
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set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clock100]
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create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clock100]
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# Make data ram use block ram
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# set_property RAM_STYLE BLOCK [get_cells -hierarchical dataram*]
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# I have problems finding out what to write here to get rid of timing warnings
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# for inputs and outputs. Feel free to change it or remove it.
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#set_input_delay -clock [get_clocks sys_clk_pin]  0.000 [get_ports resetButton]
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#set_input_delay -clock [get_clocks sys_clk_pin] -min -add_delay 0.000 [get_ports resetButton]
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#set_input_delay -clock [get_clocks sys_clk_pin] -max -add_delay 0.000 [get_ports resetButton]
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#set_input_delay -clock [get_clocks sys_clk_pin]  0.000 [get_ports resetButtonD]
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#set_input_delay -clock [get_clocks sys_clk_pin]  0.000 [get_ports stepButton]
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#set_input_delay -clock [get_clocks sys_clk_pin]  0.000 [get_ports stepButtonD]
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#set_input_delay -clock [get_clocks sys_clk_pin]  0.000 [get_ports switch0]
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#set_input_delay -clock [get_clocks sys_clk_pin]  0.000 [get_ports switch1]
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#set_input_delay -clock [get_clocks sys_clk_pin]  0.000 [get_ports switch14]
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#set_input_delay -clock [get_clocks sys_clk_pin]  0.000 [get_ports switch15]
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#set_input_delay -clock [get_clocks sys_clk_pin]  0.000 [get_ports switch2]
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#set_input_delay -clock [get_clocks sys_clk_pin]  0.000 [get_ports switch3]
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#set_input_delay -clock [get_clocks sys_clk_pin]  0.000 [get_ports switch4]
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#
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## "-min" = hold time, "-max" = setup time
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#set_output_delay -clock [get_clocks sys_clk_pin] -min -1.000 [get_ports {digit7seg[*]}]
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#set_output_delay -clock [get_clocks sys_clk_pin] -max -4.000 [get_ports {digit7seg[*]}]
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#set_output_delay -clock [get_clocks sys_clk_pin] -min -1.000 [get_ports {segment7seg[*]}]
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#set_output_delay -clock [get_clocks sys_clk_pin] -max -4.000 [get_ports {segment7seg[*]}]
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##set_output_delay -clock [get_clocks sys_clk_pin] -max -add_delay  5.000 [get_ports {digit7seg[*]}]
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#set_output_delay -clock [get_clocks sys_clk_pin]  -min -1.000 [get_ports led0]
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#set_output_delay -clock [get_clocks sys_clk_pin]  -max -4.000 [get_ports led0]
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#set_output_delay -clock [get_clocks sys_clk_pin]  -min -1.000 [get_ports led1]
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#set_output_delay -clock [get_clocks sys_clk_pin]  -max -4.000 [get_ports led1]
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#set_output_delay -clock [get_clocks sys_clk_pin]  -min -1.000 [get_ports led2]
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#set_output_delay -clock [get_clocks sys_clk_pin]  -max -4.000 [get_ports led2]
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#set_output_delay -clock [get_clocks sys_clk_pin]  -min -2.000 [get_ports led12]
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#set_output_delay -clock [get_clocks sys_clk_pin]  -max -4.000 [get_ports led12]
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#set_output_delay -clock [get_clocks sys_clk_pin]  -min -2.000 [get_ports led13]
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#set_output_delay -clock [get_clocks sys_clk_pin]  -max -4.000 [get_ports led13]
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#set_output_delay -clock [get_clocks sys_clk_pin]  -min -2.000 [get_ports led15]
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#set_output_delay -clock [get_clocks sys_clk_pin]  -max -4.000 [get_ports led15]
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#set_switching_activity -toggle_rate 0.010 -static_probability 0.100 [get_nets {register_file_inst/genblk1[0].registers[0][63]_i_1_n_0}]
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# generated by constraints wizard:
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set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks clock100] -group [get_clocks -include_generated_clocks sys_clk_pin]
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set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks clkfbout_clock_generator] -group [get_clocks -include_generated_clocks clkfbout_clock_generator_1]
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set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks clk_out_clock_generator] -group [get_clocks -include_generated_clocks clk_out_clock_generator_1]

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