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[/] [forwardcom/] [trunk/] [config_r64.vh] - Blame information for rev 17

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1 17 Agner
//////////////////////////////////////////////////////////////////////////////////
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// Engineer:       Agner Fog
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// 
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// Create Date:    2020-06-06
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// Last modified:  2021-08-06
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// Module Name:    config_r64.vh
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// Project Name:   ForwardCom soft core model A
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// Target Devices: Artix 7
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// Tool Versions:  Vivado v. 2020.1
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// License:        CERN-OHL-W v. 2 or later
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// Description:    Configuration parameters 
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//
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// Configuration for 64 bit registers, 32kB data RAM, 64 kB code RAM
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//
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//////////////////////////////////////////////////////////////////////////////////
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`define NUM_VECTOR_UNITS       0       // number of 64-bit vector units or lanes
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// Decide if we have 64 bits support. We can use less resources and have higher speed with the 32 bit version. 
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// If 32 bits: General purpose registers are 32 bits. Temporary operand buffers are 32 bits.
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// Result buses are 32 bits. Results will be 32 bits, even for 64 bit instructions. 
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// The data write buses to data cache and code cache are still 64 bits, using any part of the bus for smaller operand sizes.
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// If 64 bits: General purpose registers are 64 bits. 64 bit operand size is supported.
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// Uncomment this to support 64-bit operand type:
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`define SUPPORT_64BIT
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`ifdef SUPPORT_64BIT
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    `define RB                    64   // size of general purpose registers, 64 bits
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    `define RB1                   63   // index of most significant bit
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`else
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    `define RB                    32   // size of general purpose registers, 32 bits
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    `define RB1                   31   // index of most significant bit
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`endif
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// number of bits used in mask registers must be TAG_WIDTH < MASKSZ <= RB
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`define MASKSZ                  16
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//`define MASKSZ                    32
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//`define MASKSZ                 `RB
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// Clock frequency
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// Xilinx-specific:
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// To change the clock frequency, click on the clock_generator source to open the
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// Vivado Clocking Wizard and set the requested output frequency.
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// Use the timing summary to check if the design can work with this frequency.
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// The frequency defined below must match the frequency set in the clocking wizard: 
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//`define CLOCK_FREQUENCY   68000000   // max clock frequency for 32-bit version
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`define CLOCK_FREQUENCY    58000000   // max clock frequency for 64-bit version
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// Serial input/output BUAD rate. 8 data bits, no parity, 1 stop bit 
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//`define BAUD_RATE      19200
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`define BAUD_RATE        57600
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//`define BAUD_RATE      115200
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// serial input  buffer size is 2**IN_BUFFER_SIZE_LOG2 bytes
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// serial output buffer size is 2**OUT_BUFFER_SIZE_LOG2 bytes
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`define IN_BUFFER_SIZE_LOG2    10      // 1 kbyte
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`define OUT_BUFFER_SIZE_LOG2   11      // 2 kbytes
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// initial code in 64-bit lines. remember to put the second 32-bit word to the left:
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`define LOADER_FILE "loader.mem"       // filename of hex file of machine code for loader
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`define MAX_LOADER_SIZE 32'H200        // >= size of loader code, in 32-bit words. Must be even
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// Loader entry address is the end of code memory - MAX_LOADER_SIZE
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// Restart address is the same address + 1
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// code ram address lines. Each line has one 32-bit word = 4 bytes
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// code ram size = 2**(CODE_ADDR_WIDTH+2)
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//`define CODE_ADDR_WIDTH 13  // 32 kB
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`define CODE_ADDR_WIDTH 14  // 64 kB
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//`define CODE_ADDR_WIDTH 15  // 128 kB
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// data ram address lines. Each line has 1 byte. 
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// data ram size = (2**DATA_ADDR_WIDTH)
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`define DATA_ADDR_WIDTH 15   // 32 kB
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// total address lines for code and data combined, used when writing code. 
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// Total address space = (2**COMMON_ADDR_WIDTH) bytes
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`define COMMON_ADDR_WIDTH ((`CODE_ADDR_WIDTH+2>`DATA_ADDR_WIDTH) ? `CODE_ADDR_WIDTH+3 : `DATA_ADDR_WIDTH+1)
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// The code address space must start immediately after the data address space if IP-addressed data are used without load-time relocation:  
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`define CODE_ADDR_START `DATA_ADDR_WIDTH   // code write address starts at 2**`CODE_ADDR_START = end of data address space
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// code ram bus width
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`define CODE_DATA_WIDTH 64
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// The number of entries in the call stack size is 2**CALL_STACK_POINTER_BITS - 1
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`define CALL_STACK_POINTER_BITS  10
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// number of system registers that behave as g.p. registers (renamed in flight)
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`define NUM_SYS_REGISTERS    3
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// number of bits in instruction ID tag. 
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// The maximum number of instruction tags in flight is 2**TAG_WIDTH - 1  
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`define TAG_WIDTH  5
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// number of error types distinguished
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`define N_ERROR_TYPES  6
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// Input/output port numbers
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`define INPORT_RS232            8      // input port for RS232 serial input
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`define INPORT_RS232_STATUS     9      // input port to read status of RS232 serial input
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`define OUTPORT_RS232          10      // output port for RS232 serial output
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`define OUTPORT_RS232_STATUS   11      // output port for RS232 serial output status
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