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1 10 Agner
/******************************************************************************
2
* Engineer: Agner Fog
3
*
4
* Create date:   2020-05-03
5
* Last modified: 2021-08-05
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* Module name:   top
7
* Project name:  ForwardCom soft core
8
* Tool versions: Vivado 2020.1
9
* License:       CERN-OHL-W version 2 or later
10
* Description:   Top level module of ForwardCom softcore
11
*
12
* The pipeline stages are connected here:
13
* 1.  fetch:            Fetch code words from code memory
14
* 2.  decoder           Decode instruction code
15
* 3.  register_read     Read registers. The register file is included in this stage
16
* 4.  addressgenerator  Calculate address of any memory operand
17
* 5.  dataread          Wait for data being read from data RAM
18
* 6a. alu               Execute the instruction and calculate the result
19
* 6b. in_out_ports      Input and output instructions etc. go here instead of into alu
20
*
21
* Other modules connected here:
22
* clock_generator:      Controls the clock frequency of the global clock
23
* code_memory:          Code memory or cache
24
* data_memory:          Data memory or cache
25
* call_stack:           Call stack for function return addresses
26
* debug_display:        Shows contents of each pipeline stage on LCD display
27
* debugger.vh:          Displays values of any signals anywhere in system on LED displays
28
*
29
******************************************************************************/
30
`include "defines.vh"
31
 
32
/*
33
Signals have name prefixes indicating the modules that generate them.
34
Handshaking signals between pipeline stages:
35
valid_in:                  Preceding stage has valid data ready
36
valid_out:                 Valid data are ready for next stage
37
stall_in:                  Keep your data for the next clock cycle
38
stall_out:                 Unable to receive new data
39
stall_predict_out:         Predict that the next stage in pipeline will stall in next clock cycle
40
There is currently no contention for result buses, but future implementation may need handshaking for this:
41
result_bus_require_out:    Needs result bus in next clock cycle
42
result_bus_acknowledge_in: No unit with higher privilege is taking the result bus
43
result_bus_enable_out:     A result is on the result bus
44
*/
45
 
46
module top (
47
    input clock100,               // board input clock 100 MHz
48
    input switch0,                // switches for debug modes
49
    input switch1,                // switches for debug modes
50
    input switch2,                // switches for debug modes
51
    input switch3,                // switches for debug modes
52
    input switch4,                // switches for debug modes
53
    input switch5,                // switches for debug modes
54
    input switch6,                // switches for debug modes
55
    input switch7,                // switches for debug modes
56
    input switch8,                // switches for debug modes
57
    input switch15,               // disables error stop
58
 
59
    input step_button,            // Single stepping (RIGHT BUTTON)
60
    input run_button,             // Stop single stepping and start free running (UP BUTTON)
61
    input reset_button,           // Reset to start of program (DOWN BUTTON)
62
    input load_button,            // Load program throung serial interfase (!CPU RESET BUTTON)
63
 
64
    input step_button_x,          // Single stepping (external button)
65
    input run_button_x,           // Stop single stepping and start free running (external button)
66
    input reset_button_x,         // Reset to start of program (external button)
67
    input load_button_x,          // Loader (external button)
68
    input external_connected_x,   // high if external debug interface is connected
69
 
70
    input debug1_switch,          // enable single-stepping, pipeline mode
71
    input debug2_switch,          // enable single-stepping, instruction mode
72
    input uart_txd_in,            // UART transmit from PC
73
    input uart_rts_in,            // UART RTS from PC
74
    output reg [7:0] segment7seg, // segment output, active low
75
    output reg [7:0] digit7seg,   // digit select output, active low
76
    output reg [3:0] lcd_data,    // data to LCD display
77
    output reg lcd_rs,            // control signal for LCD display
78
    output reg [1:0] lcd_e,       // enable signals for LCD displays
79
    output uart_rxd_out,          // UART receive to PC
80
    output uart_cts_out,          // UART CTS to PC
81
    output  led0,                 // use of led's: see below
82
    output  led1,
83
    output  led2,
84
    output  led3,
85
    output  led4,
86
    output  led5,
87
    output  led6,
88
    output  led7,
89
    output  led12,
90
    output  led13,
91
    output  led14,
92
    output  led15,
93
    output  led16R,               // RGB led
94
    output  led16G,
95
    output  led16B
96
);
97
 
98
 
99
// generate clock (Xilinx specific. Generated by Clocking Wizard)
100
clock_generator clock_generator_inst (
101
    .clk_in(clock100),            // board input clock, 100 MHz
102
    .clk_out(clock),              // synthesized clock, frequency is `CLOCK_FREQUENCY
103
    .locked()                     // clock frequency has stabilized
104
);
105
 
106
// control single stepping
107
reg single_step_mode;
108
reg step_button_debounced;
109
reg run_button_debounced;
110
reg reset_button_debounced;
111
reg load_button_debounced;
112
reg step_button_pulse;
113
reg run_button_pulse;
114
reg reset_button_pulse;
115
reg load_button_pulse;
116
 
117
reg [2:0] reset_step = 3'b111;    // shift register for system reset clock cycles
118
reg clock_enable = 0;
119
reg system_reset = 1;             // reset everything. load program
120
reg program_restart = 0;          // restart loaded program
121
 
122
 
123
// pushbutton debouncers
124
// on-board buttons are always enabled, external buttons are enabled by external_connected_x
125
logic[3:0] input_buttons;
126
logic[3:0] debounced_buttons;
127
logic[3:0] button_pulse;
128
 
129
assign input_buttons[0] = step_button  | (step_button_x & external_connected_x);
130
assign input_buttons[1] = run_button   | (run_button_x & external_connected_x);
131
assign input_buttons[2] = reset_button | (reset_button_x & external_connected_x);
132
assign input_buttons[3] = (~load_button) | (load_button_x & external_connected_x);
133
assign debounced_buttons[0] = step_button_debounced;
134
assign debounced_buttons[1] = run_button_debounced;
135
assign debounced_buttons[2] = reset_button_debounced;
136
assign debounced_buttons[3] = load_button_debounced;
137
assign button_pulse[0] = step_button_pulse;
138
assign button_pulse[1] = run_button_pulse;
139
assign button_pulse[2] = reset_button_pulse;
140
assign button_pulse[3] = load_button_pulse;
141
 
142
debounce #(.num(4) ) debounce_inst
143
(.clock(clock),
144
.buttons_in (input_buttons),
145
.buttons_out(debounced_buttons),
146
.pulse_out(button_pulse));
147
 
148
 
149
 
150
/***************************************************
151
       Signals connecting the stages
152
***************************************************/
153
 
154
// code memory
155
logic [`CODE_DATA_WIDTH-1:0] code_memory_data;              // Data out
156
logic [31:0]                 code_memory_debug;
157
 
158
// data memory
159
logic [`RB1:0] data_memory_data;
160
 
161
// call stack
162
logic [`CODE_ADDR_WIDTH-1:0] call_stack_pop_data;          // return address popped from call stack
163
logic call_stack_overflow;                                 // call stack overflow or underflow or error
164
 
165
// register file input
166
logic  [5:0]   debug_reada;                                // read port for debugger
167
 
168
// signals from each pipeline stage
169
 
170
// fetch stage
171
logic fetch_valid;
172
logic fetch_jump;                                          // jump instruction bypassing pipeline
173
logic fetch_call_e;                                        // executing call instruction
174
logic fetch_return_e;                                      // executing return instruction
175
logic [95:0] fetch_instruction;
176
logic [`CODE_ADDR_WIDTH-1:0] fetch_instruction_pointer;    // point to current instruction
177
logic                        fetch_read_enable;
178
logic [`CODE_ADDR_WIDTH-2:0] fetch_read_addr;              // Address for reading from code ram
179
logic [`CODE_ADDR_WIDTH-1:0] fetch_call_push_data;         // return address pushed to call stack
180
logic [31:0]                 fetch_debug1;                 // temporary debug output
181
 
182
// decoder
183
logic [`TAG_WIDTH-1:0] decoder_tag_val;                    // instruction tag value
184
logic        decoder_tag_write;                            // tag write enable
185
logic        decoder_read;                                 // read register enable
186
logic        decoder_valid;                                // An instruction is ready for output to next stage
187
logic [`CODE_ADDR_WIDTH-1:0] decoder_instruction_pointer;  // address of current instruction
188
logic [95:0] decoder_instruction;                          // first word of instruction
189
logic        decoder_stall;                                // Not ready to receive next instruction
190
logic [5:0]  decoder_tag_a;                                // register number for instruction tag
191
logic        decoder_vector;                               // this is a vector instruction
192
logic [1:0]  decoder_category;                             // 00: multiformat, 01: single format, 10: jump
193
logic [1:0]  decoder_format;                               // 00: format A, 01: format E, 10: format B, 11: format C (format D never goes through decoder)
194
logic [2:0]  decoder_rs_status;                            // use of RS
195
logic [2:0]  decoder_rt_status;                            // use of RT
196
logic [1:0]  decoder_ru_status;                            // 1: RU is used
197
logic [1:0]  decoder_rd_status;                            // 1: RD is used as input
198
logic [1:0]  decoder_mask_status;                          // what the mask register is used for
199
logic        decoder_mask_options;                         // 1: mask register may contain options
200
logic        decoder_mask_alternative;                     // mask register and fallback register used for alternative purposes
201
logic [2:0]  decoder_fallback_use;                         // 0: no fallback, 1: same as first source operand, 2-4: RU, RS, RT
202
logic [1:0]  decoder_num_operands;                         // number of source operands
203
logic [1:0]  decoder_result_type;                          // type of result: 0: register, 1: system register, 2: memory, 3: other or nothing
204
logic [1:0]  decoder_offset_field;                         // address offset. 0: none, 1: 8 bit, possibly scaled, 2: 16 bit, 3: 32 bit
205
logic [1:0]  decoder_immediate_field;                      // immediate data field. 0: none, 1: 8 bit, 2: 16 bit, 3: 32 or 64 bit
206
logic [1:0]  decoder_scale_factor;                         // 00: index is not scaled, 01: index is scaled by operand size, 10: index is scaled by -1
207
logic        decoder_index_limit;                          // index has a limit
208
logic [31:0] decoder_debug1;                               // temporary debug output
209
 
210
// register read stage
211
logic         registerread_valid;                          // An instruction is ready for output to next stage
212
logic [`CODE_ADDR_WIDTH-1:0] registerread_instruction_pointer; // address of current instruction
213
logic [95:0]  registerread_instruction;                    // first word of instruction
214
logic         registerread_stall_predict;                  // predict next stage will stall
215
logic [`TAG_WIDTH-1:0] registerread_tag_val;               // instruction tag value
216
logic         registerread_vector;                         // this is a vector instruction
217
logic [1:0]   registerread_category;                       // 00: multiformat, 01: single format, 10: jump
218
logic [1:0]   registerread_format;                         // 00: format A, 01: format E, 10: format B, 11: format C (format D never goes through decoder)
219
logic [1:0]   registerread_num_operands;                   // number of source operands
220
logic [1:0]   registerread_result_type;                    // type of result: 0: register, 1: system register, 2: memory, 3: other or nothing
221
logic [1:0]   registerread_offset_field;                   // address offset. 0: none, 1: 8 bit, possibly scaled, 2: 16 bit, 3: 32 bit
222
logic [1:0]   registerread_immediate_field;                // immediate data field. 0: none, 1: 8 bit, 2: 16 bit, 3: 32 or 64 bit
223
logic [1:0]   registerread_scale_factor;                   // 00: index is not scaled, 01: index is scaled by operand size, 10: index is scaled by -1
224
logic         registerread_index_limit;                    // The field indicated by offset_field contains a limit to the index
225
logic [`RB:0] registerread_rd_val;                         // value of register operand RD, bit `RB indicates missing
226
logic [`RB:0] registerread_rs_val;                         // value of register operand RS, bit `RB indicates missing
227
logic [`RB:0] registerread_rt_val;                         // value of register operand RT, bit `RB indicates missing
228
logic [`RB:0] registerread_ru_val;                         // value of register operand RU, bit `RB indicates missing
229
logic [`MASKSZ:0] registerread_regmask_val;                // value of mask register, bit 32 indicates missing
230
logic [1:0]   registerread_rd_status;                      // RD is used as input
231
logic [2:0]   registerread_rs_status;                      // use of RS
232
logic [2:0]   registerread_rt_status;                      // use of RT
233
logic [1:0]   registerread_ru_status;                      // RU is used
234
logic [1:0]   registerread_mask_status;                    // mask register is used
235
logic         registerread_mask_alternative;               // mask register and fallback register used for alternative purposes
236
logic [2:0]   registerread_fallback_use;                   // 0: no fallback, 1: same as first source operand, 2-4: RU, RS, RT
237
logic [32:0]  registerread_debugport;                      // register read by debugger
238
 
239
// address generator
240
logic [`COMMON_ADDR_WIDTH-1:0] addrgen_read_write_address; // address of memory operand
241
logic        addrgen_read_enable;                          // read from data memory
242
logic [1:0]  addrgen_read_data_size;
243
logic [7:0]  addrgen_write_enable;
244
logic [63:0] addrgen_write_data;                           // Any part of the 64 bits write bus can be used when the operand size is less than 64 bits
245
logic        addrgen_valid;                                // An instruction is ready for output to next stage
246
logic [`CODE_ADDR_WIDTH-1:0] addrgen_instruction_pointer;  // address of current instruction
247
logic [63:0] addrgen_instruction;                          // first word of instruction
248
logic        addrgen_stall_next;                           // address generator waiting for an operand
249
logic [`TAG_WIDTH-1:0] addrgen_tag_val;                    // instruction tag value
250
logic [`RB:0] addrgen_operand1;                            // value of first register operand
251
logic [`RB:0] addrgen_operand2;                            // value of second register operand
252
logic [`RB:0] addrgen_operand3;                            // value of last operand
253
logic [`MASKSZ:0] addrgen_regmask_val;                     // value of mask register, bit 32 indicates valid
254
logic        addrgen_vector;                               // this is a vector instruction
255
logic [1:0]  addrgen_category;                             // instruction category: multiformat, single format, jump
256
logic [1:0]  addrgen_format;                               // instruction format: A, E, B, D
257
logic        addrgen_mask_status;                          // mask register is used
258
logic        addrgen_mask_alternative;                     // mask register and fallback register used for alternative purposes
259
logic [2:0]  addrgen_fallback_use;                         // 0: no fallback, 1: same as first source operand, 2-4: RU, RS, RT
260
logic [1:0]  addrgen_num_operands;                         // number of source operands
261
logic [1:0]  addrgen_result_type;                          // type of result: 0: register, 1: system register, 2: memory, 3: other or nothing
262
logic [1:0]  addrgen_offset_field;                         // unused
263
logic [1:0]  addrgen_immediate_field;                      // immediate data field. 0: none, 1: 8 bit, 2: 16 bit, 3: 32 or 64 bit
264
logic [1:0]  addrgen_scale_factor;                         // 00: index is not scaled, 01: index is scaled by operand size, 10: index is scaled by -1
265
logic        addrgen_memory_operand;                       // The instruction has a memory operand
266
logic        addrgen_array_error;                          // Array index exceeds limit
267
 
268
logic [31:0] addrgen_debug1;                               // temporary debug output
269
logic [31:0] addrgen_debug2;                               // temporary debug output
270
logic [31:0] addrgen_debug3;                               // temporary debug output
271
 
272
// data read stage
273
logic        dataread_valid;                               // An instruction is ready for output to next stage
274
logic [`CODE_ADDR_WIDTH-1:0] dataread_instruction_pointer; // address of current instruction
275
logic [31:0] dataread_instruction;                         // first word of instruction
276
logic        dataread_stall_predict;                       // predict next stage will stall
277
logic [`TAG_WIDTH-1:0] dataread_tag_val;                   // instruction tag value
278
logic [`RB:0] dataread_operand1;                           // value of first operand
279
logic [`RB:0] dataread_operand2;                           // value of second operand
280
logic [`RB:0] dataread_operand3;                           // value of last operand
281
logic [`MASKSZ:0] dataread_mask_val;                       // value of mask, bit 32 is 0 if valid
282
logic        dataread_opr2_from_ram;                       // value of operand 2 comes from data memory
283
logic        dataread_opr3_from_ram;                       // value of last operand comes from data memory
284
logic        dataread_vector;                              // this is a vector instruction
285
logic [1:0]  dataread_category;                            // 00: multiformat, 01: single format, 10: jump
286
logic [1:0]  dataread_format;                              // 00: format A, 01: format E, 10: format B, 11: format C (format D never goes through decoder)
287
logic [1:0]  dataread_num_operands;                        // number of source operands
288
logic        dataread_opr1_used;                           // opr1_val_out is needed
289
logic        dataread_opr2_used;                           // opr2_val_out is needed
290
logic        dataread_opr3_used;                           // opr3_val_out is needed
291
logic        dataread_regmask_used;                        // regmask_val_out is needed
292
logic        dataread_mask_alternative;                    // mask register and fallback register used for alternative purposes
293
logic [1:0]  dataread_result_type;                         // type of result: 0: register, 1: system register, 2: memory, 3: other or nothing
294
logic [3:0]  dataread_exe_unit;                            // each bit enables a particular execution unit
295
                                                           // 1: ALU, 10: MUL, 100: DIV, 1000: IN/OUT
296
logic [6:0]  dataread_opx;                                 // operation ID in execution unit. This is mostly equal to op1 for multiformat instructions
297
logic [5:0]  dataread_opj;                                 // operation ID for conditional jump instructions
298
logic [2:0]  dataread_ot;                                  // operand type
299
logic [5:0]  dataread_option_bits;                         // option bits from IM3 or mask
300
logic [15:0] dataread_im2_bits;                            // constant bits from IM2 as extra operand
301
logic        dataread_trap;                                // trap instruction detected. enable single step mode
302
logic        dataread_array_error;                         // array index out of bounds
303
logic        dataread_read_address_error;                  // invalid read memory address
304
logic        dataread_write_address_error;                 // invalid write memory address
305
logic        dataread_misaligned_address_error;            // misaligned read/write memory address
306
logic [31:0] dataread_debug;                               // output for debugging
307
 
308
// alu stage
309
logic        alu_valid;                                    // for debug display: alu is active
310
logic        alu_write_en;                                 // write value to register file
311
logic [5:0]  alu_register_a;                               // register to write
312
logic [`RB1:0] alu_result;                                 // result to write
313
logic [`TAG_WIDTH-1:0] alu_tag;                            // instruction tag value
314
logic        alu_jump;                                     //  jump instruction: jump taken
315
logic        alu_nojump;                                   // jump instruction: jump not taken
316
logic [`CODE_ADDR_WIDTH-1:0] alu_jump_pointer;             // jump target to fetch unit
317
logic alu_stall;
318
logic alu_stall_next;
319
logic alu_error;                                           // unknown instruction
320
logic alu_error_parm;                                      // wrong parameter for instruction
321
logic [31:0] alu_debug1;                                   // output for debugger
322
logic [31:0] alu_debug2;                                   // output for debugger
323
 
324
// mul/div alu
325
logic        muldiv_valid;                                 // for debug display: alu is active
326
logic        muldiv_write_en;                              // write value to register file
327
logic [4:0]  muldiv_register_a;                            // register to write
328
logic [`RB1:0] muldiv_result;                              // result to write
329
logic [`TAG_WIDTH-1:0] muldiv_tag;                         // instruction tag value
330
logic muldiv_stall;
331
logic muldiv_stall_next;
332
logic muldiv_error;                                        // unknown instruction
333
logic muldiv_error_parm;                                   // wrong parameter for instruction
334
logic [31:0] muldiv_debug1;                                // output for debugger
335
logic [31:0] muldiv_debug2;                                // output for debugger
336
 
337
// in_out_ports
338
logic inout_valid;                                         // for debug display: in_out is active
339
logic inout_write_en;                                      // write value to register file
340
logic [5:0] inout_register_a;                              // register to write
341
logic [`RB1:0] inout_result;                               // result to write
342
logic [`TAG_WIDTH-1:0] inout_tag;                          // instruction tag value
343
logic inout_nojump;                                        // serializing instruction read_perf gives jump not taken signal to resume pipeline
344
logic inout_stall;
345
logic inout_stall_next;
346
logic inout_error;                                         // unknown instruction
347
logic inout_error_parm;                                    // wrong parameter for instruction
348
logic [`N_ERROR_TYPES-1:0] inout_capab_disable_errors;     // capab2 register: disable errors
349
logic [3:0] inout_first_error;                             // error type for first error, stored in inout module
350
logic [`CODE_ADDR_WIDTH-1:0] inout_first_error_address;    // code address of first error
351
logic [31:0] inout_debug;                                  // output for debugger
352
 
353
// error handling
354
logic [`N_ERROR_TYPES-1:0] errors_detect;                  // one bit for each type of error detected
355
logic clear_error;                                         // clear error on debug display
356
reg   show_error;                                          // show error on debug display
357
 
358
 
359
/***************************************************
360
       Top level logic signals
361
***************************************************/
362
// result bus 1
363
logic bus1_write_en;                                       // write value to register file
364
logic [5:0] bus1_register_a;                               // register to write (includes system registers)
365
logic [`RB1:0] bus1_value;                                 // value to write
366
logic [`TAG_WIDTH-1:0] bus1_tag;                           // result tag for value on bus 1
367
 
368
// result bus 2
369
logic bus2_write_en;                                       // write value to register file
370
logic [4:0] bus2_register_a;                               // register to write
371
logic [`RB1:0] bus2_value;                                 // value to write
372
logic [`TAG_WIDTH-1:0] bus2_tag;                           // result tag for value on bus 2
373
 
374
// signals for predicting when a result will be available
375
logic [`TAG_WIDTH-1:0] predict_tag1;                       // result tag value on bus 1 in next clock cycle
376
logic [`TAG_WIDTH-1:0] predict_tag2;                       // result tag value on bus 2 in next clock cycle
377
 
378
logic [`CODE_ADDR_WIDTH-2:0] code_read_addr;               // Address for reading from ram
379
 
380
reg [2:0] color_led16;                                     // RGB led
381
 
382
always_comb begin
383
    // result bus 1
384
    // There are no tri-state buffers inside the FPGA so we have to simulate the buses by OR'ing results:
385
    bus1_write_en  = alu_write_en | inout_write_en;        // write value to register file
386
    bus1_register_a = alu_register_a | inout_register_a;   // register to write
387
    bus1_value = alu_result | inout_result;                // value to write
388
    bus1_tag = alu_tag | inout_tag;                        // tag for result on bus 1
389
 
390
    // result bus 2 not yet used
391
    bus2_write_en  = muldiv_write_en;                      // write value to register file
392
    bus2_register_a = muldiv_register_a;                   // register to write
393
    bus2_value = muldiv_result;                            // value to write
394
    bus2_tag = muldiv_tag;                                 // tag for result on bus 2
395
 
396
    // read address for code memory. comes from fetch unit, except for taken conditional or indirect jumps/calls
397
    code_read_addr = alu_jump ? (alu_jump_pointer >> 1) : fetch_read_addr;
398
    // predict next tag on bus 1
399
    predict_tag1 = (dataread_exe_unit[0] | dataread_exe_unit[3]) ? dataread_tag_val : 0;
400
    // predict next tag on bus 2. To do: insert propagation delay !!
401
    predict_tag2 = (dataread_exe_unit[1] | dataread_exe_unit[2]) ? dataread_tag_val : 0;
402
 
403
    // error detection
404
    errors_detect[0] = alu_error | muldiv_error | inout_error; // unknown instruction
405
    errors_detect[1] = alu_error_parm | muldiv_error_parm | inout_error_parm | call_stack_overflow; // wrong parameter for instruction
406
    errors_detect[2] = dataread_array_error;               // array index out of bounds
407
    errors_detect[3] = dataread_read_address_error;        // read address violation
408
    errors_detect[4] = dataread_write_address_error;       // write address violation
409
    errors_detect[5] = dataread_misaligned_address_error;  // misaligned memory address
410
    clear_error = reset_button_debounced | step_button_pulse | run_button_pulse | load_button_debounced; // clear error on debug display
411
 
412
end
413
 
414
// single step and reset control
415
always_ff @(posedge clock) begin
416
    reset_step[2:0] <= {reset_step[1:0],(reset_button_debounced|load_button_debounced)}; // shift register delaying reset button
417
    if (reset_button_debounced) begin
418
        clock_enable <= 1;                                 // enable clock while resetting
419
        system_reset <= 1;                                 // reset everything for 3 clock cycles
420
        program_restart <= 1;
421
        single_step_mode <= 0;
422
    end else if (load_button_debounced) begin
423
        clock_enable <= 1;                                 // enable clock while resetting
424
        system_reset <= 1;                                 // reset everything for 3 clock cycles
425
        program_restart <= 0;
426
        single_step_mode <= 0;
427
    end else if (reset_step != 0) begin
428
        clock_enable <= 1;                                 // enable clock while resetting
429
        system_reset <= 1;                                 // reset everything for 3 clock cycles
430
        single_step_mode <= 0;                             // start in single step mode
431
    end else if (single_step_mode) begin                   // single-stepping for debugging
432
        clock_enable <= step_button_pulse;                 // enable for one clock cycle
433
        system_reset <= 0;
434
        program_restart <= 0;
435
    end else begin                                         // not single_step_mode
436
        clock_enable <= 1;
437
        system_reset <= 0;
438
        program_restart <= 0;
439
    end
440
 
441
    // set or clear single step mode
442
    if (run_button_pulse)  single_step_mode <= 0;
443
    if (step_button_pulse) single_step_mode <= 1;
444
    if (dataread_trap)     single_step_mode <= 1;          // breakpoint sets single step mode
445
    if (|(errors_detect & ~inout_capab_disable_errors) && !switch15) single_step_mode <= 1; // error detected
446
 
447
    if (clear_error) show_error <= 0;
448
    if (|(errors_detect & ~inout_capab_disable_errors)) show_error <= 1;
449
end
450
 
451
 
452
/***************************************************
453
       Memory modules
454
***************************************************/
455
 
456
// code memory
457
code_memory code_memory_inst(
458
    .clock(clock),                                         // clock
459
    .clock_enable(clock_enable),
460
    .read_enable(fetch_read_enable | alu_jump),            // read enable
461
    .write_enable(addrgen_write_enable),
462
    .write_addr_in(addrgen_read_write_address),
463
    .write_data_in(addrgen_write_data),                    // Data in
464
    .read_addr_in(code_read_addr),                         // Address for reading from code ram
465
    .data_out(code_memory_data),                           // Data out
466
    .debug_out(code_memory_debug)
467
);
468
 
469
 
470
// read/write data memory
471
data_memory data_memory_inst (
472
    .clock(clock),                                         // clock
473
    .clock_enable(clock_enable),                           // clock enable. Used when single-stepping
474
    .read_write_addr(addrgen_read_write_address),          // Address for reading from ram
475
    .read_enable(addrgen_read_enable),                     // read enable
476
    .read_data_size(addrgen_read_data_size),
477
    .write_enable(addrgen_write_enable),                   // write enable for each byte separately
478
    .write_data_in(addrgen_write_data),
479
    .read_data_out(data_memory_data)                       // Data out
480
);
481
 
482
// call stack
483
call_stack call_stack_instance(
484
    .clock(clock),                                         // clock
485
    .clock_enable(clock_enable),                           // clock enable
486
    .reset(system_reset),                                  // reset
487
    .call_e(fetch_call_e),                                 // Executing call instruction
488
    .return_e(fetch_return_e),                             // Executing return instruction
489
    .push_data(fetch_call_push_data),                      // Return address pushed at call instruction
490
    .pop_data(call_stack_pop_data),                        // Return address popped at return instruction
491
    .overflow(call_stack_overflow));                       // stack overflow or underflow or error
492
 
493
 
494
/***************************************************
495
       Pipeline stages
496
***************************************************/
497
 
498
// code fetch module
499
fetch fetch_inst(
500
    .clock(clock),                                         // system clock (100 MHz)
501
    .clock_enable(clock_enable),                           // clock enable. Used when single-stepping
502
    .reset(system_reset),                                  // system reset.
503
    .restart(program_restart),                             // restart loaded program
504
    .valid_in(1),                                          // data from code memory ready
505
    .stall_in(registerread_stall_predict | addrgen_stall_next | dataread_stall_predict | alu_stall_next | muldiv_stall_next | inout_stall_next),   // pipeline is stalled
506
    .jump_in(alu_jump),                                    // a jump target is coming from the ALU.
507
    .nojump_in(alu_nojump | inout_nojump),                 // jump target is next instruction
508
    .jump_pointer(alu_jump_pointer),                       // jump target from ALU. jump_pointer is also sent to the code memory
509
    .read_data(code_memory_data),                          // data from code memory
510
    .return_pop_data(call_stack_pop_data),                 // Return address popped here at return instruction
511
    .read_addr_out(fetch_read_addr),                       // code read address relative to code memory start
512
    .read_enable_out(fetch_read_enable),                   // code memory read enable
513
    .valid_out(fetch_valid),                               // An instruction is ready for output to decoder
514
    .jump_out(fetch_jump),                                 // Jump instruction bypassing pipeline
515
    .instruction_pointer_out(fetch_instruction_pointer),   // address of current instruction
516
    .instruction_out(fetch_instruction),                   // current instruction, up to 3 32-bit words long
517
    .call_e_out(fetch_call_e),                             // Executing call instruction. push_data contains return address
518
    .return_e_out(fetch_return_e),                         // Executing return instruction. return address is available in advance on pop_data
519
    .stall_predict_out(),                                  // predict stall in decoder
520
    .call_push_data_out(fetch_call_push_data) ,            // Return address pushed here at call instruction
521
    .debug1_out(fetch_debug1)                              // temporary debug output
522
);
523
 
524
decoder decoder_inst (
525
    .clock(clock),                                         // system clock (100 MHz)
526
    .clock_enable(clock_enable),                           // clock enable. Used when single-stepping
527
    .reset(system_reset),                                  // system reset.
528
    .valid_in(fetch_valid),                                // data from fetch module ready
529
    .stall_in(registerread_stall_predict | addrgen_stall_next | dataread_stall_predict | alu_stall_next | muldiv_stall_next | inout_stall_next),   // pipeline is stalled
530
    .instruction_pointer_in(fetch_inst.instruction_pointer_out), // address of current instruction
531
    .instruction_in(fetch_instruction),                    // current instruction, up to 3 words long
532
    .write_en1(bus1_write_en),                             // a result is written to bus 1
533
    .write_tag1(bus1_tag),                                 // tag of result in bus 1
534
    .write_en2(bus2_write_en),                             // a result is written to bus 2
535
    .write_tag2(bus2_tag),                                 // tag of result in bus 2
536
 
537
    .valid_out(decoder_valid),                             // An instruction is ready for output to next stage
538
    .instruction_pointer_out(decoder_instruction_pointer), // address of current instruction
539
    .instruction_out(decoder_instruction),                 // first word of instruction
540
    .stall_out(decoder_stall),                             // Not ready to receive next instruction
541
    .tag_a_out(decoder_tag_a),                             // register number for instruction tag
542
    .tag_val_out(decoder_tag_val),                         // instruction tag value
543
    .tag_write_out(decoder_tag_write),                     // instruction tag write enable
544
    .vector_out(decoder_vector),                           // this is a vector instruction
545
    .category_out(decoder_category),                       // 00: multiformat, 01: single format, 10: jump
546
    .format_out(decoder_format),                           // 00: format A, 01: format E, 10: format B, 11: format C (format D never goes through decoder)
547
    .rs_status_out(decoder_rs_status),                     // use of RS
548
    .rt_status_out(decoder_rt_status),                     // use of RT
549
    .ru_status_out(decoder_ru_status),                     // 1: RU is used
550
    .rd_status_out(decoder_rd_status),                     // 1: RD is used as input
551
    .mask_status_out(decoder_mask_status),                 // What the mask register is used for
552
    .mask_options_out(decoder_mask_options),               // 1: mask register may contain options
553
    .mask_alternative_out(decoder_mask_alternative),       // mask register and fallback register used for alternative purposes
554
    .fallback_use_out(decoder_fallback_use),               // 0: no fallback, 1: same as first source operand, 2-4: RU, RS, RT
555
    .num_operands_out(decoder_num_operands),               // number of source operands
556
    .result_type_out(decoder_result_type),                 // type of result: 0: register, 1: system register, 2: memory, 3: other or nothing
557
    .offset_field_out(decoder_offset_field),               // address offset. 0: none, 1: 8 bit, possibly scaled, 2: 16 bit, 3: 32 bit
558
    .immediate_field_out(decoder_immediate_field),         // immediate data field. 0: none, 1: 8 bit, 2: 16 bit, 3: 32 or 64 bit
559
    .scale_factor_out(decoder_scale_factor),               // 00: index is not scaled, 01: index is scaled by operand size, 10: index is scaled by -1
560
    .index_limit_out(decoder_index_limit),                 // The field indicated by offset_field contains a limit to the index
561
    .debug1_out(decoder_debug1)                            // temporary debug output
562
);
563
 
564
register_read register_read_inst (
565
    .clock(clock),                                         // system clock
566
    .clock_enable(clock_enable),                           // clock enable. Used when single-stepping
567
    .reset(system_reset),                                  // system reset.
568
    .valid_in(decoder_valid),                              // data from fetch module ready
569
    .stall_in(registerread_stall_predict | addrgen_stall_next | dataread_stall_predict | alu_stall_next | muldiv_stall_next | inout_stall_next),   // pipeline is stalled
570
    .instruction_pointer_in(decoder_instruction_pointer),  // address of current instruction
571
    .instruction_in(decoder_instruction),                  // current instruction, up to 3 words long
572
    .tag_write_in(decoder_tag_write),                      // write tag
573
    .tag_val_in(decoder_tag_val),                          // instruction tag value
574
    .vector_in(decoder_vector),                            // this is a vector instruction
575
    .category_in(decoder_category),                        // 00: multiformat, 01: single format, 10: jump
576
    .format_in(decoder_format),                            // 00: format A, 01: format E, 10: format B, 11: format C (format D never goes through decoder)
577
    .rs_status_in(decoder_rs_status),                      // 1: RS is register operand
578
    .rt_status_in(decoder_rt_status),                      // 1: RT is register operand
579
    .ru_status_in(decoder_ru_status),                      // 1: RU is used
580
    .rd_status_in(decoder_rd_status),                      // 1: RD is used as input
581
    .mask_status_in(decoder_mask_status),                  // use of mask
582
    .mask_options_in(decoder_mask_options),                // 1: mask register may contain options
583
    .mask_alternative_in(decoder_mask_alternative),        // mask register and fallback register used for alternative purposes
584
    .fallback_use_in(decoder_fallback_use),                // 0: no fallback, 1: same as first source operand, 2-4: RU, RS, RT
585
    .num_operands_in(decoder_num_operands),                // number of source operands
586
    .result_type_in(decoder_result_type),                  // type of result: 0: register, 1: system register, 2: memory, 3: other or nothing
587
    .offset_field_in(decoder_offset_field),                // address offset. 0: none, 1: 8 bit, possibly scaled, 2: 16 bit, 3: 32 bit
588
    .immediate_field_in(decoder_immediate_field),          // immediate data field. 0: none, 1: 8 bit, 2: 16 bit, 3: 32 or 64 bit
589
    .scale_factor_in(decoder_scale_factor),                // 00: index is not scaled, 01: index is scaled by operand size, 10: index is scaled by -1
590
    .index_limit_in(decoder_index_limit),                  // The field indicated by offset_field contains a limit to the index
591
    .writeport1(bus1_value),                               // result bus 1
592
    .writea1(bus1_register_a),                             // address input for bus 1
593
    .write_en1(bus1_write_en),                             // a result is written to bus 1
594
    .write_tag1(bus1_tag),                                 // tag of result in bus 1
595
    .writeport2(bus2_value),                               // result bus 2
596
    .writea2(bus2_register_a),                             // address input for bus 2
597
    .write_en2(bus2_write_en),                             // a result is written to bus 2
598
    .write_tag2(bus2_tag),                                 // tag of result in bus 2
599
    .debug_reada(debug_reada),                             // register read port for debugger
600
 
601
    .valid_out(registerread_valid),                        // An instruction is ready for output to next stage
602
    .instruction_pointer_out(registerread_instruction_pointer), // address of current instruction
603
    .instruction_out(registerread_instruction),            // first word of instruction
604
    .stall_predict_out(registerread_stall_predict),        // predict next stage will stall
605
    .tag_val_out(registerread_tag_val),                    // instruction tag value
606
    .vector_out(registerread_vector),                      // this is a vector instruction
607
    .category_out(registerread_category),                  // 00: multiformat, 01: single format, 10: jump
608
    .format_out(registerread_format),                      // 00: format A, 01: format E, 10: format B, 11: format C (format D never goes through decoder)
609
    .num_operands_out(registerread_num_operands),          // number of source operands
610
    .result_type_out(registerread_result_type),            // type of result: 0: register, 1: system register, 2: memory, 3: other or nothing
611
    .offset_field_out(registerread_offset_field),          // address offset. 0: none, 1: 8 bit, possibly scaled, 2: 16 bit, 3: 32 bit
612
    .immediate_field_out(registerread_immediate_field),    // immediate data field. 0: none, 1: 8 bit, 2: 16 bit, 3: 32 or 64 bit
613
    .scale_factor_out(registerread_scale_factor),          // 00: index is not scaled, 01: index is scaled by operand size, 10: index is scaled by -1
614
    .index_limit_out(registerread_index_limit),            // The field indicated by offset_field contains a limit to the index
615
    .rd_val_out(registerread_rd_val),                      // value of register operand RD, bit `RB indicates missing
616
    .rs_val_out(registerread_rs_val),                      // value of register operand RS, bit `RB indicates missing
617
    .rt_val_out(registerread_rt_val),                      // value of register operand RT, bit `RB indicates missing
618
    .ru_val_out(registerread_ru_val),                      // value of register operand RU, bit `RB indicates missing
619
    .regmask_val_out(registerread_regmask_val),            // value of mask register, bit 32 indicates missing
620
    .rd_status_out(registerread_rd_status),                // 1: RD is used as input
621
    .rs_status_out(registerread_rs_status),                // use of RS
622
    .rt_status_out(registerread_rt_status),                // use of RT
623
    .ru_status_out(registerread_ru_status),                // 1: RU is used
624
    .mask_status_out(registerread_mask_status),            // 1: mask register is used
625
    .mask_alternative_out(registerread_mask_alternative),  // mask register and fallback register used for alternative purposes
626
    .fallback_use_out(registerread_fallback_use),          // 0: no fallback, 1: same as first source operand, 2-4: RU, RS, RT
627
    .debugport_out(registerread_debugport)                 // read for debugging purpose
628
);
629
 
630
addressgenerator addressgenerator_inst (
631
    .clock(clock),                                         // system clock (100 MHz)
632
    .clock_enable(clock_enable),                           // clock enable. Used when single-stepping
633
    .reset(system_reset),                                  // system reset.
634
    .valid_in(registerread_valid),                         // data from fetch module ready
635
    .stall_in(dataread_stall_predict | alu_stall_next | muldiv_stall_next | inout_stall_next),   // pipeline is stalled
636
    .instruction_pointer_in(registerread_instruction_pointer), // address of current instruction
637
    .instruction_in(registerread_instruction),             // current instruction, up to 3 words long
638
    .tag_val_in(registerread_tag_val),                     // instruction tag value
639
    .vector_in(registerread_vector),                       // this is a vector instruction
640
    .category_in(registerread_category),                   // 00: multiformat, 01: single format, 10: jump
641
    .format_in(registerread_format),                       // 00: format A, 01: format E, 10: format B, 11: format C (format D never goes through decoder)
642
    .rs_status_in(registerread_rs_status),                 // use of RS
643
    .rt_status_in(registerread_rt_status),                 // use of RT
644
    .ru_status_in(registerread_ru_status),                 // RU is used
645
    .rd_status_in(registerread_rd_status),                 // RD is used as input
646
    .mask_status_in(registerread_mask_status),             // mask register used
647
    .mask_alternative_in(registerread_mask_alternative),   // mask register and fallback register used for alternative purposes
648
    .fallback_use_in(registerread_fallback_use),           // 0: no fallback, 1: same as first source operand, 2-4: RU, RS, RT
649
    .num_operands_in(registerread_num_operands),           // number of source operands
650
    .result_type_in(registerread_result_type),             // type of result: 0: register, 1: system register, 2: memory, 3: other or nothing
651
    .offset_field_in(registerread_offset_field),           // address offset. 0: none, 1: 8 bit, possibly scaled, 2: 16 bit, 3: 32 bit
652
    .immediate_field_in(registerread_immediate_field),     // immediate data field. 0: none, 1: 8 bit, 2: 16 bit, 3: 32 or 64 bit
653
    .scale_factor_in(registerread_scale_factor),           // 00: index is not scaled, 01: index is scaled by operand size, 10: index is scaled by -1
654
    .index_limit_in(registerread_index_limit),             // The field indicated by offset_field contains a limit to the index
655
    .rd_val_in(registerread_rd_val),                       // value of register operand RD, bit `RB indicates missing
656
    .rs_val_in(registerread_rs_val),                       // value of register operand RS, bit `RB indicates missing
657
    .rt_val_in(registerread_rt_val),                       // value of register operand RT, bit `RB indicates missing
658
    .ru_val_in(registerread_ru_val),                       // value of register operand RU, bit `RB indicates missing
659
    .regmask_val_in(registerread_regmask_val),             // mask register
660
    .write_en1(bus1_write_en),                             // a result is written to bus 1
661
    .write_tag1_in(bus1_tag),                              // tag of result in bus 1
662
    .writeport1_in(bus1_value),                            // result bus 1
663
    .write_en2(bus2_write_en),                             // a result is written to bus 2
664
    .write_tag2_in(bus2_tag),                              // tag of result in bus 2
665
    .writeport2_in(bus2_value),                            // result bus 2
666
    .predict_tag1_in(predict_tag1),                        // tag on result bus 1 in next clock cycle
667
    .predict_tag2_in(predict_tag2),                        // tag on result bus 2 in next clock cycle
668
    .read_write_address_out(addrgen_read_write_address),   // address of read memory operand
669
    .read_enable_out(addrgen_read_enable),                 // enable read from data memory
670
    .read_data_size_out(addrgen_read_data_size),           // data size for memory read
671
    .write_enable_out(addrgen_write_enable),               // write enable for each byte separately
672
    .write_data_out(addrgen_write_data),                   // data to write
673
    .valid_out(addrgen_valid),                             // An instruction is ready for output to next stage
674
    .instruction_pointer_out(addrgen_instruction_pointer), // address of current instruction
675
    .instruction_out(addrgen_instruction),                 // first word of instruction
676
    .stall_predict_out(addrgen_stall_next),                // will be waiting for an operand
677
    .tag_val_out(addrgen_tag_val),                         // instruction tag value
678
    .operand1_out(addrgen_operand1),                       // value of first operand, bit `RB indicates invalid
679
    .operand2_out(addrgen_operand2),                       // value of second operand, bit `RB indicates invalid
680
    .operand3_out(addrgen_operand3),                       // value of last, bit `RB indicates valid
681
    .regmask_val_out(addrgen_regmask_val),                 // value of mask register, bit 32 indicates valid
682
    .vector_out(addrgen_vector),                           // this is a vector instruction
683
    .category_out(addrgen_category),                       // 00: multiformat, 01: single format, 10: jump
684
    .format_out(addrgen_format),                           // 00: format A, 01: format E, 10: format B, 11: format C (format D never goes through decoder)
685
    .mask_status_out(addrgen_mask_status),                 // 1: mask register used
686
    .mask_alternative_out(addrgen_mask_alternative),       // mask register and fallback register used for alternative purposes
687
    .fallback_use_out(addrgen_fallback_use),               // 0: no fallback, 1: same as first source operand, 2-4: RU, RS, RT
688
    .num_operands_out(addrgen_num_operands),               // number of source operands
689
    .result_type_out(addrgen_result_type),                 // type of result: 0: register, 1: system register, 2: memory, 3: other or nothing
690
    .offset_field_out(addrgen_offset_field),               // address offset. 0: none, 1: 8 bit, possibly scaled, 2: 16 bit, 3: 32 bit
691
    .immediate_field_out(addrgen_immediate_field),         // immediate data field. 0: none, 1: 8 bit, 2: 16 bit, 3: 32 or 64 bit
692
    .scale_factor_out(addrgen_scale_factor),               // 00: index is not scaled, 01: index is scaled by operand size, 10: index is scaled by -1
693
    .memory_operand_out(addrgen_memory_operand),           // The instruction has a memory operand
694
    .array_error_out(addrgen_array_error),                 // Array index exceeds limit
695
    .options3_out(addrgen_options3),                       // IM3 containts option bits
696
    .debug1_out(addrgen_debug1),                           // Temporary output for debugging purpose
697
    .debug2_out(addrgen_debug2),                           // Temporary output for debugging purpose
698
    .debug3_out(addrgen_debug3)                            // Temporary output for debugging purpose
699
);
700
 
701
dataread dataread_inst (
702
    .clock(clock),                                         // system clock
703
    .clock_enable(clock_enable),                           // clock enable. Used when single-stepping
704
    .reset(system_reset),                                  // system reset.
705
    .valid_in(addrgen_valid),                              // data from fetch module ready
706
    .stall_in(dataread_stall_predict | alu_stall_next | muldiv_stall_next | inout_stall_next),   // pipeline is stalled
707
    .instruction_pointer_in(addrgen_instruction_pointer),  // address of current instruction
708
    .instruction_in(addrgen_instruction),                  // current instruction, up to 3 words long
709
    .tag_val_in(addrgen_tag_val),                          // instruction tag value
710
    .vector_in(addrgen_vector),                            // this is a vector instruction
711
    .category_in(addrgen_category),                        // 00: multiformat, 01: single format, 10: jump
712
    .format_in(addrgen_format),                            // 00: format A, 01: format E, 10: format B, 11: format C (format D never goes through decoder)
713
    .mask_status_in(addrgen_mask_status),                  // 1: mask register used
714
    .mask_alternative_in(addrgen_mask_alternative),        // mask register and fallback register used for alternative purposes
715
    .num_operands_in(addrgen_num_operands),                // number of source operands
716
    .result_type_in(addrgen_result_type),                  // type of result: 0: register, 1: system register, 2: memory, 3: other or nothing
717
    .immediate_field_in(addrgen_immediate_field),          // immediate data field. 0: none, 1: 8 bit, 2: 16 bit, 3: 32 or 64 bit
718
    .memory_operand_in(addrgen_memory_operand),            // the instruction has a memory operand
719
    .array_error_in(addrgen_array_error),                  // Array index exceeds limit
720
    .options3_in(addrgen_options3),                        // IM3 containts option bits
721
    .write_en1(bus1_write_en),                             // a result is written to bus 1
722
    .write_tag1_in(bus1_tag),                              // tag of result in bus 1
723
    .writeport1_in(bus1_value),                            // result bus 1
724
    .write_en2(bus2_write_en),                             // a result is written to bus 2
725
    .write_tag2_in(bus2_tag),                              // tag of result in bus 2
726
    .writeport2_in(bus2_value),                            // result bus 2
727
    .predict_tag1_in(predict_tag1),                        // result tag value on bus 1 in next clock cycle
728
    .predict_tag2_in(predict_tag2),                        // result tag value on bus 2 in next clock cycle
729
    .operand1_in(addrgen_operand1),                        // value of first operand
730
    .operand2_in(addrgen_operand2),                        // value of second operand
731
    .operand3_in(addrgen_operand3),                        // value of last operand
732
    .regmask_val_in(addrgen_regmask_val),                  // mask register
733
    .address_in(addrgen_read_write_address),               // address of memory operand
734
    .ram_data_in(data_memory_data),                        // memory operand from data memory
735
    .valid_out(dataread_valid),                            // An instruction is ready for output to next stage
736
    .instruction_pointer_out(dataread_instruction_pointer),// address of current instruction
737
    .instruction_out(dataread_instruction),                // first word of instruction
738
    .stall_predict_out(dataread_stall_predict),            // predict next stage will stall
739
    .tag_val_out(dataread_tag_val),                        // instruction tag value
740
    .operand1_out(dataread_operand1),                      // value of first operand for 3-op instructions, bit `RB is 0 if valid
741
    .operand2_out(dataread_operand2),                      // value of second operand, bit `RB is 0 if valid
742
    .operand3_out(dataread_operand3),                      // value of last operand, bit `RB is 0 if valid
743
    .mask_val_out(dataread_mask_val),                      // value of mask, bit 32 is 0 if valid
744
    .opr2_from_ram_out(dataread_opr2_from_ram),            // value of operand 2 comes from data memory
745
    .opr3_from_ram_out(dataread_opr3_from_ram),            // value of last operand comes from data memory
746
    .vector_out(dataread_vector),                          // this is a vector instruction
747
    .category_out(dataread_category),                      // 00: multiformat, 01: single format, 10: jump
748
    .format_out(dataread_format),                          // 00: format A, 01: format E, 10: format B, 11: format C (format D never goes through decoder)
749
    .num_operands_out(dataread_num_operands),              // number of source operands
750
    .result_type_out(dataread_result_type),                // type of result: 0: register, 1: system register, 2: memory, 3: other or nothing
751
    .opr1_used_out(dataread_opr1_used),                    // operand1 is needed
752
    .opr2_used_out(dataread_opr2_used),                    // operand2 is needed
753
    .opr3_used_out(dataread_opr3_used),                    // operand3 is needed
754
    .regmask_used_out(dataread_regmask_used),              // regmask_val_out is needed
755
    .mask_alternative_out(dataread_mask_alternative),      // mask register and fallback register used for alternative purposes
756
    .exe_unit_out(dataread_exe_unit),                      // each bit enables a particular execution unit
757
    .opx_out(dataread_opx),                                // operation ID in execution unit. This is mostly equal to op1 for multiformat instructions
758
    .opj_out(dataread_opj),                                // operation ID for conditional jump instructions
759
    .ot_out(dataread_ot),                                  // operand type
760
    .option_bits_out(dataread_option_bits),                // instruction option bits
761
    .im2_bits_out(dataread_im2_bits),                      // constant bits from IM2 as extra operand
762
    .trap_out(dataread_trap),                              // trap instruction detected
763
    .array_error_out(dataread_array_error),                // array index out of bounds
764
    .read_address_error_out(dataread_read_address_error),  // invalid read memory address
765
    .write_address_error_out(dataread_write_address_error),// invalid write memory address
766
    .misaligned_address_error_out(dataread_misaligned_address_error), // misaligned read/write memory address
767
    .debug_out(dataread_debug)                             // output for debugging
768
);
769
 
770
alu alu_inst (
771
    .clock(clock),                                         // system clock
772
    .clock_enable(clock_enable),                           // clock enable. Used when single-stepping
773
    .reset(system_reset),                                  // system reset.
774
    .valid_in(dataread_valid & dataread_exe_unit[0]),      // data from previous stage ready
775
    .stall_in(alu_stall_next | muldiv_stall_next | inout_stall_next),// pipeline is stalled
776
    .instruction_pointer_in(dataread_instruction_pointer), // address of current instruction
777
    .instruction_in(dataread_instruction),                 // current instruction, first word only
778
    .tag_val_in(dataread_tag_val),                         // instruction tag value
779
    .category_in(dataread_category),                       // 00: multiformat, 01: single format, 10: jump
780
    .mask_alternative_in(dataread_mask_alternative),       // mask register and fallback register used for alternative purposes
781
    .result_type_in(dataread_result_type),                 // type of result: 0: register, 1: system register, 2: memory, 3: other or nothing
782
    .vector_in(dataread_vector),                           // vector instruction
783
    .opx_in(dataread_opx),                                 // operation ID in execution unit. This is mostly equal to op1 for multiformat instructions
784
    .opj_in(dataread_opj),                                 // operation ID for conditional jump instructions
785
    .ot_in(dataread_ot),                                   // operand type
786
    .option_bits_in(dataread_option_bits),                 // option bits from IM3 or mask
787
    .im2_bits_in(dataread_im2_bits),                       // constant bits from IM2 as extra operand
788
 
789
    // monitor result buses:
790
    .write_en1(bus1_write_en),                             // a result is written to bus 1
791
    .write_tag1_in(bus1_tag),                              // tag of result in bus 1
792
    .writeport1_in(bus1_value),                            // result bus 1
793
    .write_en2(bus2_write_en),                             // a result is written to bus 2
794
    .write_tag2_in(bus2_tag),                              // tag of result in bus 2
795
    .writeport2_in(bus2_value),                            // result bus 2
796
    .predict_tag1_in(predict_tag1),                        // result tag value on bus 1 in next clock cycle
797
    .predict_tag2_in(predict_tag2),                        // result tag value on bus 2 in next clock cycle
798
    // Register values sampled from result bus in previous stages
799
    .operand1_in(dataread_operand1),                       // first operand or fallback value
800
    .operand2_in(dataread_operand2),                       // second operand value
801
    .operand3_in(dataread_operand3),                       // last operand value
802
    .regmask_val_in(dataread_mask_val),                    // mask register
803
    .ram_data_in(data_memory_data),                        // memory operand from data memory
804
    .opr2_from_ram_in(dataread_opr2_from_ram),             // value of operand 2 comes from data memory
805
    .opr3_from_ram_in(dataread_opr3_from_ram),             // value of last operand comes from data memory
806
    .opr1_used_in(dataread_opr1_used),                     // opr1_val_in is needed
807
    .opr2_used_in(dataread_opr2_used),                     // opr2_val_in is needed
808
    .opr3_used_in(dataread_opr3_used),                     // opr3_val_in is needed
809
    .regmask_used_in(dataread_regmask_used),               // regmask_val_in is needed
810
    .valid_out(alu_valid),                                 // alu is active
811
    .register_write_out(alu_write_en),                     // write enable for bus 1
812
    .register_a_out(alu_register_a),                       // register to write
813
    .result_out(alu_result),                               //
814
    .tag_val_out(alu_tag),                                 // instruction tag value
815
    .jump_out(alu_jump),                                   //  jump instruction: jump taken
816
    .nojump_out(alu_nojump),                               // jump instruction: jump not taken
817
    .jump_pointer_out(alu_jump_pointer),                   // jump target to fetch unit
818
    .stall_out(alu_stall),                                 // alu is waiting for an operand or not ready to receive a new instruction
819
    .stall_next_out(alu_stall_next),                       // alu will be waiting in next clock cycle
820
    .error_out(alu_error),                                 // unknown instruction
821
    .error_parm_out(alu_error_parm),                       // wrong parameter for instruction
822
    .debug1_out(alu_debug1),                               // debug information
823
    .debug2_out(alu_debug2)                                // debug information
824
);
825
 
826
mul_div muldiv_inst (
827
    .clock(clock),                                         // system clock
828
    .clock_enable(clock_enable),                           // clock enable. Used when single-stepping
829
    .reset(system_reset),                                  // system reset.
830
    .valid_in(dataread_valid & (dataread_exe_unit[1] | dataread_exe_unit[2])), // data from previous stage ready
831
    .stall_in(alu_stall_next | muldiv_stall_next | inout_stall_next),// pipeline is stalled
832
    .instruction_in(dataread_instruction[31:0]),           // current instruction, up to 3 words long
833
    .tag_val_in(dataread_tag_val),                         // instruction tag value
834
    .category_in(dataread_category),                       // 00: multiformat, 01: single format, 10: jump
835
    .mask_alternative_in(dataread_mask_alternative),       // mask register and fallback register used for alternative purposes
836
    .result_type_in(dataread_result_type),                 // type of result: 0: register, 1: system register, 2: memory, 3: other or nothing
837
    .vector_in(dataread_vector),                           // vector instruction
838
    .opx_in(dataread_opx),                                 // operation ID in execution unit. This is mostly equal to op1 for multiformat instructions
839
    .ot_in(dataread_ot),                                   // operand type
840
    .option_bits_in(dataread_option_bits),                 // option bits from IM3 or mask
841
 
842
    // monitor result buses:
843
    .write_en1(bus1_write_en),                             // a result is written to bus 1
844
    .write_tag1_in(bus1_tag),                              // tag of result in bus 1
845
    .writeport1_in(bus1_value),                            // result bus 1
846
    .write_en2(bus2_write_en),                             // a result is written to bus 2
847
    .write_tag2_in(bus2_tag),                              // tag of result in bus 2
848
    .writeport2_in(bus2_value),                            // result bus 2
849
    .predict_tag1_in(predict_tag1),                        // result tag value on bus 1 in next clock cycle
850
    .predict_tag2_in(predict_tag2),                        // result tag value on bus 2 in next clock cycle
851
    // Register values sampled from result bus in previous stages
852
    .operand1_in(dataread_operand1),                       // first operand or fallback value
853
    .operand2_in(dataread_operand2),                       // second operand value
854
    .operand3_in(dataread_operand3),                       // last operand value
855
    .regmask_val_in(dataread_mask_val),                    // mask register
856
    .ram_data_in(data_memory_data),                        // memory operand from data memory
857
    .opr2_from_ram_in(dataread_opr2_from_ram),             // value of operand 2 comes from data memory
858
    .opr3_from_ram_in(dataread_opr3_from_ram),             // value of last operand comes from data memory
859
    .opr1_used_in(dataread_opr1_used),                     // opr1_val_in is needed
860
    .opr2_used_in(dataread_opr2_used),                     // opr2_val_in is needed
861
    .opr3_used_in(dataread_opr3_used),                     // opr3_val_in is needed
862
    .regmask_used_in(dataread_regmask_used),               // regmask_val_in is needed
863
 
864
    .valid_out(muldiv_valid),                              // alu is active
865
    .register_write_out(muldiv_write_en),                  // write enable for bus 1
866
    .register_a_out(muldiv_register_a),                    // register to write
867
    .result_out(muldiv_result),                            //
868
    .tag_val_out(muldiv_tag),                              // instruction tag value
869
    .stall_out(muldiv_stall),                              // alu is waiting for an operand or not ready to receive a new instruction
870
    .stall_next_out(muldiv_stall_next),                    // alu will be waiting in next clock cycle
871
    .error_out(muldiv_error),                              // unknown instruction
872
    .error_parm_out(muldiv_error_parm),                    // wrong parameter for instruction
873
    .debug1_out(muldiv_debug1),                            // debug information
874
    .debug2_out(muldiv_debug2)                             // debug information
875
);
876
 
877
/***************************************************
878
       Input and output ports
879
***************************************************/
880
 
881
in_out_ports in_out_ports_inst (
882
    .clock(clock),                                         // system clock
883
    .clock_enable(clock_enable),                           // clock enable. Used when single-stepping
884
    .reset(system_reset),                                  // system reset
885
    .valid_in(dataread_valid & dataread_exe_unit[3]),      // data from previous stage ready
886
    .stall_in(alu_stall_next | muldiv_stall_next | inout_stall_next),// pipeline is stalled
887
    .instruction_in(dataread_instruction[31:0]),           // current instruction, up to 3 words long
888
    .tag_val_in(dataread_tag_val),                         // instruction tag value
889
    .category_in(dataread_category),                       // 00: multiformat, 01: single format, 10: jump
890
    .result_type_in(dataread_result_type),                 // type of result: 0: register, 1: system register, 2: memory, 3: other or nothing
891
    .mask_alternative_in(dataread_mask_alternative),       // mask register and fallback register used for alternative purposes
892
    .vector_in(dataread_vector),                           // vector instruction
893
    .opx_in(dataread_opx),                                 // operation ID in execution unit. This is mostly equal to op1 for multiformat instructions
894
    .opj_in(dataread_opj),                                 // operation ID for conditional jump instructions
895
    .ot_in(dataread_ot),                                   // operand type
896
    .regmask_used_in(dataread_regmask_used),               // regmask_val_in is needed
897
 
898
    // connections to UART
899
    .uart_bit_in(uart_txd_in),                             // serial input
900
    .uart_rts_in(uart_rts_in),                             // ready to send input
901
 
902
    // monitor result buses:
903
    .write_en1(bus1_write_en),                             // a result is written to bus 1
904
    .write_tag1_in(bus1_tag),                              // tag of result in bus 1
905
    .writeport1_in(bus1_value),                            // result bus 1
906
    .write_en2(bus2_write_en),                             // a result is written to bus 2
907
    .write_tag2_in(bus2_tag),                              // tag of result in bus 2
908
    .writeport2_in(bus2_value),                            // result bus 2
909
    .predict_tag1_in(predict_tag1),                        // result tag value on bus 1 in next clock cycle
910
    .predict_tag2_in(predict_tag2),                        // result tag value on bus 2 in next clock cycle
911
 
912
    // Register values sampled from result bus in previous stages
913
    .operand1_in(dataread_operand1),                       // first operand or fallback value
914
    .operand2_in(dataread_operand2),                       // second operand
915
    .operand3_in(dataread_operand3),                       // last operand
916
    .regmask_val_in(dataread_mask_val),                    // mask register
917
    .opr1_used_in(dataread_opr1_used),                     // opr1_val_in is needed
918
 
919
    // signals used for performance monitoring
920
    .instruction_valid_in(dataread_valid),                 // instruction is valid but possibly going to a different exe unit
921
    .fast_jump_in(fetch_jump),                             // a jump is bypassing the pipeline
922
    .errors_detect_in(errors_detect),                      // one bit for each type of error detected
923
    .fetch_instruction_pointer(fetch_instruction_pointer),
924
    .dataread_instruction_pointer(dataread_instruction_pointer),
925
    .dataread_valid(dataread_valid),                       // used when reconstructing alu_instruction_pointer
926
    .call_stack_overflow(call_stack_overflow),             // used for differentiating errors_detect_in[1]
927
    .clear_error_in(clear_error),                          // debug clear error
928
 
929
    // outputs
930
    .valid_out(inout_valid),                               // in_out is active
931
    .register_write_out(inout_write_en),
932
    .register_a_out(inout_register_a),                     // register to write
933
    .result_out(inout_result),
934
    .tag_val_out(inout_tag),                               // instruction tag value
935
    .nojump_out(inout_nojump),                             // serializing instruction finished
936
    .stall_out(inout_stal),                                // alu is waiting for an operand or not ready to receive a new instruction
937
    .stall_next_out(inout_stall_next),                     // alu will be waiting in next clock cycle
938
    .error_out(inout_error),                               // unknown instruction
939
    .error_parm_out(inout_error_parm),                     // wrong parameter for instruction
940
    .uart_bit_out(uart_rxd_out),                           // serial output
941
    .uart_cts_out(uart_cts_out),                           // clear to send output
942
    .capab_disable_errors(inout_capab_disable_errors),     // capab2 register: disable errors
943
    .first_error(inout_first_error),                       // error type for first error
944
    .first_error_address(inout_first_error_address),       // code address of first error
945
    .debug_out(inout_debug)                                // debug information
946
);
947
 
948
/***************************************************
949
       Debugging signals
950
***************************************************/
951
 
952
// debug display
953
debug_display debug_display_inst (
954
    .clock(clock),                                         // system clock (50 - 100 MHz)
955
    .clock_enable(clock_enable),                           // clock enable. Used when single-stepping
956
    .reset_button_debounced(reset_button_debounced),       // reset button
957
 
958
    // from fetch stage
959
    .fetch_instruction(fetch_instruction[63:0]),           // first words of instruction
960
    .fetch_instruction_pointer(fetch_instruction_pointer), // point to current instruction
961
    .fetch_valid(fetch_valid),                             // output from fetch is ready
962
    .fetch_jump(fetch_jump),                               // jump instruction bypassing pipeline
963
    .fetch_call_e(fetch_call_e),                           // executing call instruction
964
    .fetch_return_e(fetch_return_e),                       // executing return instruction
965
    .registerread_stall_predict(registerread_stall_predict),// address generation stalled next
966
    .addrgen_stall_next(addrgen_stall_next),
967
    .dataread_stall_predict(dataread_stall_predict),       // alu stalled next
968
    .alu_stall_next(alu_stall_next),                       // alu stalled next
969
    .muldiv_stall_next(muldiv_stall_next),                 // muldiv stalled next
970
    .inout_stall_next(inout_stall_next),                   // in_out_ports stalled next
971
    // from decoder
972
    .decoder_instruction(decoder_instruction[63:0]),       // first words of instruction
973
    .decoder_instruction_pointer(decoder_instruction_pointer), // address of current instruction
974
    .decoder_valid(decoder_valid),                         // output from decoder is ready
975
    // from register_read
976
    .registerread_instruction(registerread_instruction[63:0]), // first words of instruction
977
    .registerread_instruction_pointer(registerread_instruction_pointer), // address of current instruction
978
    .registerread_valid(registerread_valid),               // output from decode_wait is ready
979
    // from address generator
980
    .addrgen_instruction(addrgen_instruction[63:0]),       // first words of instruction
981
    .addrgen_instruction_pointer(addrgen_instruction_pointer), // address of current instruction
982
    .addrgen_valid(addrgen_valid),                         // output from addrgen is ready
983
    // from address_wait
984
    .dataread_instruction(dataread_instruction),           // first words of instruction
985
    .dataread_instruction_pointer(dataread_instruction_pointer), // address of current instruction
986
    .dataread_opx(dataread_opx),                           // operation ID in execution unit. This is mostly equal to op1 for multiformat instructions
987
    .dataread_valid(dataread_valid),                       // output from addrwait is ready
988
    .dataread_operand1(dataread_operand1),                 // first register operand RD or RU
989
    .dataread_operand2(dataread_operand2),                 // second register operand RS
990
    .dataread_operand3(dataread_operand3),                 // last register operand RT
991
    .dataread_mask_val(dataread_mask_val),                 // mask register value
992
    .ram_data_in(data_memory_data[15:0]),                  // memory operand from data memory
993
    .dataread_opr2_from_ram(dataread_opr2_from_ram),       // value of operand 2 comes from data ram
994
    .dataread_opr3_from_ram(dataread_opr3_from_ram),       // value of last operand comes from data ram
995
 
996
    // from ALU
997
    //.writea1(bus1_register_a),                           // register to write
998
    .alu_result(bus1_value[31:0]),                         //
999
    .write_tag1(bus1_tag),
1000
    .alu_valid(alu_valid | muldiv_valid | inout_valid),    // alu or in_out is ready
1001
    .alu_jump(alu_jump),                                   // jump instruction: jump taken
1002
    //.alu_nojump(alu_nojump),                             // jump instruction: jump not taken
1003
    .alu_jump_pointer(alu_jump_pointer),
1004
 
1005
    // from result buses
1006
    .writeport2(bus2_value[31:0]),
1007
    .write_en2(bus2_write_en),
1008
    .write_tag2(bus2_tag),
1009
 
1010
    // output to display
1011
    .lcd_rs(lcd_rs),                                       // LCD RS pin
1012
    .lcd_e(lcd_e),                                         // enable pins for two LCD displays
1013
    .lcd_data(lcd_data)                                    // LCD data, 4 bit bus
1014
);
1015
 
1016
 
1017
`include "debugger.vh"
1018
 
1019
assign led0 = load_button_debounced;
1020
assign led1 = reset_button_debounced;
1021
assign led2 = run_button_debounced;
1022
assign led3 = step_button_debounced;
1023
 
1024
assign led4 = fetch_call_e;                                // vacant. connected to something just to avoid warning
1025
assign led5 = fetch_return_e;
1026
assign led6 = fetch_valid;
1027
assign led7 = system_reset;
1028
 
1029
/*
1030
assign led12 = registerread_stall_predict;
1031
assign led13 = addrgen_stall_next;
1032
assign led14 = dataread_stall_predict;
1033
assign led15 = alu_stall_next;
1034
*/
1035
// temporary led assignments
1036
assign led12 = call_stack_overflow;
1037
assign led13 = alu_error_parm | muldiv_error_parm;
1038
assign led14 = inout_error_parm;
1039
assign led15 = show_error;
1040
 
1041
// RGB led
1042
assign led16R = color_led16[0];
1043
assign led16G = color_led16[1];
1044
assign led16B = color_led16[2];
1045
 
1046
endmodule

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