OpenCores
URL https://opencores.org/ocsvn/fp_log/fp_log/trunk

Subversion Repositories fp_log

[/] [fp_log/] [trunk/] [LAU/] [Virtex 4/] [DP-LAU/] [reg_32b_8c.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 NikosAl 
--------------------------------------------------------------------------------
2 
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
3 
--------------------------------------------------------------------------------
4 
--   ____  ____
5 
--  /   /\/   /
6 
-- /___/  \  /    Vendor: Xilinx
7 
-- \   \   \/     Version: K.39
8 
--  \   \         Application: netgen
9 
--  /   /         Filename: reg_32b_8c.vhd
10 
-- /___/   /\     Timestamp: Fri Sep 18 14:35:09 2009
11 
-- \   \  /  \
12 
--  \___\/\___\
13 
--
14 
-- Command      : -intstyle ise -w -sim -ofmt vhdl "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\reg_32b_8c.ngc" "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\reg_32b_8c.vhd"
15 
-- Device       : 5vsx95tff1136-2
16 
-- Input file   : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/reg_32b_8c.ngc
17 
-- Output file  : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/reg_32b_8c.vhd
18 
-- # of Entities        : 1
19 
-- Design Name  : reg_32b_8c
20 
-- Xilinx       : C:\Xilinx\10.1\ISE
21 
--
22 
-- Purpose:
23 
--     This VHDL netlist is a verification model and uses simulation
24 
--     primitives which may not represent the true implementation of the
25 
--     device, however the netlist is functionally correct and should not
26 
--     be modified. This file cannot be synthesized and should only be used
27 
--     with supported simulation tools.
28 
--
29 
-- Reference:
30 
--     Development System Reference Guide, Chapter 23
31 
--     Synthesis and Simulation Design Guide, Chapter 6
32 
--
33 
--------------------------------------------------------------------------------
34 
 
35 
 
36 
-- synthesis translate_off
37 
library IEEE;
38 
use IEEE.STD_LOGIC_1164.ALL;
39 
library UNISIM;
40 
use UNISIM.VCOMPONENTS.ALL;
41 
use UNISIM.VPKG.ALL;
42 
 
43 
entity reg_32b_8c is
44 
  port (
45 
    sclr : in STD_LOGIC := 'X';
46 
    clk : in STD_LOGIC := 'X';
47 
    d : in STD_LOGIC_VECTOR ( 31 downto 0 );
48 
    q : out STD_LOGIC_VECTOR ( 31 downto 0 )
49 
  );
50 
end reg_32b_8c;
51 
 
52 
architecture STRUCTURE of reg_32b_8c is
53 
  signal BU2_sset : STD_LOGIC;
54 
  signal BU2_sinit : STD_LOGIC;
55 
  signal BU2_ainit : STD_LOGIC;
56 
  signal BU2_aclr : STD_LOGIC;
57 
  signal BU2_ce : STD_LOGIC;
58 
  signal BU2_aset : STD_LOGIC;
59 
  signal BU2_U0_Mshreg_srl_sig_7_31_131 : STD_LOGIC;
60 
  signal BU2_U0_Mshreg_srl_sig_7_30_130 : STD_LOGIC;
61 
  signal BU2_U0_Mshreg_srl_sig_7_29_129 : STD_LOGIC;
62 
  signal BU2_U0_Mshreg_srl_sig_7_28_128 : STD_LOGIC;
63 
  signal BU2_U0_Mshreg_srl_sig_7_27_127 : STD_LOGIC;
64 
  signal BU2_U0_Mshreg_srl_sig_7_26_126 : STD_LOGIC;
65 
  signal BU2_U0_Mshreg_srl_sig_7_25_125 : STD_LOGIC;
66 
  signal BU2_U0_Mshreg_srl_sig_7_24_124 : STD_LOGIC;
67 
  signal BU2_U0_Mshreg_srl_sig_7_23_123 : STD_LOGIC;
68 
  signal BU2_U0_Mshreg_srl_sig_7_22_122 : STD_LOGIC;
69 
  signal BU2_U0_Mshreg_srl_sig_7_21_121 : STD_LOGIC;
70 
  signal BU2_U0_Mshreg_srl_sig_7_20_120 : STD_LOGIC;
71 
  signal BU2_U0_Mshreg_srl_sig_7_19_119 : STD_LOGIC;
72 
  signal BU2_U0_Mshreg_srl_sig_7_18_118 : STD_LOGIC;
73 
  signal BU2_U0_Mshreg_srl_sig_7_17_117 : STD_LOGIC;
74 
  signal BU2_U0_Mshreg_srl_sig_7_16_116 : STD_LOGIC;
75 
  signal BU2_U0_Mshreg_srl_sig_7_15_115 : STD_LOGIC;
76 
  signal BU2_U0_Mshreg_srl_sig_7_14_114 : STD_LOGIC;
77 
  signal BU2_U0_Mshreg_srl_sig_7_13_113 : STD_LOGIC;
78 
  signal BU2_U0_Mshreg_srl_sig_7_12_112 : STD_LOGIC;
79 
  signal BU2_U0_Mshreg_srl_sig_7_11_111 : STD_LOGIC;
80 
  signal BU2_U0_Mshreg_srl_sig_7_10_110 : STD_LOGIC;
81 
  signal BU2_U0_Mshreg_srl_sig_7_9_109 : STD_LOGIC;
82 
  signal BU2_U0_Mshreg_srl_sig_7_8_108 : STD_LOGIC;
83 
  signal BU2_U0_Mshreg_srl_sig_7_7_107 : STD_LOGIC;
84 
  signal BU2_U0_Mshreg_srl_sig_7_6_106 : STD_LOGIC;
85 
  signal BU2_U0_Mshreg_srl_sig_7_5_105 : STD_LOGIC;
86 
  signal BU2_U0_Mshreg_srl_sig_7_4_104 : STD_LOGIC;
87 
  signal BU2_U0_Mshreg_srl_sig_7_3_103 : STD_LOGIC;
88 
  signal BU2_U0_Mshreg_srl_sig_7_2_102 : STD_LOGIC;
89 
  signal BU2_U0_Mshreg_srl_sig_7_1_101 : STD_LOGIC;
90 
  signal BU2_U0_Mshreg_srl_sig_7_0_100 : STD_LOGIC;
91 
  signal BU2_U0_N1 : STD_LOGIC;
92 
  signal BU2_U0_N0 : STD_LOGIC;
93 
  signal BU2_U0_srl_sig_7_31_97 : STD_LOGIC;
94 
  signal BU2_U0_srl_sig_7_30_96 : STD_LOGIC;
95 
  signal BU2_U0_srl_sig_7_29_95 : STD_LOGIC;
96 
  signal BU2_U0_srl_sig_7_28_94 : STD_LOGIC;
97 
  signal BU2_U0_srl_sig_7_27_93 : STD_LOGIC;
98 
  signal BU2_U0_srl_sig_7_26_92 : STD_LOGIC;
99 
  signal BU2_U0_srl_sig_7_25_91 : STD_LOGIC;
100 
  signal BU2_U0_srl_sig_7_24_90 : STD_LOGIC;
101 
  signal BU2_U0_srl_sig_7_23_89 : STD_LOGIC;
102 
  signal BU2_U0_srl_sig_7_22_88 : STD_LOGIC;
103 
  signal BU2_U0_srl_sig_7_21_87 : STD_LOGIC;
104 
  signal BU2_U0_srl_sig_7_20_86 : STD_LOGIC;
105 
  signal BU2_U0_srl_sig_7_19_85 : STD_LOGIC;
106 
  signal BU2_U0_srl_sig_7_18_84 : STD_LOGIC;
107 
  signal BU2_U0_srl_sig_7_17_83 : STD_LOGIC;
108 
  signal BU2_U0_srl_sig_7_16_82 : STD_LOGIC;
109 
  signal BU2_U0_srl_sig_7_15_81 : STD_LOGIC;
110 
  signal BU2_U0_srl_sig_7_14_80 : STD_LOGIC;
111 
  signal BU2_U0_srl_sig_7_13_79 : STD_LOGIC;
112 
  signal BU2_U0_srl_sig_7_12_78 : STD_LOGIC;
113 
  signal BU2_U0_srl_sig_7_11_77 : STD_LOGIC;
114 
  signal BU2_U0_srl_sig_7_10_76 : STD_LOGIC;
115 
  signal BU2_U0_srl_sig_7_9_75 : STD_LOGIC;
116 
  signal BU2_U0_srl_sig_7_8_74 : STD_LOGIC;
117 
  signal BU2_U0_srl_sig_7_7_73 : STD_LOGIC;
118 
  signal BU2_U0_srl_sig_7_6_72 : STD_LOGIC;
119 
  signal BU2_U0_srl_sig_7_5_71 : STD_LOGIC;
120 
  signal BU2_U0_srl_sig_7_4_70 : STD_LOGIC;
121 
  signal BU2_U0_srl_sig_7_3_69 : STD_LOGIC;
122 
  signal BU2_U0_srl_sig_7_2_68 : STD_LOGIC;
123 
  signal BU2_U0_srl_sig_7_1_67 : STD_LOGIC;
124 
  signal BU2_U0_srl_sig_7_0_66 : STD_LOGIC;
125 
  signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
126 
  signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
127 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_31_Q15_UNCONNECTED : STD_LOGIC;
128 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_30_Q15_UNCONNECTED : STD_LOGIC;
129 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_29_Q15_UNCONNECTED : STD_LOGIC;
130 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_28_Q15_UNCONNECTED : STD_LOGIC;
131 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_27_Q15_UNCONNECTED : STD_LOGIC;
132 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_26_Q15_UNCONNECTED : STD_LOGIC;
133 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_25_Q15_UNCONNECTED : STD_LOGIC;
134 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_24_Q15_UNCONNECTED : STD_LOGIC;
135 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_23_Q15_UNCONNECTED : STD_LOGIC;
136 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_22_Q15_UNCONNECTED : STD_LOGIC;
137 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_21_Q15_UNCONNECTED : STD_LOGIC;
138 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_20_Q15_UNCONNECTED : STD_LOGIC;
139 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_19_Q15_UNCONNECTED : STD_LOGIC;
140 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_18_Q15_UNCONNECTED : STD_LOGIC;
141 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_17_Q15_UNCONNECTED : STD_LOGIC;
142 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_16_Q15_UNCONNECTED : STD_LOGIC;
143 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_15_Q15_UNCONNECTED : STD_LOGIC;
144 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_14_Q15_UNCONNECTED : STD_LOGIC;
145 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_13_Q15_UNCONNECTED : STD_LOGIC;
146 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_12_Q15_UNCONNECTED : STD_LOGIC;
147 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_11_Q15_UNCONNECTED : STD_LOGIC;
148 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_10_Q15_UNCONNECTED : STD_LOGIC;
149 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_9_Q15_UNCONNECTED : STD_LOGIC;
150 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_8_Q15_UNCONNECTED : STD_LOGIC;
151 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_7_Q15_UNCONNECTED : STD_LOGIC;
152 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_6_Q15_UNCONNECTED : STD_LOGIC;
153 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_5_Q15_UNCONNECTED : STD_LOGIC;
154 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_4_Q15_UNCONNECTED : STD_LOGIC;
155 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_3_Q15_UNCONNECTED : STD_LOGIC;
156 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_2_Q15_UNCONNECTED : STD_LOGIC;
157 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_1_Q15_UNCONNECTED : STD_LOGIC;
158 
  signal NLW_BU2_U0_Mshreg_srl_sig_7_0_Q15_UNCONNECTED : STD_LOGIC;
159 
  signal d_2 : STD_LOGIC_VECTOR ( 31 downto 0 );
160 
  signal q_3 : STD_LOGIC_VECTOR ( 31 downto 0 );
161 
  signal BU2_a : STD_LOGIC_VECTOR ( 3 downto 0 );
162 
begin
163 
  d_2(31) <= d(31);
164 
  d_2(30) <= d(30);
165 
  d_2(29) <= d(29);
166 
  d_2(28) <= d(28);
167 
  d_2(27) <= d(27);
168 
  d_2(26) <= d(26);
169 
  d_2(25) <= d(25);
170 
  d_2(24) <= d(24);
171 
  d_2(23) <= d(23);
172 
  d_2(22) <= d(22);
173 
  d_2(21) <= d(21);
174 
  d_2(20) <= d(20);
175 
  d_2(19) <= d(19);
176 
  d_2(18) <= d(18);
177 
  d_2(17) <= d(17);
178 
  d_2(16) <= d(16);
179 
  d_2(15) <= d(15);
180 
  d_2(14) <= d(14);
181 
  d_2(13) <= d(13);
182 
  d_2(12) <= d(12);
183 
  d_2(11) <= d(11);
184 
  d_2(10) <= d(10);
185 
  d_2(9) <= d(9);
186 
  d_2(8) <= d(8);
187 
  d_2(7) <= d(7);
188 
  d_2(6) <= d(6);
189 
  d_2(5) <= d(5);
190 
  d_2(4) <= d(4);
191 
  d_2(3) <= d(3);
192 
  d_2(2) <= d(2);
193 
  d_2(1) <= d(1);
194 
  d_2(0) <= d(0);
195 
  q(31) <= q_3(31);
196 
  q(30) <= q_3(30);
197 
  q(29) <= q_3(29);
198 
  q(28) <= q_3(28);
199 
  q(27) <= q_3(27);
200 
  q(26) <= q_3(26);
201 
  q(25) <= q_3(25);
202 
  q(24) <= q_3(24);
203 
  q(23) <= q_3(23);
204 
  q(22) <= q_3(22);
205 
  q(21) <= q_3(21);
206 
  q(20) <= q_3(20);
207 
  q(19) <= q_3(19);
208 
  q(18) <= q_3(18);
209 
  q(17) <= q_3(17);
210 
  q(16) <= q_3(16);
211 
  q(15) <= q_3(15);
212 
  q(14) <= q_3(14);
213 
  q(13) <= q_3(13);
214 
  q(12) <= q_3(12);
215 
  q(11) <= q_3(11);
216 
  q(10) <= q_3(10);
217 
  q(9) <= q_3(9);
218 
  q(8) <= q_3(8);
219 
  q(7) <= q_3(7);
220 
  q(6) <= q_3(6);
221 
  q(5) <= q_3(5);
222 
  q(4) <= q_3(4);
223 
  q(3) <= q_3(3);
224 
  q(2) <= q_3(2);
225 
  q(1) <= q_3(1);
226 
  q(0) <= q_3(0);
227 
  VCC_0 : VCC
228 
    port map (
229 
      P => NLW_VCC_P_UNCONNECTED
230 
    );
231 
  GND_1 : GND
232 
    port map (
233 
      G => NLW_GND_G_UNCONNECTED
234 
    );
235 
  BU2_U0_srl_sig_7_31 : FDE
236 
    generic map(
237 
      INIT => '0'
238 
    )
239 
    port map (
240 
      C => clk,
241 
      CE => BU2_U0_N1,
242 
      D => BU2_U0_Mshreg_srl_sig_7_31_131,
243 
      Q => BU2_U0_srl_sig_7_31_97
244 
    );
245 
  BU2_U0_Mshreg_srl_sig_7_31 : SRLC16E
246 
    generic map(
247 
      INIT => X"0000"
248 
    )
249 
    port map (
250 
      A0 => BU2_U0_N0,
251 
      A1 => BU2_U0_N1,
252 
      A2 => BU2_U0_N1,
253 
      A3 => BU2_U0_N0,
254 
      CE => BU2_U0_N1,
255 
      CLK => clk,
256 
      D => d_2(31),
257 
      Q => BU2_U0_Mshreg_srl_sig_7_31_131,
258 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_31_Q15_UNCONNECTED
259 
    );
260 
  BU2_U0_srl_sig_7_30 : FDE
261 
    generic map(
262 
      INIT => '0'
263 
    )
264 
    port map (
265 
      C => clk,
266 
      CE => BU2_U0_N1,
267 
      D => BU2_U0_Mshreg_srl_sig_7_30_130,
268 
      Q => BU2_U0_srl_sig_7_30_96
269 
    );
270 
  BU2_U0_Mshreg_srl_sig_7_30 : SRLC16E
271 
    generic map(
272 
      INIT => X"0000"
273 
    )
274 
    port map (
275 
      A0 => BU2_U0_N0,
276 
      A1 => BU2_U0_N1,
277 
      A2 => BU2_U0_N1,
278 
      A3 => BU2_U0_N0,
279 
      CE => BU2_U0_N1,
280 
      CLK => clk,
281 
      D => d_2(30),
282 
      Q => BU2_U0_Mshreg_srl_sig_7_30_130,
283 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_30_Q15_UNCONNECTED
284 
    );
285 
  BU2_U0_srl_sig_7_29 : FDE
286 
    generic map(
287 
      INIT => '0'
288 
    )
289 
    port map (
290 
      C => clk,
291 
      CE => BU2_U0_N1,
292 
      D => BU2_U0_Mshreg_srl_sig_7_29_129,
293 
      Q => BU2_U0_srl_sig_7_29_95
294 
    );
295 
  BU2_U0_Mshreg_srl_sig_7_29 : SRLC16E
296 
    generic map(
297 
      INIT => X"0000"
298 
    )
299 
    port map (
300 
      A0 => BU2_U0_N0,
301 
      A1 => BU2_U0_N1,
302 
      A2 => BU2_U0_N1,
303 
      A3 => BU2_U0_N0,
304 
      CE => BU2_U0_N1,
305 
      CLK => clk,
306 
      D => d_2(29),
307 
      Q => BU2_U0_Mshreg_srl_sig_7_29_129,
308 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_29_Q15_UNCONNECTED
309 
    );
310 
  BU2_U0_srl_sig_7_28 : FDE
311 
    generic map(
312 
      INIT => '0'
313 
    )
314 
    port map (
315 
      C => clk,
316 
      CE => BU2_U0_N1,
317 
      D => BU2_U0_Mshreg_srl_sig_7_28_128,
318 
      Q => BU2_U0_srl_sig_7_28_94
319 
    );
320 
  BU2_U0_Mshreg_srl_sig_7_28 : SRLC16E
321 
    generic map(
322 
      INIT => X"0000"
323 
    )
324 
    port map (
325 
      A0 => BU2_U0_N0,
326 
      A1 => BU2_U0_N1,
327 
      A2 => BU2_U0_N1,
328 
      A3 => BU2_U0_N0,
329 
      CE => BU2_U0_N1,
330 
      CLK => clk,
331 
      D => d_2(28),
332 
      Q => BU2_U0_Mshreg_srl_sig_7_28_128,
333 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_28_Q15_UNCONNECTED
334 
    );
335 
  BU2_U0_srl_sig_7_27 : FDE
336 
    generic map(
337 
      INIT => '0'
338 
    )
339 
    port map (
340 
      C => clk,
341 
      CE => BU2_U0_N1,
342 
      D => BU2_U0_Mshreg_srl_sig_7_27_127,
343 
      Q => BU2_U0_srl_sig_7_27_93
344 
    );
345 
  BU2_U0_Mshreg_srl_sig_7_27 : SRLC16E
346 
    generic map(
347 
      INIT => X"0000"
348 
    )
349 
    port map (
350 
      A0 => BU2_U0_N0,
351 
      A1 => BU2_U0_N1,
352 
      A2 => BU2_U0_N1,
353 
      A3 => BU2_U0_N0,
354 
      CE => BU2_U0_N1,
355 
      CLK => clk,
356 
      D => d_2(27),
357 
      Q => BU2_U0_Mshreg_srl_sig_7_27_127,
358 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_27_Q15_UNCONNECTED
359 
    );
360 
  BU2_U0_srl_sig_7_26 : FDE
361 
    generic map(
362 
      INIT => '0'
363 
    )
364 
    port map (
365 
      C => clk,
366 
      CE => BU2_U0_N1,
367 
      D => BU2_U0_Mshreg_srl_sig_7_26_126,
368 
      Q => BU2_U0_srl_sig_7_26_92
369 
    );
370 
  BU2_U0_Mshreg_srl_sig_7_26 : SRLC16E
371 
    generic map(
372 
      INIT => X"0000"
373 
    )
374 
    port map (
375 
      A0 => BU2_U0_N0,
376 
      A1 => BU2_U0_N1,
377 
      A2 => BU2_U0_N1,
378 
      A3 => BU2_U0_N0,
379 
      CE => BU2_U0_N1,
380 
      CLK => clk,
381 
      D => d_2(26),
382 
      Q => BU2_U0_Mshreg_srl_sig_7_26_126,
383 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_26_Q15_UNCONNECTED
384 
    );
385 
  BU2_U0_srl_sig_7_25 : FDE
386 
    generic map(
387 
      INIT => '0'
388 
    )
389 
    port map (
390 
      C => clk,
391 
      CE => BU2_U0_N1,
392 
      D => BU2_U0_Mshreg_srl_sig_7_25_125,
393 
      Q => BU2_U0_srl_sig_7_25_91
394 
    );
395 
  BU2_U0_Mshreg_srl_sig_7_25 : SRLC16E
396 
    generic map(
397 
      INIT => X"0000"
398 
    )
399 
    port map (
400 
      A0 => BU2_U0_N0,
401 
      A1 => BU2_U0_N1,
402 
      A2 => BU2_U0_N1,
403 
      A3 => BU2_U0_N0,
404 
      CE => BU2_U0_N1,
405 
      CLK => clk,
406 
      D => d_2(25),
407 
      Q => BU2_U0_Mshreg_srl_sig_7_25_125,
408 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_25_Q15_UNCONNECTED
409 
    );
410 
  BU2_U0_srl_sig_7_24 : FDE
411 
    generic map(
412 
      INIT => '0'
413 
    )
414 
    port map (
415 
      C => clk,
416 
      CE => BU2_U0_N1,
417 
      D => BU2_U0_Mshreg_srl_sig_7_24_124,
418 
      Q => BU2_U0_srl_sig_7_24_90
419 
    );
420 
  BU2_U0_Mshreg_srl_sig_7_24 : SRLC16E
421 
    generic map(
422 
      INIT => X"0000"
423 
    )
424 
    port map (
425 
      A0 => BU2_U0_N0,
426 
      A1 => BU2_U0_N1,
427 
      A2 => BU2_U0_N1,
428 
      A3 => BU2_U0_N0,
429 
      CE => BU2_U0_N1,
430 
      CLK => clk,
431 
      D => d_2(24),
432 
      Q => BU2_U0_Mshreg_srl_sig_7_24_124,
433 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_24_Q15_UNCONNECTED
434 
    );
435 
  BU2_U0_srl_sig_7_23 : FDE
436 
    generic map(
437 
      INIT => '0'
438 
    )
439 
    port map (
440 
      C => clk,
441 
      CE => BU2_U0_N1,
442 
      D => BU2_U0_Mshreg_srl_sig_7_23_123,
443 
      Q => BU2_U0_srl_sig_7_23_89
444 
    );
445 
  BU2_U0_Mshreg_srl_sig_7_23 : SRLC16E
446 
    generic map(
447 
      INIT => X"0000"
448 
    )
449 
    port map (
450 
      A0 => BU2_U0_N0,
451 
      A1 => BU2_U0_N1,
452 
      A2 => BU2_U0_N1,
453 
      A3 => BU2_U0_N0,
454 
      CE => BU2_U0_N1,
455 
      CLK => clk,
456 
      D => d_2(23),
457 
      Q => BU2_U0_Mshreg_srl_sig_7_23_123,
458 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_23_Q15_UNCONNECTED
459 
    );
460 
  BU2_U0_srl_sig_7_22 : FDE
461 
    generic map(
462 
      INIT => '0'
463 
    )
464 
    port map (
465 
      C => clk,
466 
      CE => BU2_U0_N1,
467 
      D => BU2_U0_Mshreg_srl_sig_7_22_122,
468 
      Q => BU2_U0_srl_sig_7_22_88
469 
    );
470 
  BU2_U0_Mshreg_srl_sig_7_22 : SRLC16E
471 
    generic map(
472 
      INIT => X"0000"
473 
    )
474 
    port map (
475 
      A0 => BU2_U0_N0,
476 
      A1 => BU2_U0_N1,
477 
      A2 => BU2_U0_N1,
478 
      A3 => BU2_U0_N0,
479 
      CE => BU2_U0_N1,
480 
      CLK => clk,
481 
      D => d_2(22),
482 
      Q => BU2_U0_Mshreg_srl_sig_7_22_122,
483 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_22_Q15_UNCONNECTED
484 
    );
485 
  BU2_U0_srl_sig_7_21 : FDE
486 
    generic map(
487 
      INIT => '0'
488 
    )
489 
    port map (
490 
      C => clk,
491 
      CE => BU2_U0_N1,
492 
      D => BU2_U0_Mshreg_srl_sig_7_21_121,
493 
      Q => BU2_U0_srl_sig_7_21_87
494 
    );
495 
  BU2_U0_Mshreg_srl_sig_7_21 : SRLC16E
496 
    generic map(
497 
      INIT => X"0000"
498 
    )
499 
    port map (
500 
      A0 => BU2_U0_N0,
501 
      A1 => BU2_U0_N1,
502 
      A2 => BU2_U0_N1,
503 
      A3 => BU2_U0_N0,
504 
      CE => BU2_U0_N1,
505 
      CLK => clk,
506 
      D => d_2(21),
507 
      Q => BU2_U0_Mshreg_srl_sig_7_21_121,
508 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_21_Q15_UNCONNECTED
509 
    );
510 
  BU2_U0_srl_sig_7_20 : FDE
511 
    generic map(
512 
      INIT => '0'
513 
    )
514 
    port map (
515 
      C => clk,
516 
      CE => BU2_U0_N1,
517 
      D => BU2_U0_Mshreg_srl_sig_7_20_120,
518 
      Q => BU2_U0_srl_sig_7_20_86
519 
    );
520 
  BU2_U0_Mshreg_srl_sig_7_20 : SRLC16E
521 
    generic map(
522 
      INIT => X"0000"
523 
    )
524 
    port map (
525 
      A0 => BU2_U0_N0,
526 
      A1 => BU2_U0_N1,
527 
      A2 => BU2_U0_N1,
528 
      A3 => BU2_U0_N0,
529 
      CE => BU2_U0_N1,
530 
      CLK => clk,
531 
      D => d_2(20),
532 
      Q => BU2_U0_Mshreg_srl_sig_7_20_120,
533 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_20_Q15_UNCONNECTED
534 
    );
535 
  BU2_U0_srl_sig_7_19 : FDE
536 
    generic map(
537 
      INIT => '0'
538 
    )
539 
    port map (
540 
      C => clk,
541 
      CE => BU2_U0_N1,
542 
      D => BU2_U0_Mshreg_srl_sig_7_19_119,
543 
      Q => BU2_U0_srl_sig_7_19_85
544 
    );
545 
  BU2_U0_Mshreg_srl_sig_7_19 : SRLC16E
546 
    generic map(
547 
      INIT => X"0000"
548 
    )
549 
    port map (
550 
      A0 => BU2_U0_N0,
551 
      A1 => BU2_U0_N1,
552 
      A2 => BU2_U0_N1,
553 
      A3 => BU2_U0_N0,
554 
      CE => BU2_U0_N1,
555 
      CLK => clk,
556 
      D => d_2(19),
557 
      Q => BU2_U0_Mshreg_srl_sig_7_19_119,
558 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_19_Q15_UNCONNECTED
559 
    );
560 
  BU2_U0_srl_sig_7_18 : FDE
561 
    generic map(
562 
      INIT => '0'
563 
    )
564 
    port map (
565 
      C => clk,
566 
      CE => BU2_U0_N1,
567 
      D => BU2_U0_Mshreg_srl_sig_7_18_118,
568 
      Q => BU2_U0_srl_sig_7_18_84
569 
    );
570 
  BU2_U0_Mshreg_srl_sig_7_18 : SRLC16E
571 
    generic map(
572 
      INIT => X"0000"
573 
    )
574 
    port map (
575 
      A0 => BU2_U0_N0,
576 
      A1 => BU2_U0_N1,
577 
      A2 => BU2_U0_N1,
578 
      A3 => BU2_U0_N0,
579 
      CE => BU2_U0_N1,
580 
      CLK => clk,
581 
      D => d_2(18),
582 
      Q => BU2_U0_Mshreg_srl_sig_7_18_118,
583 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_18_Q15_UNCONNECTED
584 
    );
585 
  BU2_U0_srl_sig_7_17 : FDE
586 
    generic map(
587 
      INIT => '0'
588 
    )
589 
    port map (
590 
      C => clk,
591 
      CE => BU2_U0_N1,
592 
      D => BU2_U0_Mshreg_srl_sig_7_17_117,
593 
      Q => BU2_U0_srl_sig_7_17_83
594 
    );
595 
  BU2_U0_Mshreg_srl_sig_7_17 : SRLC16E
596 
    generic map(
597 
      INIT => X"0000"
598 
    )
599 
    port map (
600 
      A0 => BU2_U0_N0,
601 
      A1 => BU2_U0_N1,
602 
      A2 => BU2_U0_N1,
603 
      A3 => BU2_U0_N0,
604 
      CE => BU2_U0_N1,
605 
      CLK => clk,
606 
      D => d_2(17),
607 
      Q => BU2_U0_Mshreg_srl_sig_7_17_117,
608 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_17_Q15_UNCONNECTED
609 
    );
610 
  BU2_U0_srl_sig_7_16 : FDE
611 
    generic map(
612 
      INIT => '0'
613 
    )
614 
    port map (
615 
      C => clk,
616 
      CE => BU2_U0_N1,
617 
      D => BU2_U0_Mshreg_srl_sig_7_16_116,
618 
      Q => BU2_U0_srl_sig_7_16_82
619 
    );
620 
  BU2_U0_Mshreg_srl_sig_7_16 : SRLC16E
621 
    generic map(
622 
      INIT => X"0000"
623 
    )
624 
    port map (
625 
      A0 => BU2_U0_N0,
626 
      A1 => BU2_U0_N1,
627 
      A2 => BU2_U0_N1,
628 
      A3 => BU2_U0_N0,
629 
      CE => BU2_U0_N1,
630 
      CLK => clk,
631 
      D => d_2(16),
632 
      Q => BU2_U0_Mshreg_srl_sig_7_16_116,
633 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_16_Q15_UNCONNECTED
634 
    );
635 
  BU2_U0_srl_sig_7_15 : FDE
636 
    generic map(
637 
      INIT => '0'
638 
    )
639 
    port map (
640 
      C => clk,
641 
      CE => BU2_U0_N1,
642 
      D => BU2_U0_Mshreg_srl_sig_7_15_115,
643 
      Q => BU2_U0_srl_sig_7_15_81
644 
    );
645 
  BU2_U0_Mshreg_srl_sig_7_15 : SRLC16E
646 
    generic map(
647 
      INIT => X"0000"
648 
    )
649 
    port map (
650 
      A0 => BU2_U0_N0,
651 
      A1 => BU2_U0_N1,
652 
      A2 => BU2_U0_N1,
653 
      A3 => BU2_U0_N0,
654 
      CE => BU2_U0_N1,
655 
      CLK => clk,
656 
      D => d_2(15),
657 
      Q => BU2_U0_Mshreg_srl_sig_7_15_115,
658 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_15_Q15_UNCONNECTED
659 
    );
660 
  BU2_U0_srl_sig_7_14 : FDE
661 
    generic map(
662 
      INIT => '0'
663 
    )
664 
    port map (
665 
      C => clk,
666 
      CE => BU2_U0_N1,
667 
      D => BU2_U0_Mshreg_srl_sig_7_14_114,
668 
      Q => BU2_U0_srl_sig_7_14_80
669 
    );
670 
  BU2_U0_Mshreg_srl_sig_7_14 : SRLC16E
671 
    generic map(
672 
      INIT => X"0000"
673 
    )
674 
    port map (
675 
      A0 => BU2_U0_N0,
676 
      A1 => BU2_U0_N1,
677 
      A2 => BU2_U0_N1,
678 
      A3 => BU2_U0_N0,
679 
      CE => BU2_U0_N1,
680 
      CLK => clk,
681 
      D => d_2(14),
682 
      Q => BU2_U0_Mshreg_srl_sig_7_14_114,
683 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_14_Q15_UNCONNECTED
684 
    );
685 
  BU2_U0_srl_sig_7_13 : FDE
686 
    generic map(
687 
      INIT => '0'
688 
    )
689 
    port map (
690 
      C => clk,
691 
      CE => BU2_U0_N1,
692 
      D => BU2_U0_Mshreg_srl_sig_7_13_113,
693 
      Q => BU2_U0_srl_sig_7_13_79
694 
    );
695 
  BU2_U0_Mshreg_srl_sig_7_13 : SRLC16E
696 
    generic map(
697 
      INIT => X"0000"
698 
    )
699 
    port map (
700 
      A0 => BU2_U0_N0,
701 
      A1 => BU2_U0_N1,
702 
      A2 => BU2_U0_N1,
703 
      A3 => BU2_U0_N0,
704 
      CE => BU2_U0_N1,
705 
      CLK => clk,
706 
      D => d_2(13),
707 
      Q => BU2_U0_Mshreg_srl_sig_7_13_113,
708 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_13_Q15_UNCONNECTED
709 
    );
710 
  BU2_U0_srl_sig_7_12 : FDE
711 
    generic map(
712 
      INIT => '0'
713 
    )
714 
    port map (
715 
      C => clk,
716 
      CE => BU2_U0_N1,
717 
      D => BU2_U0_Mshreg_srl_sig_7_12_112,
718 
      Q => BU2_U0_srl_sig_7_12_78
719 
    );
720 
  BU2_U0_Mshreg_srl_sig_7_12 : SRLC16E
721 
    generic map(
722 
      INIT => X"0000"
723 
    )
724 
    port map (
725 
      A0 => BU2_U0_N0,
726 
      A1 => BU2_U0_N1,
727 
      A2 => BU2_U0_N1,
728 
      A3 => BU2_U0_N0,
729 
      CE => BU2_U0_N1,
730 
      CLK => clk,
731 
      D => d_2(12),
732 
      Q => BU2_U0_Mshreg_srl_sig_7_12_112,
733 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_12_Q15_UNCONNECTED
734 
    );
735 
  BU2_U0_srl_sig_7_11 : FDE
736 
    generic map(
737 
      INIT => '0'
738 
    )
739 
    port map (
740 
      C => clk,
741 
      CE => BU2_U0_N1,
742 
      D => BU2_U0_Mshreg_srl_sig_7_11_111,
743 
      Q => BU2_U0_srl_sig_7_11_77
744 
    );
745 
  BU2_U0_Mshreg_srl_sig_7_11 : SRLC16E
746 
    generic map(
747 
      INIT => X"0000"
748 
    )
749 
    port map (
750 
      A0 => BU2_U0_N0,
751 
      A1 => BU2_U0_N1,
752 
      A2 => BU2_U0_N1,
753 
      A3 => BU2_U0_N0,
754 
      CE => BU2_U0_N1,
755 
      CLK => clk,
756 
      D => d_2(11),
757 
      Q => BU2_U0_Mshreg_srl_sig_7_11_111,
758 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_11_Q15_UNCONNECTED
759 
    );
760 
  BU2_U0_srl_sig_7_10 : FDE
761 
    generic map(
762 
      INIT => '0'
763 
    )
764 
    port map (
765 
      C => clk,
766 
      CE => BU2_U0_N1,
767 
      D => BU2_U0_Mshreg_srl_sig_7_10_110,
768 
      Q => BU2_U0_srl_sig_7_10_76
769 
    );
770 
  BU2_U0_Mshreg_srl_sig_7_10 : SRLC16E
771 
    generic map(
772 
      INIT => X"0000"
773 
    )
774 
    port map (
775 
      A0 => BU2_U0_N0,
776 
      A1 => BU2_U0_N1,
777 
      A2 => BU2_U0_N1,
778 
      A3 => BU2_U0_N0,
779 
      CE => BU2_U0_N1,
780 
      CLK => clk,
781 
      D => d_2(10),
782 
      Q => BU2_U0_Mshreg_srl_sig_7_10_110,
783 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_10_Q15_UNCONNECTED
784 
    );
785 
  BU2_U0_srl_sig_7_9 : FDE
786 
    generic map(
787 
      INIT => '0'
788 
    )
789 
    port map (
790 
      C => clk,
791 
      CE => BU2_U0_N1,
792 
      D => BU2_U0_Mshreg_srl_sig_7_9_109,
793 
      Q => BU2_U0_srl_sig_7_9_75
794 
    );
795 
  BU2_U0_Mshreg_srl_sig_7_9 : SRLC16E
796 
    generic map(
797 
      INIT => X"0000"
798 
    )
799 
    port map (
800 
      A0 => BU2_U0_N0,
801 
      A1 => BU2_U0_N1,
802 
      A2 => BU2_U0_N1,
803 
      A3 => BU2_U0_N0,
804 
      CE => BU2_U0_N1,
805 
      CLK => clk,
806 
      D => d_2(9),
807 
      Q => BU2_U0_Mshreg_srl_sig_7_9_109,
808 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_9_Q15_UNCONNECTED
809 
    );
810 
  BU2_U0_srl_sig_7_8 : FDE
811 
    generic map(
812 
      INIT => '0'
813 
    )
814 
    port map (
815 
      C => clk,
816 
      CE => BU2_U0_N1,
817 
      D => BU2_U0_Mshreg_srl_sig_7_8_108,
818 
      Q => BU2_U0_srl_sig_7_8_74
819 
    );
820 
  BU2_U0_Mshreg_srl_sig_7_8 : SRLC16E
821 
    generic map(
822 
      INIT => X"0000"
823 
    )
824 
    port map (
825 
      A0 => BU2_U0_N0,
826 
      A1 => BU2_U0_N1,
827 
      A2 => BU2_U0_N1,
828 
      A3 => BU2_U0_N0,
829 
      CE => BU2_U0_N1,
830 
      CLK => clk,
831 
      D => d_2(8),
832 
      Q => BU2_U0_Mshreg_srl_sig_7_8_108,
833 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_8_Q15_UNCONNECTED
834 
    );
835 
  BU2_U0_srl_sig_7_7 : FDE
836 
    generic map(
837 
      INIT => '0'
838 
    )
839 
    port map (
840 
      C => clk,
841 
      CE => BU2_U0_N1,
842 
      D => BU2_U0_Mshreg_srl_sig_7_7_107,
843 
      Q => BU2_U0_srl_sig_7_7_73
844 
    );
845 
  BU2_U0_Mshreg_srl_sig_7_7 : SRLC16E
846 
    generic map(
847 
      INIT => X"0000"
848 
    )
849 
    port map (
850 
      A0 => BU2_U0_N0,
851 
      A1 => BU2_U0_N1,
852 
      A2 => BU2_U0_N1,
853 
      A3 => BU2_U0_N0,
854 
      CE => BU2_U0_N1,
855 
      CLK => clk,
856 
      D => d_2(7),
857 
      Q => BU2_U0_Mshreg_srl_sig_7_7_107,
858 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_7_Q15_UNCONNECTED
859 
    );
860 
  BU2_U0_srl_sig_7_6 : FDE
861 
    generic map(
862 
      INIT => '0'
863 
    )
864 
    port map (
865 
      C => clk,
866 
      CE => BU2_U0_N1,
867 
      D => BU2_U0_Mshreg_srl_sig_7_6_106,
868 
      Q => BU2_U0_srl_sig_7_6_72
869 
    );
870 
  BU2_U0_Mshreg_srl_sig_7_6 : SRLC16E
871 
    generic map(
872 
      INIT => X"0000"
873 
    )
874 
    port map (
875 
      A0 => BU2_U0_N0,
876 
      A1 => BU2_U0_N1,
877 
      A2 => BU2_U0_N1,
878 
      A3 => BU2_U0_N0,
879 
      CE => BU2_U0_N1,
880 
      CLK => clk,
881 
      D => d_2(6),
882 
      Q => BU2_U0_Mshreg_srl_sig_7_6_106,
883 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_6_Q15_UNCONNECTED
884 
    );
885 
  BU2_U0_srl_sig_7_5 : FDE
886 
    generic map(
887 
      INIT => '0'
888 
    )
889 
    port map (
890 
      C => clk,
891 
      CE => BU2_U0_N1,
892 
      D => BU2_U0_Mshreg_srl_sig_7_5_105,
893 
      Q => BU2_U0_srl_sig_7_5_71
894 
    );
895 
  BU2_U0_Mshreg_srl_sig_7_5 : SRLC16E
896 
    generic map(
897 
      INIT => X"0000"
898 
    )
899 
    port map (
900 
      A0 => BU2_U0_N0,
901 
      A1 => BU2_U0_N1,
902 
      A2 => BU2_U0_N1,
903 
      A3 => BU2_U0_N0,
904 
      CE => BU2_U0_N1,
905 
      CLK => clk,
906 
      D => d_2(5),
907 
      Q => BU2_U0_Mshreg_srl_sig_7_5_105,
908 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_5_Q15_UNCONNECTED
909 
    );
910 
  BU2_U0_srl_sig_7_4 : FDE
911 
    generic map(
912 
      INIT => '0'
913 
    )
914 
    port map (
915 
      C => clk,
916 
      CE => BU2_U0_N1,
917 
      D => BU2_U0_Mshreg_srl_sig_7_4_104,
918 
      Q => BU2_U0_srl_sig_7_4_70
919 
    );
920 
  BU2_U0_Mshreg_srl_sig_7_4 : SRLC16E
921 
    generic map(
922 
      INIT => X"0000"
923 
    )
924 
    port map (
925 
      A0 => BU2_U0_N0,
926 
      A1 => BU2_U0_N1,
927 
      A2 => BU2_U0_N1,
928 
      A3 => BU2_U0_N0,
929 
      CE => BU2_U0_N1,
930 
      CLK => clk,
931 
      D => d_2(4),
932 
      Q => BU2_U0_Mshreg_srl_sig_7_4_104,
933 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_4_Q15_UNCONNECTED
934 
    );
935 
  BU2_U0_srl_sig_7_3 : FDE
936 
    generic map(
937 
      INIT => '0'
938 
    )
939 
    port map (
940 
      C => clk,
941 
      CE => BU2_U0_N1,
942 
      D => BU2_U0_Mshreg_srl_sig_7_3_103,
943 
      Q => BU2_U0_srl_sig_7_3_69
944 
    );
945 
  BU2_U0_Mshreg_srl_sig_7_3 : SRLC16E
946 
    generic map(
947 
      INIT => X"0000"
948 
    )
949 
    port map (
950 
      A0 => BU2_U0_N0,
951 
      A1 => BU2_U0_N1,
952 
      A2 => BU2_U0_N1,
953 
      A3 => BU2_U0_N0,
954 
      CE => BU2_U0_N1,
955 
      CLK => clk,
956 
      D => d_2(3),
957 
      Q => BU2_U0_Mshreg_srl_sig_7_3_103,
958 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_3_Q15_UNCONNECTED
959 
    );
960 
  BU2_U0_srl_sig_7_2 : FDE
961 
    generic map(
962 
      INIT => '0'
963 
    )
964 
    port map (
965 
      C => clk,
966 
      CE => BU2_U0_N1,
967 
      D => BU2_U0_Mshreg_srl_sig_7_2_102,
968 
      Q => BU2_U0_srl_sig_7_2_68
969 
    );
970 
  BU2_U0_Mshreg_srl_sig_7_2 : SRLC16E
971 
    generic map(
972 
      INIT => X"0000"
973 
    )
974 
    port map (
975 
      A0 => BU2_U0_N0,
976 
      A1 => BU2_U0_N1,
977 
      A2 => BU2_U0_N1,
978 
      A3 => BU2_U0_N0,
979 
      CE => BU2_U0_N1,
980 
      CLK => clk,
981 
      D => d_2(2),
982 
      Q => BU2_U0_Mshreg_srl_sig_7_2_102,
983 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_2_Q15_UNCONNECTED
984 
    );
985 
  BU2_U0_srl_sig_7_1 : FDE
986 
    generic map(
987 
      INIT => '0'
988 
    )
989 
    port map (
990 
      C => clk,
991 
      CE => BU2_U0_N1,
992 
      D => BU2_U0_Mshreg_srl_sig_7_1_101,
993 
      Q => BU2_U0_srl_sig_7_1_67
994 
    );
995 
  BU2_U0_Mshreg_srl_sig_7_1 : SRLC16E
996 
    generic map(
997 
      INIT => X"0000"
998 
    )
999 
    port map (
1000 
      A0 => BU2_U0_N0,
1001 
      A1 => BU2_U0_N1,
1002 
      A2 => BU2_U0_N1,
1003 
      A3 => BU2_U0_N0,
1004 
      CE => BU2_U0_N1,
1005 
      CLK => clk,
1006 
      D => d_2(1),
1007 
      Q => BU2_U0_Mshreg_srl_sig_7_1_101,
1008 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_1_Q15_UNCONNECTED
1009 
    );
1010 
  BU2_U0_srl_sig_7_0 : FDE
1011 
    generic map(
1012 
      INIT => '0'
1013 
    )
1014 
    port map (
1015 
      C => clk,
1016 
      CE => BU2_U0_N1,
1017 
      D => BU2_U0_Mshreg_srl_sig_7_0_100,
1018 
      Q => BU2_U0_srl_sig_7_0_66
1019 
    );
1020 
  BU2_U0_Mshreg_srl_sig_7_0 : SRLC16E
1021 
    generic map(
1022 
      INIT => X"0000"
1023 
    )
1024 
    port map (
1025 
      A0 => BU2_U0_N0,
1026 
      A1 => BU2_U0_N1,
1027 
      A2 => BU2_U0_N1,
1028 
      A3 => BU2_U0_N0,
1029 
      CE => BU2_U0_N1,
1030 
      CLK => clk,
1031 
      D => d_2(0),
1032 
      Q => BU2_U0_Mshreg_srl_sig_7_0_100,
1033 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_7_0_Q15_UNCONNECTED
1034 
    );
1035 
  BU2_U0_XST_VCC : VCC
1036 
    port map (
1037 
      P => BU2_U0_N1
1038 
    );
1039 
  BU2_U0_XST_GND : GND
1040 
    port map (
1041 
      G => BU2_U0_N0
1042 
    );
1043 
  BU2_U0_gen_output_regs_output_regs_fd_output_32 : FDR
1044 
    generic map(
1045 
      INIT => '0'
1046 
    )
1047 
    port map (
1048 
      C => clk,
1049 
      D => BU2_U0_srl_sig_7_31_97,
1050 
      R => sclr,
1051 
      Q => q_3(31)
1052 
    );
1053 
  BU2_U0_gen_output_regs_output_regs_fd_output_31 : FDR
1054 
    generic map(
1055 
      INIT => '0'
1056 
    )
1057 
    port map (
1058 
      C => clk,
1059 
      D => BU2_U0_srl_sig_7_30_96,
1060 
      R => sclr,
1061 
      Q => q_3(30)
1062 
    );
1063 
  BU2_U0_gen_output_regs_output_regs_fd_output_30 : FDR
1064 
    generic map(
1065 
      INIT => '0'
1066 
    )
1067 
    port map (
1068 
      C => clk,
1069 
      D => BU2_U0_srl_sig_7_29_95,
1070 
      R => sclr,
1071 
      Q => q_3(29)
1072 
    );
1073 
  BU2_U0_gen_output_regs_output_regs_fd_output_29 : FDR
1074 
    generic map(
1075 
      INIT => '0'
1076 
    )
1077 
    port map (
1078 
      C => clk,
1079 
      D => BU2_U0_srl_sig_7_28_94,
1080 
      R => sclr,
1081 
      Q => q_3(28)
1082 
    );
1083 
  BU2_U0_gen_output_regs_output_regs_fd_output_28 : FDR
1084 
    generic map(
1085 
      INIT => '0'
1086 
    )
1087 
    port map (
1088 
      C => clk,
1089 
      D => BU2_U0_srl_sig_7_27_93,
1090 
      R => sclr,
1091 
      Q => q_3(27)
1092 
    );
1093 
  BU2_U0_gen_output_regs_output_regs_fd_output_27 : FDR
1094 
    generic map(
1095 
      INIT => '0'
1096 
    )
1097 
    port map (
1098 
      C => clk,
1099 
      D => BU2_U0_srl_sig_7_26_92,
1100 
      R => sclr,
1101 
      Q => q_3(26)
1102 
    );
1103 
  BU2_U0_gen_output_regs_output_regs_fd_output_26 : FDR
1104 
    generic map(
1105 
      INIT => '0'
1106 
    )
1107 
    port map (
1108 
      C => clk,
1109 
      D => BU2_U0_srl_sig_7_25_91,
1110 
      R => sclr,
1111 
      Q => q_3(25)
1112 
    );
1113 
  BU2_U0_gen_output_regs_output_regs_fd_output_25 : FDR
1114 
    generic map(
1115 
      INIT => '0'
1116 
    )
1117 
    port map (
1118 
      C => clk,
1119 
      D => BU2_U0_srl_sig_7_24_90,
1120 
      R => sclr,
1121 
      Q => q_3(24)
1122 
    );
1123 
  BU2_U0_gen_output_regs_output_regs_fd_output_24 : FDR
1124 
    generic map(
1125 
      INIT => '0'
1126 
    )
1127 
    port map (
1128 
      C => clk,
1129 
      D => BU2_U0_srl_sig_7_23_89,
1130 
      R => sclr,
1131 
      Q => q_3(23)
1132 
    );
1133 
  BU2_U0_gen_output_regs_output_regs_fd_output_23 : FDR
1134 
    generic map(
1135 
      INIT => '0'
1136 
    )
1137 
    port map (
1138 
      C => clk,
1139 
      D => BU2_U0_srl_sig_7_22_88,
1140 
      R => sclr,
1141 
      Q => q_3(22)
1142 
    );
1143 
  BU2_U0_gen_output_regs_output_regs_fd_output_22 : FDR
1144 
    generic map(
1145 
      INIT => '0'
1146 
    )
1147 
    port map (
1148 
      C => clk,
1149 
      D => BU2_U0_srl_sig_7_21_87,
1150 
      R => sclr,
1151 
      Q => q_3(21)
1152 
    );
1153 
  BU2_U0_gen_output_regs_output_regs_fd_output_21 : FDR
1154 
    generic map(
1155 
      INIT => '0'
1156 
    )
1157 
    port map (
1158 
      C => clk,
1159 
      D => BU2_U0_srl_sig_7_20_86,
1160 
      R => sclr,
1161 
      Q => q_3(20)
1162 
    );
1163 
  BU2_U0_gen_output_regs_output_regs_fd_output_20 : FDR
1164 
    generic map(
1165 
      INIT => '0'
1166 
    )
1167 
    port map (
1168 
      C => clk,
1169 
      D => BU2_U0_srl_sig_7_19_85,
1170 
      R => sclr,
1171 
      Q => q_3(19)
1172 
    );
1173 
  BU2_U0_gen_output_regs_output_regs_fd_output_19 : FDR
1174 
    generic map(
1175 
      INIT => '0'
1176 
    )
1177 
    port map (
1178 
      C => clk,
1179 
      D => BU2_U0_srl_sig_7_18_84,
1180 
      R => sclr,
1181 
      Q => q_3(18)
1182 
    );
1183 
  BU2_U0_gen_output_regs_output_regs_fd_output_18 : FDR
1184 
    generic map(
1185 
      INIT => '0'
1186 
    )
1187 
    port map (
1188 
      C => clk,
1189 
      D => BU2_U0_srl_sig_7_17_83,
1190 
      R => sclr,
1191 
      Q => q_3(17)
1192 
    );
1193 
  BU2_U0_gen_output_regs_output_regs_fd_output_17 : FDR
1194 
    generic map(
1195 
      INIT => '0'
1196 
    )
1197 
    port map (
1198 
      C => clk,
1199 
      D => BU2_U0_srl_sig_7_16_82,
1200 
      R => sclr,
1201 
      Q => q_3(16)
1202 
    );
1203 
  BU2_U0_gen_output_regs_output_regs_fd_output_16 : FDR
1204 
    generic map(
1205 
      INIT => '0'
1206 
    )
1207 
    port map (
1208 
      C => clk,
1209 
      D => BU2_U0_srl_sig_7_15_81,
1210 
      R => sclr,
1211 
      Q => q_3(15)
1212 
    );
1213 
  BU2_U0_gen_output_regs_output_regs_fd_output_15 : FDR
1214 
    generic map(
1215 
      INIT => '0'
1216 
    )
1217 
    port map (
1218 
      C => clk,
1219 
      D => BU2_U0_srl_sig_7_14_80,
1220 
      R => sclr,
1221 
      Q => q_3(14)
1222 
    );
1223 
  BU2_U0_gen_output_regs_output_regs_fd_output_14 : FDR
1224 
    generic map(
1225 
      INIT => '0'
1226 
    )
1227 
    port map (
1228 
      C => clk,
1229 
      D => BU2_U0_srl_sig_7_13_79,
1230 
      R => sclr,
1231 
      Q => q_3(13)
1232 
    );
1233 
  BU2_U0_gen_output_regs_output_regs_fd_output_13 : FDR
1234 
    generic map(
1235 
      INIT => '0'
1236 
    )
1237 
    port map (
1238 
      C => clk,
1239 
      D => BU2_U0_srl_sig_7_12_78,
1240 
      R => sclr,
1241 
      Q => q_3(12)
1242 
    );
1243 
  BU2_U0_gen_output_regs_output_regs_fd_output_12 : FDR
1244 
    generic map(
1245 
      INIT => '0'
1246 
    )
1247 
    port map (
1248 
      C => clk,
1249 
      D => BU2_U0_srl_sig_7_11_77,
1250 
      R => sclr,
1251 
      Q => q_3(11)
1252 
    );
1253 
  BU2_U0_gen_output_regs_output_regs_fd_output_11 : FDR
1254 
    generic map(
1255 
      INIT => '0'
1256 
    )
1257 
    port map (
1258 
      C => clk,
1259 
      D => BU2_U0_srl_sig_7_10_76,
1260 
      R => sclr,
1261 
      Q => q_3(10)
1262 
    );
1263 
  BU2_U0_gen_output_regs_output_regs_fd_output_10 : FDR
1264 
    generic map(
1265 
      INIT => '0'
1266 
    )
1267 
    port map (
1268 
      C => clk,
1269 
      D => BU2_U0_srl_sig_7_9_75,
1270 
      R => sclr,
1271 
      Q => q_3(9)
1272 
    );
1273 
  BU2_U0_gen_output_regs_output_regs_fd_output_9 : FDR
1274 
    generic map(
1275 
      INIT => '0'
1276 
    )
1277 
    port map (
1278 
      C => clk,
1279 
      D => BU2_U0_srl_sig_7_8_74,
1280 
      R => sclr,
1281 
      Q => q_3(8)
1282 
    );
1283 
  BU2_U0_gen_output_regs_output_regs_fd_output_8 : FDR
1284 
    generic map(
1285 
      INIT => '0'
1286 
    )
1287 
    port map (
1288 
      C => clk,
1289 
      D => BU2_U0_srl_sig_7_7_73,
1290 
      R => sclr,
1291 
      Q => q_3(7)
1292 
    );
1293 
  BU2_U0_gen_output_regs_output_regs_fd_output_7 : FDR
1294 
    generic map(
1295 
      INIT => '0'
1296 
    )
1297 
    port map (
1298 
      C => clk,
1299 
      D => BU2_U0_srl_sig_7_6_72,
1300 
      R => sclr,
1301 
      Q => q_3(6)
1302 
    );
1303 
  BU2_U0_gen_output_regs_output_regs_fd_output_6 : FDR
1304 
    generic map(
1305 
      INIT => '0'
1306 
    )
1307 
    port map (
1308 
      C => clk,
1309 
      D => BU2_U0_srl_sig_7_5_71,
1310 
      R => sclr,
1311 
      Q => q_3(5)
1312 
    );
1313 
  BU2_U0_gen_output_regs_output_regs_fd_output_5 : FDR
1314 
    generic map(
1315 
      INIT => '0'
1316 
    )
1317 
    port map (
1318 
      C => clk,
1319 
      D => BU2_U0_srl_sig_7_4_70,
1320 
      R => sclr,
1321 
      Q => q_3(4)
1322 
    );
1323 
  BU2_U0_gen_output_regs_output_regs_fd_output_4 : FDR
1324 
    generic map(
1325 
      INIT => '0'
1326 
    )
1327 
    port map (
1328 
      C => clk,
1329 
      D => BU2_U0_srl_sig_7_3_69,
1330 
      R => sclr,
1331 
      Q => q_3(3)
1332 
    );
1333 
  BU2_U0_gen_output_regs_output_regs_fd_output_3 : FDR
1334 
    generic map(
1335 
      INIT => '0'
1336 
    )
1337 
    port map (
1338 
      C => clk,
1339 
      D => BU2_U0_srl_sig_7_2_68,
1340 
      R => sclr,
1341 
      Q => q_3(2)
1342 
    );
1343 
  BU2_U0_gen_output_regs_output_regs_fd_output_2 : FDR
1344 
    generic map(
1345 
      INIT => '0'
1346 
    )
1347 
    port map (
1348 
      C => clk,
1349 
      D => BU2_U0_srl_sig_7_1_67,
1350 
      R => sclr,
1351 
      Q => q_3(1)
1352 
    );
1353 
  BU2_U0_gen_output_regs_output_regs_fd_output_1 : FDR
1354 
    generic map(
1355 
      INIT => '0'
1356 
    )
1357 
    port map (
1358 
      C => clk,
1359 
      D => BU2_U0_srl_sig_7_0_66,
1360 
      R => sclr,
1361 
      Q => q_3(0)
1362 
    );
1363 
 
1364 
end STRUCTURE;
1365 
 
1366 
-- synthesis translate_on

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.