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[/] [fp_log/] [trunk/] [LAU/] [Virtex 4/] [SP-LAU/] [reg_32b_18c.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 NikosAl 
--------------------------------------------------------------------------------
2 
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
3 
--------------------------------------------------------------------------------
4 
--   ____  ____
5 
--  /   /\/   /
6 
-- /___/  \  /    Vendor: Xilinx
7 
-- \   \   \/     Version: K.39
8 
--  \   \         Application: netgen
9 
--  /   /         Filename: reg_32b_18c.vhd
10 
-- /___/   /\     Timestamp: Fri Sep 18 15:02:34 2009
11 
-- \   \  /  \
12 
--  \___\/\___\
13 
--
14 
-- Command      : -intstyle ise -w -sim -ofmt vhdl "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\reg_32b_18c.ngc" "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\reg_32b_18c.vhd"
15 
-- Device       : 4vsx55ff1148-12
16 
-- Input file   : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/reg_32b_18c.ngc
17 
-- Output file  : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/reg_32b_18c.vhd
18 
-- # of Entities        : 1
19 
-- Design Name  : reg_32b_18c
20 
-- Xilinx       : C:\Xilinx\10.1\ISE
21 
--
22 
-- Purpose:
23 
--     This VHDL netlist is a verification model and uses simulation
24 
--     primitives which may not represent the true implementation of the
25 
--     device, however the netlist is functionally correct and should not
26 
--     be modified. This file cannot be synthesized and should only be used
27 
--     with supported simulation tools.
28 
--
29 
-- Reference:
30 
--     Development System Reference Guide, Chapter 23
31 
--     Synthesis and Simulation Design Guide, Chapter 6
32 
--
33 
--------------------------------------------------------------------------------
34 
 
35 
 
36 
-- synthesis translate_off
37 
library IEEE;
38 
use IEEE.STD_LOGIC_1164.ALL;
39 
library UNISIM;
40 
use UNISIM.VCOMPONENTS.ALL;
41 
use UNISIM.VPKG.ALL;
42 
 
43 
entity reg_32b_18c is
44 
  port (
45 
    sclr : in STD_LOGIC := 'X';
46 
    clk : in STD_LOGIC := 'X';
47 
    d : in STD_LOGIC_VECTOR ( 31 downto 0 );
48 
    q : out STD_LOGIC_VECTOR ( 31 downto 0 )
49 
  );
50 
end reg_32b_18c;
51 
 
52 
architecture STRUCTURE of reg_32b_18c is
53 
  signal BU2_sset : STD_LOGIC;
54 
  signal BU2_sinit : STD_LOGIC;
55 
  signal BU2_ainit : STD_LOGIC;
56 
  signal BU2_aclr : STD_LOGIC;
57 
  signal BU2_ce : STD_LOGIC;
58 
  signal BU2_aset : STD_LOGIC;
59 
  signal BU2_U0_Mshreg_srl_sig_22_31_1_163 : STD_LOGIC;
60 
  signal BU2_U0_Mshreg_srl_sig_22_31_0_162 : STD_LOGIC;
61 
  signal BU2_U0_Mshreg_srl_sig_22_30_1_161 : STD_LOGIC;
62 
  signal BU2_U0_Mshreg_srl_sig_22_30_0_160 : STD_LOGIC;
63 
  signal BU2_U0_Mshreg_srl_sig_22_29_1_159 : STD_LOGIC;
64 
  signal BU2_U0_Mshreg_srl_sig_22_29_0_158 : STD_LOGIC;
65 
  signal BU2_U0_Mshreg_srl_sig_22_28_1_157 : STD_LOGIC;
66 
  signal BU2_U0_Mshreg_srl_sig_22_28_0_156 : STD_LOGIC;
67 
  signal BU2_U0_Mshreg_srl_sig_22_27_1_155 : STD_LOGIC;
68 
  signal BU2_U0_Mshreg_srl_sig_22_27_0_154 : STD_LOGIC;
69 
  signal BU2_U0_Mshreg_srl_sig_22_26_1_153 : STD_LOGIC;
70 
  signal BU2_U0_Mshreg_srl_sig_22_26_0_152 : STD_LOGIC;
71 
  signal BU2_U0_Mshreg_srl_sig_22_25_1_151 : STD_LOGIC;
72 
  signal BU2_U0_Mshreg_srl_sig_22_25_0_150 : STD_LOGIC;
73 
  signal BU2_U0_Mshreg_srl_sig_22_24_1_149 : STD_LOGIC;
74 
  signal BU2_U0_Mshreg_srl_sig_22_24_0_148 : STD_LOGIC;
75 
  signal BU2_U0_Mshreg_srl_sig_22_23_1_147 : STD_LOGIC;
76 
  signal BU2_U0_Mshreg_srl_sig_22_23_0_146 : STD_LOGIC;
77 
  signal BU2_U0_Mshreg_srl_sig_22_22_1_145 : STD_LOGIC;
78 
  signal BU2_U0_Mshreg_srl_sig_22_22_0_144 : STD_LOGIC;
79 
  signal BU2_U0_Mshreg_srl_sig_22_21_1_143 : STD_LOGIC;
80 
  signal BU2_U0_Mshreg_srl_sig_22_21_0_142 : STD_LOGIC;
81 
  signal BU2_U0_Mshreg_srl_sig_22_20_1_141 : STD_LOGIC;
82 
  signal BU2_U0_Mshreg_srl_sig_22_20_0_140 : STD_LOGIC;
83 
  signal BU2_U0_Mshreg_srl_sig_22_19_1_139 : STD_LOGIC;
84 
  signal BU2_U0_Mshreg_srl_sig_22_19_0_138 : STD_LOGIC;
85 
  signal BU2_U0_Mshreg_srl_sig_22_18_1_137 : STD_LOGIC;
86 
  signal BU2_U0_Mshreg_srl_sig_22_18_0_136 : STD_LOGIC;
87 
  signal BU2_U0_Mshreg_srl_sig_22_17_1_135 : STD_LOGIC;
88 
  signal BU2_U0_Mshreg_srl_sig_22_17_0_134 : STD_LOGIC;
89 
  signal BU2_U0_Mshreg_srl_sig_22_16_1_133 : STD_LOGIC;
90 
  signal BU2_U0_Mshreg_srl_sig_22_16_0_132 : STD_LOGIC;
91 
  signal BU2_U0_Mshreg_srl_sig_22_15_1_131 : STD_LOGIC;
92 
  signal BU2_U0_Mshreg_srl_sig_22_15_0_130 : STD_LOGIC;
93 
  signal BU2_U0_Mshreg_srl_sig_22_14_1_129 : STD_LOGIC;
94 
  signal BU2_U0_Mshreg_srl_sig_22_14_0_128 : STD_LOGIC;
95 
  signal BU2_U0_Mshreg_srl_sig_22_13_1_127 : STD_LOGIC;
96 
  signal BU2_U0_Mshreg_srl_sig_22_13_0_126 : STD_LOGIC;
97 
  signal BU2_U0_Mshreg_srl_sig_22_12_1_125 : STD_LOGIC;
98 
  signal BU2_U0_Mshreg_srl_sig_22_12_0_124 : STD_LOGIC;
99 
  signal BU2_U0_Mshreg_srl_sig_22_11_1_123 : STD_LOGIC;
100 
  signal BU2_U0_Mshreg_srl_sig_22_11_0_122 : STD_LOGIC;
101 
  signal BU2_U0_Mshreg_srl_sig_22_10_1_121 : STD_LOGIC;
102 
  signal BU2_U0_Mshreg_srl_sig_22_10_0_120 : STD_LOGIC;
103 
  signal BU2_U0_Mshreg_srl_sig_22_9_1_119 : STD_LOGIC;
104 
  signal BU2_U0_Mshreg_srl_sig_22_9_0_118 : STD_LOGIC;
105 
  signal BU2_U0_Mshreg_srl_sig_22_8_1_117 : STD_LOGIC;
106 
  signal BU2_U0_Mshreg_srl_sig_22_8_0_116 : STD_LOGIC;
107 
  signal BU2_U0_Mshreg_srl_sig_22_7_1_115 : STD_LOGIC;
108 
  signal BU2_U0_Mshreg_srl_sig_22_7_0_114 : STD_LOGIC;
109 
  signal BU2_U0_Mshreg_srl_sig_22_6_1_113 : STD_LOGIC;
110 
  signal BU2_U0_Mshreg_srl_sig_22_6_0_112 : STD_LOGIC;
111 
  signal BU2_U0_Mshreg_srl_sig_22_5_1_111 : STD_LOGIC;
112 
  signal BU2_U0_Mshreg_srl_sig_22_5_0_110 : STD_LOGIC;
113 
  signal BU2_U0_Mshreg_srl_sig_22_4_1_109 : STD_LOGIC;
114 
  signal BU2_U0_Mshreg_srl_sig_22_4_0_108 : STD_LOGIC;
115 
  signal BU2_U0_Mshreg_srl_sig_22_3_1_107 : STD_LOGIC;
116 
  signal BU2_U0_Mshreg_srl_sig_22_3_0_106 : STD_LOGIC;
117 
  signal BU2_U0_Mshreg_srl_sig_22_2_1_105 : STD_LOGIC;
118 
  signal BU2_U0_Mshreg_srl_sig_22_2_0_104 : STD_LOGIC;
119 
  signal BU2_U0_Mshreg_srl_sig_22_1_1_103 : STD_LOGIC;
120 
  signal BU2_U0_Mshreg_srl_sig_22_1_0_102 : STD_LOGIC;
121 
  signal BU2_U0_Mshreg_srl_sig_22_0_1_101 : STD_LOGIC;
122 
  signal BU2_U0_Mshreg_srl_sig_22_0_0_100 : STD_LOGIC;
123 
  signal BU2_U0_N1 : STD_LOGIC;
124 
  signal BU2_U0_N0 : STD_LOGIC;
125 
  signal BU2_U0_srl_sig_22_31_97 : STD_LOGIC;
126 
  signal BU2_U0_srl_sig_22_30_96 : STD_LOGIC;
127 
  signal BU2_U0_srl_sig_22_29_95 : STD_LOGIC;
128 
  signal BU2_U0_srl_sig_22_28_94 : STD_LOGIC;
129 
  signal BU2_U0_srl_sig_22_27_93 : STD_LOGIC;
130 
  signal BU2_U0_srl_sig_22_26_92 : STD_LOGIC;
131 
  signal BU2_U0_srl_sig_22_25_91 : STD_LOGIC;
132 
  signal BU2_U0_srl_sig_22_24_90 : STD_LOGIC;
133 
  signal BU2_U0_srl_sig_22_23_89 : STD_LOGIC;
134 
  signal BU2_U0_srl_sig_22_22_88 : STD_LOGIC;
135 
  signal BU2_U0_srl_sig_22_21_87 : STD_LOGIC;
136 
  signal BU2_U0_srl_sig_22_20_86 : STD_LOGIC;
137 
  signal BU2_U0_srl_sig_22_19_85 : STD_LOGIC;
138 
  signal BU2_U0_srl_sig_22_18_84 : STD_LOGIC;
139 
  signal BU2_U0_srl_sig_22_17_83 : STD_LOGIC;
140 
  signal BU2_U0_srl_sig_22_16_82 : STD_LOGIC;
141 
  signal BU2_U0_srl_sig_22_15_81 : STD_LOGIC;
142 
  signal BU2_U0_srl_sig_22_14_80 : STD_LOGIC;
143 
  signal BU2_U0_srl_sig_22_13_79 : STD_LOGIC;
144 
  signal BU2_U0_srl_sig_22_12_78 : STD_LOGIC;
145 
  signal BU2_U0_srl_sig_22_11_77 : STD_LOGIC;
146 
  signal BU2_U0_srl_sig_22_10_76 : STD_LOGIC;
147 
  signal BU2_U0_srl_sig_22_9_75 : STD_LOGIC;
148 
  signal BU2_U0_srl_sig_22_8_74 : STD_LOGIC;
149 
  signal BU2_U0_srl_sig_22_7_73 : STD_LOGIC;
150 
  signal BU2_U0_srl_sig_22_6_72 : STD_LOGIC;
151 
  signal BU2_U0_srl_sig_22_5_71 : STD_LOGIC;
152 
  signal BU2_U0_srl_sig_22_4_70 : STD_LOGIC;
153 
  signal BU2_U0_srl_sig_22_3_69 : STD_LOGIC;
154 
  signal BU2_U0_srl_sig_22_2_68 : STD_LOGIC;
155 
  signal BU2_U0_srl_sig_22_1_67 : STD_LOGIC;
156 
  signal BU2_U0_srl_sig_22_0_66 : STD_LOGIC;
157 
  signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
158 
  signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
159 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_31_0_Q_UNCONNECTED : STD_LOGIC;
160 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_30_0_Q_UNCONNECTED : STD_LOGIC;
161 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_29_0_Q_UNCONNECTED : STD_LOGIC;
162 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_28_0_Q_UNCONNECTED : STD_LOGIC;
163 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_27_0_Q_UNCONNECTED : STD_LOGIC;
164 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_26_0_Q_UNCONNECTED : STD_LOGIC;
165 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_25_0_Q_UNCONNECTED : STD_LOGIC;
166 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_24_0_Q_UNCONNECTED : STD_LOGIC;
167 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_23_0_Q_UNCONNECTED : STD_LOGIC;
168 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_22_0_Q_UNCONNECTED : STD_LOGIC;
169 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_21_0_Q_UNCONNECTED : STD_LOGIC;
170 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_20_0_Q_UNCONNECTED : STD_LOGIC;
171 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_19_0_Q_UNCONNECTED : STD_LOGIC;
172 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_18_0_Q_UNCONNECTED : STD_LOGIC;
173 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_17_0_Q_UNCONNECTED : STD_LOGIC;
174 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_16_0_Q_UNCONNECTED : STD_LOGIC;
175 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_15_0_Q_UNCONNECTED : STD_LOGIC;
176 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_14_0_Q_UNCONNECTED : STD_LOGIC;
177 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_13_0_Q_UNCONNECTED : STD_LOGIC;
178 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_12_0_Q_UNCONNECTED : STD_LOGIC;
179 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_11_0_Q_UNCONNECTED : STD_LOGIC;
180 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_10_0_Q_UNCONNECTED : STD_LOGIC;
181 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_9_0_Q_UNCONNECTED : STD_LOGIC;
182 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_8_0_Q_UNCONNECTED : STD_LOGIC;
183 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_7_0_Q_UNCONNECTED : STD_LOGIC;
184 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_6_0_Q_UNCONNECTED : STD_LOGIC;
185 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_5_0_Q_UNCONNECTED : STD_LOGIC;
186 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_4_0_Q_UNCONNECTED : STD_LOGIC;
187 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_3_0_Q_UNCONNECTED : STD_LOGIC;
188 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_2_0_Q_UNCONNECTED : STD_LOGIC;
189 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_1_0_Q_UNCONNECTED : STD_LOGIC;
190 
  signal NLW_BU2_U0_Mshreg_srl_sig_22_0_0_Q_UNCONNECTED : STD_LOGIC;
191 
  signal d_2 : STD_LOGIC_VECTOR ( 31 downto 0 );
192 
  signal q_3 : STD_LOGIC_VECTOR ( 31 downto 0 );
193 
  signal BU2_a : STD_LOGIC_VECTOR ( 3 downto 0 );
194 
begin
195 
  d_2(31) <= d(31);
196 
  d_2(30) <= d(30);
197 
  d_2(29) <= d(29);
198 
  d_2(28) <= d(28);
199 
  d_2(27) <= d(27);
200 
  d_2(26) <= d(26);
201 
  d_2(25) <= d(25);
202 
  d_2(24) <= d(24);
203 
  d_2(23) <= d(23);
204 
  d_2(22) <= d(22);
205 
  d_2(21) <= d(21);
206 
  d_2(20) <= d(20);
207 
  d_2(19) <= d(19);
208 
  d_2(18) <= d(18);
209 
  d_2(17) <= d(17);
210 
  d_2(16) <= d(16);
211 
  d_2(15) <= d(15);
212 
  d_2(14) <= d(14);
213 
  d_2(13) <= d(13);
214 
  d_2(12) <= d(12);
215 
  d_2(11) <= d(11);
216 
  d_2(10) <= d(10);
217 
  d_2(9) <= d(9);
218 
  d_2(8) <= d(8);
219 
  d_2(7) <= d(7);
220 
  d_2(6) <= d(6);
221 
  d_2(5) <= d(5);
222 
  d_2(4) <= d(4);
223 
  d_2(3) <= d(3);
224 
  d_2(2) <= d(2);
225 
  d_2(1) <= d(1);
226 
  d_2(0) <= d(0);
227 
  q(31) <= q_3(31);
228 
  q(30) <= q_3(30);
229 
  q(29) <= q_3(29);
230 
  q(28) <= q_3(28);
231 
  q(27) <= q_3(27);
232 
  q(26) <= q_3(26);
233 
  q(25) <= q_3(25);
234 
  q(24) <= q_3(24);
235 
  q(23) <= q_3(23);
236 
  q(22) <= q_3(22);
237 
  q(21) <= q_3(21);
238 
  q(20) <= q_3(20);
239 
  q(19) <= q_3(19);
240 
  q(18) <= q_3(18);
241 
  q(17) <= q_3(17);
242 
  q(16) <= q_3(16);
243 
  q(15) <= q_3(15);
244 
  q(14) <= q_3(14);
245 
  q(13) <= q_3(13);
246 
  q(12) <= q_3(12);
247 
  q(11) <= q_3(11);
248 
  q(10) <= q_3(10);
249 
  q(9) <= q_3(9);
250 
  q(8) <= q_3(8);
251 
  q(7) <= q_3(7);
252 
  q(6) <= q_3(6);
253 
  q(5) <= q_3(5);
254 
  q(4) <= q_3(4);
255 
  q(3) <= q_3(3);
256 
  q(2) <= q_3(2);
257 
  q(1) <= q_3(1);
258 
  q(0) <= q_3(0);
259 
  VCC_0 : VCC
260 
    port map (
261 
      P => NLW_VCC_P_UNCONNECTED
262 
    );
263 
  GND_1 : GND
264 
    port map (
265 
      G => NLW_GND_G_UNCONNECTED
266 
    );
267 
  BU2_U0_srl_sig_22_31 : FD
268 
    generic map(
269 
      INIT => '0'
270 
    )
271 
    port map (
272 
      C => clk,
273 
      D => BU2_U0_Mshreg_srl_sig_22_31_1_163,
274 
      Q => BU2_U0_srl_sig_22_31_97
275 
    );
276 
  BU2_U0_Mshreg_srl_sig_22_31_1 : SRL16
277 
    generic map(
278 
      INIT => X"0000"
279 
    )
280 
    port map (
281 
      A0 => BU2_U0_N1,
282 
      A1 => BU2_U0_N0,
283 
      A2 => BU2_U0_N1,
284 
      A3 => BU2_U0_N0,
285 
      CLK => clk,
286 
      D => BU2_U0_Mshreg_srl_sig_22_31_0_162,
287 
      Q => BU2_U0_Mshreg_srl_sig_22_31_1_163
288 
    );
289 
  BU2_U0_Mshreg_srl_sig_22_31_0 : SRLC16
290 
    generic map(
291 
      INIT => X"0000"
292 
    )
293 
    port map (
294 
      A0 => BU2_U0_N1,
295 
      A1 => BU2_U0_N1,
296 
      A2 => BU2_U0_N1,
297 
      A3 => BU2_U0_N1,
298 
      CLK => clk,
299 
      D => d_2(31),
300 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_31_0_Q_UNCONNECTED,
301 
      Q15 => BU2_U0_Mshreg_srl_sig_22_31_0_162
302 
    );
303 
  BU2_U0_srl_sig_22_30 : FD
304 
    generic map(
305 
      INIT => '0'
306 
    )
307 
    port map (
308 
      C => clk,
309 
      D => BU2_U0_Mshreg_srl_sig_22_30_1_161,
310 
      Q => BU2_U0_srl_sig_22_30_96
311 
    );
312 
  BU2_U0_Mshreg_srl_sig_22_30_1 : SRL16
313 
    generic map(
314 
      INIT => X"0000"
315 
    )
316 
    port map (
317 
      A0 => BU2_U0_N1,
318 
      A1 => BU2_U0_N0,
319 
      A2 => BU2_U0_N1,
320 
      A3 => BU2_U0_N0,
321 
      CLK => clk,
322 
      D => BU2_U0_Mshreg_srl_sig_22_30_0_160,
323 
      Q => BU2_U0_Mshreg_srl_sig_22_30_1_161
324 
    );
325 
  BU2_U0_Mshreg_srl_sig_22_30_0 : SRLC16
326 
    generic map(
327 
      INIT => X"0000"
328 
    )
329 
    port map (
330 
      A0 => BU2_U0_N1,
331 
      A1 => BU2_U0_N1,
332 
      A2 => BU2_U0_N1,
333 
      A3 => BU2_U0_N1,
334 
      CLK => clk,
335 
      D => d_2(30),
336 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_30_0_Q_UNCONNECTED,
337 
      Q15 => BU2_U0_Mshreg_srl_sig_22_30_0_160
338 
    );
339 
  BU2_U0_srl_sig_22_29 : FD
340 
    generic map(
341 
      INIT => '0'
342 
    )
343 
    port map (
344 
      C => clk,
345 
      D => BU2_U0_Mshreg_srl_sig_22_29_1_159,
346 
      Q => BU2_U0_srl_sig_22_29_95
347 
    );
348 
  BU2_U0_Mshreg_srl_sig_22_29_1 : SRL16
349 
    generic map(
350 
      INIT => X"0000"
351 
    )
352 
    port map (
353 
      A0 => BU2_U0_N1,
354 
      A1 => BU2_U0_N0,
355 
      A2 => BU2_U0_N1,
356 
      A3 => BU2_U0_N0,
357 
      CLK => clk,
358 
      D => BU2_U0_Mshreg_srl_sig_22_29_0_158,
359 
      Q => BU2_U0_Mshreg_srl_sig_22_29_1_159
360 
    );
361 
  BU2_U0_Mshreg_srl_sig_22_29_0 : SRLC16
362 
    generic map(
363 
      INIT => X"0000"
364 
    )
365 
    port map (
366 
      A0 => BU2_U0_N1,
367 
      A1 => BU2_U0_N1,
368 
      A2 => BU2_U0_N1,
369 
      A3 => BU2_U0_N1,
370 
      CLK => clk,
371 
      D => d_2(29),
372 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_29_0_Q_UNCONNECTED,
373 
      Q15 => BU2_U0_Mshreg_srl_sig_22_29_0_158
374 
    );
375 
  BU2_U0_srl_sig_22_28 : FD
376 
    generic map(
377 
      INIT => '0'
378 
    )
379 
    port map (
380 
      C => clk,
381 
      D => BU2_U0_Mshreg_srl_sig_22_28_1_157,
382 
      Q => BU2_U0_srl_sig_22_28_94
383 
    );
384 
  BU2_U0_Mshreg_srl_sig_22_28_1 : SRL16
385 
    generic map(
386 
      INIT => X"0000"
387 
    )
388 
    port map (
389 
      A0 => BU2_U0_N1,
390 
      A1 => BU2_U0_N0,
391 
      A2 => BU2_U0_N1,
392 
      A3 => BU2_U0_N0,
393 
      CLK => clk,
394 
      D => BU2_U0_Mshreg_srl_sig_22_28_0_156,
395 
      Q => BU2_U0_Mshreg_srl_sig_22_28_1_157
396 
    );
397 
  BU2_U0_Mshreg_srl_sig_22_28_0 : SRLC16
398 
    generic map(
399 
      INIT => X"0000"
400 
    )
401 
    port map (
402 
      A0 => BU2_U0_N1,
403 
      A1 => BU2_U0_N1,
404 
      A2 => BU2_U0_N1,
405 
      A3 => BU2_U0_N1,
406 
      CLK => clk,
407 
      D => d_2(28),
408 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_28_0_Q_UNCONNECTED,
409 
      Q15 => BU2_U0_Mshreg_srl_sig_22_28_0_156
410 
    );
411 
  BU2_U0_srl_sig_22_27 : FD
412 
    generic map(
413 
      INIT => '0'
414 
    )
415 
    port map (
416 
      C => clk,
417 
      D => BU2_U0_Mshreg_srl_sig_22_27_1_155,
418 
      Q => BU2_U0_srl_sig_22_27_93
419 
    );
420 
  BU2_U0_Mshreg_srl_sig_22_27_1 : SRL16
421 
    generic map(
422 
      INIT => X"0000"
423 
    )
424 
    port map (
425 
      A0 => BU2_U0_N1,
426 
      A1 => BU2_U0_N0,
427 
      A2 => BU2_U0_N1,
428 
      A3 => BU2_U0_N0,
429 
      CLK => clk,
430 
      D => BU2_U0_Mshreg_srl_sig_22_27_0_154,
431 
      Q => BU2_U0_Mshreg_srl_sig_22_27_1_155
432 
    );
433 
  BU2_U0_Mshreg_srl_sig_22_27_0 : SRLC16
434 
    generic map(
435 
      INIT => X"0000"
436 
    )
437 
    port map (
438 
      A0 => BU2_U0_N1,
439 
      A1 => BU2_U0_N1,
440 
      A2 => BU2_U0_N1,
441 
      A3 => BU2_U0_N1,
442 
      CLK => clk,
443 
      D => d_2(27),
444 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_27_0_Q_UNCONNECTED,
445 
      Q15 => BU2_U0_Mshreg_srl_sig_22_27_0_154
446 
    );
447 
  BU2_U0_srl_sig_22_26 : FD
448 
    generic map(
449 
      INIT => '0'
450 
    )
451 
    port map (
452 
      C => clk,
453 
      D => BU2_U0_Mshreg_srl_sig_22_26_1_153,
454 
      Q => BU2_U0_srl_sig_22_26_92
455 
    );
456 
  BU2_U0_Mshreg_srl_sig_22_26_1 : SRL16
457 
    generic map(
458 
      INIT => X"0000"
459 
    )
460 
    port map (
461 
      A0 => BU2_U0_N1,
462 
      A1 => BU2_U0_N0,
463 
      A2 => BU2_U0_N1,
464 
      A3 => BU2_U0_N0,
465 
      CLK => clk,
466 
      D => BU2_U0_Mshreg_srl_sig_22_26_0_152,
467 
      Q => BU2_U0_Mshreg_srl_sig_22_26_1_153
468 
    );
469 
  BU2_U0_Mshreg_srl_sig_22_26_0 : SRLC16
470 
    generic map(
471 
      INIT => X"0000"
472 
    )
473 
    port map (
474 
      A0 => BU2_U0_N1,
475 
      A1 => BU2_U0_N1,
476 
      A2 => BU2_U0_N1,
477 
      A3 => BU2_U0_N1,
478 
      CLK => clk,
479 
      D => d_2(26),
480 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_26_0_Q_UNCONNECTED,
481 
      Q15 => BU2_U0_Mshreg_srl_sig_22_26_0_152
482 
    );
483 
  BU2_U0_srl_sig_22_25 : FD
484 
    generic map(
485 
      INIT => '0'
486 
    )
487 
    port map (
488 
      C => clk,
489 
      D => BU2_U0_Mshreg_srl_sig_22_25_1_151,
490 
      Q => BU2_U0_srl_sig_22_25_91
491 
    );
492 
  BU2_U0_Mshreg_srl_sig_22_25_1 : SRL16
493 
    generic map(
494 
      INIT => X"0000"
495 
    )
496 
    port map (
497 
      A0 => BU2_U0_N1,
498 
      A1 => BU2_U0_N0,
499 
      A2 => BU2_U0_N1,
500 
      A3 => BU2_U0_N0,
501 
      CLK => clk,
502 
      D => BU2_U0_Mshreg_srl_sig_22_25_0_150,
503 
      Q => BU2_U0_Mshreg_srl_sig_22_25_1_151
504 
    );
505 
  BU2_U0_Mshreg_srl_sig_22_25_0 : SRLC16
506 
    generic map(
507 
      INIT => X"0000"
508 
    )
509 
    port map (
510 
      A0 => BU2_U0_N1,
511 
      A1 => BU2_U0_N1,
512 
      A2 => BU2_U0_N1,
513 
      A3 => BU2_U0_N1,
514 
      CLK => clk,
515 
      D => d_2(25),
516 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_25_0_Q_UNCONNECTED,
517 
      Q15 => BU2_U0_Mshreg_srl_sig_22_25_0_150
518 
    );
519 
  BU2_U0_srl_sig_22_24 : FD
520 
    generic map(
521 
      INIT => '0'
522 
    )
523 
    port map (
524 
      C => clk,
525 
      D => BU2_U0_Mshreg_srl_sig_22_24_1_149,
526 
      Q => BU2_U0_srl_sig_22_24_90
527 
    );
528 
  BU2_U0_Mshreg_srl_sig_22_24_1 : SRL16
529 
    generic map(
530 
      INIT => X"0000"
531 
    )
532 
    port map (
533 
      A0 => BU2_U0_N1,
534 
      A1 => BU2_U0_N0,
535 
      A2 => BU2_U0_N1,
536 
      A3 => BU2_U0_N0,
537 
      CLK => clk,
538 
      D => BU2_U0_Mshreg_srl_sig_22_24_0_148,
539 
      Q => BU2_U0_Mshreg_srl_sig_22_24_1_149
540 
    );
541 
  BU2_U0_Mshreg_srl_sig_22_24_0 : SRLC16
542 
    generic map(
543 
      INIT => X"0000"
544 
    )
545 
    port map (
546 
      A0 => BU2_U0_N1,
547 
      A1 => BU2_U0_N1,
548 
      A2 => BU2_U0_N1,
549 
      A3 => BU2_U0_N1,
550 
      CLK => clk,
551 
      D => d_2(24),
552 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_24_0_Q_UNCONNECTED,
553 
      Q15 => BU2_U0_Mshreg_srl_sig_22_24_0_148
554 
    );
555 
  BU2_U0_srl_sig_22_23 : FD
556 
    generic map(
557 
      INIT => '0'
558 
    )
559 
    port map (
560 
      C => clk,
561 
      D => BU2_U0_Mshreg_srl_sig_22_23_1_147,
562 
      Q => BU2_U0_srl_sig_22_23_89
563 
    );
564 
  BU2_U0_Mshreg_srl_sig_22_23_1 : SRL16
565 
    generic map(
566 
      INIT => X"0000"
567 
    )
568 
    port map (
569 
      A0 => BU2_U0_N1,
570 
      A1 => BU2_U0_N0,
571 
      A2 => BU2_U0_N1,
572 
      A3 => BU2_U0_N0,
573 
      CLK => clk,
574 
      D => BU2_U0_Mshreg_srl_sig_22_23_0_146,
575 
      Q => BU2_U0_Mshreg_srl_sig_22_23_1_147
576 
    );
577 
  BU2_U0_Mshreg_srl_sig_22_23_0 : SRLC16
578 
    generic map(
579 
      INIT => X"0000"
580 
    )
581 
    port map (
582 
      A0 => BU2_U0_N1,
583 
      A1 => BU2_U0_N1,
584 
      A2 => BU2_U0_N1,
585 
      A3 => BU2_U0_N1,
586 
      CLK => clk,
587 
      D => d_2(23),
588 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_23_0_Q_UNCONNECTED,
589 
      Q15 => BU2_U0_Mshreg_srl_sig_22_23_0_146
590 
    );
591 
  BU2_U0_srl_sig_22_22 : FD
592 
    generic map(
593 
      INIT => '0'
594 
    )
595 
    port map (
596 
      C => clk,
597 
      D => BU2_U0_Mshreg_srl_sig_22_22_1_145,
598 
      Q => BU2_U0_srl_sig_22_22_88
599 
    );
600 
  BU2_U0_Mshreg_srl_sig_22_22_1 : SRL16
601 
    generic map(
602 
      INIT => X"0000"
603 
    )
604 
    port map (
605 
      A0 => BU2_U0_N1,
606 
      A1 => BU2_U0_N0,
607 
      A2 => BU2_U0_N1,
608 
      A3 => BU2_U0_N0,
609 
      CLK => clk,
610 
      D => BU2_U0_Mshreg_srl_sig_22_22_0_144,
611 
      Q => BU2_U0_Mshreg_srl_sig_22_22_1_145
612 
    );
613 
  BU2_U0_Mshreg_srl_sig_22_22_0 : SRLC16
614 
    generic map(
615 
      INIT => X"0000"
616 
    )
617 
    port map (
618 
      A0 => BU2_U0_N1,
619 
      A1 => BU2_U0_N1,
620 
      A2 => BU2_U0_N1,
621 
      A3 => BU2_U0_N1,
622 
      CLK => clk,
623 
      D => d_2(22),
624 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_22_0_Q_UNCONNECTED,
625 
      Q15 => BU2_U0_Mshreg_srl_sig_22_22_0_144
626 
    );
627 
  BU2_U0_srl_sig_22_21 : FD
628 
    generic map(
629 
      INIT => '0'
630 
    )
631 
    port map (
632 
      C => clk,
633 
      D => BU2_U0_Mshreg_srl_sig_22_21_1_143,
634 
      Q => BU2_U0_srl_sig_22_21_87
635 
    );
636 
  BU2_U0_Mshreg_srl_sig_22_21_1 : SRL16
637 
    generic map(
638 
      INIT => X"0000"
639 
    )
640 
    port map (
641 
      A0 => BU2_U0_N1,
642 
      A1 => BU2_U0_N0,
643 
      A2 => BU2_U0_N1,
644 
      A3 => BU2_U0_N0,
645 
      CLK => clk,
646 
      D => BU2_U0_Mshreg_srl_sig_22_21_0_142,
647 
      Q => BU2_U0_Mshreg_srl_sig_22_21_1_143
648 
    );
649 
  BU2_U0_Mshreg_srl_sig_22_21_0 : SRLC16
650 
    generic map(
651 
      INIT => X"0000"
652 
    )
653 
    port map (
654 
      A0 => BU2_U0_N1,
655 
      A1 => BU2_U0_N1,
656 
      A2 => BU2_U0_N1,
657 
      A3 => BU2_U0_N1,
658 
      CLK => clk,
659 
      D => d_2(21),
660 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_21_0_Q_UNCONNECTED,
661 
      Q15 => BU2_U0_Mshreg_srl_sig_22_21_0_142
662 
    );
663 
  BU2_U0_srl_sig_22_20 : FD
664 
    generic map(
665 
      INIT => '0'
666 
    )
667 
    port map (
668 
      C => clk,
669 
      D => BU2_U0_Mshreg_srl_sig_22_20_1_141,
670 
      Q => BU2_U0_srl_sig_22_20_86
671 
    );
672 
  BU2_U0_Mshreg_srl_sig_22_20_1 : SRL16
673 
    generic map(
674 
      INIT => X"0000"
675 
    )
676 
    port map (
677 
      A0 => BU2_U0_N1,
678 
      A1 => BU2_U0_N0,
679 
      A2 => BU2_U0_N1,
680 
      A3 => BU2_U0_N0,
681 
      CLK => clk,
682 
      D => BU2_U0_Mshreg_srl_sig_22_20_0_140,
683 
      Q => BU2_U0_Mshreg_srl_sig_22_20_1_141
684 
    );
685 
  BU2_U0_Mshreg_srl_sig_22_20_0 : SRLC16
686 
    generic map(
687 
      INIT => X"0000"
688 
    )
689 
    port map (
690 
      A0 => BU2_U0_N1,
691 
      A1 => BU2_U0_N1,
692 
      A2 => BU2_U0_N1,
693 
      A3 => BU2_U0_N1,
694 
      CLK => clk,
695 
      D => d_2(20),
696 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_20_0_Q_UNCONNECTED,
697 
      Q15 => BU2_U0_Mshreg_srl_sig_22_20_0_140
698 
    );
699 
  BU2_U0_srl_sig_22_19 : FD
700 
    generic map(
701 
      INIT => '0'
702 
    )
703 
    port map (
704 
      C => clk,
705 
      D => BU2_U0_Mshreg_srl_sig_22_19_1_139,
706 
      Q => BU2_U0_srl_sig_22_19_85
707 
    );
708 
  BU2_U0_Mshreg_srl_sig_22_19_1 : SRL16
709 
    generic map(
710 
      INIT => X"0000"
711 
    )
712 
    port map (
713 
      A0 => BU2_U0_N1,
714 
      A1 => BU2_U0_N0,
715 
      A2 => BU2_U0_N1,
716 
      A3 => BU2_U0_N0,
717 
      CLK => clk,
718 
      D => BU2_U0_Mshreg_srl_sig_22_19_0_138,
719 
      Q => BU2_U0_Mshreg_srl_sig_22_19_1_139
720 
    );
721 
  BU2_U0_Mshreg_srl_sig_22_19_0 : SRLC16
722 
    generic map(
723 
      INIT => X"0000"
724 
    )
725 
    port map (
726 
      A0 => BU2_U0_N1,
727 
      A1 => BU2_U0_N1,
728 
      A2 => BU2_U0_N1,
729 
      A3 => BU2_U0_N1,
730 
      CLK => clk,
731 
      D => d_2(19),
732 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_19_0_Q_UNCONNECTED,
733 
      Q15 => BU2_U0_Mshreg_srl_sig_22_19_0_138
734 
    );
735 
  BU2_U0_srl_sig_22_18 : FD
736 
    generic map(
737 
      INIT => '0'
738 
    )
739 
    port map (
740 
      C => clk,
741 
      D => BU2_U0_Mshreg_srl_sig_22_18_1_137,
742 
      Q => BU2_U0_srl_sig_22_18_84
743 
    );
744 
  BU2_U0_Mshreg_srl_sig_22_18_1 : SRL16
745 
    generic map(
746 
      INIT => X"0000"
747 
    )
748 
    port map (
749 
      A0 => BU2_U0_N1,
750 
      A1 => BU2_U0_N0,
751 
      A2 => BU2_U0_N1,
752 
      A3 => BU2_U0_N0,
753 
      CLK => clk,
754 
      D => BU2_U0_Mshreg_srl_sig_22_18_0_136,
755 
      Q => BU2_U0_Mshreg_srl_sig_22_18_1_137
756 
    );
757 
  BU2_U0_Mshreg_srl_sig_22_18_0 : SRLC16
758 
    generic map(
759 
      INIT => X"0000"
760 
    )
761 
    port map (
762 
      A0 => BU2_U0_N1,
763 
      A1 => BU2_U0_N1,
764 
      A2 => BU2_U0_N1,
765 
      A3 => BU2_U0_N1,
766 
      CLK => clk,
767 
      D => d_2(18),
768 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_18_0_Q_UNCONNECTED,
769 
      Q15 => BU2_U0_Mshreg_srl_sig_22_18_0_136
770 
    );
771 
  BU2_U0_srl_sig_22_17 : FD
772 
    generic map(
773 
      INIT => '0'
774 
    )
775 
    port map (
776 
      C => clk,
777 
      D => BU2_U0_Mshreg_srl_sig_22_17_1_135,
778 
      Q => BU2_U0_srl_sig_22_17_83
779 
    );
780 
  BU2_U0_Mshreg_srl_sig_22_17_1 : SRL16
781 
    generic map(
782 
      INIT => X"0000"
783 
    )
784 
    port map (
785 
      A0 => BU2_U0_N1,
786 
      A1 => BU2_U0_N0,
787 
      A2 => BU2_U0_N1,
788 
      A3 => BU2_U0_N0,
789 
      CLK => clk,
790 
      D => BU2_U0_Mshreg_srl_sig_22_17_0_134,
791 
      Q => BU2_U0_Mshreg_srl_sig_22_17_1_135
792 
    );
793 
  BU2_U0_Mshreg_srl_sig_22_17_0 : SRLC16
794 
    generic map(
795 
      INIT => X"0000"
796 
    )
797 
    port map (
798 
      A0 => BU2_U0_N1,
799 
      A1 => BU2_U0_N1,
800 
      A2 => BU2_U0_N1,
801 
      A3 => BU2_U0_N1,
802 
      CLK => clk,
803 
      D => d_2(17),
804 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_17_0_Q_UNCONNECTED,
805 
      Q15 => BU2_U0_Mshreg_srl_sig_22_17_0_134
806 
    );
807 
  BU2_U0_srl_sig_22_16 : FD
808 
    generic map(
809 
      INIT => '0'
810 
    )
811 
    port map (
812 
      C => clk,
813 
      D => BU2_U0_Mshreg_srl_sig_22_16_1_133,
814 
      Q => BU2_U0_srl_sig_22_16_82
815 
    );
816 
  BU2_U0_Mshreg_srl_sig_22_16_1 : SRL16
817 
    generic map(
818 
      INIT => X"0000"
819 
    )
820 
    port map (
821 
      A0 => BU2_U0_N1,
822 
      A1 => BU2_U0_N0,
823 
      A2 => BU2_U0_N1,
824 
      A3 => BU2_U0_N0,
825 
      CLK => clk,
826 
      D => BU2_U0_Mshreg_srl_sig_22_16_0_132,
827 
      Q => BU2_U0_Mshreg_srl_sig_22_16_1_133
828 
    );
829 
  BU2_U0_Mshreg_srl_sig_22_16_0 : SRLC16
830 
    generic map(
831 
      INIT => X"0000"
832 
    )
833 
    port map (
834 
      A0 => BU2_U0_N1,
835 
      A1 => BU2_U0_N1,
836 
      A2 => BU2_U0_N1,
837 
      A3 => BU2_U0_N1,
838 
      CLK => clk,
839 
      D => d_2(16),
840 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_16_0_Q_UNCONNECTED,
841 
      Q15 => BU2_U0_Mshreg_srl_sig_22_16_0_132
842 
    );
843 
  BU2_U0_srl_sig_22_15 : FD
844 
    generic map(
845 
      INIT => '0'
846 
    )
847 
    port map (
848 
      C => clk,
849 
      D => BU2_U0_Mshreg_srl_sig_22_15_1_131,
850 
      Q => BU2_U0_srl_sig_22_15_81
851 
    );
852 
  BU2_U0_Mshreg_srl_sig_22_15_1 : SRL16
853 
    generic map(
854 
      INIT => X"0000"
855 
    )
856 
    port map (
857 
      A0 => BU2_U0_N1,
858 
      A1 => BU2_U0_N0,
859 
      A2 => BU2_U0_N1,
860 
      A3 => BU2_U0_N0,
861 
      CLK => clk,
862 
      D => BU2_U0_Mshreg_srl_sig_22_15_0_130,
863 
      Q => BU2_U0_Mshreg_srl_sig_22_15_1_131
864 
    );
865 
  BU2_U0_Mshreg_srl_sig_22_15_0 : SRLC16
866 
    generic map(
867 
      INIT => X"0000"
868 
    )
869 
    port map (
870 
      A0 => BU2_U0_N1,
871 
      A1 => BU2_U0_N1,
872 
      A2 => BU2_U0_N1,
873 
      A3 => BU2_U0_N1,
874 
      CLK => clk,
875 
      D => d_2(15),
876 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_15_0_Q_UNCONNECTED,
877 
      Q15 => BU2_U0_Mshreg_srl_sig_22_15_0_130
878 
    );
879 
  BU2_U0_srl_sig_22_14 : FD
880 
    generic map(
881 
      INIT => '0'
882 
    )
883 
    port map (
884 
      C => clk,
885 
      D => BU2_U0_Mshreg_srl_sig_22_14_1_129,
886 
      Q => BU2_U0_srl_sig_22_14_80
887 
    );
888 
  BU2_U0_Mshreg_srl_sig_22_14_1 : SRL16
889 
    generic map(
890 
      INIT => X"0000"
891 
    )
892 
    port map (
893 
      A0 => BU2_U0_N1,
894 
      A1 => BU2_U0_N0,
895 
      A2 => BU2_U0_N1,
896 
      A3 => BU2_U0_N0,
897 
      CLK => clk,
898 
      D => BU2_U0_Mshreg_srl_sig_22_14_0_128,
899 
      Q => BU2_U0_Mshreg_srl_sig_22_14_1_129
900 
    );
901 
  BU2_U0_Mshreg_srl_sig_22_14_0 : SRLC16
902 
    generic map(
903 
      INIT => X"0000"
904 
    )
905 
    port map (
906 
      A0 => BU2_U0_N1,
907 
      A1 => BU2_U0_N1,
908 
      A2 => BU2_U0_N1,
909 
      A3 => BU2_U0_N1,
910 
      CLK => clk,
911 
      D => d_2(14),
912 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_14_0_Q_UNCONNECTED,
913 
      Q15 => BU2_U0_Mshreg_srl_sig_22_14_0_128
914 
    );
915 
  BU2_U0_srl_sig_22_13 : FD
916 
    generic map(
917 
      INIT => '0'
918 
    )
919 
    port map (
920 
      C => clk,
921 
      D => BU2_U0_Mshreg_srl_sig_22_13_1_127,
922 
      Q => BU2_U0_srl_sig_22_13_79
923 
    );
924 
  BU2_U0_Mshreg_srl_sig_22_13_1 : SRL16
925 
    generic map(
926 
      INIT => X"0000"
927 
    )
928 
    port map (
929 
      A0 => BU2_U0_N1,
930 
      A1 => BU2_U0_N0,
931 
      A2 => BU2_U0_N1,
932 
      A3 => BU2_U0_N0,
933 
      CLK => clk,
934 
      D => BU2_U0_Mshreg_srl_sig_22_13_0_126,
935 
      Q => BU2_U0_Mshreg_srl_sig_22_13_1_127
936 
    );
937 
  BU2_U0_Mshreg_srl_sig_22_13_0 : SRLC16
938 
    generic map(
939 
      INIT => X"0000"
940 
    )
941 
    port map (
942 
      A0 => BU2_U0_N1,
943 
      A1 => BU2_U0_N1,
944 
      A2 => BU2_U0_N1,
945 
      A3 => BU2_U0_N1,
946 
      CLK => clk,
947 
      D => d_2(13),
948 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_13_0_Q_UNCONNECTED,
949 
      Q15 => BU2_U0_Mshreg_srl_sig_22_13_0_126
950 
    );
951 
  BU2_U0_srl_sig_22_12 : FD
952 
    generic map(
953 
      INIT => '0'
954 
    )
955 
    port map (
956 
      C => clk,
957 
      D => BU2_U0_Mshreg_srl_sig_22_12_1_125,
958 
      Q => BU2_U0_srl_sig_22_12_78
959 
    );
960 
  BU2_U0_Mshreg_srl_sig_22_12_1 : SRL16
961 
    generic map(
962 
      INIT => X"0000"
963 
    )
964 
    port map (
965 
      A0 => BU2_U0_N1,
966 
      A1 => BU2_U0_N0,
967 
      A2 => BU2_U0_N1,
968 
      A3 => BU2_U0_N0,
969 
      CLK => clk,
970 
      D => BU2_U0_Mshreg_srl_sig_22_12_0_124,
971 
      Q => BU2_U0_Mshreg_srl_sig_22_12_1_125
972 
    );
973 
  BU2_U0_Mshreg_srl_sig_22_12_0 : SRLC16
974 
    generic map(
975 
      INIT => X"0000"
976 
    )
977 
    port map (
978 
      A0 => BU2_U0_N1,
979 
      A1 => BU2_U0_N1,
980 
      A2 => BU2_U0_N1,
981 
      A3 => BU2_U0_N1,
982 
      CLK => clk,
983 
      D => d_2(12),
984 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_12_0_Q_UNCONNECTED,
985 
      Q15 => BU2_U0_Mshreg_srl_sig_22_12_0_124
986 
    );
987 
  BU2_U0_srl_sig_22_11 : FD
988 
    generic map(
989 
      INIT => '0'
990 
    )
991 
    port map (
992 
      C => clk,
993 
      D => BU2_U0_Mshreg_srl_sig_22_11_1_123,
994 
      Q => BU2_U0_srl_sig_22_11_77
995 
    );
996 
  BU2_U0_Mshreg_srl_sig_22_11_1 : SRL16
997 
    generic map(
998 
      INIT => X"0000"
999 
    )
1000 
    port map (
1001 
      A0 => BU2_U0_N1,
1002 
      A1 => BU2_U0_N0,
1003 
      A2 => BU2_U0_N1,
1004 
      A3 => BU2_U0_N0,
1005 
      CLK => clk,
1006 
      D => BU2_U0_Mshreg_srl_sig_22_11_0_122,
1007 
      Q => BU2_U0_Mshreg_srl_sig_22_11_1_123
1008 
    );
1009 
  BU2_U0_Mshreg_srl_sig_22_11_0 : SRLC16
1010 
    generic map(
1011 
      INIT => X"0000"
1012 
    )
1013 
    port map (
1014 
      A0 => BU2_U0_N1,
1015 
      A1 => BU2_U0_N1,
1016 
      A2 => BU2_U0_N1,
1017 
      A3 => BU2_U0_N1,
1018 
      CLK => clk,
1019 
      D => d_2(11),
1020 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_11_0_Q_UNCONNECTED,
1021 
      Q15 => BU2_U0_Mshreg_srl_sig_22_11_0_122
1022 
    );
1023 
  BU2_U0_srl_sig_22_10 : FD
1024 
    generic map(
1025 
      INIT => '0'
1026 
    )
1027 
    port map (
1028 
      C => clk,
1029 
      D => BU2_U0_Mshreg_srl_sig_22_10_1_121,
1030 
      Q => BU2_U0_srl_sig_22_10_76
1031 
    );
1032 
  BU2_U0_Mshreg_srl_sig_22_10_1 : SRL16
1033 
    generic map(
1034 
      INIT => X"0000"
1035 
    )
1036 
    port map (
1037 
      A0 => BU2_U0_N1,
1038 
      A1 => BU2_U0_N0,
1039 
      A2 => BU2_U0_N1,
1040 
      A3 => BU2_U0_N0,
1041 
      CLK => clk,
1042 
      D => BU2_U0_Mshreg_srl_sig_22_10_0_120,
1043 
      Q => BU2_U0_Mshreg_srl_sig_22_10_1_121
1044 
    );
1045 
  BU2_U0_Mshreg_srl_sig_22_10_0 : SRLC16
1046 
    generic map(
1047 
      INIT => X"0000"
1048 
    )
1049 
    port map (
1050 
      A0 => BU2_U0_N1,
1051 
      A1 => BU2_U0_N1,
1052 
      A2 => BU2_U0_N1,
1053 
      A3 => BU2_U0_N1,
1054 
      CLK => clk,
1055 
      D => d_2(10),
1056 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_10_0_Q_UNCONNECTED,
1057 
      Q15 => BU2_U0_Mshreg_srl_sig_22_10_0_120
1058 
    );
1059 
  BU2_U0_srl_sig_22_9 : FD
1060 
    generic map(
1061 
      INIT => '0'
1062 
    )
1063 
    port map (
1064 
      C => clk,
1065 
      D => BU2_U0_Mshreg_srl_sig_22_9_1_119,
1066 
      Q => BU2_U0_srl_sig_22_9_75
1067 
    );
1068 
  BU2_U0_Mshreg_srl_sig_22_9_1 : SRL16
1069 
    generic map(
1070 
      INIT => X"0000"
1071 
    )
1072 
    port map (
1073 
      A0 => BU2_U0_N1,
1074 
      A1 => BU2_U0_N0,
1075 
      A2 => BU2_U0_N1,
1076 
      A3 => BU2_U0_N0,
1077 
      CLK => clk,
1078 
      D => BU2_U0_Mshreg_srl_sig_22_9_0_118,
1079 
      Q => BU2_U0_Mshreg_srl_sig_22_9_1_119
1080 
    );
1081 
  BU2_U0_Mshreg_srl_sig_22_9_0 : SRLC16
1082 
    generic map(
1083 
      INIT => X"0000"
1084 
    )
1085 
    port map (
1086 
      A0 => BU2_U0_N1,
1087 
      A1 => BU2_U0_N1,
1088 
      A2 => BU2_U0_N1,
1089 
      A3 => BU2_U0_N1,
1090 
      CLK => clk,
1091 
      D => d_2(9),
1092 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_9_0_Q_UNCONNECTED,
1093 
      Q15 => BU2_U0_Mshreg_srl_sig_22_9_0_118
1094 
    );
1095 
  BU2_U0_srl_sig_22_8 : FD
1096 
    generic map(
1097 
      INIT => '0'
1098 
    )
1099 
    port map (
1100 
      C => clk,
1101 
      D => BU2_U0_Mshreg_srl_sig_22_8_1_117,
1102 
      Q => BU2_U0_srl_sig_22_8_74
1103 
    );
1104 
  BU2_U0_Mshreg_srl_sig_22_8_1 : SRL16
1105 
    generic map(
1106 
      INIT => X"0000"
1107 
    )
1108 
    port map (
1109 
      A0 => BU2_U0_N1,
1110 
      A1 => BU2_U0_N0,
1111 
      A2 => BU2_U0_N1,
1112 
      A3 => BU2_U0_N0,
1113 
      CLK => clk,
1114 
      D => BU2_U0_Mshreg_srl_sig_22_8_0_116,
1115 
      Q => BU2_U0_Mshreg_srl_sig_22_8_1_117
1116 
    );
1117 
  BU2_U0_Mshreg_srl_sig_22_8_0 : SRLC16
1118 
    generic map(
1119 
      INIT => X"0000"
1120 
    )
1121 
    port map (
1122 
      A0 => BU2_U0_N1,
1123 
      A1 => BU2_U0_N1,
1124 
      A2 => BU2_U0_N1,
1125 
      A3 => BU2_U0_N1,
1126 
      CLK => clk,
1127 
      D => d_2(8),
1128 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_8_0_Q_UNCONNECTED,
1129 
      Q15 => BU2_U0_Mshreg_srl_sig_22_8_0_116
1130 
    );
1131 
  BU2_U0_srl_sig_22_7 : FD
1132 
    generic map(
1133 
      INIT => '0'
1134 
    )
1135 
    port map (
1136 
      C => clk,
1137 
      D => BU2_U0_Mshreg_srl_sig_22_7_1_115,
1138 
      Q => BU2_U0_srl_sig_22_7_73
1139 
    );
1140 
  BU2_U0_Mshreg_srl_sig_22_7_1 : SRL16
1141 
    generic map(
1142 
      INIT => X"0000"
1143 
    )
1144 
    port map (
1145 
      A0 => BU2_U0_N1,
1146 
      A1 => BU2_U0_N0,
1147 
      A2 => BU2_U0_N1,
1148 
      A3 => BU2_U0_N0,
1149 
      CLK => clk,
1150 
      D => BU2_U0_Mshreg_srl_sig_22_7_0_114,
1151 
      Q => BU2_U0_Mshreg_srl_sig_22_7_1_115
1152 
    );
1153 
  BU2_U0_Mshreg_srl_sig_22_7_0 : SRLC16
1154 
    generic map(
1155 
      INIT => X"0000"
1156 
    )
1157 
    port map (
1158 
      A0 => BU2_U0_N1,
1159 
      A1 => BU2_U0_N1,
1160 
      A2 => BU2_U0_N1,
1161 
      A3 => BU2_U0_N1,
1162 
      CLK => clk,
1163 
      D => d_2(7),
1164 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_7_0_Q_UNCONNECTED,
1165 
      Q15 => BU2_U0_Mshreg_srl_sig_22_7_0_114
1166 
    );
1167 
  BU2_U0_srl_sig_22_6 : FD
1168 
    generic map(
1169 
      INIT => '0'
1170 
    )
1171 
    port map (
1172 
      C => clk,
1173 
      D => BU2_U0_Mshreg_srl_sig_22_6_1_113,
1174 
      Q => BU2_U0_srl_sig_22_6_72
1175 
    );
1176 
  BU2_U0_Mshreg_srl_sig_22_6_1 : SRL16
1177 
    generic map(
1178 
      INIT => X"0000"
1179 
    )
1180 
    port map (
1181 
      A0 => BU2_U0_N1,
1182 
      A1 => BU2_U0_N0,
1183 
      A2 => BU2_U0_N1,
1184 
      A3 => BU2_U0_N0,
1185 
      CLK => clk,
1186 
      D => BU2_U0_Mshreg_srl_sig_22_6_0_112,
1187 
      Q => BU2_U0_Mshreg_srl_sig_22_6_1_113
1188 
    );
1189 
  BU2_U0_Mshreg_srl_sig_22_6_0 : SRLC16
1190 
    generic map(
1191 
      INIT => X"0000"
1192 
    )
1193 
    port map (
1194 
      A0 => BU2_U0_N1,
1195 
      A1 => BU2_U0_N1,
1196 
      A2 => BU2_U0_N1,
1197 
      A3 => BU2_U0_N1,
1198 
      CLK => clk,
1199 
      D => d_2(6),
1200 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_6_0_Q_UNCONNECTED,
1201 
      Q15 => BU2_U0_Mshreg_srl_sig_22_6_0_112
1202 
    );
1203 
  BU2_U0_srl_sig_22_5 : FD
1204 
    generic map(
1205 
      INIT => '0'
1206 
    )
1207 
    port map (
1208 
      C => clk,
1209 
      D => BU2_U0_Mshreg_srl_sig_22_5_1_111,
1210 
      Q => BU2_U0_srl_sig_22_5_71
1211 
    );
1212 
  BU2_U0_Mshreg_srl_sig_22_5_1 : SRL16
1213 
    generic map(
1214 
      INIT => X"0000"
1215 
    )
1216 
    port map (
1217 
      A0 => BU2_U0_N1,
1218 
      A1 => BU2_U0_N0,
1219 
      A2 => BU2_U0_N1,
1220 
      A3 => BU2_U0_N0,
1221 
      CLK => clk,
1222 
      D => BU2_U0_Mshreg_srl_sig_22_5_0_110,
1223 
      Q => BU2_U0_Mshreg_srl_sig_22_5_1_111
1224 
    );
1225 
  BU2_U0_Mshreg_srl_sig_22_5_0 : SRLC16
1226 
    generic map(
1227 
      INIT => X"0000"
1228 
    )
1229 
    port map (
1230 
      A0 => BU2_U0_N1,
1231 
      A1 => BU2_U0_N1,
1232 
      A2 => BU2_U0_N1,
1233 
      A3 => BU2_U0_N1,
1234 
      CLK => clk,
1235 
      D => d_2(5),
1236 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_5_0_Q_UNCONNECTED,
1237 
      Q15 => BU2_U0_Mshreg_srl_sig_22_5_0_110
1238 
    );
1239 
  BU2_U0_srl_sig_22_4 : FD
1240 
    generic map(
1241 
      INIT => '0'
1242 
    )
1243 
    port map (
1244 
      C => clk,
1245 
      D => BU2_U0_Mshreg_srl_sig_22_4_1_109,
1246 
      Q => BU2_U0_srl_sig_22_4_70
1247 
    );
1248 
  BU2_U0_Mshreg_srl_sig_22_4_1 : SRL16
1249 
    generic map(
1250 
      INIT => X"0000"
1251 
    )
1252 
    port map (
1253 
      A0 => BU2_U0_N1,
1254 
      A1 => BU2_U0_N0,
1255 
      A2 => BU2_U0_N1,
1256 
      A3 => BU2_U0_N0,
1257 
      CLK => clk,
1258 
      D => BU2_U0_Mshreg_srl_sig_22_4_0_108,
1259 
      Q => BU2_U0_Mshreg_srl_sig_22_4_1_109
1260 
    );
1261 
  BU2_U0_Mshreg_srl_sig_22_4_0 : SRLC16
1262 
    generic map(
1263 
      INIT => X"0000"
1264 
    )
1265 
    port map (
1266 
      A0 => BU2_U0_N1,
1267 
      A1 => BU2_U0_N1,
1268 
      A2 => BU2_U0_N1,
1269 
      A3 => BU2_U0_N1,
1270 
      CLK => clk,
1271 
      D => d_2(4),
1272 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_4_0_Q_UNCONNECTED,
1273 
      Q15 => BU2_U0_Mshreg_srl_sig_22_4_0_108
1274 
    );
1275 
  BU2_U0_srl_sig_22_3 : FD
1276 
    generic map(
1277 
      INIT => '0'
1278 
    )
1279 
    port map (
1280 
      C => clk,
1281 
      D => BU2_U0_Mshreg_srl_sig_22_3_1_107,
1282 
      Q => BU2_U0_srl_sig_22_3_69
1283 
    );
1284 
  BU2_U0_Mshreg_srl_sig_22_3_1 : SRL16
1285 
    generic map(
1286 
      INIT => X"0000"
1287 
    )
1288 
    port map (
1289 
      A0 => BU2_U0_N1,
1290 
      A1 => BU2_U0_N0,
1291 
      A2 => BU2_U0_N1,
1292 
      A3 => BU2_U0_N0,
1293 
      CLK => clk,
1294 
      D => BU2_U0_Mshreg_srl_sig_22_3_0_106,
1295 
      Q => BU2_U0_Mshreg_srl_sig_22_3_1_107
1296 
    );
1297 
  BU2_U0_Mshreg_srl_sig_22_3_0 : SRLC16
1298 
    generic map(
1299 
      INIT => X"0000"
1300 
    )
1301 
    port map (
1302 
      A0 => BU2_U0_N1,
1303 
      A1 => BU2_U0_N1,
1304 
      A2 => BU2_U0_N1,
1305 
      A3 => BU2_U0_N1,
1306 
      CLK => clk,
1307 
      D => d_2(3),
1308 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_3_0_Q_UNCONNECTED,
1309 
      Q15 => BU2_U0_Mshreg_srl_sig_22_3_0_106
1310 
    );
1311 
  BU2_U0_srl_sig_22_2 : FD
1312 
    generic map(
1313 
      INIT => '0'
1314 
    )
1315 
    port map (
1316 
      C => clk,
1317 
      D => BU2_U0_Mshreg_srl_sig_22_2_1_105,
1318 
      Q => BU2_U0_srl_sig_22_2_68
1319 
    );
1320 
  BU2_U0_Mshreg_srl_sig_22_2_1 : SRL16
1321 
    generic map(
1322 
      INIT => X"0000"
1323 
    )
1324 
    port map (
1325 
      A0 => BU2_U0_N1,
1326 
      A1 => BU2_U0_N0,
1327 
      A2 => BU2_U0_N1,
1328 
      A3 => BU2_U0_N0,
1329 
      CLK => clk,
1330 
      D => BU2_U0_Mshreg_srl_sig_22_2_0_104,
1331 
      Q => BU2_U0_Mshreg_srl_sig_22_2_1_105
1332 
    );
1333 
  BU2_U0_Mshreg_srl_sig_22_2_0 : SRLC16
1334 
    generic map(
1335 
      INIT => X"0000"
1336 
    )
1337 
    port map (
1338 
      A0 => BU2_U0_N1,
1339 
      A1 => BU2_U0_N1,
1340 
      A2 => BU2_U0_N1,
1341 
      A3 => BU2_U0_N1,
1342 
      CLK => clk,
1343 
      D => d_2(2),
1344 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_2_0_Q_UNCONNECTED,
1345 
      Q15 => BU2_U0_Mshreg_srl_sig_22_2_0_104
1346 
    );
1347 
  BU2_U0_srl_sig_22_1 : FD
1348 
    generic map(
1349 
      INIT => '0'
1350 
    )
1351 
    port map (
1352 
      C => clk,
1353 
      D => BU2_U0_Mshreg_srl_sig_22_1_1_103,
1354 
      Q => BU2_U0_srl_sig_22_1_67
1355 
    );
1356 
  BU2_U0_Mshreg_srl_sig_22_1_1 : SRL16
1357 
    generic map(
1358 
      INIT => X"0000"
1359 
    )
1360 
    port map (
1361 
      A0 => BU2_U0_N1,
1362 
      A1 => BU2_U0_N0,
1363 
      A2 => BU2_U0_N1,
1364 
      A3 => BU2_U0_N0,
1365 
      CLK => clk,
1366 
      D => BU2_U0_Mshreg_srl_sig_22_1_0_102,
1367 
      Q => BU2_U0_Mshreg_srl_sig_22_1_1_103
1368 
    );
1369 
  BU2_U0_Mshreg_srl_sig_22_1_0 : SRLC16
1370 
    generic map(
1371 
      INIT => X"0000"
1372 
    )
1373 
    port map (
1374 
      A0 => BU2_U0_N1,
1375 
      A1 => BU2_U0_N1,
1376 
      A2 => BU2_U0_N1,
1377 
      A3 => BU2_U0_N1,
1378 
      CLK => clk,
1379 
      D => d_2(1),
1380 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_1_0_Q_UNCONNECTED,
1381 
      Q15 => BU2_U0_Mshreg_srl_sig_22_1_0_102
1382 
    );
1383 
  BU2_U0_srl_sig_22_0 : FD
1384 
    generic map(
1385 
      INIT => '0'
1386 
    )
1387 
    port map (
1388 
      C => clk,
1389 
      D => BU2_U0_Mshreg_srl_sig_22_0_1_101,
1390 
      Q => BU2_U0_srl_sig_22_0_66
1391 
    );
1392 
  BU2_U0_Mshreg_srl_sig_22_0_1 : SRL16
1393 
    generic map(
1394 
      INIT => X"0000"
1395 
    )
1396 
    port map (
1397 
      A0 => BU2_U0_N1,
1398 
      A1 => BU2_U0_N0,
1399 
      A2 => BU2_U0_N1,
1400 
      A3 => BU2_U0_N0,
1401 
      CLK => clk,
1402 
      D => BU2_U0_Mshreg_srl_sig_22_0_0_100,
1403 
      Q => BU2_U0_Mshreg_srl_sig_22_0_1_101
1404 
    );
1405 
  BU2_U0_Mshreg_srl_sig_22_0_0 : SRLC16
1406 
    generic map(
1407 
      INIT => X"0000"
1408 
    )
1409 
    port map (
1410 
      A0 => BU2_U0_N1,
1411 
      A1 => BU2_U0_N1,
1412 
      A2 => BU2_U0_N1,
1413 
      A3 => BU2_U0_N1,
1414 
      CLK => clk,
1415 
      D => d_2(0),
1416 
      Q => NLW_BU2_U0_Mshreg_srl_sig_22_0_0_Q_UNCONNECTED,
1417 
      Q15 => BU2_U0_Mshreg_srl_sig_22_0_0_100
1418 
    );
1419 
  BU2_U0_XST_VCC : VCC
1420 
    port map (
1421 
      P => BU2_U0_N1
1422 
    );
1423 
  BU2_U0_XST_GND : GND
1424 
    port map (
1425 
      G => BU2_U0_N0
1426 
    );
1427 
  BU2_U0_gen_output_regs_output_regs_fd_output_32 : FDR
1428 
    generic map(
1429 
      INIT => '0'
1430 
    )
1431 
    port map (
1432 
      C => clk,
1433 
      D => BU2_U0_srl_sig_22_31_97,
1434 
      R => sclr,
1435 
      Q => q_3(31)
1436 
    );
1437 
  BU2_U0_gen_output_regs_output_regs_fd_output_31 : FDR
1438 
    generic map(
1439 
      INIT => '0'
1440 
    )
1441 
    port map (
1442 
      C => clk,
1443 
      D => BU2_U0_srl_sig_22_30_96,
1444 
      R => sclr,
1445 
      Q => q_3(30)
1446 
    );
1447 
  BU2_U0_gen_output_regs_output_regs_fd_output_30 : FDR
1448 
    generic map(
1449 
      INIT => '0'
1450 
    )
1451 
    port map (
1452 
      C => clk,
1453 
      D => BU2_U0_srl_sig_22_29_95,
1454 
      R => sclr,
1455 
      Q => q_3(29)
1456 
    );
1457 
  BU2_U0_gen_output_regs_output_regs_fd_output_29 : FDR
1458 
    generic map(
1459 
      INIT => '0'
1460 
    )
1461 
    port map (
1462 
      C => clk,
1463 
      D => BU2_U0_srl_sig_22_28_94,
1464 
      R => sclr,
1465 
      Q => q_3(28)
1466 
    );
1467 
  BU2_U0_gen_output_regs_output_regs_fd_output_28 : FDR
1468 
    generic map(
1469 
      INIT => '0'
1470 
    )
1471 
    port map (
1472 
      C => clk,
1473 
      D => BU2_U0_srl_sig_22_27_93,
1474 
      R => sclr,
1475 
      Q => q_3(27)
1476 
    );
1477 
  BU2_U0_gen_output_regs_output_regs_fd_output_27 : FDR
1478 
    generic map(
1479 
      INIT => '0'
1480 
    )
1481 
    port map (
1482 
      C => clk,
1483 
      D => BU2_U0_srl_sig_22_26_92,
1484 
      R => sclr,
1485 
      Q => q_3(26)
1486 
    );
1487 
  BU2_U0_gen_output_regs_output_regs_fd_output_26 : FDR
1488 
    generic map(
1489 
      INIT => '0'
1490 
    )
1491 
    port map (
1492 
      C => clk,
1493 
      D => BU2_U0_srl_sig_22_25_91,
1494 
      R => sclr,
1495 
      Q => q_3(25)
1496 
    );
1497 
  BU2_U0_gen_output_regs_output_regs_fd_output_25 : FDR
1498 
    generic map(
1499 
      INIT => '0'
1500 
    )
1501 
    port map (
1502 
      C => clk,
1503 
      D => BU2_U0_srl_sig_22_24_90,
1504 
      R => sclr,
1505 
      Q => q_3(24)
1506 
    );
1507 
  BU2_U0_gen_output_regs_output_regs_fd_output_24 : FDR
1508 
    generic map(
1509 
      INIT => '0'
1510 
    )
1511 
    port map (
1512 
      C => clk,
1513 
      D => BU2_U0_srl_sig_22_23_89,
1514 
      R => sclr,
1515 
      Q => q_3(23)
1516 
    );
1517 
  BU2_U0_gen_output_regs_output_regs_fd_output_23 : FDR
1518 
    generic map(
1519 
      INIT => '0'
1520 
    )
1521 
    port map (
1522 
      C => clk,
1523 
      D => BU2_U0_srl_sig_22_22_88,
1524 
      R => sclr,
1525 
      Q => q_3(22)
1526 
    );
1527 
  BU2_U0_gen_output_regs_output_regs_fd_output_22 : FDR
1528 
    generic map(
1529 
      INIT => '0'
1530 
    )
1531 
    port map (
1532 
      C => clk,
1533 
      D => BU2_U0_srl_sig_22_21_87,
1534 
      R => sclr,
1535 
      Q => q_3(21)
1536 
    );
1537 
  BU2_U0_gen_output_regs_output_regs_fd_output_21 : FDR
1538 
    generic map(
1539 
      INIT => '0'
1540 
    )
1541 
    port map (
1542 
      C => clk,
1543 
      D => BU2_U0_srl_sig_22_20_86,
1544 
      R => sclr,
1545 
      Q => q_3(20)
1546 
    );
1547 
  BU2_U0_gen_output_regs_output_regs_fd_output_20 : FDR
1548 
    generic map(
1549 
      INIT => '0'
1550 
    )
1551 
    port map (
1552 
      C => clk,
1553 
      D => BU2_U0_srl_sig_22_19_85,
1554 
      R => sclr,
1555 
      Q => q_3(19)
1556 
    );
1557 
  BU2_U0_gen_output_regs_output_regs_fd_output_19 : FDR
1558 
    generic map(
1559 
      INIT => '0'
1560 
    )
1561 
    port map (
1562 
      C => clk,
1563 
      D => BU2_U0_srl_sig_22_18_84,
1564 
      R => sclr,
1565 
      Q => q_3(18)
1566 
    );
1567 
  BU2_U0_gen_output_regs_output_regs_fd_output_18 : FDR
1568 
    generic map(
1569 
      INIT => '0'
1570 
    )
1571 
    port map (
1572 
      C => clk,
1573 
      D => BU2_U0_srl_sig_22_17_83,
1574 
      R => sclr,
1575 
      Q => q_3(17)
1576 
    );
1577 
  BU2_U0_gen_output_regs_output_regs_fd_output_17 : FDR
1578 
    generic map(
1579 
      INIT => '0'
1580 
    )
1581 
    port map (
1582 
      C => clk,
1583 
      D => BU2_U0_srl_sig_22_16_82,
1584 
      R => sclr,
1585 
      Q => q_3(16)
1586 
    );
1587 
  BU2_U0_gen_output_regs_output_regs_fd_output_16 : FDR
1588 
    generic map(
1589 
      INIT => '0'
1590 
    )
1591 
    port map (
1592 
      C => clk,
1593 
      D => BU2_U0_srl_sig_22_15_81,
1594 
      R => sclr,
1595 
      Q => q_3(15)
1596 
    );
1597 
  BU2_U0_gen_output_regs_output_regs_fd_output_15 : FDR
1598 
    generic map(
1599 
      INIT => '0'
1600 
    )
1601 
    port map (
1602 
      C => clk,
1603 
      D => BU2_U0_srl_sig_22_14_80,
1604 
      R => sclr,
1605 
      Q => q_3(14)
1606 
    );
1607 
  BU2_U0_gen_output_regs_output_regs_fd_output_14 : FDR
1608 
    generic map(
1609 
      INIT => '0'
1610 
    )
1611 
    port map (
1612 
      C => clk,
1613 
      D => BU2_U0_srl_sig_22_13_79,
1614 
      R => sclr,
1615 
      Q => q_3(13)
1616 
    );
1617 
  BU2_U0_gen_output_regs_output_regs_fd_output_13 : FDR
1618 
    generic map(
1619 
      INIT => '0'
1620 
    )
1621 
    port map (
1622 
      C => clk,
1623 
      D => BU2_U0_srl_sig_22_12_78,
1624 
      R => sclr,
1625 
      Q => q_3(12)
1626 
    );
1627 
  BU2_U0_gen_output_regs_output_regs_fd_output_12 : FDR
1628 
    generic map(
1629 
      INIT => '0'
1630 
    )
1631 
    port map (
1632 
      C => clk,
1633 
      D => BU2_U0_srl_sig_22_11_77,
1634 
      R => sclr,
1635 
      Q => q_3(11)
1636 
    );
1637 
  BU2_U0_gen_output_regs_output_regs_fd_output_11 : FDR
1638 
    generic map(
1639 
      INIT => '0'
1640 
    )
1641 
    port map (
1642 
      C => clk,
1643 
      D => BU2_U0_srl_sig_22_10_76,
1644 
      R => sclr,
1645 
      Q => q_3(10)
1646 
    );
1647 
  BU2_U0_gen_output_regs_output_regs_fd_output_10 : FDR
1648 
    generic map(
1649 
      INIT => '0'
1650 
    )
1651 
    port map (
1652 
      C => clk,
1653 
      D => BU2_U0_srl_sig_22_9_75,
1654 
      R => sclr,
1655 
      Q => q_3(9)
1656 
    );
1657 
  BU2_U0_gen_output_regs_output_regs_fd_output_9 : FDR
1658 
    generic map(
1659 
      INIT => '0'
1660 
    )
1661 
    port map (
1662 
      C => clk,
1663 
      D => BU2_U0_srl_sig_22_8_74,
1664 
      R => sclr,
1665 
      Q => q_3(8)
1666 
    );
1667 
  BU2_U0_gen_output_regs_output_regs_fd_output_8 : FDR
1668 
    generic map(
1669 
      INIT => '0'
1670 
    )
1671 
    port map (
1672 
      C => clk,
1673 
      D => BU2_U0_srl_sig_22_7_73,
1674 
      R => sclr,
1675 
      Q => q_3(7)
1676 
    );
1677 
  BU2_U0_gen_output_regs_output_regs_fd_output_7 : FDR
1678 
    generic map(
1679 
      INIT => '0'
1680 
    )
1681 
    port map (
1682 
      C => clk,
1683 
      D => BU2_U0_srl_sig_22_6_72,
1684 
      R => sclr,
1685 
      Q => q_3(6)
1686 
    );
1687 
  BU2_U0_gen_output_regs_output_regs_fd_output_6 : FDR
1688 
    generic map(
1689 
      INIT => '0'
1690 
    )
1691 
    port map (
1692 
      C => clk,
1693 
      D => BU2_U0_srl_sig_22_5_71,
1694 
      R => sclr,
1695 
      Q => q_3(5)
1696 
    );
1697 
  BU2_U0_gen_output_regs_output_regs_fd_output_5 : FDR
1698 
    generic map(
1699 
      INIT => '0'
1700 
    )
1701 
    port map (
1702 
      C => clk,
1703 
      D => BU2_U0_srl_sig_22_4_70,
1704 
      R => sclr,
1705 
      Q => q_3(4)
1706 
    );
1707 
  BU2_U0_gen_output_regs_output_regs_fd_output_4 : FDR
1708 
    generic map(
1709 
      INIT => '0'
1710 
    )
1711 
    port map (
1712 
      C => clk,
1713 
      D => BU2_U0_srl_sig_22_3_69,
1714 
      R => sclr,
1715 
      Q => q_3(3)
1716 
    );
1717 
  BU2_U0_gen_output_regs_output_regs_fd_output_3 : FDR
1718 
    generic map(
1719 
      INIT => '0'
1720 
    )
1721 
    port map (
1722 
      C => clk,
1723 
      D => BU2_U0_srl_sig_22_2_68,
1724 
      R => sclr,
1725 
      Q => q_3(2)
1726 
    );
1727 
  BU2_U0_gen_output_regs_output_regs_fd_output_2 : FDR
1728 
    generic map(
1729 
      INIT => '0'
1730 
    )
1731 
    port map (
1732 
      C => clk,
1733 
      D => BU2_U0_srl_sig_22_1_67,
1734 
      R => sclr,
1735 
      Q => q_3(1)
1736 
    );
1737 
  BU2_U0_gen_output_regs_output_regs_fd_output_1 : FDR
1738 
    generic map(
1739 
      INIT => '0'
1740 
    )
1741 
    port map (
1742 
      C => clk,
1743 
      D => BU2_U0_srl_sig_22_0_66,
1744 
      R => sclr,
1745 
      Q => q_3(0)
1746 
    );
1747 
 
1748 
end STRUCTURE;
1749 
 
1750 
-- synthesis translate_on

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